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updated testbench (not functional yet)

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This commit is contained in:
Markus Fröschle
2014-12-21 08:32:20 +00:00
parent 132f136d3a
commit db93ec6026
9 changed files with 1256 additions and 630 deletions
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135
vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
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@@ -13,7 +13,7 @@
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
---- K ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ----
@@ -53,18 +53,18 @@ ENTITY DDR_CTRL IS
fb_adr : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fb_cs1_n : IN STD_LOGIC;
fb_oe_n : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
FB_WRn : IN STD_LOGIC;
FIFO_CLR : IN STD_LOGIC;
fb_size0 : IN STD_LOGIC;
fb_size1 : IN STD_LOGIC;
fb_ale : IN STD_LOGIC;
fb_wr_n : IN STD_LOGIC;
fifo_clr : IN STD_LOGIC;
video_control_register : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
blitter_adr : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
blitter_sig : IN STD_LOGIC;
blitter_wr : IN STD_LOGIC;
ddrclk0 : IN STD_LOGIC;
CLK_33M : IN STD_LOGIC;
clk_33m : IN STD_LOGIC;
fifo_mw : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); -- video Adress bus at the DDR chips
@@ -85,7 +85,7 @@ ENTITY DDR_CTRL IS
VIDEO_DDR_TA : OUT STD_LOGIC;
sr_blitter_dack : OUT STD_LOGIC;
BA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
ddrwr_d_sel1 : OUT STD_LOGIC;
VDM_SEL : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
data_in : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
@@ -183,7 +183,7 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS
SIGNAL ba_p : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL tsiz : STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
tsiz <= FB_SIZE1 & FB_SIZE0;
tsiz <= fb_size1 & fb_size0;
WITH tsiz SELECT
access_width <= LONG WHEN "11",
WORD WHEN "00",
@@ -208,17 +208,17 @@ BEGIN
------------------------------------ cpu READ (REG DDR => cpu) AND WRITE (cpu => REG DDR) ---------------------------------------------------------------------
fbctrl_reg : PROCESS
BEGIN
WAIT UNTIL RISING_EDGE(clk_main);
WAIT UNTIL RISING_EDGE(clk_33m);
fb_regddr <= fb_regddr_next;
END PROCESS FBCTRL_REG;
fbctrl_dec : PROCESS(fb_regddr, bus_cyc, ddr_sel, access_width, FB_WRn, ddr_cs)
fbctrl_dec : PROCESS(fb_regddr, bus_cyc, ddr_sel, access_width, fb_wr_n, ddr_cs)
BEGIN
CASE fb_regddr IS
WHEN FR_WAIT =>
IF bus_cyc = '1' THEN
fb_regddr_next <= FR_S0;
ELSIF ddr_sel = '1' AND access_width = LONG AND FB_WRn = '0' THEN
ELSIF ddr_sel = '1' AND access_width = LONG AND fb_wr_n = '0' THEN
fb_regddr_next <= FR_S0;
ELSE
fb_regddr_next <= FR_WAIT;
@@ -239,7 +239,7 @@ BEGIN
END IF;
WHEN FR_S2 =>
IF ddr_cs = '1' AND bus_cyc = '0' AND access_width = LONG AND FB_WRn = '0' THEN -- wait during long word access IF needed
IF ddr_cs = '1' AND bus_cyc = '0' AND access_width = LONG AND fb_wr_n = '0' THEN -- wait during long word access IF needed
fb_regddr_next <= FR_S2;
ELSIF ddr_cs = '1' THEN
fb_regddr_next <= fr_s3;
@@ -253,11 +253,11 @@ BEGIN
END PROCESS FBCTRL_DEC;
-- Coldfire cpu access:
FB_LE(0) <= NOT FB_WRn WHEN fb_regddr = FR_WAIT ELSE
NOT FB_WRn WHEN fb_regddr = FR_S0 AND ddr_cs = '1' ELSE '0';
FB_LE(1) <= NOT FB_WRn WHEN fb_regddr = fr_s1 AND ddr_cs = '1' ELSE '0';
FB_LE(2) <= NOT FB_WRn WHEN fb_regddr = FR_S2 AND ddr_cs = '1' ELSE '0';
FB_LE(3) <= NOT FB_WRn WHEN fb_regddr = fr_s3 AND ddr_cs = '1' ELSE '0';
FB_LE(0) <= NOT fb_wr_n WHEN fb_regddr = FR_WAIT ELSE
NOT fb_wr_n WHEN fb_regddr = FR_S0 AND ddr_cs = '1' ELSE '0';
FB_LE(1) <= NOT fb_wr_n WHEN fb_regddr = fr_s1 AND ddr_cs = '1' ELSE '0';
FB_LE(2) <= NOT fb_wr_n WHEN fb_regddr = FR_S2 AND ddr_cs = '1' ELSE '0';
FB_LE(3) <= NOT fb_wr_n WHEN fb_regddr = fr_s3 AND ddr_cs = '1' ELSE '0';
-- Video data access:
VIDEO_DDR_TA <= '1' WHEN fb_regddr = FR_S0 AND ddr_cs = '1' ELSE
@@ -269,10 +269,10 @@ BEGIN
-- Write access for video data:
FB_VDOE(0) <= '1' WHEN fb_regddr = FR_S0 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' AND access_width = LONG ELSE
'1' WHEN fb_regddr = FR_S0 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' AND access_width /= LONG AND clk_main = '0' ELSE '0';
'1' WHEN fb_regddr = FR_S0 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' AND access_width /= LONG AND clk_33m = '0' ELSE '0';
FB_VDOE(1) <= '1' WHEN fb_regddr = fr_s1 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' ELSE '0';
FB_VDOE(2) <= '1' WHEN fb_regddr = FR_S2 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' ELSE '0';
FB_VDOE(3) <= '1' WHEN fb_regddr = fr_s3 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' AND clk_main = '0' ELSE '0';
FB_VDOE(3) <= '1' WHEN fb_regddr = fr_s3 AND ddr_cs = '1' AND fb_oe_n = '0' AND ddr_config = '0' AND clk_33m = '0' ELSE '0';
bus_cyc_end <= '1' WHEN fb_regddr = FR_S0 AND ddr_cs = '1' AND access_width /= LONG ELSE
'1' WHEN fb_regddr = fr_s3 AND ddr_cs = '1' ELSE '0';
@@ -285,7 +285,7 @@ BEGIN
ddr_state <= ddr_next_state;
END PROCESS ddr_state_reg;
ddr_state_dec: PROCESS(ddr_state, ddr_refresh_req, cpu_ddr_sync, ddr_config, FB_WRn, ddr_access, blitter_wr, fifo_req, fifo_bank_ok,
ddr_state_dec: PROCESS(ddr_state, ddr_refresh_req, cpu_ddr_sync, ddr_config, fb_wr_n, ddr_access, blitter_wr, fifo_req, fifo_bank_ok,
fifo_mw, cpu_req, video_adr_cnt, ddr_sel, tsiz, data_in, fifo_ba, ddr_refresh_sig)
BEGIN
CASE ddr_state IS
@@ -309,7 +309,7 @@ BEGIN
ddr_next_state <= ds_t3;
WHEN ds_t3 =>
IF ddr_access = cpu AND FB_WRn = '0' THEN
IF ddr_access = cpu AND fb_wr_n = '0' THEN
ddr_next_state <= DS_T4W;
ELSIF ddr_access = blitter AND blitter_wr = '1' THEN
ddr_next_state <= DS_T4W;
@@ -399,7 +399,7 @@ BEGIN
END IF;
WHEN ds_t10f =>
IF ddr_sel = '1' AND (FB_WRn = '1' OR tsiz /= "11") AND data_in(13 DOWNTO 12) /= fifo_ba THEN
IF ddr_sel = '1' AND (fb_wr_n = '1' OR tsiz /= "11") AND data_in(13 DOWNTO 12) /= fifo_ba THEN
ddr_next_state <= ds_t3;
ELSE
ddr_next_state <= ds_t7f;
@@ -481,10 +481,14 @@ BEGIN
sr_ddr_wr <= '0';
sr_ddrwr_d_sel <= '0';
mcs <= mcs(0) & clk_main; -- sync on clk_main
mcs <= mcs(0) & clk_33m; -- sync on clk_33m
blitter_req <= blitter_sig AND NOT video_control_register(vrcr_config_on) AND video_control_register(vrcr_vcke) AND video_control_register(vrcr_vcs);
fifo_clr_sync <= FIFO_CLR;
blitter_req <= blitter_sig AND NOT
video_control_register(vrcr_config_on) AND
video_control_register(vrcr_vcke) AND
video_control_register(vrcr_vcs);
fifo_clr_sync <= fifo_clr;
clear_fifo_cnt <= fifo_clr_sync OR NOT fifo_active;
stop <= fifo_clr_sync OR clear_fifo_cnt;
@@ -492,7 +496,12 @@ BEGIN
fifo_req <= '1';
ELSIF fifo_mw < STD_LOGIC_VECTOR (TO_UNSIGNED(fifo_hwm, fifo_mw'LENGTH)) AND fifo_req = '1' THEN
fifo_req <= '1';
ELSIF fifo_active = '1' AND clear_fifo_cnt = '0' AND stop = '0' AND ddr_config = '0' AND video_control_register(vrcr_vcke) = '1' AND video_control_register(vrcr_vcs) = '1' THEN
ELSIF fifo_active = '1' AND
clear_fifo_cnt = '0' AND
stop = '0' AND
ddr_config = '0' AND
video_control_register(vrcr_vcke) = '1' AND
video_control_register(vrcr_vcs) = '1' THEN
fifo_req <= '1';
ELSE
fifo_req <= '1';
@@ -516,7 +525,7 @@ BEGIN
ddr_refresh_req <= '0';
END IF;
IF ddr_refresh_cnt = 0 AND clk_main = '0' THEN
IF ddr_refresh_cnt = 0 AND clk_33m = '0' THEN
refresh_time <= '1';
ELSE
refresh_time <= '0';
@@ -534,13 +543,13 @@ BEGIN
bus_cyc <= '0';
ELSIF ddr_state = ds_t1 AND cpu_ddr_sync = '1' AND cpu_req = '1' THEN
bus_cyc <= '1';
ELSIF ddr_state = ds_t2a AND ddr_sel = '1' AND FB_WRn = '0' THEN
ELSIF ddr_state = ds_t2a AND ddr_sel = '1' AND fb_wr_n = '0' THEN
bus_cyc <= '1';
ELSIF ddr_state = ds_t2a AND ddr_sel = '1' AND access_width /= LONG THEN
bus_cyc <= '1';
ELSIF ddr_state = ds_t2b THEN
bus_cyc <= '1';
ELSIF ddr_state = ds_t10f AND FB_WRn = '0' AND data_in(13 DOWNTO 12) = fifo_ba THEN
ELSIF ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba THEN
bus_cyc <= '1';
ELSIF ddr_state = ds_t10f AND access_width /= LONG AND data_in(13 DOWNTO 12) = fifo_ba THEN
bus_cyc <= '1';
@@ -560,7 +569,7 @@ BEGIN
va_p <= blitter_row_adr;
ba_p <= blitter_ba;
ddr_access <= blitter;
ELSIF ddr_state = ds_t2a AND ddr_sel = '1' AND FB_WRn = '0' THEN
ELSIF ddr_state = ds_t2a AND ddr_sel = '1' AND fb_wr_n = '0' THEN
va_s(10) <= '1';
ddr_access <= cpu;
ELSIF ddr_state = ds_t2a AND ddr_sel = '1' AND access_width /= LONG THEN
@@ -579,7 +588,7 @@ BEGIN
fifo_bank_ok <= '0';
ELSIF ddr_state = ds_t3 THEN
va_s(10) <= va_s(10);
IF (FB_WRn = '0' AND ddr_access = cpu) OR (blitter_wr = '1' AND ddr_access = blitter) THEN
IF (fb_wr_n = '0' AND ddr_access = cpu) OR (blitter_wr = '1' AND ddr_access = blitter) THEN
va_s(9 DOWNTO 0) <= cpu_col_adr;
ba_s <= cpu_ba;
ELSIF fifo_active = '1' THEN
@@ -671,7 +680,7 @@ BEGIN
ba_p <= fifo_ba;
ELSIF ddr_state = ds_t9f THEN
va_s(10) <= '1';
ELSIF ddr_state = ds_t10f AND FB_WRn = '0' AND data_in(13 DOWNTO 12) = fifo_ba THEN
ELSIF ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba THEN
va_s(10) <= '1';
ddr_access <= cpu;
ELSIF ddr_state = ds_t10f AND access_width /= LONG AND data_in(13 DOWNTO 12) = fifo_ba THEN
@@ -692,12 +701,12 @@ BEGIN
END IF;
END PROCESS p_clk0;
ddr_sel <= '1' WHEN FB_ALE = '1' AND data_in(31 DOWNTO 30) = "01" ELSE '0';
ddr_sel <= '1' WHEN fb_ale = '1' AND data_in(31 DOWNTO 30) = "01" ELSE '0';
p_ddr_cs: PROCESS
BEGIN
WAIT UNTIL RISING_EDGE(clk_main);
IF FB_ALE = '1' THEN
WAIT UNTIL RISING_EDGE(clk_33m);
IF fb_ale = '1' THEN
ddr_cs <= ddr_sel;
END IF;
END PROCESS p_ddr_cs;
@@ -706,13 +715,13 @@ BEGIN
BEGIN
WAIT UNTIL RISING_EDGE(ddr_sync_66m);
IF ddr_sel = '1' AND FB_WRn = '1' AND ddr_config = '0' THEN
IF ddr_sel = '1' AND fb_wr_n = '1' AND ddr_config = '0' THEN
cpu_req <= '1';
ELSIF ddr_sel = '1' AND access_width /= LONG AND ddr_config = '0' THEN -- Start WHEN NOT config AND NOT long word access.
cpu_req <= '1';
ELSIF ddr_sel = '1' AND ddr_config = '1' THEN -- Config, start immediately.
cpu_req <= '1';
ELSIF fb_regddr = fr_s1 AND FB_WRn = '0' THEN -- Long word write later.
ELSIF fb_regddr = fr_s1 AND fb_wr_n = '0' THEN -- Long word write later.
cpu_req <= '1';
ELSIF fb_regddr /= fr_s1 AND fb_regddr /= fr_s3 AND bus_cyc_end = '0' AND bus_cyc = '0' THEN -- Halt, bus cycle IN progress OR ready.
cpu_req <= '0';
@@ -723,35 +732,35 @@ BEGIN
-- Refresh: Always 8 at a time every 7.8us.
-- 7.8us x 8 = 62.4us = 2059 -> 2048 @ 33MHz.
BEGIN
WAIT UNTIL RISING_EDGE(CLK_33M);
ddr_refresh_cnt <= ddr_refresh_cnt + 1; -- Count 0 to 2047.
WAIT UNTIL RISING_EDGE(clk_33m);
ddr_refresh_cnt <= ddr_refresh_cnt + 1; -- Count from 0 to 2047
END PROCESS p_refresh;
sr_fifo_wre <= sr_fifo_wre_i;
va <= data_in(26 DOWNTO 14) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND FB_WRn = '0' ELSE
data_in(26 DOWNTO 14) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') ELSE
va <= data_in(26 DOWNTO 14) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND fb_wr_n = '0' ELSE
data_in(26 DOWNTO 14) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (fb_size0 = '0' OR fb_size1= '0') ELSE
va_p WHEN ddr_state = ds_t2a ELSE
data_in(26 DOWNTO 14) WHEN ddr_state = ds_t10f AND FB_WRn = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE
data_in(26 DOWNTO 14) WHEN ddr_state = ds_t10f AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE
data_in(26 DOWNTO 14) WHEN ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE
data_in(26 DOWNTO 14) WHEN ddr_state = ds_t10f AND (fb_size0 = '0' OR fb_size1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE
va_p WHEN ddr_state = ds_t10f ELSE
"0010000000000" WHEN ddr_state = ds_r2 AND ddr_refresh_sig = x"9" ELSE va_s;
BA <= data_in(13 DOWNTO 12) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND FB_WRn = '0' ELSE
data_in(13 DOWNTO 12) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') ELSE
ba <= data_in(13 DOWNTO 12) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND fb_wr_n = '0' ELSE
data_in(13 DOWNTO 12) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (fb_size0 = '0' OR fb_size1= '0') ELSE
ba_p WHEN ddr_state = ds_t2a ELSE
data_in(13 DOWNTO 12) WHEN ddr_state = ds_t10f AND FB_WRn = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE
data_in(13 DOWNTO 12) WHEN ddr_state = ds_t10f AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE
data_in(13 DOWNTO 12) WHEN ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE
data_in(13 DOWNTO 12) WHEN ddr_state = ds_t10f AND (fb_size0 = '0' OR fb_size1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE
ba_p WHEN ddr_state = ds_t10f ELSE ba_s;
vras <= '1' WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND FB_WRn = '0' ELSE
'1' WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') ELSE
vras <= '1' WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND fb_wr_n = '0' ELSE
'1' WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (fb_size0 = '0' OR fb_size1= '0') ELSE
'1' WHEN ddr_state = ds_t2a AND ddr_access = fifo AND fifo_req = '1' ELSE
'1' WHEN ddr_state = ds_t2a AND ddr_access = blitter AND blitter_req = '1' ELSE
'1' WHEN ddr_state = ds_t2b ELSE
'1' WHEN ddr_state = ds_t10f AND FB_WRn = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE
'1' WHEN ddr_state = ds_t10f AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE
data_in(18) AND NOT FB_WRn AND NOT FB_SIZE0 AND NOT FB_SIZE1 WHEN ddr_state = ds_c7 ELSE
'1' WHEN ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE
'1' WHEN ddr_state = ds_t10f AND (fb_size0 = '0' OR fb_size1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE
data_in(18) AND NOT fb_wr_n AND NOT fb_size0 AND NOT fb_size1 WHEN ddr_state = ds_c7 ELSE
'1' WHEN ddr_state = ds_cb6 ELSE
'1' WHEN ddr_state = ds_cb8 ELSE
'1' WHEN ddr_state = ds_r2 ELSE '0';
@@ -762,11 +771,11 @@ BEGIN
'1' WHEN ddr_state = ds_t6f ELSE
'1' WHEN ddr_state = DS_T8F ELSE
'1' WHEN ddr_state = ds_t10f AND vras = '0' ELSE
data_in(17) AND NOT FB_WRn AND NOT FB_SIZE0 AND NOT FB_SIZE1 WHEN ddr_state = ds_c7 ELSE
data_in(17) AND NOT fb_wr_n AND NOT fb_size0 AND NOT fb_size1 WHEN ddr_state = ds_c7 ELSE
'1' WHEN ddr_state = ds_r2 AND ddr_refresh_sig /= x"9" ELSE '0';
vwe <= '1' WHEN ddr_state = DS_T6W ELSE
data_in(16) AND NOT FB_WRn AND NOT FB_SIZE0 AND NOT FB_SIZE1 WHEN ddr_state = ds_c7 ELSE
data_in(16) AND NOT fb_wr_n AND NOT fb_size0 AND NOT fb_size1 WHEN ddr_state = ds_c7 ELSE
'1' WHEN ddr_state = ds_cb6 ELSE
'1' WHEN ddr_state = ds_cb8 ELSE
'1' WHEN ddr_state = ds_r2 AND ddr_refresh_sig = x"9" ELSE '0';
@@ -811,20 +820,20 @@ BEGIN
p_video_regs : PROCESS
-- Video registers.
BEGIN
WAIT UNTIL RISING_EDGE(clk_main);
IF video_base_l = '1' AND FB_WRn = '0' AND byte_sel(1) = '1' THEN
WAIT UNTIL RISING_EDGE(clk_33m);
IF video_base_l = '1' AND fb_wr_n = '0' AND byte_sel(1) = '1' THEN
video_base_l_d <= data_in(23 DOWNTO 16); -- 16 byte boarders.
END IF;
IF video_base_m = '1' AND FB_WRn = '0' AND byte_sel(3) = '1' THEN
IF video_base_m = '1' AND fb_wr_n = '0' AND byte_sel(3) = '1' THEN
video_base_m_d <= data_in(23 DOWNTO 16);
END IF;
IF video_base_h = '1' AND FB_WRn = '0' AND byte_sel(1) = '1' THEN
IF video_base_h = '1' AND fb_wr_n = '0' AND byte_sel(1) = '1' THEN
video_base_h_d <= data_in(23 DOWNTO 16);
END IF;
IF video_base_h = '1' AND FB_WRn = '0' AND byte_sel(0) = '1' THEN
IF video_base_h = '1' AND fb_wr_n = '0' AND byte_sel(0) = '1' THEN
video_base_x_d <= data_in(26 DOWNTO 24);
END IF;
END PROCESS p_video_regs;
@@ -856,8 +865,8 @@ END ARCHITECTURE BEHAVIOUR;
-- va : Video DDR address multiplexed
-- va_p : latched va, wenn FIFO_AC, BLITTER_AC
-- va_s : latch for default va
-- BA : Video DDR bank address multiplexed
-- ba_p : latched BA, wenn FIFO_AC, BLITTER_AC
-- ba_s : latch for default BA
-- ba : Video DDR bank address multiplexed
-- ba_p : latched ba, wenn FIFO_AC, BLITTER_AC
-- ba_s : latch for default ba
--
--FB_SIZE ersetzen.

296
vhdl/rtl/vhdl/Firebee/Firebee.vhd
View File

@@ -98,21 +98,21 @@ ENTITY firebee IS
PORT(
RSTO_MCFn : IN STD_LOGIC; -- reset SIGNAL from Coldfire
CLK_33M : IN STD_LOGIC; -- 33 MHz clock
CLK_MAIN : IN STD_LOGIC; -- 33 MHz clock
clk_main : IN STD_LOGIC; -- 33 MHz clock
CLK_24M576 : OUT STD_LOGIC; --
CLK_25M : OUT STD_LOGIC;
clk_ddr_OUT : OUT STD_LOGIC;
clk_ddr_OUTn : OUT STD_LOGIC;
CLK_USB : OUT STD_LOGIC;
clk_usb : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
FB_ALE : IN STD_LOGIC;
fb_ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fb_ale : IN STD_LOGIC;
FB_BURSTn : IN STD_LOGIC;
FB_CSn : IN STD_LOGIC_VECTOR (3 DOWNTO 1);
FB_SIZE : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
fb_size : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
FB_OEn : IN STD_LOGIC;
FB_WRn : IN STD_LOGIC;
fb_wr_n : IN STD_LOGIC;
FB_TAn : OUT STD_LOGIC;
DACK1n : IN STD_LOGIC;
@@ -121,43 +121,43 @@ ENTITY firebee IS
MASTERn : IN STD_LOGIC; -- determines if the Firebee is PCI master (='0') OR slave. Not used so far.
TOUT0n : IN STD_LOGIC; -- Not used so far.
LED_FPGA_OK : OUT STD_LOGIC;
RESERVED_1 : OUT STD_LOGIC;
led_fpga_ok : OUT STD_LOGIC;
reserved_1 : OUT STD_LOGIC;
VA : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
BA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
VWEn : OUT STD_LOGIC;
VcaSn : OUT STD_LOGIC;
VRASn : OUT STD_LOGIC;
vrASn : OUT STD_LOGIC;
VCSn : OUT STD_LOGIC;
CLK_PIXEL : OUT STD_LOGIC;
clk_pixel : OUT STD_LOGIC;
SYNCn : OUT STD_LOGIC;
VSYNC : OUT STD_LOGIC;
HSYNC : OUT STD_LOGIC;
BLANKn : OUT STD_LOGIC;
VR : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
VG : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
VB : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
vr : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
vg : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
vb : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
VDM : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
vdm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
VD : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
VD_QS : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
vd : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
vd_qs : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
PD_VGAn : OUT STD_LOGIC;
VCKE : OUT STD_LOGIC;
PIC_INT : IN STD_LOGIC;
E0_INT : IN STD_LOGIC;
DVI_INT : IN STD_LOGIC;
PD_vgAn : OUT STD_LOGIC;
vcke : OUT STD_LOGIC;
pic_int : IN STD_LOGIC;
e0_int : IN STD_LOGIC;
dvi_int : IN STD_LOGIC;
PCI_INTAn : IN STD_LOGIC;
PCI_INTBn : IN STD_LOGIC;
PCI_INTCn : IN STD_LOGIC;
PCI_INTDn : IN STD_LOGIC;
IRQn : OUT STD_LOGIC_VECTOR (7 DOWNTO 2);
TIN0 : OUT STD_LOGIC;
tin0 : OUT STD_LOGIC;
YM_QA : OUT STD_LOGIC;
YM_QB : OUT STD_LOGIC;
@@ -244,9 +244,9 @@ ENTITY firebee IS
DSP_SRWEn : OUT STD_LOGIC;
DSP_SROEn : OUT STD_LOGIC;
IDE_INT : IN STD_LOGIC;
IDE_RDY : IN STD_LOGIC;
IDE_RES : OUT STD_LOGIC;
ide_int : IN STD_LOGIC;
ide_rdy : IN STD_LOGIC;
ide_res : OUT STD_LOGIC;
IDE_WRn : OUT STD_LOGIC;
IDE_RDn : OUT STD_LOGIC;
IDE_CSn : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
@@ -490,7 +490,7 @@ ARCHITECTURE Structure of firebee is
BEGIN
I_PLL1: altpll1
PORT MAP(
inclk0 => CLK_MAIN,
inclk0 => clk_main,
c0 => clk_2m4576, -- 2.4576 MHz
c1 => CLK_24M576, -- 24.576 MHz
c2 => clk_48m, -- 48 MHz
@@ -499,7 +499,7 @@ BEGIN
I_PLL2: altpll2
PORT MAP(
inclk0 => CLK_MAIN,
inclk0 => clk_main,
c0 => clk_ddr(0), -- 132 MHz / 240°
c1 => clk_ddr(1), -- 132 MHz / 0°
c2 => clk_ddr(2), -- 132 MHz / 180°
@@ -509,7 +509,7 @@ BEGIN
I_PLL3: altpll3
PORT MAP(
inclk0 => CLK_MAIN,
inclk0 => clk_main,
c0 => clk_2m0, -- 2 MHz
c1 => clk_fdc, -- 16 MHz
c2 => clk_25m_i, -- 25 MHz
@@ -518,7 +518,7 @@ BEGIN
I_PLL4: altpll4
PORT MAP(
inclk0 => CLK_MAIN,
inclk0 => clk_main,
areset => pll_areset,
scanclk => pll_scanclk,
scandata => pll_scandata,
@@ -535,12 +535,12 @@ BEGIN
reconfig => video_reconfig,
read_param => vr_rd,
write_param => vr_wr,
data_in => FB_AD (24 DOWNTO 16), -- FIXED: this looks like a typo. Must be FB_AD(24 DOWNTO 16) instead of fb_adr(24 DOWNTO 16)
data_in => fb_ad (24 DOWNTO 16), -- FIXED: this looks like a typo. Must be fb_ad(24 DOWNTO 16) instead of fb_adr(24 DOWNTO 16)
counter_type => fb_adr (5 DOWNTO 2),
counter_param => fb_adr (8 DOWNTO 6),
pll_scandataout => pll_scandataout,
pll_scandone => pll_scandone,
clock => CLK_MAIN,
clock => clk_main,
reset => NOT reset_n,
pll_areset_in => '0', -- Not used.
busy => vr_busy,
@@ -553,31 +553,33 @@ BEGIN
);
CLK_25M <= clk_25m_i;
CLK_USB <= clk_48m;
clk_usb <= clk_48m;
clk_ddr_OUT <= clk_ddr(0);
clk_ddr_OUTn <= NOT clk_ddr(0);
CLK_PIXEL <= clk_pixel_i;
clk_pixel <= clk_pixel_i;
P_timebase: PROCESS
p_timebase: PROCESS
BEGIN
WAIT UNTIL RISING_EDGE(clk_500k);
timebase <= timebase + 1;
END PROCESS P_timebase;
END PROCESS p_timebase;
reset_n <= RSTO_MCFn and locked;
IDE_RES <= NOT ide_res_i and reset_n;
ide_res <= NOT ide_res_i and reset_n;
DREQ1n <= DACK1n;
LED_FPGA_OK <= timebase(17);
led_fpga_ok <= timebase(17); -- won't work: doesn't seem to be connected
falcon_io_ta <= acia_cs OR sndcs OR NOT dtack_out_mfp_n OR paddle_cs OR ide_cf_ta OR dma_cs;
FB_TAn <= '0' WHEN (blitter_ta OR video_ddr_ta OR video_mod_ta OR falcon_io_ta OR dsp_ta OR int_handler_ta)= '1' ELSE 'Z';
FB_TAn <= '0' WHEN (blitter_ta OR video_ddr_ta OR video_mod_ta OR falcon_io_ta OR dsp_ta OR int_handler_ta) = '1' ELSE 'Z';
acia_cs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 3) & "000" = x"FFFC00" ELSE '0'; -- FFFC00 - FFFC07
mfp_cs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 6) & "000000" = x"FFFA00" ELSE '0'; -- FFFA00/40
paddle_cs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 6) & "000000"= x"FF9200" ELSE '0'; -- FF9200-FF923F
sndcs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 2) & "00" = x"FF8800" ELSE '0'; -- FF8800-FF8803
sndcs_i <= '1' WHEN sndcs = '1' and fb_adr (1) = '0' ELSE '0';
sndir_i <= '1' WHEN sndcs = '1' and FB_WRn = '0' ELSE '0';
sndir_i <= '1' WHEN sndcs = '1' and fb_wr_n = '0' ELSE '0';
LP_D <= lp_d_x WHEN lp_dir_x = '0' ELSE (OTHERS => 'Z');
LP_DIR <= lp_dir_x;
@@ -603,18 +605,18 @@ BEGIN
lds <= '1' WHEN mfp_cs = '1' OR mfp_intack = '1' ELSE '0';
acia_irq_n <= irq_keybd_n and irq_midi_n;
mfp_intack <= '1' WHEN FB_CSn(2) = '0' and fb_adr(19 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000
dint_n <= '0' WHEN IDE_INT = '1' and fbee_conf(28) = '1' ELSE
dint_n <= '0' WHEN ide_int = '1' and fbee_conf(28) = '1' ELSE
'0' WHEN fd_int = '1' ELSE
'0' WHEN scsi_int = '1' and fbee_conf(28) = '1' ELSE '1';
MIDI_TLR <= midi_out;
MIDI_OLR <= midi_out;
byte <= '1' WHEN FB_SIZE(1) = '0' and FB_SIZE(0) = '1' ELSE '0';
byte <= '1' WHEN fb_size(1) = '0' and fb_size(0) = '1' ELSE '0';
fb_b0 <= '1' WHEN fb_adr(0) = '0' OR byte = '0' ELSE '0';
fb_b1 <= '1' WHEN fb_adr(0) = '1' OR byte = '0' ELSE '0';
FB_AD(31 DOWNTO 24) <= data_out_blitter(31 DOWNTO 24) WHEN data_en_blitter = '1' ELSE
fb_ad(31 DOWNTO 24) <= data_out_blitter(31 DOWNTO 24) WHEN data_en_blitter = '1' ELSE
vdp_q1(31 DOWNTO 24) WHEN fb_vdoe = x"2" ELSE
vdp_q2(31 DOWNTO 24) WHEN fb_vdoe = x"4" ELSE
vdp_q3(31 DOWNTO 24) WHEN fb_vdoe = x"8" ELSE
@@ -637,7 +639,7 @@ BEGIN
x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"10" and FB_OEn = '0' ELSE
x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"11" and FB_OEn = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= data_out_blitter(23 DOWNTO 16) WHEN data_en_blitter = '1' ELSE
fb_ad(23 DOWNTO 16) <= data_out_blitter(23 DOWNTO 16) WHEN data_en_blitter = '1' ELSE
vdp_q1(23 DOWNTO 16) WHEN fb_vdoe = x"2" ELSE
vdp_q2(23 DOWNTO 16) WHEN fb_vdoe = x"4" ELSE
vdp_q3(23 DOWNTO 16) WHEN fb_vdoe = x"8" ELSE
@@ -659,7 +661,7 @@ BEGIN
x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"10" and FB_OEn = '0' ELSE
x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"11" and FB_OEn = '0' ELSE (OTHERS => 'Z');
FB_AD(15 DOWNTO 8) <= data_out_blitter(15 DOWNTO 8) WHEN data_en_blitter = '1' ELSE
fb_ad(15 DOWNTO 8) <= data_out_blitter(15 DOWNTO 8) WHEN data_en_blitter = '1' ELSE
vdp_q1(15 DOWNTO 8) WHEN fb_vdoe = x"2" ELSE
vdp_q2(15 DOWNTO 8) WHEN fb_vdoe = x"4" ELSE
vdp_q3(15 DOWNTO 8) WHEN fb_vdoe = x"8" ELSE
@@ -670,7 +672,7 @@ BEGIN
vdr(15 DOWNTO 8) WHEN fb_vdoe = x"1" ELSE
"000000" & data_out_mfp(7 DOWNTO 6) WHEN mfp_intack = '1' and FB_OEn = '0' ELSE (OTHERS => 'Z');
FB_AD(7 DOWNTO 0) <= data_out_blitter(7 DOWNTO 0) WHEN data_en_blitter = '1' ELSE
fb_ad(7 DOWNTO 0) <= data_out_blitter(7 DOWNTO 0) WHEN data_en_blitter = '1' ELSE
vdp_q1(7 DOWNTO 0) WHEN fb_vdoe = x"2" ELSE
vdp_q2(7 DOWNTO 0) WHEN fb_vdoe = x"4" ELSE
vdp_q3(7 DOWNTO 0) WHEN fb_vdoe = x"8" ELSE
@@ -684,32 +686,32 @@ BEGIN
synchronization : PROCESS
BEGIN
WAIT UNTIL RISING_EDGE(ddr_sync_66m);
IF FB_ALE = '1' THEN
fb_adr <= FB_AD; -- latch Flexbus address
IF fb_ale = '1' THEN
fb_adr <= fb_ad; -- latch Flexbus address
END IF;
--
IF vd_en_i = '0' THEN
vdr <= VD;
vdr <= vd;
ELSE
vdr <= vd_out;
END IF;
--
IF fb_le(0) = '1' THEN
fb_ddr(127 DOWNTO 96) <= FB_AD;
fb_ddr(127 DOWNTO 96) <= fb_ad;
END IF;
--
IF fb_le(1) = '1' THEN
fb_ddr(95 DOWNTO 64) <= FB_AD;
fb_ddr(95 DOWNTO 64) <= fb_ad;
END IF;
--
IF fb_le(2) = '1' THEN
fb_ddr(63 DOWNTO 32) <= FB_AD;
fb_ddr(63 DOWNTO 32) <= fb_ad;
END IF;
--
IF fb_le(3) = '1' THEN
fb_ddr(31 DOWNTO 0) <= FB_AD;
fb_ddr(31 DOWNTO 0) <= fb_ad;
END IF;
END PROCESS SYNCHRONIZATION;
END PROCESS synchronization;
video_out : PROCESS
BEGIN
@@ -727,24 +729,24 @@ BEGIN
END PROCESS p_ddr_wr;
vd_qs_en <= ddr_wr;
VD <= vd_out WHEN vd_en = '1' ELSE (OTHERS => 'Z');
vd <= vd_out WHEN vd_en = '1' ELSE (OTHERS => 'Z');
vd_qs_out(0) <= clk_ddr(0);
vd_qs_out(1) <= clk_ddr(0);
vd_qs_out(2) <= clk_ddr(0);
vd_qs_out(3) <= clk_ddr(0);
VD_QS <= vd_qs_out WHEN vd_qs_en = '1' ELSE (OTHERS => 'Z');
vd_qs <= vd_qs_out WHEN vd_qs_en = '1' ELSE (OTHERS => 'Z');
ddr_data_in_n : PROCESS
BEGIN
WAIT UNTIL RISING_EDGE(clk_ddr(1));
ddr_d_in_n <= VD;
ddr_d_in_n <= vd;
END PROCESS ddr_data_in_n;
--
ddr_data_in_p : PROCESS
BEGIN
WAIT UNTIL RISING_EDGE(clk_ddr(1));
vdp_in(31 DOWNTO 0) <= VD;
vdp_in(31 DOWNTO 0) <= vd;
vdp_in(63 DOWNTO 32) <= ddr_d_in_n;
END PROCESS ddr_data_in_p;
@@ -790,32 +792,32 @@ BEGIN
I_DDR_CTRL: DDR_CTRL
PORT MAP(
CLK_MAIN => CLK_MAIN,
clk_main => clk_main,
ddr_sync_66m => ddr_sync_66m,
fb_adr => fb_adr,
FB_CS1_n => FB_CSn(1),
FB_OE_n => FB_OEn,
FB_SIZE0 => FB_SIZE(0),
FB_SIZE1 => FB_SIZE(1),
FB_ALE => FB_ALE,
FB_WRn => FB_WRn,
fb_cs1_n => FB_CSn(1),
fb_oe_n => FB_OEn,
fb_size0 => fb_size(0),
fb_size1 => fb_size(1),
fb_ale => fb_ale,
fb_wr_n => fb_wr_n,
blitter_adr => blitter_adr,
blitter_sig => blitter_sig,
blitter_wr => blitter_wr,
SR_BLITTER_DACK => blitter_dack_sr,
BA => BA,
VA => VA,
ba => ba,
va => va,
fb_le => fb_le,
CLK_33M => CLK_33M,
VRASn => VRASn,
vrASn => vrASn,
VcaSn => VcaSn,
VWEn => VWEn,
VCSn => VCSn,
fifo_clr => fifo_clr,
DDRCLK0 => clk_ddr(0),
video_control_register => video_ram_ctr,
VCKE => VCKE,
DATA_IN => FB_AD,
vcke => vcke,
DATA_IN => fb_ad,
DATA_OUT => data_out_ddr_ctrl,
DATA_EN_H => data_en_h_ddr_ctrl,
DATA_EN_L => data_en_l_ddr_ctrl,
@@ -834,16 +836,16 @@ BEGIN
-- I_BLITTER: FBEE_BLITTER
-- PORT MAP(
-- resetn => reset_n,
-- CLK_MAIN => CLK_MAIN,
-- clk_main => clk_main,
-- clk_ddr0 => clk_ddr(0),
-- fb_adr => fb_adr,
-- FB_ALE => FB_ALE,
-- FB_SIZE1 => FB_SIZE(1),
-- FB_SIZE0 => FB_SIZE(0),
-- fb_ale => fb_ale,
-- fb_size1 => fb_size(1),
-- fb_size0 => fb_size(0),
-- FB_CSn => FB_CSn,
-- FB_OEn => FB_OEn,
-- FB_WRn => FB_WRn,
-- DATA_IN => FB_AD,
-- fb_wr_n => fb_wr_n,
-- DATA_IN => fb_ad,
-- DATA_OUT => data_out_blitter,
-- DATA_EN => data_en_blitter,
-- blitter_adr => blitter_adr,
@@ -859,29 +861,29 @@ BEGIN
I_VIDEOSYSTEM: VIDEO_SYSTEM
PORT MAP(
CLK_MAIN => CLK_MAIN,
clk_main => clk_main,
CLK_33M => CLK_33M,
CLK_25M => clk_25m_i,
clk_video => clk_video,
clk_ddr3 => clk_ddr(3),
clk_ddr2 => clk_ddr(2),
clk_ddr0 => clk_ddr(0),
CLK_PIXEL => clk_pixel_i,
clk_pixel => clk_pixel_i,
vr_d => vr_d,
vr_busy => vr_busy,
fb_adr => fb_adr,
FB_AD_IN => FB_AD,
FB_AD_OUT => fb_ad_out_video,
FB_AD_EN_31_16 => fb_ad_en_31_16_video,
FB_AD_EN_15_0 => fb_ad_en_15_0_video,
FB_ALE => FB_ALE,
fb_ad_in => fb_ad,
fb_ad_out => fb_ad_out_video,
fb_ad_en_31_16 => fb_ad_en_31_16_video,
fb_ad_en_15_0 => fb_ad_en_15_0_video,
fb_ale => fb_ale,
FB_CSn => FB_CSn,
FB_OEn => FB_OEn,
FB_WRn => FB_WRn,
FB_SIZE1 => FB_SIZE(1),
FB_SIZE0 => FB_SIZE(0),
fb_wr_n => FB_WR_n,
fb_size1 => fb_size(1),
fb_size0 => fb_size(0),
vdp_in => vdp_in,
@@ -889,15 +891,15 @@ BEGIN
vr_wr => vr_wr,
video_reconfig => video_reconfig,
RED => VR,
GREEN => VG,
BLUE => VB,
RED => vr,
GREEN => vg,
BLUE => vb,
VSYNC => vsync_i,
HSYNC => hsync_i,
SYNCn => SYNCn,
BLANKn => blank_i_n,
PD_VGAn => PD_VGAn,
PD_vgAn => PD_vgAn,
video_mod_ta => video_mod_ta,
vd_vz => vd_vz,
@@ -907,30 +909,30 @@ BEGIN
vdm_sel => vdm_sel,
video_ram_ctr => video_ram_ctr,
fifo_clr => fifo_clr,
VDM => VDM,
vdm => vdm,
blitter_on => blitter_on,
blitter_run => blitter_run
);
-- I_INTHANDLER: INTHANDLER
-- PORT MAP(
-- CLK_MAIN => CLK_MAIN,
-- clk_main => clk_main,
-- resetn => reset_n,
-- fb_adr => fb_adr,
-- FB_CSn => FB_CSn(2 DOWNTO 1),
-- FB_OEn => FB_OEn,
-- FB_SIZE0 => FB_SIZE(0),
-- FB_SIZE1 => FB_SIZE(1),
-- FB_WRn => FB_WRn,
-- FB_AD_IN => FB_AD,
-- FB_AD_OUT => fb_ad_out_ih,
-- FB_AD_EN_31_24 => fb_ad_en_31_24_ih,
-- FB_AD_EN_23_16 => fb_ad_en_23_16_ih,
-- FB_AD_EN_15_8 => fb_ad_en_15_8_ih,
-- FB_AD_EN_7_0 => fb_ad_en_7_0_ih,
-- PIC_INT => PIC_INT,
-- E0_INT => E0_INT,
-- DVI_INT => DVI_INT,
-- fb_size0 => fb_size(0),
-- fb_size1 => fb_size(1),
-- fb_wr_n => fb_wr_n,
-- fb_ad_IN => fb_ad,
-- fb_ad_OUT => fb_ad_out_ih,
-- fb_ad_EN_31_24 => fb_ad_en_31_24_ih,
-- fb_ad_EN_23_16 => fb_ad_en_23_16_ih,
-- fb_ad_EN_15_8 => fb_ad_en_15_8_ih,
-- fb_ad_EN_7_0 => fb_ad_en_7_0_ih,
-- pic_int => pic_int,
-- e0_int => e0_int,
-- dvi_int => dvi_int,
-- PCI_INTAn => PCI_INTAn,
-- PCI_INTBn => PCI_INTBn,
-- PCI_INTCn => PCI_INTCn,
@@ -943,27 +945,27 @@ BEGIN
-- IRQn => IRQn,
-- int_handler_ta => int_handler_ta,
-- fbee_conf => fbee_conf,
-- TIN0 => TIN0
-- tin0 => tin0
-- );
-- I_DMA: FBEE_DMA
-- PORT MAP(
-- RESET => NOT reset_n,
-- CLK_MAIN => CLK_MAIN,
-- clk_main => clk_main,
-- clk_fdc => clk_fdc,
--
-- fb_adr => fb_adr(26 DOWNTO 0),
-- FB_ALE => FB_ALE,
-- FB_SIZE => FB_SIZE,
-- fb_ale => fb_ale,
-- fb_size => fb_size,
-- FB_CSn => FB_CSn(2 DOWNTO 1),
-- FB_OEn => FB_OEn,
-- FB_WRn => FB_WRn,
-- FB_AD_IN => FB_AD,
-- FB_AD_OUT => fb_ad_out_dma,
-- FB_AD_EN_31_24 => fb_ad_en_31_24_dma,
-- FB_AD_EN_23_16 => fb_ad_en_23_16_dma,
-- FB_AD_EN_15_8 => fb_ad_en_15_8_dma,
-- FB_AD_EN_7_0 => fb_ad_en_7_0_dma,
-- fb_wr_n => fb_wr_n,
-- fb_ad_IN => fb_ad,
-- fb_ad_OUT => fb_ad_out_dma,
-- fb_ad_EN_31_24 => fb_ad_en_31_24_dma,
-- fb_ad_EN_23_16 => fb_ad_en_23_16_dma,
-- fb_ad_EN_15_8 => fb_ad_en_15_8_dma,
-- fb_ad_EN_7_0 => fb_ad_en_7_0_dma,
--
-- ACSI_DIR => ACSI_DIR,
-- ACSI_D_IN => ACSI_D,
@@ -995,18 +997,18 @@ BEGIN
-- fdc_csn => fdc_cs_n,
-- fdc_wrn => fdc_wr_n,
-- fd_int => fd_int,
-- IDE_INT => IDE_INT,
-- ide_int => ide_int,
-- dma_cs => dma_cs
-- );
-- I_IDE_CF_SD_ROM: IDE_CF_SD_ROM
-- PORT MAP(
-- RESET => NOT reset_n,
-- CLK_MAIN => CLK_MAIN,
-- clk_main => clk_main,
--
-- fb_adr => fb_adr(19 DOWNTO 5),
-- FB_CS1n => FB_CSn(1),
-- FB_WRn => FB_WRn,
-- fb_wr_n => fb_wr_n,
-- fb_b0 => fb_b0,
-- fb_b1 => fb_b1,
--
@@ -1028,7 +1030,7 @@ BEGIN
-- SD_caRD_DETECT => SD_caRD_DETECT,
-- SD_WP => SD_WP,
--
-- IDE_RDY => IDE_RDY,
-- ide_rdy => ide_rdy,
-- IDE_WRn => IDE_WRn,
-- IDE_RDn => IDE_RDn,
-- IDE_CSn => IDE_CSn,
@@ -1045,13 +1047,13 @@ BEGIN
-- I_DSP: DSP
-- PORT MAP(
-- CLK_33M => CLK_33M,
-- CLK_MAIN => CLK_MAIN,
-- clk_main => clk_main,
-- FB_OEn => FB_OEn,
-- FB_WRn => FB_WRn,
-- fb_wr_n => fb_wr_n,
-- FB_CS1n => FB_CSn(1),
-- FB_CS2n => FB_CSn(2),
-- FB_SIZE0 => FB_SIZE(0),
-- FB_SIZE1 => FB_SIZE(1),
-- fb_size0 => fb_size(0),
-- fb_size1 => fb_size(1),
-- FB_BURSTn => FB_BURSTn,
-- fb_adr => fb_adr,
-- resetn => reset_n,
@@ -1063,9 +1065,9 @@ BEGIN
-- SROEn => DSP_SROEn,
-- dsp_int => dsp_int,
-- dsp_ta => dsp_ta,
-- FB_AD_IN => FB_AD,
-- FB_AD_OUT => fb_ad_out_dsp,
-- FB_AD_EN => fb_ad_en_dsp,
-- fb_ad_IN => fb_ad,
-- fb_ad_OUT => fb_ad_out_dsp,
-- fb_ad_EN => fb_ad_en_dsp,
-- IO_IN => DSP_IO,
-- IO_OUT => dsp_io_out,
-- IO_EN => dsp_io_en,
@@ -1076,7 +1078,7 @@ BEGIN
-- I_SOUND: WF2149IP_TOP_SOC
-- PORT MAP(
-- SYS_CLK => CLK_MAIN,
-- SYS_CLK => clk_main,
-- resetn => reset_n,
--
-- WAV_CLK => clk_2m0,
@@ -1088,7 +1090,7 @@ BEGIN
--
-- A9n => '0',
-- A8 => '1',
-- DA_IN => FB_AD(31 DOWNTO 24),
-- DA_IN => fb_ad(31 DOWNTO 24),
-- DA_OUT => da_out_x,
--
-- IO_A_IN => x"00", -- All port pINs are dedicated OUTputs.
@@ -1097,7 +1099,7 @@ BEGIN
-- IO_A_OUT(5) => LP_STR,
-- IO_A_OUT(4) => DTR,
-- IO_A_OUT(3) => RTS,
-- IO_A_OUT(2) => RESERVED_1,
-- IO_A_OUT(2) => reserved_1,
-- IO_A_OUT(1) => DSA_D,
-- IO_A_OUT(0) => FDD_SDSELn,
-- -- IO_A_EN => TOUT0n, -- Not required.
@@ -1113,16 +1115,16 @@ BEGIN
I_MFP: WF68901IP_TOP_SOC
PORT MAP(
-- System control:
CLK => CLK_MAIN,
CLK => clk_main,
resetn => reset_n,
-- Asynchronous bus control:
DSn => NOT lds,
CSn => NOT mfp_cs,
RWn => FB_WRn,
RWn => fb_wr_n,
DTACKn => dtack_out_mfp_n,
-- Data and Adresses:
RS => fb_adr(5 DOWNTO 1),
DATA_IN => FB_AD(23 DOWNTO 16),
DATA_IN => fb_ad(23 DOWNTO 16),
DATA_OUT => data_out_mfp,
-- DATA_EN => DATA_EN_MFP, -- Not used.
GPIP_IN(7) => NOT drq11_dma,
@@ -1161,17 +1163,17 @@ BEGIN
-- I_ACIA_MIDI: WF6850IP_TOP_SOC
-- PORT MAP(
-- CLK => CLK_MAIN,
-- CLK => clk_main,
-- resetn => reset_n,
--
-- CS2n => '0',
-- CS1 => fb_adr(2),
-- CS0 => acia_cs,
-- E => acia_cs,
-- RWn => FB_WRN,
-- RWn => fb_wr_n,
-- RS => fb_adr(1),
--
-- DATA_IN => FB_AD(31 DOWNTO 24),
-- DATA_IN => fb_ad(31 DOWNTO 24),
-- DATA_OUT => data_out_acia_iI,
-- -- DATA_EN => -- Not used.
--
@@ -1188,17 +1190,17 @@ BEGIN
I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
PORT MAP(
CLK => CLK_MAIN,
CLK => clk_main,
resetn => reset_n,
CS2n => fb_adr(2),
CS1 => '1',
CS0 => acia_cs,
E => acia_cs,
RWn => FB_WRn,
RWn => fb_wr_n,
RS => fb_adr(1),
DATA_IN => FB_AD(31 DOWNTO 24),
DATA_IN => fb_ad(31 DOWNTO 24),
DATA_OUT => data_out_acia_i,
-- DATA_EN => Not used.
@@ -1295,17 +1297,17 @@ BEGIN
-- I_RTC: RTC
-- PORT MAP(
-- CLK_MAIN => CLK_MAIN,
-- clk_main => clk_main,
-- fb_adr => fb_adr(19 DOWNTO 0),
-- FB_CS1n => FB_CSn(1),
-- FB_SIZE0 => FB_SIZE(0),
-- FB_SIZE1 => FB_SIZE(1),
-- FB_WRn => FB_WRn,
-- fb_size0 => fb_size(0),
-- fb_size1 => fb_size(1),
-- fb_wr_n => fb_wr_n,
-- FB_OEn => FB_OEn,
-- FB_AD_IN => FB_AD(23 DOWNTO 16),
-- FB_AD_OUT => fb_ad_out_rtc,
-- FB_AD_EN_23_16 => fb_ad_en_rtc,
-- PIC_INT => PIC_INT
-- fb_ad_IN => fb_ad(23 DOWNTO 16),
-- fb_ad_OUT => fb_ad_out_rtc,
-- fb_ad_EN_23_16 => fb_ad_en_rtc,
-- pic_int => pic_int
-- );
END ARCHITECTURE;

20
vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd
View File

@@ -66,7 +66,7 @@ package firebee_pkg is
FB_ALE : in std_logic;
FB_CSn : in std_logic_vector(3 downto 1);
FB_OEn : in std_logic;
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
FB_SIZE1 : in std_logic;
FB_SIZE0 : in std_logic;
@@ -106,7 +106,7 @@ package firebee_pkg is
port(
CLK_MAIN : in std_logic;
FB_CSn : in std_logic_vector(2 downto 1);
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
FB_OEn : in std_logic;
FB_SIZE : in std_logic_vector(1 downto 0);
FB_ADR : in std_logic_vector(31 downto 0);
@@ -159,12 +159,12 @@ package firebee_pkg is
CLK_MAIN : in std_logic;
DDR_SYNC_66M : in std_logic;
FB_ADR : in std_logic_vector(31 downto 0);
FB_CS1_n : in std_logic;
fb_cs1_n : in std_logic;
FB_OE_n : in std_logic;
FB_SIZE0 : in std_logic;
FB_SIZE1 : in std_logic;
FB_ALE : in std_logic;
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
FIFO_CLR : in std_logic;
video_control_register : in std_logic_vector(15 downto 0);
BLITTER_ADR : in std_logic_vector(31 downto 0);
@@ -206,7 +206,7 @@ package firebee_pkg is
FB_CSn : in std_logic_vector(2 downto 1);
FB_SIZE0 : in std_logic;
FB_SIZE1 : in std_logic;
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
FB_OEn : in std_logic;
FB_AD_IN : in std_logic_vector(31 downto 0);
FB_AD_OUT : out std_logic_vector(31 downto 0);
@@ -244,7 +244,7 @@ package firebee_pkg is
FB_SIZE : in std_logic_vector(1 downto 0);
FB_CSn : in std_logic_vector(2 downto 1);
FB_OEn : in std_logic;
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
FB_AD_IN : in std_logic_vector(31 downto 0);
FB_AD_OUT : out std_logic_vector(31 downto 0);
FB_AD_EN_31_24 : out std_logic;
@@ -294,7 +294,7 @@ package firebee_pkg is
FB_ADR : in std_logic_vector(19 downto 5);
FB_CS1n : in std_logic;
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
FB_B0 : in std_logic;
FB_B1 : in std_logic;
@@ -342,7 +342,7 @@ package firebee_pkg is
FB_SIZE0 : in std_logic;
FB_CSn : in std_logic_vector(3 downto 1);
FB_OEn : in std_logic;
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_EN : out std_logic;
@@ -363,7 +363,7 @@ package firebee_pkg is
CLK_33M : in std_logic;
CLK_MAIN : in std_logic;
FB_OEn : in std_logic;
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
FB_CS1n : in std_logic;
FB_CS2n : in std_logic;
FB_SIZE0 : in std_logic;
@@ -567,7 +567,7 @@ package firebee_pkg is
FB_CS1n : in std_logic;
FB_SIZE0 : in std_logic;
FB_SIZE1 : in std_logic;
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
FB_OEn : in std_logic;
FB_AD_IN : in std_logic_vector(23 downto 16);
FB_AD_OUT : out std_logic_vector(23 downto 16);

152
vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd
View File

@@ -50,7 +50,7 @@ entity VIDEO_CTRL is
port(
CLK_MAIN : in std_logic;
FB_CSn : in std_logic_vector(2 downto 1);
FB_WRn : in std_logic;
fb_wr_n : in std_logic;
FB_OEn : in std_logic;
FB_SIZE : in std_logic_vector(1 downto 0);
FB_ADR : in std_logic_vector(31 downto 0);
@@ -272,7 +272,7 @@ begin
-- Firebee CLUT:
FBEE_CLUT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 10) = "000000000000000000" else '0'; -- 0-3FF/1024
FBEE_CLUT_RD <= '1' when FBEE_CLUT_CS = '1' and FB_OEn = '0' else '0';
FBEE_CLUT_WR <= FB_B when FBEE_CLUT_CS = '1' and FB_WRn = '0' else x"0";
FBEE_CLUT_WR <= FB_B when FBEE_CLUT_CS = '1' and fb_wr_n = '0' else x"0";
P_CLUT_TA : process
begin
@@ -292,13 +292,13 @@ begin
FALCON_CLUT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 10) = "1111100110" else '0'; -- $F9800/$400
FALCON_CLUT_RDH <= '1' when FALCON_CLUT_CS = '1' and FB_OEn = '0' and FB_ADR(1) = '0' else '0'; -- High word.
FALCON_CLUT_RDL <= '1' when FALCON_CLUT_CS = '1' and FB_OEn = '0' and FB_ADR(1) = '1' else '0'; -- Low word.
FALCON_CLUT_WR(1 downto 0) <= FB_16B when FB_ADR(1) = '0' and FALCON_CLUT_CS = '1' and FB_WRn = '0' else "00";
FALCON_CLUT_WR(3 downto 2) <= FB_16B when FB_ADR(1) = '1' and FALCON_CLUT_CS = '1' and FB_WRn = '0' else "00";
FALCON_CLUT_WR(1 downto 0) <= FB_16B when FB_ADR(1) = '0' and FALCON_CLUT_CS = '1' and fb_wr_n = '0' else "00";
FALCON_CLUT_WR(3 downto 2) <= FB_16B when FB_ADR(1) = '1' and FALCON_CLUT_CS = '1' and fb_wr_n = '0' else "00";
-- ST CLUT:
ST_CLUT_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 5) = "111110000010010" else '0'; -- $F8240/$2
CLUT_ST_RD <= '1' when ST_CLUT_CS = '1' and FB_OEn = '0' else '0';
CLUT_ST_WR <= FB_16B when ST_CLUT_CS = '1' and FB_WRn = '0' else "00";
CLUT_ST_WR <= FB_16B when ST_CLUT_CS = '1' and fb_wr_n = '0' else "00";
ST_SHIFT_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100110000" else '0'; -- $F8260/$2.
FALCON_SHIFT_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = "1111100000100110011" else '0'; -- $F8266/$2.
@@ -311,13 +311,13 @@ begin
P_VIDEO_CONTROL : process
begin
wait until rising_edge(CLK_MAIN);
if ST_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(0) = '1' then
if ST_SHIFT_MODE_CS = '1' and fb_wr_n = '0' and FB_B(0) = '1' then
ST_SHIFT_MODE <= DATA_IN(25 downto 24);
end if;
if FALCON_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(2) = '1' then
if FALCON_SHIFT_MODE_CS = '1' and fb_wr_n = '0' and FB_B(2) = '1' then
FALCON_SHIFT_MODE(10 downto 8) <= DATA_IN(26 downto 24);
elsif FALCON_SHIFT_MODE_CS = '1' and FB_WRn = '0' and FB_B(3) = '1' then
elsif FALCON_SHIFT_MODE_CS = '1' and fb_wr_n = '0' and FB_B(3) = '1' then
FALCON_SHIFT_MODE(7 downto 0) <= DATA_IN(23 downto 16);
end if;
@@ -327,72 +327,72 @@ begin
-- Bit 6 = FALCON SHIFT MODE, 7 = ST SHIFT MODE, 9..8 = VCLK frequency,
-- Bit 15 = SYNC ALLOWED, 31..16 = VIDEO_RAM_CTR,
-- Bit 25 = RANDFARBE EINSCHALTEN, 26 = STANDARD ATARI SYNCS.
if FBEE_VCTR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if FBEE_VCTR_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
FBEE_VCTR(31 downto 24) <= DATA_IN(31 downto 24);
elsif FBEE_VCTR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif FBEE_VCTR_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
FBEE_VCTR(23 downto 16) <= DATA_IN(23 downto 16);
elsif FBEE_VCTR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
elsif FBEE_VCTR_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
FBEE_VCTR(15 downto 8) <= DATA_IN(15 downto 8);
elsif FBEE_VCTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif FBEE_VCTR_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
FBEE_VCTR(5 downto 0) <= DATA_IN(5 downto 0);
end if;
-- ST or Falcon shift mode: assert when X..shift register:
if FALCON_SHIFT_MODE_CS = '1' and FB_WRn = '0' then
FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
if FALCON_SHIFT_MODE_CS = '1' and fb_wr_n = '0' then
FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not fb_wr_n and not FBEE_VIDEO_ON;
FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not fb_wr_n and not FBEE_VIDEO_ON;
end if;
if ST_SHIFT_MODE_CS = '1' and FB_WRn = '0' then
FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
if ST_SHIFT_MODE_CS = '1' and fb_wr_n = '0' then
FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not fb_wr_n and not FBEE_VIDEO_ON;
FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not fb_wr_n and not FBEE_VIDEO_ON;
end if;
if FBEE_VCTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' and DATA_IN(0) = '1' then
FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not FB_WRn and not FBEE_VIDEO_ON;
if FBEE_VCTR_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' and DATA_IN(0) = '1' then
FBEE_VCTR(7) <= FALCON_SHIFT_MODE_CS and not fb_wr_n and not FBEE_VIDEO_ON;
FBEE_VCTR(6) <= ST_SHIFT_MODE_CS and not fb_wr_n and not FBEE_VIDEO_ON;
end if;
-- ATARI ST mode
-- Horizontal timing 640x480:
if ATARI_HH_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if ATARI_HH_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
ATARI_HH(31 downto 24) <= DATA_IN(31 downto 24);
elsif ATARI_HH_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif ATARI_HH_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
ATARI_HH(23 downto 16) <= DATA_IN(23 downto 16);
elsif ATARI_HH_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
elsif ATARI_HH_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
ATARI_HH(15 downto 8) <= DATA_IN(15 downto 8);
elsif ATARI_HH_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif ATARI_HH_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
ATARI_HH(7 downto 0) <= DATA_IN(7 downto 0);
end if;
-- Vertical timing 640x480:
if ATARI_VH_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if ATARI_VH_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
ATARI_VH(31 downto 24) <= DATA_IN(31 downto 24);
elsif ATARI_VH_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif ATARI_VH_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
ATARI_VH(23 downto 16) <= DATA_IN(23 downto 16);
elsif ATARI_VH_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
elsif ATARI_VH_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
ATARI_VH(15 downto 8) <= DATA_IN(15 downto 8);
elsif ATARI_VH_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif ATARI_VH_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
ATARI_VH(7 downto 0) <= DATA_IN(7 downto 0);
end if;
-- Horizontal timing 320x240:
if ATARI_HL_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if ATARI_HL_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
ATARI_HL(31 downto 24) <= DATA_IN(31 downto 24);
elsif ATARI_HL_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif ATARI_HL_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
ATARI_HL(23 downto 16) <= DATA_IN(23 downto 16);
elsif ATARI_HL_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
elsif ATARI_HL_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
ATARI_HL(15 downto 8) <= DATA_IN(15 downto 8);
elsif ATARI_HL_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif ATARI_HL_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
ATARI_HL(7 downto 0) <= DATA_IN(7 downto 0);
end if;
-- Vertical timing 320x240:
if ATARI_VL_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if ATARI_VL_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
ATARI_VL(31 downto 24) <= DATA_IN(31 downto 24);
elsif ATARI_VL_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif ATARI_VL_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
ATARI_VL(23 downto 16) <= DATA_IN(23 downto 16);
elsif ATARI_VL_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
elsif ATARI_VL_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
ATARI_VL(15 downto 8) <= DATA_IN(15 downto 8);
elsif ATARI_VL_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif ATARI_VL_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
ATARI_VL(7 downto 0) <= DATA_IN(7 downto 0);
end if;
end process P_VIDEO_CONTROL;
@@ -422,14 +422,14 @@ begin
-- VIDEO PLL config and reconfig:
VIDEO_PLL_CONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_B(1) = '1' and FB_ADR(27 downto 9) = "0000000000000000011" else '0'; -- $(F)000'0600-7FF -> 6/2 word and long only.
VIDEO_PLL_RECONFIG_CS <= '1' when FB_CSn(2) = '0' and FB_B(0) = '1' and FB_ADR(27 downto 0) = x"0000800" else '0'; -- $(F)000'0800.
VR_RD_I <= '1' when VIDEO_PLL_CONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' else '0';
VR_RD_I <= '1' when VIDEO_PLL_CONFIG_CS = '1' and fb_wr_n = '0' and VR_BUSY = '0' else '0';
P_VIDEO_CONFIG: process
variable LOCK : boolean;
begin
wait until rising_edge(CLK_MAIN);
if VIDEO_PLL_CONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' and VR_WR_I = '0' then
if VIDEO_PLL_CONFIG_CS = '1' and fb_wr_n = '0' and VR_BUSY = '0' and VR_WR_I = '0' then
VR_WR_I <= '1'; -- This is a strobe.
else
VR_WR_I <= '0';
@@ -443,10 +443,10 @@ begin
VR_FRQ <= DATA_IN(23 downto 16);
end if;
if VIDEO_PLL_RECONFIG_CS = '1' and FB_WRn = '0' and VR_BUSY = '0' and LOCK = false then
if VIDEO_PLL_RECONFIG_CS = '1' and fb_wr_n = '0' and VR_BUSY = '0' and LOCK = false then
VIDEO_RECONFIG_I <= '1'; -- This is a strobe.
LOCK := true;
elsif VIDEO_PLL_RECONFIG_CS = '0' or FB_WRn = '1' or VR_BUSY = '1' then
elsif VIDEO_PLL_RECONFIG_CS = '0' or fb_wr_n = '1' or VR_BUSY = '1' then
VIDEO_RECONFIG_I <= '0';
LOCK := false;
else
@@ -490,128 +490,128 @@ begin
wait until rising_edge(CLK_MAIN);
-- Colour of video borders
if CCR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
if CCR_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
CCR_I(23 downto 16) <= DATA_IN(23 downto 16);
elsif CCR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
elsif CCR_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
CCR_I(15 downto 8) <= DATA_IN(15 downto 8);
elsif CCR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif CCR_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
CCR_I(7 downto 0) <= DATA_IN(7 downto 0);
end if;
-- SYS CTRL:
if SYS_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
if SYS_CTR_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
SYS_CTR <= DATA_IN(22 downto 16);
end if;
--VDL_LOF:
if VDL_LOF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
if VDL_LOF_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
VDL_LOF(15 downto 8) <= DATA_IN(31 downto 24);
elsif VDL_LOF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif VDL_LOF_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
VDL_LOF(7 downto 0) <= DATA_IN(23 downto 16);
end if;
--VDL_LWD
if VDL_LWD_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if VDL_LWD_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
VDL_LWD(15 downto 8) <= DATA_IN(31 downto 24);
elsif VDL_LWD_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif VDL_LWD_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
VDL_LWD(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- Horizontal:
-- VDL_HHT:
if VDL_HHT_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
if VDL_HHT_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
VDL_HHT(11 downto 8) <= DATA_IN(27 downto 24);
elsif VDL_HHT_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif VDL_HHT_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
VDL_HHT(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_HBE:
if VDL_HBE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
if VDL_HBE_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
VDL_HBE(11 downto 8) <= DATA_IN(27 downto 24);
elsif VDL_HBE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif VDL_HBE_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
VDL_HBE(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_HDB:
if VDL_HDB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if VDL_HDB_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
VDL_HDB(11 downto 8) <= DATA_IN(27 downto 24);
elsif VDL_HDB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif VDL_HDB_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
VDL_HDB(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_HDE:
if VDL_HDE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
if VDL_HDE_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
VDL_HDE(11 downto 8) <= DATA_IN(27 downto 24);
elsif VDL_HDE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif VDL_HDE_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
VDL_HDE(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_HBB:
if VDL_HBB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if VDL_HBB_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
VDL_HBB(11 downto 8) <= DATA_IN(27 downto 24);
elsif VDL_HBB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif VDL_HBB_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
VDL_HBB(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_HSS:
if VDL_HSS_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if VDL_HSS_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
VDL_HSS(11 downto 8) <= DATA_IN(27 downto 24);
elsif VDL_HSS_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif VDL_HSS_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
VDL_HSS(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- Vertical:
-- VDL_VBE:
if VDL_VBE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
if VDL_VBE_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
VDL_VBE(10 downto 8) <= DATA_IN(26 downto 24);
elsif VDL_VBE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif VDL_VBE_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
VDL_VBE(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_VDB:
if VDL_VDB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if VDL_VDB_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
VDL_VDB(10 downto 8) <= DATA_IN(26 downto 24);
elsif VDL_VDB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif VDL_VDB_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
VDL_VDB(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_VDE:
if VDL_VDE_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
if VDL_VDE_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
VDL_VDE(10 downto 8) <= DATA_IN(26 downto 24);
elsif VDL_VDE_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif VDL_VDE_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
VDL_VDE(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_VBB:
if VDL_VBB_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if VDL_VBB_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
VDL_VBB(10 downto 8) <= DATA_IN(26 downto 24);
elsif VDL_VBB_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif VDL_VBB_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
VDL_VBB(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_VSS
if VDL_VSS_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if VDL_VSS_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
VDL_VSS(10 downto 8) <= DATA_IN(26 downto 24);
elsif VDL_VSS_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif VDL_VSS_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
VDL_VSS(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_VFT
if VDL_VFT_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
if VDL_VFT_CS = '1' and FB_B(2) = '1' and fb_wr_n = '0' then
VDL_VFT(10 downto 8) <= DATA_IN(26 downto 24);
elsif VDL_VFT_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
elsif VDL_VFT_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
VDL_VFT(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_VCT(2): 1 = 32MHz CLK_PIXEL, 0 = 25MHZ; VDL_VCT(0): 1 = linedoubling.
if VDL_VCT_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
if VDL_VCT_CS = '1' and FB_B(0) = '1' and fb_wr_n = '0' then
VDL_VCT(8) <= DATA_IN(24);
elsif VDL_VCT_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
elsif VDL_VCT_CS = '1' and FB_B(1) = '1' and fb_wr_n = '0' then
VDL_VCT(7 downto 0) <= DATA_IN(23 downto 16);
end if;
-- VDL_VMD(2): 1 = CLK_PIXEL/2.
if VDL_VMD_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
if VDL_VMD_CS = '1' and FB_B(3) = '1' and fb_wr_n = '0' then
VDL_VMD <= DATA_IN(19 downto 16);
end if;
end process P_MISC_CTRL;

4
vhdl/rtl/vhdl/Video/Video_Top.vhd
View File

@@ -72,7 +72,7 @@ ENTITY VIDEO_SYSTEM IS
FB_ALE : IN STD_LOGIC;
FB_CSn : IN STD_LOGIC_VECTOR(3 DOWNTO 1);
FB_OEn : IN STD_LOGIC;
FB_WRn : IN STD_LOGIC;
fb_wr_n : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
@@ -502,7 +502,7 @@ BEGIN
CLK_MAIN => CLK_MAIN,
FB_CSn(1) => FB_CSn(1),
FB_CSn(2) => FB_CSn(2),
FB_WRn => FB_WRn,
fb_wr_n => fb_wr_n,
FB_OEn => FB_OEn,
FB_SIZE(0) => FB_SIZE0,
FB_SIZE(1) => FB_SIZE1,

226
vhdl/rtl/vhdl/WF_UART6850_IP/wf6850ip_top_soc.vhd
View File

@@ -23,17 +23,17 @@
---- Copyright (C) 2006 - 2011 Wolfgang Foerster ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- restriction provided that this copyright statement IS not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- This source file IS free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- This source IS distributed IN the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
@@ -59,131 +59,131 @@
-- Introduced a minor RTSn correction.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
entity WF6850IP_TOP_SOC is
port (
CLK : in std_logic;
RESETn : in std_logic;
ENTITY WF6850IP_TOP_SOC IS
PORT (
CLK : IN STD_LOGIC;
RESETn : IN STD_LOGIC;
CS2n, CS1, CS0 : in std_logic;
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
CS2n, CS1, CS0 : IN STD_LOGIC;
E : IN STD_LOGIC;
RWn : IN STD_LOGIC;
RS : IN STD_LOGIC;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
DATA_EN : OUT STD_LOGIC;
TXCLK : in std_logic;
RXCLK : in std_logic;
RXDATA : in std_logic;
CTSn : in std_logic;
DCDn : in std_logic;
TXCLK : IN STD_LOGIC;
RXCLK : IN STD_LOGIC;
RXDATA : IN STD_LOGIC;
CTSn : IN STD_LOGIC;
DCDn : IN STD_LOGIC;
IRQn : out std_logic;
TXDATA : out std_logic;
RTSn : out std_logic
IRQn : OUT STD_LOGIC;
TXDATA : OUT STD_LOGIC;
RTSn : OUT STD_LOGIC
);
end entity WF6850IP_TOP_SOC;
END ENTITY WF6850IP_TOP_SOC;
architecture STRUCTURE of WF6850IP_TOP_SOC is
component WF6850IP_CTRL_STATUS
port (
CLK : in std_logic;
RESETn : in std_logic;
CS : in std_logic_vector(2 downto 0);
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
RDRF : in std_logic;
TDRE : in std_logic;
DCDn : in std_logic;
CTSn : in std_logic;
FE : in std_logic;
OVR : in std_logic;
PE : in std_logic;
MCLR : out std_logic;
RTSn : out std_logic;
CDS : out std_logic_vector(1 downto 0);
WS : out std_logic_vector(2 downto 0);
TC : out std_logic_vector(1 downto 0);
IRQn : out std_logic
ARCHITECTURE STRUCTURE of WF6850IP_TOP_SOC IS
COMPONENT WF6850IP_CTRL_STATUS
PORT (
CLK : IN STD_LOGIC;
RESETn : IN STD_LOGIC;
CS : IN STD_LOGIC_VECTOR(2 downto 0);
E : IN STD_LOGIC;
RWn : IN STD_LOGIC;
RS : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
DATA_EN : OUT STD_LOGIC;
RDRF : IN STD_LOGIC;
TDRE : IN STD_LOGIC;
DCDn : IN STD_LOGIC;
CTSn : IN STD_LOGIC;
FE : IN STD_LOGIC;
OVR : IN STD_LOGIC;
PE : IN STD_LOGIC;
MCLR : OUT STD_LOGIC;
RTSn : OUT STD_LOGIC;
CDS : OUT STD_LOGIC_VECTOR(1 downto 0);
WS : OUT STD_LOGIC_VECTOR(2 downto 0);
TC : OUT STD_LOGIC_VECTOR(1 downto 0);
IRQn : OUT STD_LOGIC
);
end component;
END COMPONENT;
component WF6850IP_RECEIVE
port (
CLK : in std_logic;
RESETn : in std_logic;
MCLR : in std_logic;
CS : in std_logic_vector(2 downto 0);
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_EN : out std_logic;
WS : in std_logic_vector(2 downto 0);
CDS : in std_logic_vector(1 downto 0);
RXCLK : in std_logic;
RXDATA : in std_logic;
RDRF : out std_logic;
OVR : out std_logic;
PE : out std_logic;
FE : out std_logic
COMPONENT WF6850IP_RECEIVE
PORT (
CLK : IN STD_LOGIC;
RESETn : IN STD_LOGIC;
MCLR : IN STD_LOGIC;
CS : IN STD_LOGIC_VECTOR(2 downto 0);
E : IN STD_LOGIC;
RWn : IN STD_LOGIC;
RS : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
DATA_EN : OUT STD_LOGIC;
WS : IN STD_LOGIC_VECTOR(2 downto 0);
CDS : IN STD_LOGIC_VECTOR(1 downto 0);
RXCLK : IN STD_LOGIC;
RXDATA : IN STD_LOGIC;
RDRF : OUT STD_LOGIC;
OVR : OUT STD_LOGIC;
PE : OUT STD_LOGIC;
FE : OUT STD_LOGIC
);
end component;
END COMPONENT;
component WF6850IP_TRANSMIT
port (
CLK : in std_logic;
RESETn : in std_logic;
MCLR : in std_logic;
CS : in std_logic_vector(2 downto 0);
E : in std_logic;
RWn : in std_logic;
RS : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
CTSn : in std_logic;
TC : in std_logic_vector(1 downto 0);
WS : in std_logic_vector(2 downto 0);
CDS : in std_logic_vector(1 downto 0);
TXCLK : in std_logic;
TDRE : out std_logic;
TXDATA : out std_logic
COMPONENT WF6850IP_TRANSMIT
PORT (
CLK : IN STD_LOGIC;
RESETn : IN STD_LOGIC;
MCLR : IN STD_LOGIC;
CS : IN STD_LOGIC_VECTOR(2 downto 0);
E : IN STD_LOGIC;
RWn : IN STD_LOGIC;
RS : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
CTSn : IN STD_LOGIC;
TC : IN STD_LOGIC_VECTOR(1 downto 0);
WS : IN STD_LOGIC_VECTOR(2 downto 0);
CDS : IN STD_LOGIC_VECTOR(1 downto 0);
TXCLK : IN STD_LOGIC;
TDRE : OUT STD_LOGIC;
TXDATA : OUT STD_LOGIC
);
end component;
END COMPONENT;
signal DATA_IN_I : std_logic_vector(7 downto 0);
signal DATA_RX : std_logic_vector(7 downto 0);
signal DATA_RX_EN : std_logic;
signal DATA_CTRL : std_logic_vector(7 downto 0);
signal DATA_CTRL_EN : std_logic;
signal RDRF_I : std_logic;
signal TDRE_I : std_logic;
signal FE_I : std_logic;
signal OVR_I : std_logic;
signal PE_I : std_logic;
signal MCLR_I : std_logic;
signal CDS_I : std_logic_vector(1 downto 0);
signal WS_I : std_logic_vector(2 downto 0);
signal TC_I : std_logic_vector(1 downto 0);
signal IRQ_In : std_logic;
begin
SIGNAL DATA_IN_I : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL DATA_RX : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL DATA_RX_EN : STD_LOGIC;
SIGNAL DATA_CTRL : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL DATA_CTRL_EN : STD_LOGIC;
SIGNAL RDRF_I : STD_LOGIC;
SIGNAL TDRE_I : STD_LOGIC;
SIGNAL FE_I : STD_LOGIC;
SIGNAL OVR_I : STD_LOGIC;
SIGNAL PE_I : STD_LOGIC;
SIGNAL MCLR_I : STD_LOGIC;
SIGNAL CDS_I : STD_LOGIC_VECTOR(1 downto 0);
SIGNAL WS_I : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL TC_I : STD_LOGIC_VECTOR(1 downto 0);
SIGNAL IRQ_In : STD_LOGIC;
BEGIN
DATA_IN_I <= (DATA_IN);
DATA_EN <= DATA_RX_EN or DATA_CTRL_EN;
DATA_OUT <= (DATA_RX) when DATA_RX_EN = '1' else
(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0');
DATA_OUT <= (DATA_RX) WHEN DATA_RX_EN = '1' ELSE
(DATA_CTRL) WHEN DATA_CTRL_EN = '1' ELSE (others => '0');
IRQn <= '0' when IRQ_In = '0' else '1';
IRQn <= '0' WHEN IRQ_In = '0' ELSE '1';
I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS
port map(
PORT MAP(
CLK => CLK,
RESETn => RESETn,
CS(2) => CS2n,
@@ -211,7 +211,7 @@ begin
);
I_UART_RECEIVE: WF6850IP_RECEIVE
port map (
PORT MAP (
CLK => CLK,
RESETn => RESETn,
MCLR => MCLR_I,
@@ -234,7 +234,7 @@ begin
);
I_UART_TRANSMIT: WF6850IP_TRANSMIT
port map (
PORT MAP (
CLK => CLK,
RESETn => RESETn,
MCLR => MCLR_I,
@@ -253,4 +253,4 @@ begin
TXCLK => TXCLK,
TXDATA => TXDATA
);
end architecture STRUCTURE;
END ARCHITECTURE STRUCTURE;