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new experimental branch with changed MMU behaviour

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This commit is contained in:
Markus Fröschle
2014-09-25 08:00:36 +00:00
parent a2f01a7fa4
commit db847ec588
246 changed files with 117874 additions and 0 deletions
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429
Bas_gcc_mmu/sys/BaS.c Normal file
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/*
* BaS
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2011 - 2012 V. Riviere
* Copyright 2012 M. Froeschle
*/
#include <bas_types.h>
#include "MCF5475.h"
#include "startcf.h"
#include "sysinit.h"
#include "util.h"
#include "cache.h"
#include "bas_printf.h"
#include "bas_string.h"
#include "bas_types.h"
#include "sd_card.h"
#include "wait.h"
#include "diskio.h"
#include "ff.h"
#include "s19reader.h"
#include "mmu.h"
#include "dma.h"
#include "net.h"
#include "eth.h"
#include "nbuf.h"
#include "nif.h"
#include "fec.h"
#include "bootp.h"
#include "interrupts.h"
#include "exceptions.h"
#include "net_timer.h"
//#define BAS_DEBUG
#if defined(BAS_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
/* imported routines */
extern int vec_init();
/* Symbols from the linker script */
extern uint8_t _STRAM_END[];
#define STRAM_END ((uint32_t)_STRAM_END)
extern uint8_t _TOS[];
#define TOS ((uint32_t)_TOS) /* final TOS location */
extern uint8_t _FASTRAM_END[];
#define FASTRAM_END ((uint32_t)_FASTRAM_END)
extern uint8_t _EMUTOS[];
#define EMUTOS ((uint32_t)_EMUTOS) /* where EmuTOS is stored in flash */
extern uint8_t _EMUTOS_SIZE[];
#define EMUTOS_SIZE ((uint32_t)_EMUTOS_SIZE) /* size of EmuTOS, in bytes */
/*
* check if it is possible to transfer data to PIC
*/
static inline bool pic_txready(void)
{
if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
return true;
return false;
}
/*
* check if it is possible to receive data from PIC
*/
static inline bool pic_rxready(void)
{
if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
return true;
return false;
}
void write_pic_byte(uint8_t value)
{
/* Wait until the transmitter is ready or 1000us are passed */
waitfor(1000, pic_txready);
/* Transmit the byte */
*(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
}
uint8_t read_pic_byte(void)
{
/* Wait until a byte has been received or 1000us are passed */
waitfor(1000, pic_rxready);
/* Return the received byte */
return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
}
void pic_init(void)
{
char answer[4] = "OLD";
xprintf("initialize the PIC: ");
/* Send the PIC initialization string */
write_pic_byte('A');
write_pic_byte('C');
write_pic_byte('P');
write_pic_byte('F');
/* Read the 3-char answer string. Should be "OK!". */
answer[0] = read_pic_byte();
answer[1] = read_pic_byte();
answer[2] = read_pic_byte();
answer[3] = '\0';
if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
{
dbg("PIC initialization failed. Already initialized?\r\n");
}
else
{
xprintf("%s\r\n", answer);
}
}
void nvram_init(void)
{
int i;
xprintf("Restore the NVRAM data: ");
/* Request for NVRAM backup data */
write_pic_byte(0x01);
/* Check answer type */
if (read_pic_byte() != 0x81)
{
// FIXME: PIC protocol error
xprintf("FAILED\r\n");
return;
}
/* Restore the NVRAM backup to the FPGA */
for (i = 0; i < 64; i++)
{
uint8_t data = read_pic_byte();
*(volatile uint8_t*)0xffff8961 = i;
*(volatile uint8_t*)0xffff8963 = data;
}
xprintf("finished\r\n");
}
#define KBD_ACIA_CONTROL ((uint8_t *) 0xfffffc00)
#define MIDI_ACIA_CONTROL ((uint8_t *) 0xfffffc04)
#define MFP_INTR_IN_SERVICE_A ((uint8_t *) 0xfffffa0f)
#define MFP_INTR_IN_SERVICE_B ((uint8_t *) 0xfffffa11)
void acia_init()
{
xprintf("init ACIA: ");
/* init ACIA */
* KBD_ACIA_CONTROL = 3; /* master reset */
NOP();
* MIDI_ACIA_CONTROL = 3; /* master reset */
NOP();
* KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
NOP();
* MFP_INTR_IN_SERVICE_A = -1;
NOP();
* MFP_INTR_IN_SERVICE_B = -1;
NOP();
xprintf("finished\r\n");
}
/* ACP interrupt controller */
#define FPGA_INTR_CONTRL (volatile uint32_t *) 0xf0010000
#define FPGA_INTR_ENABLE (volatile uint8_t *) 0xf0010004
#define FPGA_INTR_PENDIN (volatile uint32_t *) 0xf0010008
void enable_coldfire_interrupts()
{
xprintf("enable interrupts: ");
#if defined(MACHINE_FIREBEE)
*FPGA_INTR_CONTRL = 0L; /* disable all interrupts */
#endif /* MACHINE_FIREBEE */
MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */
#if defined(MACHINE_FIREBEE)
/*
* TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
* access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
*/
MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */
MCF_GPT_GMS_IEN |
MCF_GPT_GMS_TMS(1);
/* route GPT0 interrupt on interrupt controller */
MCF_INTC_ICR62 = 0x3f; /* interrupt level 7, interrupt priority 7 */
*FPGA_INTR_ENABLE = 0xfe; /* enable int 1-7 */
MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
#endif
xprintf("finished\r\n");
}
void disable_coldfire_interrupts()
{
#if defined(MACHINE_FIREBEE)
*FPGA_INTR_ENABLE = 0; /* disable all interrupts */
#endif /* MACHINE_FIREBEE */
MCF_EPORT_EPIER = 0x0;
MCF_EPORT_EPFR = 0x0;
MCF_INTC_IMRL = 0xfffffffe;
MCF_INTC_IMRH = 0xffffffff;
}
NIF nif1;
#if defined(MACHINE_M5484LITE)
NIF nif2;
#endif
/*
* initialize the interrupt handler tables to dispatch interrupt requests from Coldfire devices
*/
void init_isr(void)
{
isr_init(); /* need to call that explicitely, otherwise isr table might be full */
/*
* register the FEC interrupt handler
*/
if (!isr_register_handler(64 + INT_SOURCE_FEC0, fec0_interrupt_handler, NULL, (void *) &nif1))
{
dbg("unable to register isr for FEC0\r\n");
return;
}
/*
* Register the DMA interrupt handler
*/
if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL,NULL))
{
dbg("Error: Unable to register isr for DMA\r\n");
return;
}
dma_irq_enable(5, 3); /* TODO: need to match the FEC driver's specs in MiNT? */
/*
* register the PIC interrupt handler
*/
if (isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL))
{
dbg("Error: unable to register ISR for PSC3\r\n");
return;
}
}
void BaS(void)
{
uint8_t *src;
uint8_t *dst = (uint8_t *) TOS;
#if defined(MACHINE_FIREBEE) /* LITE board has no pic and (currently) no nvram */
pic_init();
nvram_init();
#endif /* MACHINE_FIREBEE */
xprintf("copy EmuTOS: ");
/* copy EMUTOS */
src = (uint8_t *) EMUTOS;
dma_memcpy(dst, src, EMUTOS_SIZE);
xprintf("finished\r\n");
xprintf("initialize MMU: ");
mmu_init();
xprintf("finished\r\n");
xprintf("initialize exception vector table: ");
vec_init();
xprintf("finished\r\n");
xprintf("flush caches: ");
flush_and_invalidate_caches();
xprintf("finished\r\n");
xprintf("enable MMU: ");
MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */
NOP(); /* force pipeline sync */
xprintf("finished\r\n");
#ifdef MACHINE_FIREBEE
xprintf("IDE reset: ");
/* IDE reset */
* (volatile uint8_t *) (0xffff8802 - 2) = 14;
* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
wait(1);
* (volatile uint8_t *) (0xffff8802 - 0) = 0;
xprintf("finished\r\n");
xprintf("enable video: ");
/*
* video setup (25MHz)
*/
* (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba; /* horizontal 640x480 */
* (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a; /* vertical 640x480 */
* (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d; /* horizontal 320x240 */
* (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */
#ifdef _NOT_USED_
// 32MHz
* (volatile uint32_t *) (0xf0000410 + 0) = 0x037002ba; /* horizontal 640x480 */
* (volatile uint32_t *) (0xf0000410 + 4) = 0x020d020a; /* vertical 640x480 */
* (volatile uint32_t *) (0xf0000410 + 8) = 0x02a001e0; /* horizontal 320x240 */
* (volatile uint32_t *) (0xf0000410 + 12) = 0x05a00160; /* vertical 320x230 */
#endif /* _NOT_USED_ */
/* fifo on, refresh on, ddrcs and cke on, video dac on */
* (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
xprintf("finished\r\n");
enable_coldfire_interrupts();
#ifdef _NOT_USED_
screen_init();
/* experimental */
{
int i;
uint32_t *scradr = 0xd00000;
for (i = 0; i < 100; i++)
{
uint32_t *p = scradr;
for (p = scradr; p < scradr + 1024 * 150L; p++)
{
*p = 0xffffffff;
}
for (p = scradr; p < scradr + 1024 * 150L; p++)
{
*p = 0x0;
}
}
}
#endif /* _NOT_USED_ */
#endif /* MACHINE_FIREBEE */
sd_card_init();
/*
* memory setup
*/
memset((void *) 0x400, 0, 0x400);
#if defined(MACHINE_FIREBEE)
/* set Falcon bus control register */
/* sets bit 3 and 6. Both are undefined on an original Falcon? */
* (volatile uint8_t *) 0xffff8007 = 0x48;
#endif /* MACHINE_FIREBEE */
/* ST RAM */
* (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */
* (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */
* (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
* (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
/* TT-RAM */
* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
#if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */
acia_init();
#endif /* MACHINE_FIREBEE */
srec_execute("BASFLASH.S19");
/* Jump into the OS */
typedef void void_func(void);
struct rom_header
{
void *initial_sp;
void_func *initial_pc;
};
xprintf("BaS initialization finished, enable interrupts\r\n");
enable_coldfire_interrupts();
init_isr();
xprintf("call EmuTOS\r\n");
struct rom_header *os_header = (struct rom_header *) TOS;
os_header->initial_pc();
}

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Bas_gcc_mmu/sys/cache.c Normal file
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/*
* cache handling
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2011 - 2012 V. Riviere
* Copyright 2012 M. Froeschle
*
*/
#include "cache.h"
void cacr_set(uint32_t value)
{
extern uint32_t rt_cacr;
rt_cacr = value;
__asm__ __volatile__("movec %0, cacr\n\t"
: /* output */
: "r" (rt_cacr)
: "memory" /* clobbers */);
}
uint32_t cacr_get(void)
{
extern uint32_t rt_cacr;
return rt_cacr;
}
void disable_data_cache(void)
{
flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
}
void disable_instruction_cache(void)
{
flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
}
void enable_data_cache(void)
{
cacr_set(cacr_get() & ~CF_CACR_DCINVA);
}
void flush_and_invalidate_caches(void)
{
__asm__ __volatile__(
" clr.l d0 \n\t"
" clr.l d1 \n\t"
" move.l d0,a0 \n\t"
"cfa_setloop: \n\t"
" cpushl bc,(a0) | flush\n\t"
" lea 0x10(a0),a0 | index+1\n\t"
" addq.l #1,d1 | index+1\n\t"
" cmpi.w #512,d1 | all sets?\n\t"
" bne.s cfa_setloop | no->\n\t"
" clr.l d1 \n\t"
" addq.l #1,d0 \n\t"
" move.l d0,a0 \n\t"
" cmpi.w #4,d0 | all ways?\n\t"
" bne.s cfa_setloop | no->\n\t"
/* input */ :
/* output */ :
/* clobber */ : "cc", "d0", "d1", "a0"
);
}
/*
* flush and invalidate a specific memory region from the instruction cache
*/
void flush_icache_range(void *address, size_t size)
{
uint32_t set;
uint32_t start_set;
uint32_t end_set;
void *endaddr = address + size;
start_set = (uint32_t) address & _ICACHE_SET_MASK;
end_set = (uint32_t) endaddr & _ICACHE_SET_MASK;
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set) /* input parameters */
: "cc" /* clobbered registers */
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_ICACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3)) {
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set])"
: /* output parameters */
: [set] "a" (set)
: "cc"
);
}
}
/*
* flush and invalidate a specific region from the data cache
*/
void flush_dcache_range(void *address, size_t size)
{
unsigned long set;
unsigned long start_set;
unsigned long end_set;
void *endaddr;
endaddr = address + size;
start_set = (uint32_t) address & _DCACHE_SET_MASK;
end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_DCACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq%.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
}
/*
* flush and invalidate a specific region from the both caches. We do not know if the area is cached
* at all, we do not know in which of the four ways it is cached, but we know the index where they
* would be cached if they are, so we only need to flush and invalidate only a subset of the 512 index
* entries, but all four ways.
*/
void flush_cache_range(void *address, size_t size)
{
unsigned long set;
unsigned long start_set;
unsigned long end_set;
void *endaddr;
endaddr = address + size;
start_set = (uint32_t) address & _DCACHE_SET_MASK;
end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_DCACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" addq%.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
}

341
Bas_gcc_mmu/sys/driver_mem.c Normal file
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/*
* driver_mem.c
*
* based from Emutos / BDOS
*
* Copyright (c) 2001 Lineo, Inc.
*
* Authors: Karl T. Braun, Martin Doering, Laurent Vogel
*
* This file is distributed under the GPL, version 2 or at your
* option any later version.
*/
#include <bas_types.h>
#include "bas_string.h"
#include "bas_printf.h"
#include "usb.h"
#include "exceptions.h" /* set_ipl() */
#if defined(MACHINE_FIREBEE)
#include "firebee.h"
#elif defined(MACHINE_M5484LITE)
#include "m5484l.h"
#elif defined(MACHINE_M54455)
#include "m54455.h"
#else
#error "unknown machine!"
#endif
#define DBG_DM
#ifdef DBG_DM
#define dbg(fmt, args...) xprintf(fmt, ##args)
#else
#define dbg(fmt, args...)
#endif
extern long offscren_reserved(void);
extern uint8_t driver_mem_buffer[DRIVER_MEM_BUFFER_SIZE]; /* defined in linker control file */
/* MD - Memory Descriptor */
#define MD struct _md_
MD
{
MD *m_link;
long m_start;
long m_length;
void *m_own;
};
/* MPB - Memory Partition Block */
#define MPB struct _mpb
MPB
{
MD *mp_mfl;
MD *mp_mal;
MD *mp_rover;
};
#define MAXMD 256
static MD tab_md[MAXMD];
static MPB pmd;
static void *xmgetblk(void)
{
int i;
for (i = 0; i < MAXMD; i++)
{
if (tab_md[i].m_own == NULL)
{
tab_md[i].m_own = (void*)1L;
return(&tab_md[i]);
}
}
return NULL;
}
static void xmfreblk(void *m)
{
int i = (int)(((long) m - (long) tab_md) / sizeof(MD));
if ((i > 0) && (i < MAXMD))
{
tab_md[i].m_own = NULL;
}
}
static MD *ffit(long amount, MPB *mp)
{
MD *p, *q, *p1; /* free list is composed of MD's */
int maxflg;
long maxval;
if (amount != -1)
{
amount += 15; /* 16 bytes alignment */
amount &= 0xFFFFFFF0;
}
if ((q = mp->mp_rover) == 0) /* get rotating pointer */
{
return 0;
}
maxval = 0;
maxflg = ((amount == -1) ? true : false) ;
p = q->m_link; /* start with next MD */
do /* search the list for an MD with enough space */
{
if (p == 0)
{
/* at end of list, wrap back to start */
q = (MD *) &mp->mp_mfl; /* q => mfl field */
p = q->m_link; /* p => 1st MD */
}
if ((!maxflg) && (p->m_length >= amount))
{
/* big enough */
if (p->m_length == amount)
{
q->m_link = p->m_link; /* take the whole thing */
}
else
{
/*
* break it up - 1st allocate a new
* MD to describe the remainder
*/
p1 = xmgetblk();
if (p1 == NULL)
{
return(NULL);
}
/* init new MD */
p1->m_length = p->m_length - amount;
p1->m_start = p->m_start + amount;
p1->m_link = p->m_link;
p->m_length = amount; /* adjust allocated block */
q->m_link = p1;
}
/* link allocate block into allocated list,
mark owner of block, & adjust rover */
p->m_link = mp->mp_mal;
mp->mp_mal = p;
mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
return(p); /* got some */
}
else if (p->m_length > maxval)
maxval = p->m_length;
p = ( q=p )->m_link;
} while(q != mp->mp_rover);
/*
* return either the max, or 0 (error)
*/
if (maxflg)
{
maxval -= 15; /* 16 bytes alignment */
if (maxval < 0)
{
maxval = 0;
}
else
{
maxval &= 0xFFFFFFF0;
}
}
return(maxflg ? (MD *) maxval : 0);
}
static void freeit(MD *m, MPB *mp)
{
MD *p, *q;
q = 0;
for (p = mp->mp_mfl; p ; p = (q = p) -> m_link)
{
if (m->m_start <= p->m_start)
{
break;
}
}
m->m_link = p;
if (q)
{
q->m_link = m;
}
else
{
mp->mp_mfl = m;
}
if (!mp->mp_rover)
{
mp->mp_rover = m;
}
if (p)
{
if (m->m_start + m->m_length == p->m_start)
{
/* join to higher neighbor */
m->m_length += p->m_length;
m->m_link = p->m_link;
if (p == mp->mp_rover)
{
mp->mp_rover = m;
}
xmfreblk(p);
}
}
if (q)
{
if (q->m_start + q->m_length == m->m_start)
{
/* join to lower neighbor */
q->m_length += m->m_length;
q->m_link = m->m_link;
if (m == mp->mp_rover)
{
mp->mp_rover = q;
}
xmfreblk(m);
}
}
}
int32_t driver_mem_free(void *addr)
{
int level;
MD *p, **q;
MPB *mpb;
mpb = &pmd;
level = set_ipl(7);
for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
{
if ((long) addr == p->m_start)
{
break;
}
}
if (!p)
{
set_ipl(level);
return(-1);
}
*q = p->m_link;
freeit(p, mpb);
set_ipl(level);
dbg("%s: driver_mem_free(0x%08X)\r\n", __FUNCTION__, addr);
return(0);
}
void *driver_mem_alloc(uint32_t amount)
{
void *ret = NULL;
int level;
MD *m;
if (amount == -1L)
{
return (void *) ffit(-1L, &pmd);
}
if (amount <= 0 )
{
return(0);
}
if ((amount & 1))
{
amount++;
}
level = set_ipl(7);
m = ffit(amount, &pmd);
if (m != NULL)
{
ret = (void *) m->m_start;
}
set_ipl(level);
dbg("%s: driver_mem_alloc(%d) = 0x%08X\r\n", __FUNCTION__, amount, ret);
return ret;
}
static int use_count = 0;
int driver_mem_init(void)
{
if (use_count == 0)
{
dbg("%s: initialise driver_mem_buffer[] at %p, size 0x%x\r\n", __FUNCTION__, driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE);
pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
tab_md[0].m_link = (MD *) NULL;
tab_md[0].m_start = ((long) driver_mem_buffer + 15) & ~15;
tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;
tab_md[0].m_own = (void *) 1L;
pmd.mp_mal = (MD *) NULL;
memset(driver_mem_buffer, 0, tab_md[0].m_length);
dbg("%s: uncached driver memory buffer at 0x%08X size %d\r\n", __FUNCTION__, tab_md[0].m_start, tab_md[0].m_length);
}
use_count++;
dbg("%s: driver_mem now has a use count of %d\r\n", __FUNCTION__, use_count);
return 0;
}
void driver_mem_release(void)
{
if (use_count-- == 0)
{
#ifndef CONFIG_USB_MEM_NO_CACHE
#ifdef USE_RADEON_MEMORY
if (driver_mem_buffer == (void *) offscren_reserved())
return;
#endif
#endif
}
dbg("%s: driver_mem use count now %d\r\n", __FUNCTION__, use_count);
}

798
Bas_gcc_mmu/sys/exceptions.S Normal file
View File

@@ -0,0 +1,798 @@
/*
* initialize exception vectors
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 26.02.2013
* Author: Markus Fröschle
*/
#include "startcf.h"
#if MACHINE_FIREBEE
#include "firebee.h"
#elif MACHINE_M5484LITE
#include "m5484l.h"
#endif /* MACHINE_FIREBEE */
.extern __SUP_SP
.extern _rom_entry
.extern __RAMBAR0
.extern _rt_mod
.extern _rt_ssp
.extern _rt_usp
.extern _rt_vbr
.extern _mmutr_miss
.extern __MBAR
.extern __MMUBAR
.extern _video_tlb
.extern _video_sbt
.extern _flush_and_invalidate_caches
/* PCI interrupt handlers */
.extern _irq5_handler
.extern _irq7_handler
/* Register read/write macros */
#define MCF_EPORT_EPPAR __MBAR+0xF00
#define MCF_EPORT_EPDDR __MBAR+0xF04
#define MCF_EPORT_EPIER __MBAR+0xF05
#define MCF_EPORT_EPDR __MBAR+0xF08
#define MCF_EPORT_EPPDR __MBAR+0xF09
#define MCF_EPORT_EPFR __MBAR+0xF0C
#define MCF_GPIO_PODR_FEC1L __MBAR+0xA07
#define MCF_PSC0_PSCTB_8BIT __MBAR+0x860C
.global _vec_init
// interrupt sources
.equ INT_SOURCE_EPORT_EPF1,1 // edge port flag 1
.equ INT_SOURCE_EPORT_EPF2,2 // edge port flag 2
.equ INT_SOURCE_EPORT_EPF3,3 // edge port flag 3
.equ INT_SOURCE_EPORT_EPF4,4 // edge port flag 4
.equ INT_SOURCE_EPORT_EPF5,5 // edge port flag 5
.equ INT_SOURCE_EPORT_EPF6,6 // edge port flag 6
.equ INT_SOURCE_EPORT_EPF7,7 // edge port flag 7
.equ INT_SOURCE_USB_EP0ISR,15 // USB endpoint 0 interrupt
.equ INT_SOURCE_USB_EP1ISR,16 // USB endpoint 1 interrupt
.equ INT_SOURCE_USB_EP2ISR,17 // USB endpoint 2 interrupt
.equ INT_SOURCE_USB_EP3ISR,18 // USB endpoint 3 interrupt
.equ INT_SOURCE_USB_EP4ISR,19 // USB endpoint 4 interrupt
.equ INT_SOURCE_USB_EP5ISR,20 // USB endpoint 5 interrupt
.equ INT_SOURCE_USB_EP6ISR,21 // USB endpoint 6 interrupt
.equ INT_SOURCE_USB_USBISR,22 // USB general interrupt
.equ INT_SOURCE_USB_USBAISR,23 // USB core interrupt
.equ INT_SOURCE_USB_ANY,24 // OR of all USB interrupts
.equ INT_SOURCE_USB_DSPI_OVF,25 // DSPI overflow or underflow
.equ INT_SOURCE_USB_DSPI_RFOF,26 // receive FIFO overflow interrupt
.equ INT_SOURCE_USB_DSPI_RFDF,27 // receive FIFO drain interrupt
.equ INT_SOURCE_USB_DSPI_TFUF,28 // transmit FIFO underflow interrupt
.equ INT_SOURCE_USB_DSPI_TCF,29 // transfer complete interrupt
.equ INT_SOURCE_USB_DSPI_TFFF,30 // transfer FIFO fill interrupt
.equ INT_SOURCE_USB_DSPI_EOQF,31 // end of queue interrupt
.equ INT_SOURCE_PSC3,32 // PSC3 interrupt
.equ INT_SOURCE_PSC2,33 // PSC2 interrupt
.equ INT_SOURCE_PSC1,34 // PSC1 interrupt
.equ INT_SOURCE_PSC0,35 // PSC0 interrupt
.equ INT_SOURCE_CTIMERS,36 // combined source for comm timers
.equ INT_SOURCE_SEC,37 // SEC interrupt
.equ INT_SOURCE_FEC1,38 // FEC1 interrupt
.equ INT_SOURCE_FEC0,39 // FEC0 interrupt
.equ INT_SOURCE_I2C,40 // I2C interrupt
.equ INT_SOURCE_PCIARB,41 // PCI arbiter interrupt
.equ INT_SOURCE_CBPCI,42 // COMM bus PCI interrupt
.equ INT_SOURCE_XLBPCI,43 // XLB PCI interrupt
.equ INT_SOURCE_XLBARB,47 // XLBARB to PCI interrupt
.equ INT_SOURCE_DMA,48 // multichannel DMA interrupt
.equ INT_SOURCE_CAN0_ERROR,49 // FlexCAN error interrupt
.equ INT_SOURCE_CAN0_BUSOFF,50 // FlexCAN bus off interrupt
.equ INT_SOURCE_CAN0_MBOR,51 // message buffer ORed interrupt
.equ INT_SOURCE_SLT1,53 // slice timer 1 interrupt
.equ INT_SOURCE_SLT0,54 // slice timer 0 interrupt
.equ INT_SOURCE_CAN1_ERROR,55 // FlexCAN error interrupt
.equ INT_SOURCE_CAN1_BUSOFF,56 // FlexCAN bus off interrupt
.equ INT_SOURCE_CAN1_MBOR,57 // message buffer ORed interrupt
.equ INT_SOURCE_GPT3,59 // GPT3 timer interrupt
.equ INT_SOURCE_GPT2,60 // GPT2 timer interrupt
.equ INT_SOURCE_GPT1,61 // GPT1 timer interrupt
.equ INT_SOURCE_GPT0,62 // GPT0 timer interrupt
// Atari register equates (provided by FPGA)
.equ vbasehi, 0xffff8201
//mmu ---------------------------------------------------
/* Register read/write macros */
#define MCF_MMU_MMUCR __MMUBAR
#define MCF_MMU_MMUOR __MMUBAR + 0x04
#define MCF_MMU_MMUSR __MMUBAR + 0x08
#define MCF_MMU_MMUAR __MMUBAR + 0x10
#define MCF_MMU_MMUTR __MMUBAR + 0x14
#define MCF_MMU_MMUDR __MMUBAR + 0x18
/* Bit definitions and macros for MCF_MMU_MMUCR */
#define MCF_MMU_MMUCR_EN (0x1)
#define MCF_MMU_MMUCR_ASM (0x2)
/* Bit definitions and macros for MCF_MMU_MMUOR */
#define MCF_MMU_MMUOR_UAA (0x1) /* update allocation address, i.e. write to TLB */
#define MCF_MMU_MMUOR_ACC (0x2) /* activate access to TLB */
#define MCF_MMU_MMUOR_RW (0x4) /* read/write TLB */
#define MCF_MMU_MMUOR_ADR (0x8) /* search by address/TLB address */
#define MCF_MMU_MMUOR_ITLB (0x10) /* act on instruction/data TLBs */
#define MCF_MMU_MMUOR_CAS (0x20) /* clear all unlocked TLBs with matching ASID */
#define MCF_MMU_MMUOR_CNL (0x40) /* clear all unlocked TLBs regardless of ASID */
#define MCF_MMU_MMUOR_CA (0x80) /* clear all TLBs */
#define MCF_MMU_MMUOR_STLB (0x100) /* search TLBs */
#define MCF_MMU_MMUOR_AA(x) (((x) & 0xFFFF) << 0x10) /* TLB allocation address */
/* Bit definitions and macros for MCF_MMU_MMUSR */
#define MCF_MMU_MMUSR_HIT (0x2) /* last lookup had a hit in TLB */
#define MCF_MMU_MMUSR_WF (0x8) /* indicate write fault */
#define MCF_MMU_MMUSR_RF (0x10) /* indicate read fault */
#define MCF_MMU_MMUSR_SPF (0x20) /* indicate supervisor protect fault */
/* Bit definitions and macros for MCF_MMU_MMUAR */
#define MCF_MMU_MMUAR_FA(x) (((x) & 0xFFFFFFFF) << 0)
/* Bit definitions and macros for MCF_MMU_MMUTR */
#define MCF_MMU_MMUTR_V (0x1) /* valid bit for TLB */
#define MCF_MMU_MMUTR_SG (0x2) /* set page as shared global */
#define MCF_MMU_MMUTR_ID(x) (((x) & 0xFF) << 0x2) /* ASID (address space id) of page */
#define MCF_MMU_MMUTR_VA(x) (((x) & 0x3FFFFF) << 0xA) /* virtual address of page */
/* Bit definitions and macros for MCF_MMU_MMUDR */
#define MCF_MMU_MMUDR_LK (0x2) /* lock page */
#define MCF_MMU_MMUDR_X (0x4) /* allow code execution in memory page */
#define MCF_MMU_MMUDR_W (0x8) /* allow write to memory page */
#define MCF_MMU_MMUDR_R (0x10) /* allow read from memory page */
#define MCF_MMU_MMUDR_SP (0x20) /* supervisor protect memory page */
#define MCF_MMU_MMUDR_CM(x) (((x) & 0x3) << 0x6) /* cache mode */
#define MCF_MMU_MMUDR_SZ(x) (((x) & 0x3) << 0x8) /* page size */
#define MCF_MMU_MMUDR_PA(x) (((x) & 0x3FFFFF) << 0xA) /* page physical address */
#define std_mmutr (MCF_MMU_MMUTR_SG | MCF_MMU_MMUTR_V)
#define writethrough_mmudr (MCF_MMU_MMUDR_SZ(00) | MCF_MMU_MMUDR_CM(00) | MCF_MMU_MMUDR_R | MCF_MMU_MMUDR_W | MCF_MMU_MMUDR_X)
#define copyback_mmudr (MCF_MMU_MMUDR_SZ(00) | MCF_MMU_MMUDR_CM(01) | MCF_MMU_MMUDR_R | MCF_MMU_MMUDR_W | MCF_MMU_MMUDR_X)
/*
*
* General Purpose Timers (GPT)
*
*/
/* Register read/write macros */
#define MCF_GPT0_GMS __MBAR+0x800
/*
*
* Slice Timers (SLT)
*
*/
#define MCF_SLT0_SCNT __MBAR+0x908
/**********************************************************/
// macros
/**********************************************************/
.altmacro
.macro irq vector,int_mask,clr_int
//move.w #0x2700,sr // disable interrupt
subq.l #8,sp
movem.l d0/a5,(sp) // save registers
lea MCF_EPORT_EPFR,a5
move.b #\clr_int,(a5) // clear int pending
movem.l (sp),d0/a5 // restore registers
addq.l #8,sp
move.l \vector,-(sp)
move #0x2\int_mask\()00,sr
rts
.endm
/*
* FIXME: this is a GNU gas kludge. Ugly, but I just can't come up with any smarter solution
*
* GNU as does not support multi-character constants. At least I don't know of any way it would.
* The following might look more than strange, but I considered the statement
*
* mchar move.l, 'T,'E,'S,'T,-(SP)
*
* somewhat more readable than
*
* move.l #1413829460,-(SP)
*
* If anybody knows of any better way on how to do this - please do!
*
*/
.macro mchar st,a,b,c,d,tgt
\st #\a << 24|\b<<16|\c<<8|\d,\tgt
.endm
.text
_vec_init:
move.l a2,-(sp) // Backup registers
mov3q.l #-1,_rt_mod // rt_mod auf super
clr.l _rt_ssp
clr.l _rt_usp
clr.l _rt_vbr
move.l #__RAMBAR0,d0 // exception vectors reside in rambar0
movec d0,VBR
move.l d0,a0
move.l a0,a2
init_vec:
move.l #256,d0
lea std_exc_vec(pc),a1 // standard vector
init_vec_loop:
move.l a1,(a2)+ // set standard vector for all exceptions
subq.l #1,d0
bne init_vec_loop
move.l #__SUP_SP,(a0) // set initial stack pointer at start of exception vector table
lea reset_vector(pc),a1 // set reset vector
move.l a1,0x04(a0)
lea access(pc),a1 // set illegal access exception handler
move.l a1,0x08(a0)
.extern _get_bas_drivers
// trap #0 (without any parameters for now) is used to provide BaS' driver addresses to the OS
lea _get_bas_drivers(pc),a1
move.l a1,0x80(a0) // trap #0 exception vector
#ifdef MACHINE_FIREBEE
// ACP interrupts 1-7 (user-defined, generated by FPGA on the FireBee, M5484LITE has irq7 and irq5 for PCI)
lea irq1(pc),a1
move.l a1,0x104(a0)
lea irq2(pc),a1
move.l a1,0x108(a0)
lea irq3(pc),a1
move.l a1,0x10c(a0)
lea irq4(pc),a1
move.l a1,0x110(a0)
lea irq5(pc),a1
move.l a1,0x114(a0)
lea irq6(pc),a1
move.l a1,0x118(a0)
lea irq7(pc),a1
move.l a1,0x11c(a0)
// timer vectors (triggers when vbashi gets changed, used for video page copy)
lea handler_gpt0(pc),a1
// GPT0 interrupt source = 62
move.l a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
#endif /* MACHINE_FIREBEE */
// install lowlevel_isr_handler for the three GPT timers
lea _lowlevel_isr_handler(pc),a1
move.l a1,(INT_SOURCE_GPT1 + 64) * 4(a0)
move.l a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
// install lowlevel_isr_handler for the FEC0 interrupt
move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
// install lowlevel_isr_handler for the PSC3 interrupt
move.l a1,(INT_SOURCE_PSC3 + 64) * 4(a0)
#ifndef MACHINE_FIREBEE
// FEC1 not wired on the FireBee, but used on other machines
move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
#endif
// install lowlevel_isr_handler for DMA interrupts
move.l a1,(INT_SOURCE_DMA + 64) * 4(a0)
move.l (sp)+,a2 // Restore registers
rts
/*
* exception vector routines
*/
vector_table_start:
std_exc_vec:
//move.w #0x2700,sr // disable interrupt
subq.l #8,sp
movem.l d0/a5,(sp) // save registers
move.w 8(sp),d0 // fetch vector
and.l #0x3fc,d0 // mask out vector number
#ifdef DBG_EXC
// printout vector number of exception
lea -4 * 4(sp),sp // reserve stack space
movem.l d0-d1/a0-a1,(sp) // save gcc scratch registers
lsr.l #2,d0 // shift vector number in place
cmp.l #33,d0
beq noprint
cmp.l #34,d0
beq noprint
cmp.l #45,d0
beq noprint
cmp.l #46,d0
beq noprint
move.l 4 * 4 + 8 + 4(sp),-(sp) // pc at exception
move.l d0,-(sp) // provide it to xprintf()
pea exception_text
jsr _xprintf // call xprintf()
add.l #3*4,sp // adjust stack
noprint:
movem.l (sp),d0-d1/a0-a1 // restore registers
lea 4 * 4(sp),sp
#endif /* DBG_EXC */
add.l _rt_vbr,d0 // + VBR
move.l d0,a5
move.l (a5),d0 // fetch exception routine address
move.l 4(sp),a5 // restore a5
move.l d0,4(sp) // store exception routine address
//move.w 10(sp),d0 // restore original SR
//bset #13,d0 // set supervisor bit
//move.w d0,sr //
move.l (sp)+,d0 // restore d0
rts // jump to exception routine
exception_text:
.ascii "DEBUG: EXCEPTION %d caught at %p"
.byte 13, 10, 0
.align 4
reset_vector:
move.w #0x2700,sr // disable interrupt
move.l #0x31415926,d0
cmp.l 0x426,d0 // _resvalid: reset vector valid?
beq std_exc_vec // yes->
jmp _rom_entry // no, cold start machine
access:
move.w #0x2700,sr // disable interrupts
move.l d0,-(sp) // ++ vr
move.w 4(sp),d0 // get format_status word from stack
andi.l #0x0c03,d0 // mask out fault status bits
cmpi.l #0x0401,d0 // TLB miss on opword of instruction fetch?
beq access_mmu // yes
cmpi.l #0x0402,d0 // TLB miss on extension word of instruction fetch?
beq access_mmu // yes
cmpi.l #0x0802,d0 // TLB miss on data write?
beq access_mmu // yes
cmpi.l #0x0c02,d0 // TLB miss on data read, or read-modify-write?
beq access_mmu // yes
bra bus_error // everything else is a classic bus error
access_mmu:
move.l MCF_MMU_MMUSR,d0 // did the last fault hit in TLB?
btst #1,d0 // yes, it did. So we already mapped that page
bne bus_error // and this must be a real bus error
btst #5,d0 // supervisor protection fault?
bne bus_error
btst #4,d0 // read access fault?
bne bus_error
btst #3,d0 // write access fault?
bne bus_error
move.l MCF_MMU_MMUAR,d0
cmp.l #__FASTRAM_END,d0 // above max User RAM area?
bge bus_error // -> bus error
lea -3 * 4(sp),sp // save gcc scratch registers
movem.l d1/a0-a1,(sp)
move.l 3 * 4 + 4 (sp),-(sp) // push exception stack frame
move.l 5 * 4 + 4 (sp),-(sp) // push program counter at exception
move.l d0,-(sp) // fault address
jsr _mmutr_miss // else we have an MMU TLB miss
add.l #3 * 4,sp // adjust stack
movem.l (sp),d1/a0-a1 // restore gcc scratch registers
lea 3 * 4(sp),sp
move.l (sp)+,d0 // restore register
rte
bus_error:
move.l (sp)+,d0 // restore register
bra std_exc_vec
zero_divide:
move.w #0x2700,sr // disable interrupt
move.l a0,-(sp)
move.l d0,-(sp)
move.l 12(sp),a0 // pc
move.w (a0)+,d0 // command word
btst #7,d0 // long?
beq zd_word // nein->
addq.l #2,a0
zd_word:
and.l 0x3f,d0 // mask out ea field
cmp.w #0x08,d0 // -(ax) or less?
ble zd_end
addq.l #2,a0
cmp.w #0x39,d0 // xxx.L
bne zd_nal
addq.l #2,a0
bra zd_end
zd_nal: cmp.w #0x3c,d0 // immediate?
bne zd_end // no->
btst #7,d0 // long?
beq zd_end // no
addq.l #2,a0
zd_end:
move.l a0,12(sp)
move.l (sp)+,d0
move.l (sp)+,a0
rte
#ifdef _NOT_USED_
linea:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
linef:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
format:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
//floating point
flpoow:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
#endif /* _NOT_USED */
irq1:
irq 0x64,1,0x02
irq2: // hbl
// move.b #3,2(sp)
// rte
irq 0x68,2,0x04
irq3:
irq 0x6c,3,0x08
irq4: // vbl
irq 0x70,4,0x10
#if MACHINE_M5484LITE_notyet // handlers for M5484LITE
irq5: // irq5 is tied to PCI INTC# and PCI INTD# on the M5484LITE
move.w #0x2700,sr // disable interrupts
lea -4*4(sp),sp // save gcc scratch registers
movem.l d0-d1/a0-a1,(sp)
jsr _irq5_handler // call C handler routine
movem.l (sp),d0-d1/a0-a1 // restore registers
lea 4*4(sp),sp
rte // return from exception
irq5text:
.ascii "IRQ5!"
.dc.b 13,10,0
irq6:
irq 0x74,5,0x20
irq7: // irq7 is tied to PCI INTA# and PCI INTB# on the M5484LITE
move.w #0x2700,sr // disable interrupts
lea -4*4(sp),sp // save gcc scratch registers
movem.l d0-d1/a0-a1,(sp)
jsr _irq7_handler // call C handler routine
movem.l (sp),d0-d1/a0-a1 // restore registers
lea 4*4(sp),sp
rte // return from exception
irq7text:
.data
.ascii "IRQ7!"
.dc.b 13,10,0
.text
#elif MACHINE_FIREBEE /* these handlers are only meaningful for the Firebee */
irq5: // irq5 is tied to PCI INTC# and PCI INTD# on the M5484LITE
irq 0x74,5,0x20
irq6: // MFP interrupt from FPGA
move.w #0x2700,sr // disable interrupt
subq.l #8,sp
movem.l d0/a5,(sp) // save registers
lea MCF_EPORT_EPFR,a5 // clear int6 from edge port
bset #6,(a5)
// screen adr change timed out?
move.l _video_sbt,d0
beq irq6_non_sca // nothing to do if 0
sub.l #0x70000000,d0 // substract 14 seconds
lea MCF_SLT0_SCNT,a5
cmp.l (a5),d0 // time reached?
ble irq6_non_sca // not yet
lea -7 * 4(sp),sp // save more registers
movem.l d0-d4/a0-a1,(sp) //
clr.l d3 // beginn mit 0
// jsr _flush_and_invalidate_caches FIXME: why should we need that?
// eintrag suchen
irq6_next_sca:
move.l d3,d0
move.l d0,MCF_MMU_MMUAR // addresse
move.l #0x106,d4
move.l d4,MCF_MMU_MMUOR // suchen ->
nop
move.l MCF_MMU_MMUOR,d4
clr.w d4
swap d4
move.l d4,MCF_MMU_MMUAR
mvz.w #0x10e,d4
move.l d4,MCF_MMU_MMUOR // einträge holen aus mmu
nop
move.l MCF_MMU_MMUTR,d4 // ID holen
lsr.l #2,d4 // bit 9 bis 2
cmp.w #sca_page_ID,d4 // ist screen change ID?
bne irq6_sca_pn // nein -> page keine screen area next
// eintrag <EFBFBD>ndern
add.l #std_mmutr,d0
move.l d3,d1 // page 0?
beq irq6_sca_pn0 // ja ->
add.l #copyback_mmudr,d1 // sonst page cb
bra irq6_sca_pn1c
irq6_sca_pn0:
add.l #writethrough_mmudr/*|MCF_MMU_MMUDR_LK*/,d1 // page wt and locked
irq6_sca_pn1c:
mvz.w #0x10b,d2 // MMU update
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // setze tlb data only
nop
// page copy
move.l d3,a0
add.l #0x60000000,a0
move.l d3,a1
move.l #0x10000,d4 // one whole page (1 MB)
irq6_vcd0_loop:
move.l (a0)+,(a1)+ // page copy
move.l (a0)+,(a1)+
move.l (a0)+,(a1)+
move.l (a0)+,(a1)+
subq.l #1,d4
bne irq6_vcd0_loop
irq6_sca_pn:
add.l #0x00100000,d3 // next
cmp.l #0x00d00000,d3 // ende?
blt irq6_next_sca // nein->
move.l #0x2000,d0
move.l d0,_video_tlb // anfangszustand wieder herstellen
clr.l _video_sbt // zeit löschen
movem.l (sp),d0-d4/a0-a1 // restore registers
lea 7 * 4(sp),sp
irq6_non_sca:
// test auf acsi dma -----------------------------------------------------------------
lea 0xfffffa0b,a5
bset #7,-4(a5) // int ena
btst.b #7,(a5) // acsi dma int?
beq non_acsi_dma
bsr acsi_dma
non_acsi_dma:
// ----------------------------------------------------------------------------------
tst.b (a5)
bne irq6_1
tst.b 2(a5)
bne irq6_1
movem.l (sp),d0/a5
addq.l #8,sp
rte
irq6_1:
lea MCF_GPIO_PODR_FEC1L,a5
bclr.b #4,(a5) // led on
lea blinker,a5
addq.l #1,(a5) // +1
move.l (a5),d0
and.l #0x80,d0
bne irq6_2
lea MCF_GPIO_PODR_FEC1L,a5
bset.b #4,(a5) // led off
irq6_2:
move.l 0xF0020000,a5 // vector holen
add.l _rt_vbr,a5 // basis
move.l (a5),d0 // vector holen
move.l 4(sp),a5 // a5 zurück
move.l d0,4(sp) // vector eintragen
move.l (sp)+,d0 // d0 zurück
move #0x2600,sr
rts
.data
blinker:.long 0
.text
/*
* pseudo dma
*/
acsi_dma: // atari dma
move.l a1,-(sp)
move.l d1,-(sp)
lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr
mchar move.l, 'D,'M','A,'\ ,(a1)
//move.l #"DMA ",(a1)
mchar move.l,'I,'N,'T,'!,(a1)
// move.l #'INT!',(a1)
lea 0xf0020110,a5 // fifo daten
acsi_dma_start:
move.l -12(a5),a1 // dma adresse
move.l -8(a5),d0 // byt counter
ble acsi_dma_end
btst.b #0,-16(a5) // write? (dma modus reg)
bne acsi_dma_wl // ja->
acsi_dma_rl:
tst.b -4(a5) // dma req?
bpl acsi_dma_finished // nein->
move.l (a5),(a1)+ // read 4 bytes
move.l (a5),(a1)+ // read 4 bytes
move.l (a5),(a1)+ // read 4 bytes
move.l (a5),(a1)+ // read 4 bytes
moveq #'.',d1
move.b d1,MCF_PSC0_PSCTB_8BIT
sub.l #16,d0 // byt counter -16
bpl acsi_dma_rl
bra acsi_dma_finished
acsi_dma_wl:
tst.b -4(a5) // dma req?
bpl acsi_dma_finished // nein->
move.l (a1)+,(a5) // write 4 byts
move.l (a1)+,(a5) // write 4 byts
move.l (a1)+,(a5) // write 4 byts
move.l (a1)+,(a5) // write 4 byts
moveq #'.',d1
move.b d1,MCF_PSC0_PSCTB_8BIT
sub.l #16,d0 // byt counter -16
bpl acsi_dma_wl
acsi_dma_finished:
move.l a1,-12(a5) // adresse zur<EFBFBD>ck
move.l d0,-8(a5) // byt counter zur<EFBFBD>ck
acsi_dma_end:
tst.b -4(a5) // dma req?
bmi acsi_dma_start // ja->
lea 0xfffffa0b,a5
bclr.b #7,4(a5) // clear int in service mfp
bclr.b #7,(a5) // clear int pending mfp 0xfffffa0b
move.w #0x0d0a,d1
move.w d1,MCF_PSC0_PSCTB_8BIT
move.l (sp)+,d1
move.l (sp)+,a1
rts
/*
* irq 7 = pseudo bus error
*/
irq7:
lea -12(sp),sp
movem.l d0/a0,(sp)
move.l __RAMBAR0+0x008,a0 // real access error handler
move.l a0,8(sp) // this will be the return address for rts
move.w 12(sp),d0 // format/vector word
andi.l #0xf000,d0 // keep only the format
ori.l #2*4,d0 // simulate vector #2, no fault
move.w d0,12(sp)
// TODO: Inside an interrupt handler, 16(sp) is the return address.
// For an Access Error, it should be the address of the fault instruction instead
lea MCF_EPORT_EPFR,a0
bset #7,(a0) // clear int 7
move.l (sp)+,d0 // restore registers
move.l (sp)+,a0
rts // Forward to the Access Error handler
/*
* general purpose timer 0 (GPT0): video change, later also others.
*
* GPT0 is used as input trigger. It is connected to the TIN0 signal of
* the FPGA and triggers everytime vbasehi is written to, i.e.
* when the video base address gets changed
*/
handler_gpt0:
.extern _gpt0_interrupt_handler
move.w #0x2700,sr // disable interrupts
link a6,#-4 * 4 // make room for
movem.l d0-d1/a0-a1,(sp) // gcc scratch registers and save them,
// other registers will be handled by gcc itself
move.w 4(a6),d0 // fetch vector number from stack
move.l d0,-(sp) // push it
jsr _gpt0_interrupt_handler // call C handler
addq.l #4,sp // adjust stack
unlk a6
rte
#endif /* MACHINE_FIREBEE */
/*
* low-level interrupt service routine for routines registered with
* isr_register_handler()
*/
.global _lowlevel_isr_handler
.extern _isr_execute_handler
_lowlevel_isr_handler:
move.w #0x2700,sr // do not disturb
link a6,#-4 * 4 // make room for
movem.l d0-d1/a0-a1,(sp) // gcc scratch registers and save them,
// other registers will be handled by gcc itself
move.w 4(a6),d0 // fetch vector number from stack
lsr.l #2,d0 // move it in place
andi.l #0xff,d0 // mask it out
move.l d0,-(sp) // push it
jsr _isr_execute_handler // call the C handler
addq.l #4,sp // adjust stack
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6
rte

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/*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* provide an early exception vector branch table to catch exceptions _before_ VBR has been setup eventually
* (to RAMBAR0, in exceptions.S)
*/
#include "MCF5475.h"
#include "bas_types.h"
#include "bas_printf.h"
typedef void (*exception_handler)(void);
extern exception_handler SDRAM_VECTOR_TABLE[];
/*
* decipher Coldfire exception stack frame and print it out in cleartext
*/
void fault_handler(uint32_t pc, uint32_t format_status)
{
int format;
int fault_status;
int vector;
int sr;
xprintf("\007\007exception! Processor halted.\r\n");
xprintf("format_status: %lx\r\n", format_status);
xprintf("pc: %lx\r\n", pc);
/*
* extract info from format-/status word
*/
format = (format_status & 0b11110000000000000000000000000000) >> 28;
fault_status = ((format_status & 0b00001100000000000000000000000000) >> 26) |
((format_status & 0b00000000000000110000000000000000) >> 16);
vector = (format_status & 0b00000011111111000000000000000000) >> 18;
sr = (format_status & 0b00000000000000001111111111111111);
xprintf("format: %x\r\n", format);
xprintf("fault_status: %x (", fault_status);
switch (fault_status)
{
case 0:
xprintf("not an access or address error nor an interrupted debug service routine");
break;
case 1:
case 3:
case 11:
xprintf("reserved");
break;
case 2:
xprintf("interrupt during a debug service routine for faults other than access errors");
break;
case 4:
xprintf("error (for example, protection fault) on instruction fetch");
break;
case 5:
xprintf("TLB miss on opword or instruction fetch");
break;
case 6:
xprintf("TLB miss on extension word of instruction fetch");
break;
case 7:
xprintf("IFP access error while executing in emulator mode");
break;
case 8:
xprintf("error on data write");
break;
case 9:
xprintf("error on attempted write to write-protected space");
break;
case 10:
xprintf("TLB miss on data write");
break;
case 12:
xprintf("error on data read");
break;
case 13:
xprintf("attempted read, read-modify-write of protected space");
break;
case 14:
xprintf("TLB miss on data read or read-modify-write");
break;
case 15:
xprintf("OEP access error while executing in emulator mode");
}
xprintf(")\r\n");
xprintf("vector = %02x (", vector);
switch (vector)
{
case 2:
xprintf("access error");
break;
case 3:
xprintf("address error");
break;
case 4:
xprintf("illegal instruction");
break;
case 5:
xprintf("divide by zero");
break;
case 8:
xprintf("privilege violation");
break;
case 9:
xprintf("trace");
break;
case 10:
xprintf("unimplemented line-a opcode");
break;
case 11:
xprintf("unimplemented line-f opcode");
break;
case 12:
xprintf("non-PC breakpoint debug interrupt");
break;
case 13:
xprintf("PC breakpoint debug interrupt");
break;
case 14:
xprintf("format error");
break;
case 24:
xprintf("spurious interrupt");
break;
default:
if ( ((fault_status >= 6) && (fault_status <= 7)) ||
((fault_status >= 16) && (fault_status <= 23)))
{
xprintf("reserved");
}
else if ((fault_status >= 25) && (fault_status <= 31))
{
xprintf("level %d autovectored interrupt", fault_status - 24);
}
else if ((fault_status >= 32) && (fault_status <= 47))
{
xprintf("trap #%d", fault_status - 32);
}
else
{
xprintf("unknown fault status");
}
}
xprintf(")\r\n");
xprintf("sr=%4x\r\n", sr);
}
void __attribute__((interrupt)) handler(void)
{
/*
* Prepare exception stack contents so it can be handled by a C routine.
*
* For standard routines, we'd have to save registers here.
* Since we do not intend to return anyway, we just ignore that requirement.
*/
__asm__ __volatile__("move.l (sp),-(sp)\n\t"\
"move.l 8(sp),-(sp)\n\t"\
"bsr _fault_handler\n\t"\
"halt\n\t"\
: : : "memory");
}
void setup_vectors(void)
{
int i;
xprintf("\r\ninstall early exception vector table:");
for (i = 8; i < 256; i++)
{
SDRAM_VECTOR_TABLE[i] = &handler;
}
/*
* make sure VBR points to our table
*/
__asm__ __volatile__("clr.l d0\n\t"\
"movec.l d0,VBR\n\t"\
"nop\n\t"\
"move.l d0,_rt_vbr"
: /* outputs */
: /* inputs */
: "d0", "memory", "cc" /* clobbered registers */
);
xprintf("finished.\r\n");
}

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/*
* init_fpga.c
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2011 - 2012 V. Riviere
* Copyright 2012 M. Froeschle
*
*/
#include "MCF5475.h"
#include "sysinit.h"
#include "bas_printf.h"
#include "wait.h"
// #define FPGA_DEBUG
#if defined(FPGA_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
#define FPGA_STATUS (1 << 0)
#define FPGA_CLOCK (1 << 1)
#define FPGA_CONFIG (1 << 2)
#define FPGA_DATA0 (1 << 3)
#define FPGA_CONF_DONE (1 << 5)
extern uint8_t _FPGA_CONFIG[];
#define FPGA_FLASH_DATA &_FPGA_CONFIG[0]
extern uint8_t _FPGA_CONFIG_SIZE[];
#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_CONFIG_SIZE[0])
/*
* flag located in processor SRAM1 that indicates that the FPGA configuration has
* been loaded through JTAG. init_fpga() will honour this and not overwrite config.
*/
extern bool _FPGA_JTAG_LOADED;
extern long _FPGA_JTAG_VALID;
#define VALID_JTAG 0xaffeaffe
void config_gpio_for_fpga_config(void)
{
#if defined(MACHINE_FIREBEE)
/*
* Configure GPIO FEC1L port directions (needed to load FPGA configuration)
*/
MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */
0 | /* bit 6 = input */
0 | /* bit 5 = input */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 | /* bit 2 = FPGA_CONFIG => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 | /* bit 1 = PRG_CLK (FPGA) => output */
0; /* bit 0 => input */
#endif /* MACHINE_FIREBEE */
}
void config_gpio_for_jtag_config(void)
{
/*
* configure FEC1L port directions to enable external JTAG configuration download to FPGA
*/
MCF_GPIO_PDDR_FEC1L = 0 |
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */
/*
* unfortunately, the GPIO module cannot trigger interrupts. That means CONF_DONE needs to be polled to detect
* external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
*/
}
/*
* load FPGA
*/
bool init_fpga(void)
{
uint8_t *fpga_data;
volatile int32_t time, start, end;
int i;
dbg("FPGA load config\r\n(_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
if (_FPGA_JTAG_LOADED == true && _FPGA_JTAG_VALID == VALID_JTAG)
{
dbg("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
/* reset the flag so that next boot will load config again from flash */
_FPGA_JTAG_LOADED = 0;
return true;
}
start = MCF_SLT0_SCNT;
config_gpio_for_fpga_config();
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */
/* pulling FPGA_CONFIG to low resets the FPGA */
MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */
wait(10); /* give it some time to do its reset stuff */
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS)); /* wait until status becomes high */
/*
* excerpt from an Altera configuration manual:
*
* The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The
* configuration cycle consists of 3 stages<65>reset, configuration, and initialization.
* While nCONFIG is low, the device is in reset. When the device comes out of reset,
* nCONFIG must be at a logic high level in order for the device to release the open-drain
* nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
* is ready to receive configuration data. Before and during configuration, all user I/O pins
* are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors
* on the I/O pins which are on, before and during configuration.
*
* To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay
* configuration by holding the nCONFIG low. The device receives configuration data on its
* DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After
* the FPGA has received all configuration data successfully, it releases the CONF_DONE pin,
* which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates
* configuration is complete and initialization of the device can begin.
*/
const uint8_t *fpga_flash_data_end = FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE;
fpga_data = (uint8_t *) FPGA_FLASH_DATA;
do
{
uint8_t value = *fpga_data++;
for (i = 0; i < 8; i++, value >>= 1)
{
if (value & 1)
{
/* bit set -> toggle DATA0 to high */
MCF_GPIO_PODR_FEC1L |= FPGA_DATA0;
}
else
{
/* bit is cleared -> toggle DATA0 to low */
MCF_GPIO_PODR_FEC1L &= ~FPGA_DATA0;
}
/* toggle DCLK -> FPGA reads the bit */
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
}
} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < fpga_flash_data_end));
if (fpga_data < fpga_flash_data_end)
{
#ifdef _NOT_USED_
while (fpga_data++ < fpga_flash_data_end)
{
/* toggle a little more since it's fun ;) */
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
}
#endif /* _NOT_USED_ */
end = MCF_SLT0_SCNT;
time = (start - end) / (SYSCLK / 1000) / 1000;
xprintf("finished (took %f seconds).\r\n", time / 1000.0);
config_gpio_for_jtag_config();
return true;
}
xprintf("FAILED!\r\n");
config_gpio_for_jtag_config();
return false;
}

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/*
* Interrupts
*
* Handle interrupts, the levels.
*
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 26.02.2013
* Author: Markus Fröschle
*/
#include <bas_types.h>
#include "MCF5475.h"
#include "bas_utils.h"
#include "bas_printf.h"
#include "bas_string.h"
#include "exceptions.h"
#include "interrupts.h"
#include "bas_printf.h"
#include "startcf.h"
#include "cache.h"
#include "util.h"
#include "dma.h"
extern void (*rt_vbr[])(void);
#define VBR rt_vbr
#define IRQ_DEBUG
#if defined(IRQ_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
/*
* register an interrupt handler at the Coldfire interrupt controller and add the handler to
* the interrupt vector table
*/
int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void))
{
int ipl;
int i;
volatile uint8_t *ICR = &MCF_INTC_ICR01 - 1;
uint8_t lp;
source &= 63;
priority &= 7;
if (source < 1 || source > 63)
{
dbg("interrupt source %d not defined\r\n", source);
return -1;
}
lp = MCF_INTC_ICR_IL(level) | MCF_INTC_ICR_IP(priority);
/* check if this combination is already set somewhere */
for (i = 1; i < 64; i++)
{
if (ICR[i] == lp)
{
dbg("level %d and priority %d already used for interrupt source %d!\r\n",
level, priority, i);
return -1;
}
}
/* disable interrupts */
ipl = set_ipl(7);
VBR[64 + source] = handler; /* first 64 vectors are system exceptions */
/* set level and priority in interrupt controller */
ICR[source] = lp;
/* set interrupt mask to where it was before */
set_ipl(ipl);
return 0;
}
#ifndef MAX_ISR_ENTRY
#define MAX_ISR_ENTRY (20)
#endif
struct isrentry
{
int vector;
int (*handler)(void *, void *);
void *hdev;
void *harg;
};
static struct isrentry isrtab[MAX_ISR_ENTRY]; /* list of interrupt service routines */
/*
* clear the table of interrupt service handlers
*/
void isr_init(void)
{
memset(isrtab, 0, sizeof(isrtab));
}
/*
* This function places an interrupt handler in the ISR table,
* thereby registering it so that the low-level handler may call it.
*
* The two parameters are intended for the first arg to be a
* pointer to the device itself, and the second a pointer to a data
* structure used by the device driver for that particular device.
*/
int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg)
{
int index;
if ((vector == 0) || (handler == NULL))
{
dbg("illegal vector or handler!\r\n");
return false;
}
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].vector == vector)
{
/* one cross each, only! */
dbg("already set handler with this vector (%d, %d)\r\n", vector);
return false;
}
if (isrtab[index].vector == 0)
{
isrtab[index].vector = vector;
isrtab[index].handler = handler;
isrtab[index].hdev = hdev;
isrtab[index].harg = harg;
return true;
}
}
dbg("no available slots to register handler for vector %d\n\r", vector);
return false; /* no available slots */
}
void isr_remove_handler(int (*handler)(void *, void *))
{
/*
* This routine removes from the ISR table all
* entries that matches 'handler'.
*/
int index;
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].handler == handler)
{
memset(&isrtab[index], 0, sizeof(struct isrentry));
return;
}
}
dbg("no such handler registered (handler=%p\r\n", handler);
}
/*
* This routine searches the ISR table for an entry that matches
* 'vector'. If one is found, then 'handler' is executed.
*/
bool isr_execute_handler(int vector)
{
int index;
bool retval = false;
/*
* locate a BaS Interrupt Service Routine handler.
*/
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].vector == vector)
{
retval = true;
if (isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg))
{
return retval;
}
}
}
dbg("no BaS isr handler for vector %d found\r\n", vector);
return retval;
}
/*
* PIC interrupt handler for Firebee
*
* Handles PIC requests that come in from PSC3 serial interface. Currently, that
* is RTC/NVRAM requests only
*/
int pic_interrupt_handler(void *arg1, void *arg2)
{
uint8_t rcv_byte;
rcv_byte = MCF_PSC3_PSCRB_8BIT;
if (rcv_byte == 2) // PIC requests RTC data
{
uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
uint8_t *rtc_data = (uint8_t *) 0xffff8963;
int index = 0;
xprintf("PIC interrupt: requesting RTC data\r\n");
MCF_PSC3_PSCTB_8BIT = 0x82; // header byte to PIC
do
{
*rtc_reg = 0;
MCF_PSC3_PSCTB_8BIT = *rtc_data;
} while (index++ < 64);
}
return 1;
}
extern int32_t video_sbt;
extern int32_t video_tlb;
void video_addr_timeout(void)
{
uint32_t addr = 0x0L;
uint32_t *src;
uint32_t *dst;
uint32_t asid;
dbg("video address timeout\r\n");
flush_and_invalidate_caches();
do
{
uint32_t tlb;
uint32_t page_attr;
/*
* search tlb entry id for addr (if not available, the MMU
* will provide a new one based on its LRU algorithm)
*/
MCF_MMU_MMUAR = addr;
MCF_MMU_MMUOR =
MCF_MMU_MMUOR_STLB |
MCF_MMU_MMUOR_RW |
MCF_MMU_MMUOR_ACC;
NOP();
tlb = (MCF_MMU_MMUOR >> 16) & 0xffff;
/*
* retrieve tlb entry with the found TLB entry id
*/
MCF_MMU_MMUAR = tlb;
MCF_MMU_MMUOR =
MCF_MMU_MMUOR_STLB |
MCF_MMU_MMUOR_ADR |
MCF_MMU_MMUOR_RW |
MCF_MMU_MMUOR_ACC;
NOP();
asid = (MCF_MMU_MMUTR >> 2) & 0x1fff; /* fetch ASID of page */;
if (asid != sca_page_ID) /* check if screen area */
{
addr += 0x100000;
continue; /* next page */
}
/* modify found TLB entry */
if (addr == 0x0)
{
page_attr =
MCF_MMU_MMUDR_LK |
MCF_MMU_MMUDR_SZ(0) |
MCF_MMU_MMUDR_CM(0) |
MCF_MMU_MMUDR_R |
MCF_MMU_MMUDR_W |
MCF_MMU_MMUDR_X;
}
else
{
page_attr =
MCF_MMU_MMUTR_SG |
MCF_MMU_MMUTR_V;
}
MCF_MMU_MMUTR = addr;
MCF_MMU_MMUDR = page_attr;
MCF_MMU_MMUOR =
MCF_MMU_MMUOR_STLB |
MCF_MMU_MMUOR_ADR |
MCF_MMU_MMUOR_ACC |
MCF_MMU_MMUOR_UAA;
NOP();
dst = (uint32_t *) 0x60000000 + addr;
src = (uint32_t *) addr;
while (dst < (uint32_t *) 0x60000000 + addr + 0x10000)
{
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
}
addr += 0x100000;
} while (addr < 0xd00000);
video_tlb = 0x2000;
video_sbt = 0;
}
/*
* blink the Firebee's LED to show we are still alive
*/
void blink_led(void)
{
static uint16_t blinker = 0;
if ((blinker++ & 0x80) > 0)
{
MCF_GPIO_PODR_FEC1L |= (1 << 4); /* LED off */
}
else
{
MCF_GPIO_PODR_FEC1L &= ~(1 << 4); /* LED on */
}
}
/*
* Atari MFP interrupt registers.
*
* TODO: should go into a header file
*/
#define FALCON_MFP_IERA *((volatile uint8_t *) 0xfffffa07)
#define FALCON_MFP_IERB *((volatile uint8_t *) 0xfffffa09)
#define FALCON_MFP_IPRA *((volatile uint8_t *) 0xfffffa0b)
#define FALCON_MFP_IPRB *((volatile uint8_t *) 0xfffffa0d)
#define FALCON_MFP_IMRA *((volatile uint8_t *) 0xfffffa13)
#define FALCON_MFP_IMRB *((volatile uint8_t *) 0xfffffa15)
bool irq6_acsi_dma_interrupt(void)
{
dbg("ACSI DMA interrupt\r\n");
/*
* TODO: implement handler
*/
return false;
}
bool irq6_interrupt_handler(uint32_t sf1, uint32_t sf2)
{
bool handled = false;
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
if (video_sbt != 0 && (video_sbt - 0x70000000) > MCF_SLT0_SCNT)
{
video_addr_timeout();
handled = true;
}
/*
* check if ACSI DMA interrupt
*/
if (FALCON_MFP_IERA & (1 << 7))
{
/* ACSI interrupt is enabled */
if (FALCON_MFP_IPRA & (1 << 7))
{
irq6_acsi_dma_interrupt();
handled = true;
}
}
if (FALCON_MFP_IPRA || FALCON_MFP_IPRB)
{
blink_led();
}
return handled;
}
#if defined(MACHINE_FIREBEE)
#define vbasehi (* (volatile uint8_t *) 0xffff8201)
#define vbasemid (* (volatile uint8_t *) 0xffff8203)
#define vbaselow (* (volatile uint8_t *) 0xffff820d)
#define vwrap (* (volatile uint16_t *) 0xffff8210)
#define vde (* (volatile uint16_t *) 0xffff82aa)
#define vdb (* (volatile uint16_t *) 0xffff82a8)
/*
* this is the higlevel interrupt service routine for gpt0 timer interrupts.
*
* It is called from handler_gpt0 in exceptions.S
*
* The gpt0 timer is not used as a timer, but as interrupt trigger by the FPGA which fires
* everytime the video base address high byte (0xffff8201) gets written by user code (i.e.
* everytime the video base address is set).
* The interrupt service routine checks if that page was already set as a video page (in that
* case it does nothing), if not (if we have a newly set page), it sets up an MMU mapping for
* that page (effectively rerouting any further access to Falcon video RAM to Firebee FPGA
* video RAM starting at 0x60000000) and copies SDRAM contents of that page to the video
* RAM page.
*/
void gpt0_interrupt_handler(void)
{
uint32_t video_address;
uint32_t video_end_address;
int page_number;
bool already_set;
extern uint32_t _STRAM_END;
dbg("screen base = 0x%x\r\n", vbasehi);
if (vbasehi < 2) /* screen base lower than 0x20000? */
{
goto rearm_trigger; /* do nothing */
}
else if (vbasehi >= 0xd0) /* higher than 0xd00000 (normal Falcon address)? */
{
video_sbt = MCF_SLT0_SCNT; /* FIXME: no idea why we need to save the time here */
}
video_address = (vbasehi << 16) | (vbasemid << 8) | vbaselow;
page_number = video_address >> 20; /* calculate a page number */
already_set = (video_tlb & (1 << page_number)); /* already in bitset? */
video_tlb |= page_number; /* set it */
if (! already_set) /* newly set page, need to copy contents */
{
flush_and_invalidate_caches();
dma_memcpy((uint8_t *) video_address + 0x60000000, (uint8_t *) video_address, 0x100000);
/*
* create an MMU TLB entry for the new video page
*/
/*
* first search for an existing entry with our address. If none is found,
* the MMU will propose a new one
*/
MCF_MMU_MMUAR = video_address;
MCF_MMU_MMUOR = 0x106;
NOP();
/*
* take this MMU TLB entry and set it to our video address and page mapping
*/
MCF_MMU_MMUAR = (MCF_MMU_MMUOR >> 16) & 0xffff; /* set TLB id */
MCF_MMU_MMUTR = video_address |
MCF_MMU_MMUTR_ID(sca_page_ID) | /* set video page ID */
MCF_MMU_MMUTR_SG | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
MCF_MMU_MMUDR = (video_address + 0x60000000) | /* physical address */
MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
MCF_MMU_MMUDR_CM(0) | /* writethrough */
MCF_MMU_MMUDR_R | /* readable */
MCF_MMU_MMUDR_W | /* writeable */
MCF_MMU_MMUDR_X; /* executable */
MCF_MMU_MMUOR = 0x10b; /* update TLB entry */
}
/*
* Calculate the effective screen memory size to see if we need to map another page
* in case the new screen spans more than one single page
*/
video_end_address = video_address + (vde - vdb) * vwrap;
if (video_end_address < _STRAM_END)
{
page_number = video_end_address >> 20; /* calculate a page number */
already_set = (video_tlb & (1 << page_number)); /* already in bitset? */
video_tlb |= page_number; /* set it */
if (! already_set) /* newly set page, need to copy contents */
{
flush_and_invalidate_caches();
dma_memcpy((uint8_t *) video_end_address + 0x60000000, (uint8_t *) video_end_address, 0x100000);
/*
* create an MMU TLB entry for the new video page
*/
/*
* first search for an existing entry with our address. If none is found,
* the MMU will propose a new one
*/
MCF_MMU_MMUAR = video_end_address;
MCF_MMU_MMUOR = 0x106;
NOP();
/*
* take this MMU TLB entry and set it to our video address and page mapping
*/
MCF_MMU_MMUAR = (MCF_MMU_MMUOR >> 16) & 0xffff; /* set TLB id */
MCF_MMU_MMUTR = video_end_address |
MCF_MMU_MMUTR_ID(sca_page_ID) | /* set video page ID */
MCF_MMU_MMUTR_SG | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
MCF_MMU_MMUDR = (video_end_address + 0x60000000) | /* physical address */
MCF_MMU_MMUDR_SZ(0) | /* 1 MB page size */
MCF_MMU_MMUDR_CM(0) | /* writethrough */
MCF_MMU_MMUDR_R | /* readable */
MCF_MMU_MMUDR_W | /* writeable */
MCF_MMU_MMUDR_X; /* executable */
MCF_MMU_MMUOR = 0x10b; /* update TLB entry */
}
}
rearm_trigger:
MCF_GPT0_GMS &= ~1; /* rearm trigger */
NOP();
MCF_GPT0_GMS |= 1;
}
#endif /* MACHINE_FIREBEE */

434
Bas_gcc_mmu/sys/mmu.c Normal file
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@@ -0,0 +1,434 @@
#include "mmu.h"
#include "acia.h"
/*
* mmu.c
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* derived from original assembler sources:
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2013 M. Froeschle
*/
#define ACR_BA(x) ((x) & 0xffff0000)
#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
#define ACR_E(x) (((x) & 1) << 15)
#define ACR_S(x) (((x) & 3) << 13)
#define ACR_S_USERMODE 0
#define ACR_S_SUPERVISOR_MODE 1
#define ACR_S_ALL 2
#define ACR_AMM(x) (((x) & 1) << 10)
#define ACR_CM(x) (((x) & 3) << 5)
#define ACR_CM_CACHEABLE_WT 0x0
#define ACR_CM_CACHEABLE_CB 0x1
#define ACR_CM_CACHE_INH_PRECISE 0x2
#define ACR_CM_CACHE_INH_IMPRECISE 0x3
#define ACR_SP(x) (((x) & 1) << 3)
#define ACR_W(x) (((x) & 1) << 2)
#include <stdint.h>
#include "bas_printf.h"
#include "bas_types.h"
#include "MCF5475.h"
#include "pci.h"
#include "cache.h"
#include "util.h"
#if defined(MACHINE_FIREBEE)
#include "firebee.h"
#elif defined(MACHINE_M5484LITE)
#include "m5484l.h"
#elif defined(MACHINE_M54455)
#include "m54455.h"
#else
#error "unknown machine!"
#endif /* MACHINE_FIREBEE */
// #define DEBUG_MMU
#ifdef DEBUG_MMU
#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
#else
#define dbg(format, arg...) do {;} while (0)
#endif /* DEBUG_MMU */
/*
* set ASID register
* saves new value to rt_asid and returns former value
*/
inline uint32_t set_asid(uint32_t value)
{
extern long rt_asid;
uint32_t ret = rt_asid;
__asm__ __volatile__(
"movec %[value],ASID\n\t"
: /* no output */
: [value] "r" (value)
:
);
rt_asid = value;
return ret;
}
/*
* set ACRx register
* saves new value to rt_acrx and returns former value
*/
inline uint32_t set_acr0(uint32_t value)
{
extern uint32_t rt_acr0;
uint32_t ret = rt_acr0;
__asm__ __volatile__(
"movec %[value],ACR0\n\t"
: /* not output */
: [value] "r" (value)
:
);
rt_acr0 = value;
return ret;
}
/*
* set ACRx register
* saves new value to rt_acrx and returns former value
*/
inline uint32_t set_acr1(uint32_t value)
{
extern uint32_t rt_acr1;
uint32_t ret = rt_acr1;
__asm__ __volatile__(
"movec %[value],ACR1\n\t"
: /* not output */
: [value] "r" (value)
:
);
rt_acr1 = value;
return ret;
}
/*
* set ACRx register
* saves new value to rt_acrx and returns former value
*/
inline uint32_t set_acr2(uint32_t value)
{
extern uint32_t rt_acr2;
uint32_t ret = rt_acr2;
__asm__ __volatile__(
"movec %[value],ACR2\n\t"
: /* not output */
: [value] "r" (value)
:
);
rt_acr2 = value;
return ret;
}
/*
* set ACRx register
* saves new value to rt_acrx and returns former value
*/
inline uint32_t set_acr3(uint32_t value)
{
extern uint32_t rt_acr3;
uint32_t ret = rt_acr3;
__asm__ __volatile__(
"movec %[value],ACR3\n\t"
: /* not output */
: [value] "r" (value)
:
);
rt_acr3 = value;
return ret;
}
inline uint32_t set_mmubar(uint32_t value)
{
extern uint32_t rt_mmubar;
uint32_t ret = rt_mmubar;
__asm__ __volatile__(
"movec %[value],MMUBAR\n\t"
: /* no output */
: [value] "r" (value)
: /* no clobber */
);
rt_mmubar = value;
NOP();
return ret;
}
/*
* map a page of memory using virt and phys as addresses with the Coldfire MMU.
*
* Theory of operation: the Coldfire MMU in the Firebee has 64 TLB entries, 32 for data (DTLB), 32 for
* instructions (ITLB). Mappings can either be done locked (normal MMU TLB misses will not consider them
* for replacement) or unlocked (mappings will reallocate using a LRU scheme when the MMU runs out of
* TLB entries). For proper operation, the MMU needs at least two ITLBs and/or four free/allocatable DTLBs
* per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
* LRU algorithm) should be used sparsingly.
*
*
*/
int mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, const struct mmu_map_flags *flags)
{
int size_mask;
switch (sz)
{
case MMU_PAGE_SIZE_1M:
size_mask = 0xfff00000;
break;
case MMU_PAGE_SIZE_8K:
size_mask = 0xffffe000;
break;
case MMU_PAGE_SIZE_4K:
size_mask = 0xfffff000;
break;
case MMU_PAGE_SIZE_1K:
size_mask = 0xfffff800;
break;
default:
dbg("illegal map size %d\r\n", sz);
return 0;
}
/*
* add page to TLB
*/
MCF_MMU_MMUTR = ((int) virt & size_mask) | /* virtual address */
MCF_MMU_MMUTR_ID(flags->page_id) | /* address space id (ASID) */
MCF_MMU_MMUTR_SG | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
NOP();
MCF_MMU_MMUDR = ((int) phys & size_mask) | /* physical address */
MCF_MMU_MMUDR_SZ(sz) | /* page size */
MCF_MMU_MMUDR_CM(flags->cache_mode) |
(flags->access & ACCESS_READ ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
(flags->access & ACCESS_WRITE ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
(flags->access & ACCESS_EXECUTE ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */
(flags->locked ? MCF_MMU_MMUDR_LK : 0);
NOP();
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
NOP();
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
MCF_MMU_MMUOR_ACC | /* access TLB */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys);
return 1;
}
void mmu_init(void)
{
struct mmu_map_flags flags;
extern uint8_t _MMUBAR[];
uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
extern uint8_t _TOS[];
uint32_t TOS = (uint32_t) &_TOS[0];
set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */
/* set data access attributes in ACR0 and ACR1 */
set_acr0(ACR_W(0) | /* read and write accesses permitted */
ACR_SP(0) | /* supervisor and user mode access permitted */
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
ACR_AMM(0) | /* control region > 16 MB */
ACR_S(ACR_S_ALL) | /* match addresses in user and supervisor mode */
ACR_E(1) | /* enable ACR */
#if defined(MACHINE_FIREBEE)
ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */
ACR_BA(0x80000000)); /* (equals area from 3 to 4 GB */
#elif defined(MACHINE_M5484LITE)
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
ACR_BA(0x80000000));
#elif defined(MACHINE_M54455)
ACR_ADMSK(0x7f) |
ACR_BA(0x80000000)); /* FIXME: not determined yet */
#else
#error unknown machine!
#endif /* MACHINE_FIREBEE */
// set_acr1(0x601fc000);
set_acr1(ACR_W(0) |
ACR_SP(0) |
ACR_CM(0) |
#if defined(MACHINE_FIREBEE)
ACR_CM(ACR_CM_CACHEABLE_WT) | /* video RAM on the Firebee */
#elif defined(MACHINE_M5484LITE)
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* Compact Flash on the M548xLITE */
#elif defined(MACHINE_M54455)
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* FIXME: not determined yet */
#else
#error unknown machine!
#endif /* MACHINE_FIREBEE */
ACR_AMM(0) |
ACR_S(ACR_S_ALL) |
ACR_E(1) |
ACR_ADMSK(0x1f) |
ACR_BA(0x60000000));
/* set instruction access attributes in ACR2 and ACR3 */
//set_acr2(0xe007c400);
set_acr2(ACR_W(0) |
ACR_SP(0) |
ACR_CM(0) |
ACR_CM(ACR_CM_CACHEABLE_WT) |
ACR_AMM(1) |
ACR_S(ACR_S_ALL) |
ACR_E(1) |
ACR_ADMSK(0x7) |
ACR_BA(0xe0000000));
/* disable ACR3 */
set_acr3(0x0);
set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */
/* clear all MMU TLB entries */
MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA;
/* create locked TLB entries */
flags.cache_mode = CACHE_COPYBACK;
flags.protection = SV_USER;
flags.page_id = 0;
flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE;
flags.locked = true;
/* 0x0000_0000 - 0x000F_FFFF (first MB of physical memory) locked virt = phys */
mmu_map_page(0x0, 0x0, MMU_PAGE_SIZE_1M, &flags);
#if defined(MACHINE_FIREBEE)
/*
* 0x00d0'0000 - 0x00df'ffff (last megabyte of ST RAM = Falcon video memory) locked ID = 6
* mapped to physical address 0x60d0'0000 (FPGA video memory)
* video RAM: read write execute normal write true
*/
flags.cache_mode = CACHE_WRITETHROUGH;
flags.protection = SV_USER;
flags.page_id = SCA_PAGE_ID;
flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE;
flags.locked = true;
mmu_map_page(0x00d00000, 0x60d00000, MMU_PAGE_SIZE_1M, &flags);
video_tlb = 0x2000; /* set page as video page */
video_sbt = 0x0; /* clear time */
#endif /* MACHINE_FIREBEE */
/*
* Make the TOS (in SDRAM) read-only
* This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
*/
flags.cache_mode = CACHE_COPYBACK;
flags.page_id = 0;
flags.access = ACCESS_READ | ACCESS_EXECUTE;
mmu_map_page(TOS, TOS, MMU_PAGE_SIZE_1M, &flags);
#if defined(MACHINE_FIREBEE)
/*
* Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O
* area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee
*/
flags.cache_mode = CACHE_NOCACHE_PRECISE;
flags.access = ACCESS_WRITE | ACCESS_READ;
mmu_map_page(0x00f00000, 0xfff00000, MMU_PAGE_SIZE_1M, &flags);
#endif /* MACHINE_FIREBEE */
/*
* Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
* virtual address. This is also used (completely) when BaS is in RAM
*/
flags.cache_mode = CACHE_COPYBACK;
flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE;
mmu_map_page(SDRAM_START + SDRAM_SIZE - 0X00200000, SDRAM_START + SDRAM_SIZE - 0X00200000, MMU_PAGE_SIZE_1M, &flags);
/*
* Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same
* virtual address. Used uncached for drivers.
*/
flags.cache_mode = CACHE_NOCACHE_PRECISE;
flags.access = ACCESS_READ | ACCESS_WRITE;
flags.protection = SV_PROTECT;
mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00100000, SDRAM_START + SDRAM_SIZE - 0x00100000, MMU_PAGE_SIZE_1M, &flags);
}
static struct mmu_map_flags flags =
{
.cache_mode = CACHE_COPYBACK,
.protection = SV_USER,
.page_id = 0,
.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE,
.locked = false
};
void mmutr_miss(uint32_t address, uint32_t pc, uint32_t format_status)
{
dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", address, format_status, pc);
// flush_and_invalidate_caches();
switch (address)
{
case keyctl:
case keybd:
/* do something to emulate the IKBD access */
dbg("IKBD access\r\n");
break;
case midictl:
case midi:
/* do something to emulate MIDI access */
dbg("MIDI ACIA access\r\n");
break;
default:
/* add missed page to TLB */
mmu_map_page(address, address, MMU_PAGE_SIZE_1M, &flags);
dbg("DTLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
dbg("ITLB: MCF_MMU_MMUOR = %08x\r\n\r\n", MCF_MMU_MMUOR);
}
}

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Bas_gcc_mmu/sys/startcf.S Normal file
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/*
* This object file must be the first to be linked,
* so it will be placed at the very beginning of the ROM.
*/
.equ MCF_MMU_MMUCR, __MMUBAR + 0
.global _rom_header
.global _rom_entry
.extern _initialize_hardware
.extern _rt_mbar
/* ROM header */
_rom_header:
/* The first long is supposed to be the initial SP.
* We replace it by bra.s to allow running the ROM from the first byte.
* Then we add a fake jmp instruction for pretty disassembly.
*/
bra.s _rom_entry // Short jump to the real entry point
.short 0x4ef9 // Fake jmp instruction
/* The second long is the initial PC */
.long _rom_entry // Real entry point
/* ROM entry point */
_rom_entry:
/* disable interrupts */
move.w #0x2700,SR
/* Initialize MBAR */
move.l #__MBAR,d0
movec d0,MBAR
move.l d0,_rt_mbar
/* mmu off */
move.l #__MMUBAR+1,d0
movec d0,MMUBAR
clr.l d0
move.l d0,MCF_MMU_MMUCR
/* Initialize RAMBARs: locate SRAM and validate it */
move.l #__RAMBAR0 + 0x7,d0 /* supervisor only */
movec d0,RAMBAR0
move.l #__RAMBAR1 + 0x1,d0
movec d0,RAMBAR1
/* set stack pointer to end of SRAM */
lea __SUP_SP,a7
move.l #0,(sp)
/*
* Initialize the processor caches.
* The instruction cache is fully enabled.
* The data cache is enabled, but cache-inhibited by default.
* Later, the MMU will fully activate the data cache for specific areas.
* It is important to enable both caches now, otherwise cpushl would hang.
*/
move.l #0xa50c8120,d0
movec d0,cacr
andi.l #0xfefbfeff,d0 // Clear invalidate bits
move.l d0,_rt_cacr
/* initialize any hardware specific issues */
bra _initialize_hardware

1246
Bas_gcc_mmu/sys/sysinit.c Normal file
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