From 8f88ce86ac6e1cc1c613f85e459e551f8c80590c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 09:50:51 +0000 Subject: [PATCH 001/276] experimental branch to build BaS with a GNU toolchain. branched from Rev 38 of trunk From 5ddf78517943a561c34fcd7c8bce6725daadd227 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 09:54:54 +0000 Subject: [PATCH 002/276] porting BaS to GNU toolchain From 1230361e970da95bf5dc3759efac52629746a0ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 10:01:35 +0000 Subject: [PATCH 003/276] From af998f69620199a64a4646929a560d34eaeaef79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 10:02:16 +0000 Subject: [PATCH 004/276] From 2c47687428d2b5be258ac908d300c8af699112e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 14:08:39 +0000 Subject: [PATCH 005/276] --- BaS_GNU/sources/BaS.c | 264 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 264 insertions(+) create mode 100644 BaS_GNU/sources/BaS.c diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c new file mode 100644 index 0000000..fe925a6 --- /dev/null +++ b/BaS_GNU/sources/BaS.c @@ -0,0 +1,264 @@ +/* + * BaS + * + */ +#include + +#include "MCF5475.h" +#include "MCF5475_SLT.h" +#include "startcf.h" + +extern unsigned long far __SP_AFTER_RESET[]; +extern unsigned long far __Bas_base[]; + + /* imported routines */ +extern int mmu_init(); +extern int mmutr_miss(); +extern int vec_init(); +extern int illegal_table_make(); +extern int cf68k_initialize(); + +/* + * warte_routinen + */ +void warte_10ms(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 1320000; + + while (MCF_SLT_SCNT(0) > target); +} + +void warte_1ms(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 132000; + + while (MCF_SLT_SCNT(0) > target); +} + +void warte_100us(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 13200; + + while (MCF_SLT_SCNT(0) > target); +} + +void warte_50us(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 6600; + + while (MCF_SLT_SCNT(0) > target); +} + +void warte_10us(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 1320; + + while (MCF_SLT_SCNT(0) > target); +} + +void warte_1us(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 132; + + while (MCF_SLT_SCNT(0) > target); +} + +/********************************************************************/ +void BaS(void) +{ + int az_sectors; + int sd_status,i; + uint8_t *src; + uint8_t *dst; + az_sectors = sd_card_init(); + + if(az_sectors>0) + { + sd_card_idle(); + } + + if (DIP_SWITCH & (1 << 6)) + { + copy_firetos(); + } + + MCF_PSC3_PSCTB_8BIT = 'ACPF'; + warte_10ms(); + + MCF_PSC0_PSCTB_8BIT = 'PIC '; + + MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; + MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; + MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; + MCF_PSC0_PSCTB_8BIT = 0x0d0a; + MCF_PSC3_PSCTB_8BIT = 0x01; /* request RTC data */ + + /* copy tos */ + if (DIP_SWITCH & (1 << 6)) + { + /* copy EMUTOS */ + src = (uint8_t *) 0xe0600000L; + while (src < 0xe0700000L) + { + *dst++ = *src++; + } + } + else + { + /* copy FireTOS */ + src = 0xe0400000L; + while (src < 0xe0500000L) + { + *dst++ = *src++; + } + } + + if (!DIP_SWITCH & (1 << 6)) + { + + } + +/***************************************************************/ +/* div inits +/***************************************************************/ +div_inits: + move.b DIP_SWITCH,d0 // dip schalter adresse + btst.b #6,d0 + beq video_setup +// rtc daten, mmu set, etc nur wenn switch 6 = off + lea 0xffff8961,a0 + clr.l d1 + moveq #64,d2 + move.b (a4),d0 + cmp.b #0x81,d0 + bne not_rtc +loop_sr: + move.b (a4),d0 + move.b d1,(a0) + move.b d0,2(a0) + addq.l #1,d1 + cmp.b d1,d2 + bne loop_sr +/* + // Set the NVRAM checksum as invalid + move.b #63,(a0) + move.b 2(a0),d0 + add #1,d0 + move.b d0,2(a0) +*/ +not_rtc: + bsr mmu_init + bsr vec_init + bsr illegal_table_make + +// interrupts + clr.l 0xf0010004 // disable all interrupts + lea MCF_EPORT_EPPAR,a0 + move.w #0xaaa8,(a0) // falling edge all, + +// timer 0 on mit int -> video change ------------------------------------------- + move.l #MCF_GPT_GMS_ICT(1)|MCF_GPT_GMS_IEN|MCF_GPT_GMS_TMS(1),d0 //caputre mit int on rising edge + move.l d0,MCF_GPT0_GMS + moveq.l #0x3f,d0 // max prority interrutp + move.b d0,MCF_INTC_ICR62 // setzen +// ------------------------------------------------- + move.b #0xfe,d0 + move.b d0,0xf0010004 // enable int 1-7 + nop + lea MCF_EPORT_EPIER,a0 + move.b #0xfe,(a0) // int 1-7 on + nop + lea MCF_EPORT_EPFR,a0 + move.b #0xff,(a0) // alle pending interrupts l�schen + nop + lea MCF_INTC_IMRL,a0 + move.l #0xFFFFFF00,(a0) // int 1-7 on + lea MCF_INTC_IMRH,a0 + move.l #0xBFFFFFFE,(a0) // psc3 and timer 0 int on + + move.l #MCF_MMU_MMUCR_EN,d0 + move.l d0,MCF_MMU_MMUCR // mmu on + nop + nop +/********************************************************************/ +/* IDE reset +/********************************************************************/ + lea 0xffff8802,a0 + move.b #14,-2(a0) + move.b #0x80,(a0) + bsr warte_1ms + clr.b (a0) +/********************************************************************/ +/* video setup +/********************************************************************/ +video_setup: + lea 0xf0000410,a0 +// 25MHz + move.l #0x032002ba,(a0)+ // horizontal 640x480 + move.l #0x020c020a,(a0)+ // vertikal 640x480 + move.l #0x0190015d,(a0)+ // horizontal 320x240 + move.l #0x020C020A,(a0)+ // vertikal 320x240 */ +/* +// 32MHz + move.l #0x037002ba,(a0)+ // horizontal 640x480 + move.l #0x020d020a,(a0)+ // vertikal 640x480 + move.l #0x02A001e0,(a0)+ // horizontal 320x240 + move.l #0x05a00160,(a0)+ // vertikal 320x240 +*/ + lea -0x20(a0),a0 + move.l #0x01070002,(a0) // fifo on, refresh on, ddrcs und cke on, video dac on, +/********************************************************************/ +/* memory setup +/********************************************************************/ + lea 0x400,a0 + lea 0x800,a1 +mem_clr_loop: + clr.l (a0)+ + clr.l (a0)+ + clr.l (a0)+ + clr.l (a0)+ + cmp.l a0,a1 + bgt mem_clr_loop + + moveq #0x48,d0 + move.b d0,0xffff8007 +// stram + move.l #0xe00000,d0 // ende stram + move.l d0,0x42e + move.l #0x752019f3,d0 // memvalid + move.l d0,0x420 + move.l #0x237698aa,d0 // memval2 + move.l d0,0x43a + move.l #0x5555aaaa,d0 // memval3 + move.l d0,0x51a +// ttram + move.l #__Bas_base,d0 // ende ttram + move.l d0,0x5a4 + move.l #0x1357bd13,d0 // ramvalid + move.l d0,0x5a8 + +// init acia + moveq #3,d0 + move.b d0,0xfffffc00 + nop + move.b d0,0xfffffc04 + nop + moveq #0x96,d0 + move.b d0,0xfffffc00 + moveq #-1,d0 + nop + move.b d0,0xfffffa0f + nop + move.b d0,0xfffffa11 + nop + +// test auf protect mode --------------------- + move.b DIP_SWITCH,d0 + btst #7,d0 + beq no_protect // nein-> + move.w #0x0700,sr +no_protect: + jmp 0xe00030 + +} +} From e28abbcfa7ba53be5a86ae4b5ae397af60f73c79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 14:11:52 +0000 Subject: [PATCH 006/276] GNU toolchain Makefile --- BaS_GNU/Makefile | 55 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 BaS_GNU/Makefile diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile new file mode 100644 index 0000000..d503b1f --- /dev/null +++ b/BaS_GNU/Makefile @@ -0,0 +1,55 @@ +# +# Makefile for Firebee BaS +# +# requires the GNU toolchain +# either the m68k-atari-mint version which allows creating the binaries +# +# or +# +# the m68k-elf version which also allows to use gdb together with bdm tools for debugging +# + +TCPREFIX=m68k-atari-mint- + +CC=$(TCPREFIX)gcc +LD=$(TCPREFIX)ld + +INCLUDE=-Iinclude +CFLAGS=-mcfv4e -Wno-multichar -O1 -fomit-frame-pointer +#CFLAGS=-mcfv4e -Wno-multichar -S -O3 -fomit-frame-pointer +SRCDIR=sources + +EXEC=bas.hex + +CSRCS= \ + $(SRCDIR)/sysinit.c \ + $(SRCDIR)/BaS.c \ + $(SRCDIR)/sd_card.c \ + $(SRCDIR)/last.c + +ARCS= \ + $(SRCDIR)/startcf.S \ + $(SRCDIR)/mmu.S \ + $(SRCDIR)/exceptions.S \ + $(SRCDIR)/supervisor.S \ + $(SRCDIR)/ewf.S \ + $(SRCDIR)/illegal_instruction.S + +COBJS=$(CSRCS:.c=.o) +AOBJS=$(ASRCS:.S=.o) + +OBJS=$(COBJS) $(SOBJS) + +all: $(EXEC) + +$(EXEC): $(OBJS) + echo "generating executable" + +clean: + rm $(EXEC) *.o + +.c.o: + $(CC) -c $(CFLAGS) $(INCLUDE) $< + +.S.o: + $(CC) -c $(CFLAGS) $(INCLUDE) $< From 76c57259bd863982c8913dadc63d279c6bca2602 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 14:13:16 +0000 Subject: [PATCH 007/276] most of the CodeWarrior assembler converted to C --- BaS_GNU/sources/sysinit.c | 814 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 814 insertions(+) create mode 100644 BaS_GNU/sources/sysinit.c diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c new file mode 100644 index 0000000..da17073 --- /dev/null +++ b/BaS_GNU/sources/sysinit.c @@ -0,0 +1,814 @@ +/* + * File: sysinit.c + * Purpose: Power-on Reset configuration of the Firebee board. + * + * Notes: + * + */ +#include + +#include "MCF5475.h" +#include "startcf.h" + +extern unsigned long _VRAM; +extern unsigned long _Bas_base; +extern unsigned long BaS; +extern unsigned long _BOOT_FLASH[]; +extern int copy_end(); +extern int warte_10us(); +extern int warte_1ms(); +extern int warte_10ms(); +extern int warte_50us(); + +extern unsigned long rt_cacr; + +#define uart_out_word(a) MCF_PSC0_PSCTB_8BIT = (a); + +/* + * init SLICE TIMER 0 + * all = 32.538 sec = 30.736mHz + * BYT0 = 127.1ms/tick = 7.876Hz offset 0 + * BYT1 = 496.5us/tick = 2.014kHz offset 1 + * BYT2 = 1.939us/tick = 515.6kHz offset 2 + * BYT3 = 7.576ns/tick = 132.00MHz offset 3 + * count down!!! 132MHz!!! + */ +void init_slt(void) +{ + uart_out_word('SLT '); + uart_out_word('OK! '); + + MCF_SLT0_STCNT = 0xffffffff; + MCF_SLT0_SCR = 0x05; + + uart_out_word(0x0a0d); +} + +/* + * init GPIO ETC. + */ +void init_gpio(void) +{ + /* + * pad register P.S.:FBCTL and FBCS set correctly at reset + */ + MCF_PAD_PAR_DMA = 0b11111111; /* NORMAL ALS DREQ DACK */ + MCF_PAD_PAR_FECI2CIRQ = 0b1111001111001111; /* FEC0 NORMAL, FEC1 ALS I/O, I2C, #INT5..6 */ + MCF_PAD_PAR_PCIBG = 0b0000001000111111; /* #PCI_BG4=#TBST,#PIC_BG3=I/O,#PCI_BG2..0=NORMAL */ + MCF_PAD_PAR_PCIBR = 0b0000001000111111; /* #PCI_BR4=#INT4,#PIC_BR3=INPUT,#PCI_BR2..0=NORMAL */ + MCF_PAD_PAR_PSC3 = 0b00001100; /* PSC3=TX,RX CTS+RTS=I/O */ + MCF_PAD_PAR_PSC1 = 0b11111100; /* PSC1 NORMAL SERIELL */ + MCF_PAD_PAR_PSC0 = 0b11111100; /* PSC0 NORMAL SERIELL */ + MCF_PAD_PAR_DSPI = 0b0001111111111111; /* DSPI NORMAL */ + MCF_PAD_PAR_TIMER = 0b00101101; /* TIN3..2=#IRQ3..2;TOUT3..2=NORMAL */ +// ALLE OUTPUTS NORMAL LOW + +// ALLE DIR NORMAL INPUT = 0 + MCF_GPIO_PDDR_FEC1L = 0b00011110; /* OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA) */ +} + +/********************************************************************/ +// init serial +/********************************************************************/ + +void init_serial(void) +{ + /* PSC0: SER1 */ + MCF_PSC0_PSCSICR = 0; // UART + MCF_PSC0_PSCCSR = 0xDD; + MCF_PSC0_PSCCTUR = 0x00; + MCF_PSC0_PSCCTLR = 36; // BAUD RATE = 115200 + MCF_PSC0_PSCCR = 0x20; + MCF_PSC0_PSCCR = 0x30; + MCF_PSC0_PSCCR = 0x40; + MCF_PSC0_PSCCR = 0x50; + MCF_PSC0_PSCCR = 0x10; + MCF_PSC0_PSCIMR = 0x8700; + MCF_PSC0_PSCACR = 0x03; + MCF_PSC0_PSCMR1 = 0xb3; + MCF_PSC0_PSCMR2 = 0x07; + MCF_PSC0_PSCRFCR = 0x0F; + MCF_PSC0_PSCTFCR = 0x0F; + MCF_PSC0_PSCRFAR = 0x00F0; + MCF_PSC0_PSCTFAR = 0x00F0; + MCF_PSC0_PSCOPSET = 0x01; + MCF_PSC0_PSCCR = 0x05; + + /* PSC3: PIC */ + MCF_PSC3_PSCSICR = 0; // UART + MCF_PSC3_PSCCSR = 0xDD; + MCF_PSC3_PSCCTUR = 0x00; + MCF_PSC3_PSCCTLR = 36; // BAUD RATE = 115200 + MCF_PSC3_PSCCR = 0x20; + MCF_PSC3_PSCCR = 0x30; + MCF_PSC3_PSCCR = 0x40; + MCF_PSC3_PSCCR = 0x50; + MCF_PSC3_PSCCR = 0x10; + MCF_PSC3_PSCIMR = 0x0200; // receiver interrupt enable + MCF_PSC3_PSCACR = 0x03; + MCF_PSC3_PSCMR1 = 0xb3; + MCF_PSC3_PSCMR2 = 0x07; + MCF_PSC3_PSCRFCR = 0x0F; + MCF_PSC3_PSCTFCR = 0x0F; + MCF_PSC3_PSCRFAR = 0x00F0; + MCF_PSC3_PSCTFAR = 0x00F0; + MCF_PSC3_PSCOPSET = 0x01; + MCF_PSC3_PSCCR = 0x05; + MCF_INTC_ICR32 = 0x3F; //MAXIMALE PRIORITY/**********/ + + uart_out_word('SERI'); + uart_out_word('AL O'); + uart_out_word('K! '); + uart_out_word(0x0a0d); +} + +/********************************************************************/ +/* Initialize DDR DIMMs on the EVB board */ +/********************************************************************/ + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ +void init_ddram(void) +{ + MCF_PSC0_PSCTB_8BIT = 'DDRA'; + if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) { + /* Basic configuration and initialization */ + MCF_SDRAMC_SDRAMDS = 0x000002AA; // SDRAMDS configuration + MCF_SDRAMC_CS0CFG = 0x0000001A; // SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) + MCF_SDRAMC_CS1CFG = 0x0800001A; // SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) + MCF_SDRAMC_CS2CFG = 0x1000001A; // SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF) + MCF_SDRAMC_CS3CFG = 0x1800001A; // SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +// MCF_SDRAMC_SDCFG1 = 0x53722938; // SDCFG1 + MCF_SDRAMC_SDCFG1 = 0x73622830; // SDCFG1 +// MCF_SDRAMC_SDCFG2 = 0x24330000; // SDCFG2 + MCF_SDRAMC_SDCFG2 = 0x46770000; // SDCFG2 +// MCF_SDRAMC_SDCR = 0xE10F0002; // SDCR + IPALL + MCF_SDRAMC_SDCR = 0xE10D0002; // SDCR + IPALL + MCF_SDRAMC_SDMR = 0x40010000; // SDMR (write to LEMR) +// MCF_SDRAMC_SDMR = 0x05890000; // SDRM (write to LMR) + MCF_SDRAMC_SDMR = 0x048D0000; // SDRM (write to LMR) +// MCF_SDRAMC_SDCR = 0xE10F0002; // SDCR + IPALL + MCF_SDRAMC_SDCR = 0xE10D0002; // SDCR + IPALL +// MCF_SDRAMC_SDCR = 0xE10F0004; // SDCR + IREF (first refresh) + MCF_SDRAMC_SDCR = 0xE10D0004; // SDCR + IREF (first refresh) +// MCF_SDRAMC_SDCR = 0xE10F0004; // SDCR + IREF (second refresh) + MCF_SDRAMC_SDCR = 0xE10D0004; // SDCR + IREF (second refresh) +/// MCF_SDRAMC_SDMR = 0x01890000; // SDMR (write to LMR) + MCF_SDRAMC_SDMR = 0x008D0000; // SDMR (write to LMR) +// MCF_SDRAMC_SDCR = 0x710F0F00; // SDCR (lock SDMR and enable refresh) + MCF_SDRAMC_SDCR = 0x710D0F00; // SDCR (lock SDMR and enable refresh) + } + MCF_PSC0_PSCTB_8BIT = 'M OK'; + MCF_PSC0_PSCTB_8BIT = '! '; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} + +/* + * init FB_CSx + */ +void init_fbcs() +{ + MCF_PSC0_PSCTB_8BIT = 'FBCS'; + + /* Flash */ + MCF_FBCS0_CSAR = 0xE0000000; // FLASH ADRESS + MCF_FBCS0_CSCR = 0x00001180; // 16 bit 4ws aa + MCF_FBCS0_CSMR = 0x007F0001; // 8MB on + + MCF_FBCS1_CSAR = 0xFFF00000; // ATARI I/O ADRESS + MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT + | MCF_FBCS_CSCR_WS(8) // DEFAULT 8WS + | MCF_FBCS_CSCR_AA; // AA + MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V); + + MCF_FBCS2_CSAR = 0xF0000000; // NEUER I/O ADRESS-BEREICH + MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT + | MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS + | MCF_FBCS_CSCR_AA; // AA + MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M // F000'0000-F7FF'FFFF + | MCF_FBCS_CSMR_V); + + MCF_FBCS3_CSAR = 0xF8000000; // NEUER I/O ADRESS-BEREICH + MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT + | MCF_FBCS_CSCR_AA; // AA + MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M // F800'0000-FBFF'FFFF + | MCF_FBCS_CSMR_V); + + MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BENÃœTZT, DECODE DIREKT AUF DEM FPGA + MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT + | MCF_FBCS_CSCR_BSTR // BURST READ ENABLE + | MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE + MCF_FBCS4_CSMR = (MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF + | MCF_FBCS_CSMR_V); + + MCF_PSC0_PSCTB_8BIT = ' OK!'; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} + +#ifdef _NOT_USED_ +/* + * FPGA LADEN + */ +void init_fpga(void) +{ + uart_out_word('FPGA'); + + MCF_GPIO_PODR_FEC1L |= (1 << 1); + MCF_GPIO_PODR_FEC1L |= (1 << 2); + + while ((!MCF_GPIO_PPDSDR_FEC1L & (1 << 0)) && (!MCF_GPIO_PDDSDR_FEC1L & (1 << 5))); + + warte_10us(); + MCF_GPIO_PODR_FEC1L |= (1 << 2); + warte_10us(); + + start = 0xe0700000; + + + asm { + lea MCF_GPIO_PODR_FEC1L, a1 // register adresse:write + lea MCF_GPIO_PPDSDR_FEC1L, a2 // reads + bclr #1,(a1) // clk auf low + bclr #2,(a1) // #config=low + test_nSTATUS: + btst #0,(a2) // nSTATUS==0 + bne test_nSTATUS // nein-> + btst #5,(a2) // conf done==0 + bne test_nSTATUS // nein-> + jsr warte_10us // warten + bset #2,(a1) // #config=high + jsr warte_10us // warten + test_STATUS: + btst #0,(a2) // status high? + beq test_STATUS // nein-> + jsr warte_10us // warten + lea 0xE0700000, a0 // startadresse fpga daten + word_send_loop: + cmp.l #0xE0800000,a0 + bgt fpga_error + move.b (a0)+, d0 // 32 bit holen + moveq #8,d1 // 32 bit ausgeben + bit_send_loop: + lsr.l +#1,d0 // bit rausschieben + bcs bit_is_1 bclr +#3,(a1) + bra bit_send bit_is_1: + bset +#3,(a1) + bit_send: + bset +#1,(a1) // clock=high + bclr +#1,(a1) // clock=low + subq.l +#1,d1 + bne bit_send_loop // wiederholen bis fertig + btst +#5,(a2) // fpga fertig, conf_done=high? + beq word_send_loop // nein, next word-> + move.l +#4000,d1 + overclk: + bset +#1,(a1) // clock=high + nop bclr +#1,(a1) // clock=low + subq.l +#1,d1 + bne overclk // weiter bis fertig + bra init_fpga_end +//--------------------------------------------------------- + wait_pll: + lea MCF_SLT0_SCNT, a3 move.l(a3), d0 move.l +#100000,d6 // ca 1ms + wait_pll_loop: + tst.w(a1) + bpl wait_pll_ok move.l(a3), d1 sub.l d0, d1 add.l d6, d1 bpl wait_pll_loop wait_pll_ok: + rts +// fertig + fpga_error: + } + MCF_PSC0_PSCTB_8BIT = ' NOT'; init_fpga_end: + MCF_PSC0_PSCTB_8BIT = ' OK!'; MCF_PSC0_PSCTB_8BIT = 0x0a0d; +// init pll + MCF_PSC0_PSCTB_8BIT = 'PLL '; asm { + lea 0xf0000600, a0 lea 0xf0000800, a1 bsr wait_pll move.w +#27,0x48(a0) // loopfilter r + bsr wait_pll move.w +#1,0x08(a0) // charge pump I + bsr wait_pll move.w +#12,0x0(a0) // N counter high = 12 + bsr wait_pll move.w +#12,0x40(a0) // N counter low = 12 + bsr wait_pll move.w +#1,0x114(a0) // ck1 bypass + bsr wait_pll move.w +#1,0x118(a0) // ck2 bypass + bsr wait_pll move.w +#1,0x11c(a0) // ck3 bypass + bsr wait_pll move.w +#1,0x10(a0) // ck0 high = 1 + bsr wait_pll move.w +#1,0x50(a0) // ck0 low = 1 + bsr wait_pll move.w +#1,0x144(a0) // M odd division + bsr wait_pll move.w +#1,0x44(a0) // M low = 1 + bsr wait_pll move.w +#145,0x04(a0) // M high = 145 = 146MHz + bsr wait_pll clr.b(a1) // set + } + MCF_PSC0_PSCTB_8BIT = 'SET!'; MCF_PSC0_PSCTB_8BIT = 0x0a0d;} + +/* + * INIT VIDEO DDR RAM + */ + +void init_video_ddr(void) { + asm { + +// init video ram + moveq.l #0xB,d0 + move.w d0, 0xF0000400 //set cke=1, cs=1 config=1 + nop lea __VRAM, a0 //zeiger auf video ram + nop move.l #0x00050400,(a0) //IPALL + nop move.l #0x00072000,(a0) //load EMR pll on + nop move.l #0x00070122,(a0) //load MR: reset pll, cl=2 BURST=4lw + nop move.l #0x00050400,(a0) //IPALL + nop move.l #0x00060000,(a0) //auto refresh + nop move.l #0x00060000,(a0) //auto refresh + nop move.l #0000070022,(a0) //load MR dll on + nop move.l #0x01070002,d0 // fifo on, refresh on, ddrcs und cke on, video dac on, + move.l d0, 0xf0000400} + } + +/********************************************************************/ + /* video mit auflösung 1280x1000 137MHz /* + /******************************************************************* */ + +void video_1280_1024(void) { + extern int wait_pll; + + asm { + // SPEICHER FÃœLLEM + //testmuster 1 + lea __VRAM, a2 + lea __VRAM + 0x600000,a3 + clr.l d0 + move.l #0x1000102,d1 + loop5: + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + move.l d0, (a2) + + add.l d1, d0 +flo6: + cmp.l a2, a3 + bgt loop5 +// screen setzen +//horizontal 1280 + lea 0xffff8282, a0 move.w +#1800,(a0)+ + move.w +#1380,(a0)+ + move.w +#99,(a0)+ + move.w +#100,(a0)+ + move.w +#1379,(a0)+ + move.w +#1500,(a0) +//vertical 1024 + lea 0xffff82a2, a0 move.w +#1150,(a0)+ + move.w +#1074,(a0)+ + move.w +#49,(a0)+ + move.w +#50,(a0)+ + move.w +#1073,(a0)+ + move.w +#1100,(a0)+ +// acp video on + move.l +#0x01070207,d0 + move.l d0, 0xf0000400 +// clut setzen + lea 0xf0000000, a0 move.l +#0xffffffff,(a0)+ + move.l +#0xff,(a0)+ + move.l +#0xff00,(a0)+ + move.l +#0xff0000,(a0) +// halt + } + + } + +#endif + +#define PCI_MEMORY_OFFSET (0x80000000) +#define PCI_MEMORY_SIZE (0x40000000) +#define PCI_IO_OFFSET (0xD0000000) +#define PCI_IO_SIZE (0x10000000) + +/* + * INIT PCI + */ +void init_PCI(void) { + MCF_PSC0_PSCTB_8BIT = 'PCI '; + + MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI + + MCF_PCIARB_PACR_EXTMPRI(0x1F) + + MCF_PCIARB_PACR_INTMINTEN + + MCF_PCIARB_PACR_EXTMINTEN(0x1F); + + // Setup burst parameters + MCF_PCI_PCICR1 = MCF_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32); + MCF_PCI_PCICR2 = MCF_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16); + + // Turn on error signaling + MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_TAE * MCF_PCI_PCIICR_REE + 32; + MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE; + + /* Configure Initiator Windows */ + /* initiator window 0 base / translation adress register */ + MCF_PCI_PCIIW0BTAR = PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE -1) >> 8) & 0xffff0000; + + /* initiator window 1 base / translation adress register */ + MCF_PCI_PCIIW1BTAR = PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8) & 0xffff0000; + + /* initiator window 2 base / translation address register */ + MCF_PCI_PCIIW2BTAR = 0L; /* not used */ + + /* initiator window configuration register */ + MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE + MCF_PCI_PCIIWCR_WINCTRL1_IO; + + /* reset PCI devices */ + MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR; + + MCF_PSC0_PSCTB_8BIT = 'OK! '; + MCF_PSC0_PSCTB_8BIT = 0x0d0a; +} + + +/* + * test UPC720101 (USB) + */ + +void test_upd720101(void) +{ + MCF_PSC0_PSCTB_8BIT = 'NEC '; + + /* select UPD720101 AD17 */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E + + MCF_PCI_PCICAR_DEVNUM(17) + + MCF_PCI_PCICAR_FUNCNUM(0) + + MCF_PCI_PCICAR_DWORD(0); + + if (* (uint32_t *) PCI_IO_OFFSET == 0x33103500) + { + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E + + MCF_PCI_PCICAR_DEVNUM(17) + + MCF_PCI_PCICAR_FUNCNUM(0) + + MCF_PCI_PCICAR_DWORD(57); + + * (uint8_t *) PCI_IO_OFFSET = 0x20; + } + else + { + MCF_PSC0_PSCTB_8BIT = 'NOT '; + + MCF_PCI_PCICAR = MCF_PCI_PCICAR_DEVNUM(17) + + MCF_PCI_PCICAR_FUNCNUM(0) + + MCF_PCI_PCICAR_DWORD(57); + } + MCF_PSC0_PSCTB_8BIT = 'OK! '; + MCF_PSC0_PSCTB_8BIT = 0x0d0a; +} + +/* + * TFP410 (vdi) einschalten /* + */ +void vdi_on(void) { + uint8 RBYT; + uint8 DBYT; + int versuche; + int startzeit; + + MCF_PSC0_PSCTB_8BIT = 'DVI '; + + MCF_I2C_I2FDR = 0x3c; // 100kHz standard + versuche = 0; + +loop_i2c: + if (versuche++ > 10) + goto next; + + MCF_I2C_I2ICR = 0x0; + MCF_I2C_I2CR = 0x0; + MCF_I2C_I2CR = 0xA; + RBYT = MCF_I2C_I2DR; + MCF_I2C_I2SR = 0x0; + MCF_I2C_I2CR = 0x0; + MCF_I2C_I2ICR = 0x01; + MCF_I2C_I2CR = 0xb0; + MCF_I2C_I2DR = 0x7a; // ADRESSE TFP410 + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); // warten auf fertig + + MCF_I2C_I2SR &= 0xfd; // clear bit + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + goto loop_i2c; // ack erhalten? -> nein + +tpf_410_ACK_OK: + MCF_I2C_I2DR = 0x00; // SUB ADRESS 0 + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); + + MCF_I2C_I2SR &= 0xfd; + MCF_I2C_I2CR |= 0x4; // repeat start + MCF_I2C_I2DR = 0x7b; // beginn read + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); // warten auf fertig + + MCF_I2C_I2SR &= 0xfd; // clear bit + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + goto loop_i2c; // ack erhalten? -> nein + + MCF_I2C_I2CR &= 0xef; // switch to rx + DBYT = MCF_I2C_I2DR; // dummy read + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); + + MCF_I2C_I2SR &= 0xfd; + + MCF_I2C_I2CR |= 0x08; // txak=1 + RBYT = MCF_I2C_I2DR; + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); + + MCF_I2C_I2SR &= 0xfd; + MCF_I2C_I2CR = 0x80; // stop + + DBYT = MCF_I2C_I2DR; // dummy read + + if (RBYT != 0x4c) + goto loop_i2c; + +i2c_ok: + MCF_I2C_I2CR = 0x0; // stop + MCF_I2C_I2SR = 0x0; // clear sr + + while ((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)); // wait auf bus free + + MCF_I2C_I2CR = 0xb0; // on tx master + MCF_I2C_I2DR = 0x7A; + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); // warten auf fertig + + MCF_I2C_I2SR &= 0xfd; // clear bit + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + goto loop_i2c; // ack erhalten? -> nein + + MCF_I2C_I2DR = 0x08; // SUB ADRESS 8 + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); + + MCF_I2C_I2SR &= 0xfd; + MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable + + MCF_I2C_I2CR = 0x80; // stop + DBYT = MCF_I2C_I2DR; // dummy read + MCF_I2C_I2SR = 0x0; // clear sr + + while ((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)); // wait auf bus free + + MCF_I2C_I2CR = 0xb0; + MCF_I2C_I2DR = 0x7A; + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); // warten auf fertig + + MCF_I2C_I2SR &= 0xfd; // clear bit + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + goto loop_i2c; // ack erhalten? -> nein + + MCF_I2C_I2DR = 0x08; // SUB ADRESS 8 + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); + + MCF_I2C_I2SR &= 0xfd; + MCF_I2C_I2CR |= 0x4; // repeat start + MCF_I2C_I2DR = 0x7b; // beginn read + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); // warten auf fertig + + MCF_I2C_I2SR &= 0xfd; // clear bit + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + goto loop_i2c; // ack erhalten? -> nein + + MCF_I2C_I2CR &= 0xef; // switch to rx + DBYT = MCF_I2C_I2DR; // dummy read + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); + + MCF_I2C_I2SR &= 0xfd; + MCF_I2C_I2CR |= 0x08; // txak=1 + + warte_50us(); + + RBYT = MCF_I2C_I2DR; + + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); + + MCF_I2C_I2SR &= 0xfd; + MCF_I2C_I2CR = 0x80; // stop + + DBYT = MCF_I2C_I2DR; // dummy read + + if (RBYT != 0xbf) + goto loop_i2c; + goto dvi_ok; +next: + MCF_PSC0_PSCTB_8BIT = 'NOT '; +dvi_ok: + MCF_PSC0_PSCTB_8BIT = 'OK! '; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; + MCF_I2C_I2CR = 0x0; // i2c off +} + + +/* + * AC97 + */ +void init_ac97(void) { + // PSC2: AC97 ---------- + int i; + int k; + int zm; + int x; + int va; + int vb; + int vc; + + MCF_PSC0_PSCTB_8BIT = 'AC97'; + MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS // PSC2=TX,RX BCLK,CTS->AC'97 + | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK + | MCF_PAD_PAR_PSC2_PAR_TXD2 + | MCF_PAD_PAR_PSC2_PAR_RXD2; + MCF_PSC2_PSCMR1 = 0x0; + MCF_PSC2_PSCMR2 = 0x0; + MCF_PSC2_PSCIMR = 0x0300; + MCF_PSC2_PSCSICR = 0x03; //AC97 + MCF_PSC2_PSCRFCR = 0x0f000000; + MCF_PSC2_PSCTFCR = 0x0f000000; + MCF_PSC2_PSCRFAR = 0x00F0; + MCF_PSC2_PSCTFAR = 0x00F0; + + for (zm = 0; zm < 100000; zm++) // wiederholen bis synchron + { + MCF_PSC2_PSCCR = 0x20; + MCF_PSC2_PSCCR = 0x30; + MCF_PSC2_PSCCR = 0x40; + MCF_PSC2_PSCCR = 0x05; + + // MASTER VOLUME -0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x02000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + + for (i = 2; i < 13; i++) + { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + + // read register + MCF_PSC2_PSCTB_AC97 = 0xc0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x82000000; //SLOT1:master volume + + for (i = 2; i < 13; i++) + { + MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0 + } + warte_50us(); + + va = MCF_PSC2_PSCTB_AC97; + if ((va & 0x80000fff) == 0x80000800) { + vb = MCF_PSC2_PSCTB_AC97; + vc = MCF_PSC2_PSCTB_AC97; + if ((va & 0xE0000fff) == 0xE0000800 & vb == 0x02000000 & vc == 0x00000000) { + goto livo;} + } + } + MCF_PSC0_PSCTB_8BIT = ' NOT'; +livo: + // AUX VOLUME ->-0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16 + MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME + for (i = 3; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + + // line in VOLUME +12dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 2; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + // cd in VOLUME 0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 2; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + // mono out VOLUME 0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 3; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF + MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data +ac97_end: + MCF_PSC0_PSCTB_8BIT = ' OK!'; MCF_PSC0_PSCTB_8BIT = 0x0a0d; +} + +void __initialize_hardware(void) { +_init_hardware: +asm( + "move.l #0x000C8120,D0\n\t" + "move.l D0,rt_cacr\n\t" + "movec D0,CACR\n\t" + "nop\n\t" + ); + + init_gpio(); + init_serial(); + init_slt(); + init_fbcs(); + init_ddram(); + + /* do not initialize ports if DIP switch 5 = on */ + if (DIP_SWITCH & (1 << 6)) + init_PCI(); + + init_fpga(); + init_video_ddr(); + vdi_on(); + + /* do not initialize ports if DIP switch 5 = on */ + if (DIP_SWITCH & (1 << 6)) { + test_upd720101(); + /* video_1280_1024(); */ + init_ac97(); + } + + asm volatile( + "lea copy_start,A0\n\t" + "lea BaS,A1\n\t" + "sub.l A0,A1\n\t" + "move.l #__Bas_base,A2\n\t" + "move.l A2,A3\n\t" + "add.l A1,A3\n\t" + "lea copy_end,A4\n\t" +"BaS_copy_loop: /* copy 16 bytes per turn */\n\t" + "move.l (A0)+,(A2)+\n\t" + "move.l (A0)+,(A2)+\n\t" + "move.l (A0)+,(A2)+\n\t" + "move.l (A0)+,(A2)+\n\t" + "cmp.l A4,A0\n\t" + "blt BaS_copy_loop\n\t" +"\n\t" + "intouch A3\n\t" /* we'd better update caches to contain the data we just copied */ + "jmp (A3)\n\t" +"copy_start:\n\t" + "nop\n\t" + : :); +} From 9f47161568bc3e6f5f78491a4cfeb439532c86dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 14:14:02 +0000 Subject: [PATCH 008/276] --- BaS_GNU/sources/sysinit.h | 87 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 BaS_GNU/sources/sysinit.h diff --git a/BaS_GNU/sources/sysinit.h b/BaS_GNU/sources/sysinit.h new file mode 100644 index 0000000..70bc6da --- /dev/null +++ b/BaS_GNU/sources/sysinit.h @@ -0,0 +1,87 @@ +/* + * File: sysinit.h + * Purpose: COLDARI Power-on Reset configuration + * + * Notes: + * + */ + +#ifndef __SYSINIT_H__ +#define __SYSINIT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if ENABLE_UART_SUPPORT==1 + +/* + * System Bus Clock Info + */ +// 5475EVB has 133Mhz system clock +#define SYSTEM_CLOCK_KHZ 133000 /* system bus frequency in kHz */ + + +/*** + * Serial Port Info + * The baud rate to be : 19200 + * Data bits : 8 + * Parity : None + * Stop Bits : 1 + * Flow Control : None + */ +#define TERMINAL_PORT (0) /* PSC channel used as terminal */ +#define TERMINAL_BAUD kBaud19200 /* 115200 */ +#undef HARDWARE_FLOW_CONTROL /* Flow control ON or OFF */ +#endif + +/*** + * Board Memory map definitions from linker command files: + * __SDRAM,__SDRAM_SIZE, __FLASH, __FLASH_SIZE linker + * symbols must be defined in the linker command file. + */ +extern __declspec(system) uint8 __BOOT_FLASH[]; +extern __declspec(system) uint8 __BOOT_FLASH_SIZE[]; + +extern __declspec(system) uint8 __SDRAM[]; +extern __declspec(system) uint8 __SDRAM_SIZE[]; + + +#define BOOT_FLASH_ADDRESS (uint32)__BOOT_FLASH +#define BOOT_FLASH_SIZE (uint32)__BOOT_FLASH_SIZE + +#define SDRAM_ADDRESS (uint32)__SDRAM +#define SDRAM_SIZE (uint32)__SDRAM_SIZE + + + + +/********************************************************************/ +/* __initialize_hardware Startup code routine + * + * __initialize_hardware is called by the startup code right after reset, + * with interrupt disabled and SP pre-set to a valid memory area. + * Here you should initialize memory and some peripherics; + * at this point global variables are not initialized yet. + * The startup code will initialize SP on return of this function. + */ +void __initialize_hardware(void); + +/********************************************************************/ +/* __initialize_system Startup code routine + * + * __initialize_system is called by the startup code when all languages + * specific initialization are done to allow additional hardware setup. + */ +void __initialize_system(void); + + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSINIT_H__ */ + + From fd71b22cb54852b553631dd6e4254b70ad64356c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 14:28:14 +0000 Subject: [PATCH 009/276] added include dir contents --- BaS_GNU/include/MCF5475.h | 93 +++++ BaS_GNU/include/MCF5475_CLOCK.h | 47 +++ BaS_GNU/include/MCF5475_CTM.h | 76 ++++ BaS_GNU/include/MCF5475_DMA.h | 202 +++++++++ BaS_GNU/include/MCF5475_DSPI.h | 150 +++++++ BaS_GNU/include/MCF5475_EPORT.h | 123 ++++++ BaS_GNU/include/MCF5475_FBCS.h | 100 +++++ BaS_GNU/include/MCF5475_FEC.h | 680 +++++++++++++++++++++++++++++++ BaS_GNU/include/MCF5475_GPIO.h | 543 ++++++++++++++++++++++++ BaS_GNU/include/MCF5475_GPT.h | 100 +++++ BaS_GNU/include/MCF5475_I2C.h | 69 ++++ BaS_GNU/include/MCF5475_INTC.h | 331 +++++++++++++++ BaS_GNU/include/MCF5475_MMU.h | 77 ++++ BaS_GNU/include/MCF5475_PAD.h | 233 +++++++++++ BaS_GNU/include/MCF5475_PCI.h | 376 +++++++++++++++++ BaS_GNU/include/MCF5475_PCIARB.h | 43 ++ BaS_GNU/include/MCF5475_PSC.h | 527 ++++++++++++++++++++++++ BaS_GNU/include/MCF5475_SDRAMC.h | 106 +++++ BaS_GNU/include/MCF5475_SEC.h | 398 ++++++++++++++++++ BaS_GNU/include/MCF5475_SIU.h | 52 +++ BaS_GNU/include/MCF5475_SLT.h | 59 +++ BaS_GNU/include/MCF5475_SRAM.h | 62 +++ BaS_GNU/include/MCF5475_USB.h | 554 +++++++++++++++++++++++++ BaS_GNU/include/MCF5475_XLB.h | 101 +++++ 24 files changed, 5102 insertions(+) create mode 100644 BaS_GNU/include/MCF5475.h create mode 100644 BaS_GNU/include/MCF5475_CLOCK.h create mode 100644 BaS_GNU/include/MCF5475_CTM.h create mode 100644 BaS_GNU/include/MCF5475_DMA.h create mode 100644 BaS_GNU/include/MCF5475_DSPI.h create mode 100644 BaS_GNU/include/MCF5475_EPORT.h create mode 100644 BaS_GNU/include/MCF5475_FBCS.h create mode 100644 BaS_GNU/include/MCF5475_FEC.h create mode 100644 BaS_GNU/include/MCF5475_GPIO.h create mode 100644 BaS_GNU/include/MCF5475_GPT.h create mode 100644 BaS_GNU/include/MCF5475_I2C.h create mode 100644 BaS_GNU/include/MCF5475_INTC.h create mode 100644 BaS_GNU/include/MCF5475_MMU.h create mode 100644 BaS_GNU/include/MCF5475_PAD.h create mode 100644 BaS_GNU/include/MCF5475_PCI.h create mode 100644 BaS_GNU/include/MCF5475_PCIARB.h create mode 100644 BaS_GNU/include/MCF5475_PSC.h create mode 100644 BaS_GNU/include/MCF5475_SDRAMC.h create mode 100644 BaS_GNU/include/MCF5475_SEC.h create mode 100644 BaS_GNU/include/MCF5475_SIU.h create mode 100644 BaS_GNU/include/MCF5475_SLT.h create mode 100644 BaS_GNU/include/MCF5475_SRAM.h create mode 100644 BaS_GNU/include/MCF5475_USB.h create mode 100644 BaS_GNU/include/MCF5475_XLB.h diff --git a/BaS_GNU/include/MCF5475.h b/BaS_GNU/include/MCF5475.h new file mode 100644 index 0000000..8feab2d --- /dev/null +++ b/BaS_GNU/include/MCF5475.h @@ -0,0 +1,93 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_H__ +#define __MCF5475_H__ + + +/********************************************************************/ +/* + * The basic data types + */ + +typedef unsigned char uint8; /* 8 bits */ +typedef unsigned short int uint16; /* 16 bits */ +typedef unsigned long int uint32; /* 32 bits */ + +typedef signed char int8; /* 8 bits */ +typedef signed short int int16; /* 16 bits */ +typedef signed long int int32; /* 32 bits */ + +typedef volatile uint8 vuint8; /* 8 bits */ +typedef volatile uint16 vuint16; /* 16 bits */ +typedef volatile uint32 vuint32; /* 32 bits */ + +#ifdef __cplusplus +extern "C" { +#endif + +#pragma define_section system ".system" far_absolute RW + +/*** + * MCF5475 Derivative Memory map definitions from linker command files: + * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE + * linker symbols must be defined in the linker command file. + */ + +extern __declspec(system) uint8 __MBAR[]; +extern __declspec(system) uint8 __MMUBAR[]; +extern __declspec(system) uint8 __RAMBAR0[]; +extern __declspec(system) uint8 __RAMBAR0_SIZE[]; +extern __declspec(system) uint8 __RAMBAR1[]; +extern __declspec(system) uint8 __RAMBAR1_SIZE[]; + +#define MBAR_ADDRESS (uint32)__MBAR +#define MMUBAR_ADDRESS (uint32)__MMUBAR +#define RAMBAR0_ADDRESS (uint32)__RAMBAR0 +#define RAMBAR0_SIZE (uint32)__RAMBAR0_SIZE +#define RAMBAR1_ADDRESS (uint32)__RAMBAR1 +#define RAMBAR1_SIZE (uint32)__RAMBAR1_SIZE + + +#include "MCF5475_SIU.h" +#include "MCF5475_MMU.h" +#include "MCF5475_SDRAMC.h" +#include "MCF5475_XLB.h" +#include "MCF5475_CLOCK.h" +#include "MCF5475_FBCS.h" +#include "MCF5475_INTC.h" +#include "MCF5475_GPT.h" +#include "MCF5475_SLT.h" +#include "MCF5475_GPIO.h" +#include "MCF5475_PAD.h" +#include "MCF5475_PCI.h" +#include "MCF5475_PCIARB.h" +#include "MCF5475_EPORT.h" +#include "MCF5475_CTM.h" +#include "MCF5475_DMA.h" +#include "MCF5475_PSC.h" +#include "MCF5475_DSPI.h" +#include "MCF5475_I2C.h" +#include "MCF5475_FEC.h" +#include "MCF5475_USB.h" +#include "MCF5475_SRAM.h" +#include "MCF5475_SEC.h" + +#ifdef __cplusplus +} +#endif + + +#endif /* __MCF5475_H__ */ diff --git a/BaS_GNU/include/MCF5475_CLOCK.h b/BaS_GNU/include/MCF5475_CLOCK.h new file mode 100644 index 0000000..96e173f --- /dev/null +++ b/BaS_GNU/include/MCF5475_CLOCK.h @@ -0,0 +1,47 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CLOCK_H__ +#define __MCF5475_CLOCK_H__ + + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SPCR (*(vuint32*)(&__MBAR[0x300])) + + +/* Bit definitions and macros for MCF_CLOCK_SPCR */ +#define MCF_CLOCK_SPCR_MEMEN (0x1) +#define MCF_CLOCK_SPCR_PCIEN (0x2) +#define MCF_CLOCK_SPCR_FBEN (0x4) +#define MCF_CLOCK_SPCR_CAN0EN (0x8) +#define MCF_CLOCK_SPCR_DMAEN (0x10) +#define MCF_CLOCK_SPCR_FEC0EN (0x20) +#define MCF_CLOCK_SPCR_FEC1EN (0x40) +#define MCF_CLOCK_SPCR_USBEN (0x80) +#define MCF_CLOCK_SPCR_PSCEN (0x200) +#define MCF_CLOCK_SPCR_CAN1EN (0x800) +#define MCF_CLOCK_SPCR_CRYENA (0x1000) +#define MCF_CLOCK_SPCR_CRYENB (0x2000) +#define MCF_CLOCK_SPCR_COREN (0x4000) +#define MCF_CLOCK_SPCR_PLLK (0x80000000) + + +#endif /* __MCF5475_CLOCK_H__ */ diff --git a/BaS_GNU/include/MCF5475_CTM.h b/BaS_GNU/include/MCF5475_CTM.h new file mode 100644 index 0000000..1b516fd --- /dev/null +++ b/BaS_GNU/include/MCF5475_CTM.h @@ -0,0 +1,76 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CTM_H__ +#define __MCF5475_CTM_H__ + + +/********************************************************************* +* +* Comm Timer Module (CTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CTM_CTCR0 (*(vuint32*)(&__MBAR[0x7F00])) +#define MCF_CTM_CTCR1 (*(vuint32*)(&__MBAR[0x7F04])) +#define MCF_CTM_CTCR2 (*(vuint32*)(&__MBAR[0x7F08])) +#define MCF_CTM_CTCR3 (*(vuint32*)(&__MBAR[0x7F0C])) +#define MCF_CTM_CTCR4 (*(vuint32*)(&__MBAR[0x7F10])) +#define MCF_CTM_CTCR5 (*(vuint32*)(&__MBAR[0x7F14])) +#define MCF_CTM_CTCR6 (*(vuint32*)(&__MBAR[0x7F18])) +#define MCF_CTM_CTCR7 (*(vuint32*)(&__MBAR[0x7F1C])) +#define MCF_CTM_CTCRF(x) (*(vuint32*)(&__MBAR[0x7F00 + ((x)*0x4)])) +#define MCF_CTM_CTCRV(x) (*(vuint32*)(&__MBAR[0x7F10 + ((x-4)*0x4)])) + + +/* Bit definitions and macros for MCF_CTM_CTCRF */ +#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0) +#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10) +#define MCF_CTM_CTCRF_S_CLK_1 (0) +#define MCF_CTM_CTCRF_S_CLK_2 (0x10000) +#define MCF_CTM_CTCRF_S_CLK_4 (0x20000) +#define MCF_CTM_CTCRF_S_CLK_8 (0x30000) +#define MCF_CTM_CTCRF_S_CLK_16 (0x40000) +#define MCF_CTM_CTCRF_S_CLK_32 (0x50000) +#define MCF_CTM_CTCRF_S_CLK_64 (0x60000) +#define MCF_CTM_CTCRF_S_CLK_128 (0x70000) +#define MCF_CTM_CTCRF_S_CLK_256 (0x80000) +#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000) +#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14) +#define MCF_CTM_CTCRF_PCT_100 (0) +#define MCF_CTM_CTCRF_PCT_50 (0x100000) +#define MCF_CTM_CTCRF_PCT_25 (0x200000) +#define MCF_CTM_CTCRF_PCT_12p5 (0x300000) +#define MCF_CTM_CTCRF_PCT_6p25 (0x400000) +#define MCF_CTM_CTCRF_PCT_OFF (0x500000) +#define MCF_CTM_CTCRF_M (0x800000) +#define MCF_CTM_CTCRF_IM (0x1000000) +#define MCF_CTM_CTCRF_I (0x80000000) + +/* Bit definitions and macros for MCF_CTM_CTCRV */ +#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0) +#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18) +#define MCF_CTM_CTCRV_PCT_100 (0) +#define MCF_CTM_CTCRV_PCT_50 (0x1000000) +#define MCF_CTM_CTCRV_PCT_25 (0x2000000) +#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000) +#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000) +#define MCF_CTM_CTCRV_PCT_OFF (0x5000000) +#define MCF_CTM_CTCRV_M (0x8000000) +#define MCF_CTM_CTCRV_S (0x10000000) + + +#endif /* __MCF5475_CTM_H__ */ diff --git a/BaS_GNU/include/MCF5475_DMA.h b/BaS_GNU/include/MCF5475_DMA.h new file mode 100644 index 0000000..a9667c1 --- /dev/null +++ b/BaS_GNU/include/MCF5475_DMA.h @@ -0,0 +1,202 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DMA_H__ +#define __MCF5475_DMA_H__ + + +/********************************************************************* +* +* Multichannel DMA (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_TASKBAR (*(vuint32*)(&__MBAR[0x8000])) +#define MCF_DMA_CP (*(vuint32*)(&__MBAR[0x8004])) +#define MCF_DMA_EP (*(vuint32*)(&__MBAR[0x8008])) +#define MCF_DMA_VP (*(vuint32*)(&__MBAR[0x800C])) +#define MCF_DMA_PTD (*(vuint32*)(&__MBAR[0x8010])) +#define MCF_DMA_DIPR (*(vuint32*)(&__MBAR[0x8014])) +#define MCF_DMA_DIMR (*(vuint32*)(&__MBAR[0x8018])) +#define MCF_DMA_TCR0 (*(vuint16*)(&__MBAR[0x801C])) +#define MCF_DMA_TCR1 (*(vuint16*)(&__MBAR[0x801E])) +#define MCF_DMA_TCR2 (*(vuint16*)(&__MBAR[0x8020])) +#define MCF_DMA_TCR3 (*(vuint16*)(&__MBAR[0x8022])) +#define MCF_DMA_TCR4 (*(vuint16*)(&__MBAR[0x8024])) +#define MCF_DMA_TCR5 (*(vuint16*)(&__MBAR[0x8026])) +#define MCF_DMA_TCR6 (*(vuint16*)(&__MBAR[0x8028])) +#define MCF_DMA_TCR7 (*(vuint16*)(&__MBAR[0x802A])) +#define MCF_DMA_TCR8 (*(vuint16*)(&__MBAR[0x802C])) +#define MCF_DMA_TCR9 (*(vuint16*)(&__MBAR[0x802E])) +#define MCF_DMA_TCR10 (*(vuint16*)(&__MBAR[0x8030])) +#define MCF_DMA_TCR11 (*(vuint16*)(&__MBAR[0x8032])) +#define MCF_DMA_TCR12 (*(vuint16*)(&__MBAR[0x8034])) +#define MCF_DMA_TCR13 (*(vuint16*)(&__MBAR[0x8036])) +#define MCF_DMA_TCR14 (*(vuint16*)(&__MBAR[0x8038])) +#define MCF_DMA_TCR15 (*(vuint16*)(&__MBAR[0x803A])) +#define MCF_DMA_PRIOR0 (*(vuint8 *)(&__MBAR[0x803C])) +#define MCF_DMA_PRIOR1 (*(vuint8 *)(&__MBAR[0x803D])) +#define MCF_DMA_PRIOR2 (*(vuint8 *)(&__MBAR[0x803E])) +#define MCF_DMA_PRIOR3 (*(vuint8 *)(&__MBAR[0x803F])) +#define MCF_DMA_PRIOR4 (*(vuint8 *)(&__MBAR[0x8040])) +#define MCF_DMA_PRIOR5 (*(vuint8 *)(&__MBAR[0x8041])) +#define MCF_DMA_PRIOR6 (*(vuint8 *)(&__MBAR[0x8042])) +#define MCF_DMA_PRIOR7 (*(vuint8 *)(&__MBAR[0x8043])) +#define MCF_DMA_PRIOR8 (*(vuint8 *)(&__MBAR[0x8044])) +#define MCF_DMA_PRIOR9 (*(vuint8 *)(&__MBAR[0x8045])) +#define MCF_DMA_PRIOR10 (*(vuint8 *)(&__MBAR[0x8046])) +#define MCF_DMA_PRIOR11 (*(vuint8 *)(&__MBAR[0x8047])) +#define MCF_DMA_PRIOR12 (*(vuint8 *)(&__MBAR[0x8048])) +#define MCF_DMA_PRIOR13 (*(vuint8 *)(&__MBAR[0x8049])) +#define MCF_DMA_PRIOR14 (*(vuint8 *)(&__MBAR[0x804A])) +#define MCF_DMA_PRIOR15 (*(vuint8 *)(&__MBAR[0x804B])) +#define MCF_DMA_PRIOR16 (*(vuint8 *)(&__MBAR[0x804C])) +#define MCF_DMA_PRIOR17 (*(vuint8 *)(&__MBAR[0x804D])) +#define MCF_DMA_PRIOR18 (*(vuint8 *)(&__MBAR[0x804E])) +#define MCF_DMA_PRIOR19 (*(vuint8 *)(&__MBAR[0x804F])) +#define MCF_DMA_PRIOR20 (*(vuint8 *)(&__MBAR[0x8050])) +#define MCF_DMA_PRIOR21 (*(vuint8 *)(&__MBAR[0x8051])) +#define MCF_DMA_PRIOR22 (*(vuint8 *)(&__MBAR[0x8052])) +#define MCF_DMA_PRIOR23 (*(vuint8 *)(&__MBAR[0x8053])) +#define MCF_DMA_PRIOR24 (*(vuint8 *)(&__MBAR[0x8054])) +#define MCF_DMA_PRIOR25 (*(vuint8 *)(&__MBAR[0x8055])) +#define MCF_DMA_PRIOR26 (*(vuint8 *)(&__MBAR[0x8056])) +#define MCF_DMA_PRIOR27 (*(vuint8 *)(&__MBAR[0x8057])) +#define MCF_DMA_PRIOR28 (*(vuint8 *)(&__MBAR[0x8058])) +#define MCF_DMA_PRIOR29 (*(vuint8 *)(&__MBAR[0x8059])) +#define MCF_DMA_PRIOR30 (*(vuint8 *)(&__MBAR[0x805A])) +#define MCF_DMA_PRIOR31 (*(vuint8 *)(&__MBAR[0x805B])) +#define MCF_DMA_IMCR (*(vuint32*)(&__MBAR[0x805C])) +#define MCF_DMA_TSKSZ0 (*(vuint32*)(&__MBAR[0x8060])) +#define MCF_DMA_TSKSZ1 (*(vuint32*)(&__MBAR[0x8064])) +#define MCF_DMA_DBGCOMP0 (*(vuint32*)(&__MBAR[0x8070])) +#define MCF_DMA_DBGCOMP2 (*(vuint32*)(&__MBAR[0x8074])) +#define MCF_DMA_DBGCTL (*(vuint32*)(&__MBAR[0x8078])) +#define MCF_DMA_TCR(x) (*(vuint16*)(&__MBAR[0x801C + ((x)*0x2)])) +#define MCF_DMA_PRIOR(x) (*(vuint8 *)(&__MBAR[0x803C + ((x)*0x1)])) + + +/* Bit definitions and macros for MCF_DMA_TASKBAR */ +#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_CP */ +#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_EP */ +#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_VP */ +#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_PTD */ +#define MCF_DMA_PTD_PCTL0 (0x1) +#define MCF_DMA_PTD_PCTL1 (0x2) +#define MCF_DMA_PTD_PCTL13 (0x2000) +#define MCF_DMA_PTD_PCTL14 (0x4000) +#define MCF_DMA_PTD_PCTL15 (0x8000) + +/* Bit definitions and macros for MCF_DMA_DIPR */ +#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DIMR */ +#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_TCR */ +#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0) +#define MCF_DMA_TCR_HLDINITNUM (0x20) +#define MCF_DMA_TCR_HIPRITSKEN (0x40) +#define MCF_DMA_TCR_ASTRT (0x80) +#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8) +#define MCF_DMA_TCR_ALWINIT (0x2000) +#define MCF_DMA_TCR_V (0x4000) +#define MCF_DMA_TCR_EN (0x8000) + +/* Bit definitions and macros for MCF_DMA_PRIOR */ +#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0) +#define MCF_DMA_PRIOR_HLD (0x80) + +/* Bit definitions and macros for MCF_DMA_IMCR */ +#define MCF_DMA_IMCR_IMC0(x) (((x)&0x3)<<0) +#define MCF_DMA_IMCR_IMC1(x) (((x)&0x3)<<0x2) +#define MCF_DMA_IMCR_IMC2(x) (((x)&0x3)<<0x4) +#define MCF_DMA_IMCR_IMC3(x) (((x)&0x3)<<0x6) +#define MCF_DMA_IMCR_IMC4(x) (((x)&0x3)<<0x8) +#define MCF_DMA_IMCR_IMC5(x) (((x)&0x3)<<0xA) +#define MCF_DMA_IMCR_IMC6(x) (((x)&0x3)<<0xC) +#define MCF_DMA_IMCR_IMC7(x) (((x)&0x3)<<0xE) +#define MCF_DMA_IMCR_IMC8(x) (((x)&0x3)<<0x10) +#define MCF_DMA_IMCR_IMC9(x) (((x)&0x3)<<0x12) +#define MCF_DMA_IMCR_IMC10(x) (((x)&0x3)<<0x14) +#define MCF_DMA_IMCR_IMC11(x) (((x)&0x3)<<0x16) +#define MCF_DMA_IMCR_IMC12(x) (((x)&0x3)<<0x18) +#define MCF_DMA_IMCR_IMC13(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_IMCR_IMC14(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_IMCR_IMC15(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_TSKSZ0 */ +#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_TSKSZ1 */ +#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */ +#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */ +#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCTL */ +#define MCF_DMA_DBGCTL_I (0x2) +#define MCF_DMA_DBGCTL_E (0x4) +#define MCF_DMA_DBGCTL_AND_OR (0x80) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB) +#define MCF_DMA_DBGCTL_B (0x4000) +#define MCF_DMA_DBGCTL_AA (0x8000) +#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_DMA_H__ */ diff --git a/BaS_GNU/include/MCF5475_DSPI.h b/BaS_GNU/include/MCF5475_DSPI.h new file mode 100644 index 0000000..ec4369d --- /dev/null +++ b/BaS_GNU/include/MCF5475_DSPI.h @@ -0,0 +1,150 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DSPI_H__ +#define __MCF5475_DSPI_H__ + + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DSPI_DMCR (*(vuint32*)(&__MBAR[0x8A00])) +#define MCF_DSPI_DTCR (*(vuint32*)(&__MBAR[0x8A08])) +#define MCF_DSPI_DCTAR0 (*(vuint32*)(&__MBAR[0x8A0C])) +#define MCF_DSPI_DCTAR1 (*(vuint32*)(&__MBAR[0x8A10])) +#define MCF_DSPI_DCTAR2 (*(vuint32*)(&__MBAR[0x8A14])) +#define MCF_DSPI_DCTAR3 (*(vuint32*)(&__MBAR[0x8A18])) +#define MCF_DSPI_DCTAR4 (*(vuint32*)(&__MBAR[0x8A1C])) +#define MCF_DSPI_DCTAR5 (*(vuint32*)(&__MBAR[0x8A20])) +#define MCF_DSPI_DCTAR6 (*(vuint32*)(&__MBAR[0x8A24])) +#define MCF_DSPI_DCTAR7 (*(vuint32*)(&__MBAR[0x8A28])) +#define MCF_DSPI_DSR (*(vuint32*)(&__MBAR[0x8A2C])) +#define MCF_DSPI_DIRSR (*(vuint32*)(&__MBAR[0x8A30])) +#define MCF_DSPI_DTFR (*(vuint32*)(&__MBAR[0x8A34])) +#define MCF_DSPI_DRFR (*(vuint32*)(&__MBAR[0x8A38])) +#define MCF_DSPI_DTFDR0 (*(vuint32*)(&__MBAR[0x8A3C])) +#define MCF_DSPI_DTFDR1 (*(vuint32*)(&__MBAR[0x8A40])) +#define MCF_DSPI_DTFDR2 (*(vuint32*)(&__MBAR[0x8A44])) +#define MCF_DSPI_DTFDR3 (*(vuint32*)(&__MBAR[0x8A48])) +#define MCF_DSPI_DRFDR0 (*(vuint32*)(&__MBAR[0x8A7C])) +#define MCF_DSPI_DRFDR1 (*(vuint32*)(&__MBAR[0x8A80])) +#define MCF_DSPI_DRFDR2 (*(vuint32*)(&__MBAR[0x8A84])) +#define MCF_DSPI_DRFDR3 (*(vuint32*)(&__MBAR[0x8A88])) +#define MCF_DSPI_DCTAR(x) (*(vuint32*)(&__MBAR[0x8A0C + ((x)*0x4)])) +#define MCF_DSPI_DTFDR(x) (*(vuint32*)(&__MBAR[0x8A3C + ((x)*0x4)])) +#define MCF_DSPI_DRFDR(x) (*(vuint32*)(&__MBAR[0x8A7C + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_DSPI_DMCR */ +#define MCF_DSPI_DMCR_HALT (0x1) +#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8) +#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0) +#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100) +#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200) +#define MCF_DSPI_DMCR_CRXF (0x400) +#define MCF_DSPI_DMCR_CTXF (0x800) +#define MCF_DSPI_DMCR_DRXF (0x1000) +#define MCF_DSPI_DMCR_DTXF (0x2000) +#define MCF_DSPI_DMCR_CSIS0 (0x10000) +#define MCF_DSPI_DMCR_CSIS2 (0x40000) +#define MCF_DSPI_DMCR_CSIS3 (0x80000) +#define MCF_DSPI_DMCR_CSIS5 (0x200000) +#define MCF_DSPI_DMCR_ROOE (0x1000000) +#define MCF_DSPI_DMCR_PCSSE (0x2000000) +#define MCF_DSPI_DMCR_MTFE (0x4000000) +#define MCF_DSPI_DMCR_FRZ (0x8000000) +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C) +#define MCF_DSPI_DMCR_CSCK (0x40000000) +#define MCF_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTCR */ +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DCTAR */ +#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10) +#define MCF_DSPI_DCTAR_PBR_1CLK (0) +#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000) +#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000) +#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000) +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12) +#define MCF_DSPI_DCTAR_PDT_1CLK (0) +#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000) +#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000) +#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000) +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14) +#define MCF_DSPI_DCTAR_PASC_1CLK (0) +#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000) +#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000) +#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000) +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16) +#define MCF_DSPI_DCTAR_LSBFE (0x1000000) +#define MCF_DSPI_DCTAR_CPHA (0x2000000) +#define MCF_DSPI_DCTAR_CPOL (0x4000000) +#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B) + +/* Bit definitions and macros for MCF_DSPI_DSR */ +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DSR_RFDF (0x20000) +#define MCF_DSPI_DSR_RFOF (0x80000) +#define MCF_DSPI_DSR_TFFF (0x2000000) +#define MCF_DSPI_DSR_TFUF (0x8000000) +#define MCF_DSPI_DSR_EOQF (0x10000000) +#define MCF_DSPI_DSR_TXRXS (0x40000000) +#define MCF_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DIRSR */ +#define MCF_DSPI_DIRSR_RFDFS (0x10000) +#define MCF_DSPI_DIRSR_RFDFE (0x20000) +#define MCF_DSPI_DIRSR_RFOFE (0x80000) +#define MCF_DSPI_DIRSR_TFFFS (0x1000000) +#define MCF_DSPI_DIRSR_TFFFE (0x2000000) +#define MCF_DSPI_DIRSR_TFUFE (0x8000000) +#define MCF_DSPI_DIRSR_EOQFE (0x10000000) +#define MCF_DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTFR */ +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFR_CS0 (0x10000) +#define MCF_DSPI_DTFR_CS2 (0x40000) +#define MCF_DSPI_DTFR_CS3 (0x80000) +#define MCF_DSPI_DTFR_CS5 (0x200000) +#define MCF_DSPI_DTFR_CTCNT (0x4000000) +#define MCF_DSPI_DTFR_EOQ (0x8000000) +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C) +#define MCF_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DRFR */ +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DSPI_DTFDR */ +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DRFDR */ +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0) + + +#endif /* __MCF5475_DSPI_H__ */ diff --git a/BaS_GNU/include/MCF5475_EPORT.h b/BaS_GNU/include/MCF5475_EPORT.h new file mode 100644 index 0000000..6616406 --- /dev/null +++ b/BaS_GNU/include/MCF5475_EPORT.h @@ -0,0 +1,123 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_EPORT_H__ +#define __MCF5475_EPORT_H__ + + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR (*(vuint16*)(&__MBAR[0xF00])) +#define MCF_EPORT_EPDDR (*(vuint8 *)(&__MBAR[0xF04])) +#define MCF_EPORT_EPIER (*(vuint8 *)(&__MBAR[0xF05])) +#define MCF_EPORT_EPDR (*(vuint8 *)(&__MBAR[0xF08])) +#define MCF_EPORT_EPPDR (*(vuint8 *)(&__MBAR[0xF09])) +#define MCF_EPORT_EPFR (*(vuint8 *)(&__MBAR[0xF0C])) + + + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (0x1) +#define MCF_EPORT_EPPAR_FALLING (0x2) +#define MCF_EPORT_EPPAR_BOTH (0x3) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x2) +#define MCF_EPORT_EPDDR_EPDD2 (0x4) +#define MCF_EPORT_EPDDR_EPDD3 (0x8) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x2) +#define MCF_EPORT_EPIER_EPIE2 (0x4) +#define MCF_EPORT_EPIER_EPIE3 (0x8) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x2) +#define MCF_EPORT_EPDR_EPD2 (0x4) +#define MCF_EPORT_EPDR_EPD3 (0x8) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x2) +#define MCF_EPORT_EPPDR_EPPD2 (0x4) +#define MCF_EPORT_EPPDR_EPPD3 (0x8) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x2) +#define MCF_EPORT_EPFR_EPF2 (0x4) +#define MCF_EPORT_EPFR_EPF3 (0x8) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + + +#endif /* __MCF5475_EPORT_H__ */ diff --git a/BaS_GNU/include/MCF5475_FBCS.h b/BaS_GNU/include/MCF5475_FBCS.h new file mode 100644 index 0000000..26bb585 --- /dev/null +++ b/BaS_GNU/include/MCF5475_FBCS.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FBCS_H__ +#define __MCF5475_FBCS_H__ + + +/********************************************************************* +* +* FlexBus Chip Select Module (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS0_CSAR (*(vuint32*)(&__MBAR[0x500])) +#define MCF_FBCS0_CSMR (*(vuint32*)(&__MBAR[0x504])) +#define MCF_FBCS0_CSCR (*(vuint32*)(&__MBAR[0x508])) + +#define MCF_FBCS1_CSAR (*(vuint32*)(&__MBAR[0x50C])) +#define MCF_FBCS1_CSMR (*(vuint32*)(&__MBAR[0x510])) +#define MCF_FBCS1_CSCR (*(vuint32*)(&__MBAR[0x514])) + +#define MCF_FBCS2_CSAR (*(vuint32*)(&__MBAR[0x518])) +#define MCF_FBCS2_CSMR (*(vuint32*)(&__MBAR[0x51C])) +#define MCF_FBCS2_CSCR (*(vuint32*)(&__MBAR[0x520])) + +#define MCF_FBCS3_CSAR (*(vuint32*)(&__MBAR[0x524])) +#define MCF_FBCS3_CSMR (*(vuint32*)(&__MBAR[0x528])) +#define MCF_FBCS3_CSCR (*(vuint32*)(&__MBAR[0x52C])) + +#define MCF_FBCS4_CSAR (*(vuint32*)(&__MBAR[0x530])) +#define MCF_FBCS4_CSMR (*(vuint32*)(&__MBAR[0x534])) +#define MCF_FBCS4_CSCR (*(vuint32*)(&__MBAR[0x538])) + +#define MCF_FBCS5_CSAR (*(vuint32*)(&__MBAR[0x53C])) +#define MCF_FBCS5_CSMR (*(vuint32*)(&__MBAR[0x540])) +#define MCF_FBCS5_CSCR (*(vuint32*)(&__MBAR[0x544])) + +#define MCF_FBCS_CSAR(x) (*(vuint32*)(&__MBAR[0x500 + ((x)*0xC)])) +#define MCF_FBCS_CSMR(x) (*(vuint32*)(&__MBAR[0x504 + ((x)*0xC)])) +#define MCF_FBCS_CSCR(x) (*(vuint32*)(&__MBAR[0x508 + ((x)*0xC)])) + + +/* Bit definitions and macros for MCF_FBCS_CSAR */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_FBCS_CSMR */ +#define MCF_FBCS_CSMR_V (0x1) +#define MCF_FBCS_CSMR_WP (0x100) +#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10) +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0xFF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x7F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x3F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x1F0000) +#define MCF_FBCS_CSMR_BAM_1M (0xF0000) +#define MCF_FBCS_CSMR_BAM_1024K (0xF0000) +#define MCF_FBCS_CSMR_BAM_512K (0x70000) +#define MCF_FBCS_CSMR_BAM_256K (0x30000) +#define MCF_FBCS_CSMR_BAM_128K (0x10000) +#define MCF_FBCS_CSMR_BAM_64K (0) + +/* Bit definitions and macros for MCF_FBCS_CSCR */ +#define MCF_FBCS_CSCR_BSTW (0x8) +#define MCF_FBCS_CSCR_BSTR (0x10) +#define MCF_FBCS_CSCR_BEM (0x20) +#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6) +#define MCF_FBCS_CSCR_PS_32 (0) +#define MCF_FBCS_CSCR_PS_8 (0x40) +#define MCF_FBCS_CSCR_PS_16 (0x80) +#define MCF_FBCS_CSCR_AA (0x100) +#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA) +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10) +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12) +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14) +#define MCF_FBCS_CSCR_SWSEN (0x800000) +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A) + + +#endif /* __MCF5475_FBCS_H__ */ diff --git a/BaS_GNU/include/MCF5475_FEC.h b/BaS_GNU/include/MCF5475_FEC.h new file mode 100644 index 0000000..01a0ae7 --- /dev/null +++ b/BaS_GNU/include/MCF5475_FEC.h @@ -0,0 +1,680 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FEC_H__ +#define __MCF5475_FEC_H__ + + +/********************************************************************* +* +* Fast Ethernet Controller(FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC0_EIR (*(vuint32*)(&__MBAR[0x9004])) +#define MCF_FEC0_EIMR (*(vuint32*)(&__MBAR[0x9008])) +#define MCF_FEC0_ECR (*(vuint32*)(&__MBAR[0x9024])) +#define MCF_FEC0_MMFR (*(vuint32*)(&__MBAR[0x9040])) +#define MCF_FEC0_MSCR (*(vuint32*)(&__MBAR[0x9044])) +#define MCF_FEC0_MIBC (*(vuint32*)(&__MBAR[0x9064])) +#define MCF_FEC0_RCR (*(vuint32*)(&__MBAR[0x9084])) +#define MCF_FEC0_RHR (*(vuint32*)(&__MBAR[0x9088])) +#define MCF_FEC0_TCR (*(vuint32*)(&__MBAR[0x90C4])) +#define MCF_FEC0_PALR (*(vuint32*)(&__MBAR[0x90E4])) +#define MCF_FEC0_PAHR (*(vuint32*)(&__MBAR[0x90E8])) +#define MCF_FEC0_OPD (*(vuint32*)(&__MBAR[0x90EC])) +#define MCF_FEC0_IAUR (*(vuint32*)(&__MBAR[0x9118])) +#define MCF_FEC0_IALR (*(vuint32*)(&__MBAR[0x911C])) +#define MCF_FEC0_GAUR (*(vuint32*)(&__MBAR[0x9120])) +#define MCF_FEC0_GALR (*(vuint32*)(&__MBAR[0x9124])) +#define MCF_FEC0_FECTFWR (*(vuint32*)(&__MBAR[0x9144])) +#define MCF_FEC0_FECRFDR (*(vuint32*)(&__MBAR[0x9184])) +#define MCF_FEC0_FECRFSR (*(vuint32*)(&__MBAR[0x9188])) +#define MCF_FEC0_FECRFCR (*(vuint32*)(&__MBAR[0x918C])) +#define MCF_FEC0_FECRLRFP (*(vuint32*)(&__MBAR[0x9190])) +#define MCF_FEC0_FECRLWFP (*(vuint32*)(&__MBAR[0x9194])) +#define MCF_FEC0_FECRFAR (*(vuint32*)(&__MBAR[0x9198])) +#define MCF_FEC0_FECRFRP (*(vuint32*)(&__MBAR[0x919C])) +#define MCF_FEC0_FECRFWP (*(vuint32*)(&__MBAR[0x91A0])) +#define MCF_FEC0_FECTFDR (*(vuint32*)(&__MBAR[0x91A4])) +#define MCF_FEC0_FECTFSR (*(vuint32*)(&__MBAR[0x91A8])) +#define MCF_FEC0_FECTFCR (*(vuint32*)(&__MBAR[0x91AC])) +#define MCF_FEC0_FECTLRFP (*(vuint32*)(&__MBAR[0x91B0])) +#define MCF_FEC0_FECTLWFP (*(vuint32*)(&__MBAR[0x91B4])) +#define MCF_FEC0_FECTFAR (*(vuint32*)(&__MBAR[0x91B8])) +#define MCF_FEC0_FECTFRP (*(vuint32*)(&__MBAR[0x91BC])) +#define MCF_FEC0_FECTFWP (*(vuint32*)(&__MBAR[0x91C0])) +#define MCF_FEC0_FECFRST (*(vuint32*)(&__MBAR[0x91C4])) +#define MCF_FEC0_FECCTCWR (*(vuint32*)(&__MBAR[0x91C8])) +#define MCF_FEC0_RMON_T_DROP (*(vuint32*)(&__MBAR[0x9200])) +#define MCF_FEC0_RMON_T_PACKETS (*(vuint32*)(&__MBAR[0x9204])) +#define MCF_FEC0_RMON_T_BC_PKT (*(vuint32*)(&__MBAR[0x9208])) +#define MCF_FEC0_RMON_T_MC_PKT (*(vuint32*)(&__MBAR[0x920C])) +#define MCF_FEC0_RMON_T_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9210])) +#define MCF_FEC0_RMON_T_UNDERSIZE (*(vuint32*)(&__MBAR[0x9214])) +#define MCF_FEC0_RMON_T_OVERSIZE (*(vuint32*)(&__MBAR[0x9218])) +#define MCF_FEC0_RMON_T_FRAG (*(vuint32*)(&__MBAR[0x921C])) +#define MCF_FEC0_RMON_T_JAB (*(vuint32*)(&__MBAR[0x9220])) +#define MCF_FEC0_RMON_T_COL (*(vuint32*)(&__MBAR[0x9224])) +#define MCF_FEC0_RMON_T_P64 (*(vuint32*)(&__MBAR[0x9228])) +#define MCF_FEC0_RMON_T_P65TO127 (*(vuint32*)(&__MBAR[0x922C])) +#define MCF_FEC0_RMON_T_P128TO255 (*(vuint32*)(&__MBAR[0x9230])) +#define MCF_FEC0_RMON_T_P256TO511 (*(vuint32*)(&__MBAR[0x9234])) +#define MCF_FEC0_RMON_T_P512TO1023 (*(vuint32*)(&__MBAR[0x9238])) +#define MCF_FEC0_RMON_T_P1024TO2047 (*(vuint32*)(&__MBAR[0x923C])) +#define MCF_FEC0_RMON_T_P_GTE2048 (*(vuint32*)(&__MBAR[0x9240])) +#define MCF_FEC0_RMON_T_OCTETS (*(vuint32*)(&__MBAR[0x9244])) +#define MCF_FEC0_IEEE_T_DROP (*(vuint32*)(&__MBAR[0x9248])) +#define MCF_FEC0_IEEE_T_FRAME_OK (*(vuint32*)(&__MBAR[0x924C])) +#define MCF_FEC0_IEEE_T_1COL (*(vuint32*)(&__MBAR[0x9250])) +#define MCF_FEC0_IEEE_T_MCOL (*(vuint32*)(&__MBAR[0x9254])) +#define MCF_FEC0_IEEE_T_DEF (*(vuint32*)(&__MBAR[0x9258])) +#define MCF_FEC0_IEEE_T_LCOL (*(vuint32*)(&__MBAR[0x925C])) +#define MCF_FEC0_IEEE_T_EXCOL (*(vuint32*)(&__MBAR[0x9260])) +#define MCF_FEC0_IEEE_T_MACERR (*(vuint32*)(&__MBAR[0x9264])) +#define MCF_FEC0_IEEE_T_CSERR (*(vuint32*)(&__MBAR[0x9268])) +#define MCF_FEC0_IEEE_T_SQE (*(vuint32*)(&__MBAR[0x926C])) +#define MCF_FEC0_IEEE_T_FDXFC (*(vuint32*)(&__MBAR[0x9270])) +#define MCF_FEC0_IEEE_T_OCTETS_OK (*(vuint32*)(&__MBAR[0x9274])) +#define MCF_FEC0_RMON_R_DROP (*(vuint32*)(&__MBAR[0x9280])) +#define MCF_FEC0_RMON_R_PACKETS (*(vuint32*)(&__MBAR[0x9284])) +#define MCF_FEC0_RMON_R_BC_PKT (*(vuint32*)(&__MBAR[0x9288])) +#define MCF_FEC0_RMON_R_MC_PKT (*(vuint32*)(&__MBAR[0x928C])) +#define MCF_FEC0_RMON_R_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9290])) +#define MCF_FEC0_RMON_R_UNDERSIZE (*(vuint32*)(&__MBAR[0x9294])) +#define MCF_FEC0_RMON_R_OVERSIZE (*(vuint32*)(&__MBAR[0x9298])) +#define MCF_FEC0_RMON_R_FRAG (*(vuint32*)(&__MBAR[0x929C])) +#define MCF_FEC0_RMON_R_JAB (*(vuint32*)(&__MBAR[0x92A0])) +#define MCF_FEC0_RMON_R_RESVD_0 (*(vuint32*)(&__MBAR[0x92A4])) +#define MCF_FEC0_RMON_R_P64 (*(vuint32*)(&__MBAR[0x92A8])) +#define MCF_FEC0_RMON_R_P65TO127 (*(vuint32*)(&__MBAR[0x92AC])) +#define MCF_FEC0_RMON_R_P128TO255 (*(vuint32*)(&__MBAR[0x92B0])) +#define MCF_FEC0_RMON_R_P256TO511 (*(vuint32*)(&__MBAR[0x92B4])) +#define MCF_FEC0_RMON_R_P512TO1023 (*(vuint32*)(&__MBAR[0x92B8])) +#define MCF_FEC0_RMON_R_P1024TO2047 (*(vuint32*)(&__MBAR[0x92BC])) +#define MCF_FEC0_RMON_R_P_GTE2048 (*(vuint32*)(&__MBAR[0x92C0])) +#define MCF_FEC0_RMON_R_OCTETS (*(vuint32*)(&__MBAR[0x92C4])) +#define MCF_FEC0_IEEE_R_DROP (*(vuint32*)(&__MBAR[0x92C8])) +#define MCF_FEC0_IEEE_R_FRAME_OK (*(vuint32*)(&__MBAR[0x92CC])) +#define MCF_FEC0_IEEE_R_CRC (*(vuint32*)(&__MBAR[0x92D0])) +#define MCF_FEC0_IEEE_R_ALIGN (*(vuint32*)(&__MBAR[0x92D4])) +#define MCF_FEC0_IEEE_R_MACERR (*(vuint32*)(&__MBAR[0x92D8])) +#define MCF_FEC0_IEEE_R_FDXFC (*(vuint32*)(&__MBAR[0x92DC])) +#define MCF_FEC0_IEEE_R_OCTETS_OK (*(vuint32*)(&__MBAR[0x92E0])) + +#define MCF_FEC1_EIR (*(vuint32*)(&__MBAR[0x9804])) +#define MCF_FEC1_EIMR (*(vuint32*)(&__MBAR[0x9808])) +#define MCF_FEC1_ECR (*(vuint32*)(&__MBAR[0x9824])) +#define MCF_FEC1_MMFR (*(vuint32*)(&__MBAR[0x9840])) +#define MCF_FEC1_MSCR (*(vuint32*)(&__MBAR[0x9844])) +#define MCF_FEC1_MIBC (*(vuint32*)(&__MBAR[0x9864])) +#define MCF_FEC1_RCR (*(vuint32*)(&__MBAR[0x9884])) +#define MCF_FEC1_RHR (*(vuint32*)(&__MBAR[0x9888])) +#define MCF_FEC1_TCR (*(vuint32*)(&__MBAR[0x98C4])) +#define MCF_FEC1_PALR (*(vuint32*)(&__MBAR[0x98E4])) +#define MCF_FEC1_PAHR (*(vuint32*)(&__MBAR[0x98E8])) +#define MCF_FEC1_OPD (*(vuint32*)(&__MBAR[0x98EC])) +#define MCF_FEC1_IAUR (*(vuint32*)(&__MBAR[0x9918])) +#define MCF_FEC1_IALR (*(vuint32*)(&__MBAR[0x991C])) +#define MCF_FEC1_GAUR (*(vuint32*)(&__MBAR[0x9920])) +#define MCF_FEC1_GALR (*(vuint32*)(&__MBAR[0x9924])) +#define MCF_FEC1_FECTFWR (*(vuint32*)(&__MBAR[0x9944])) +#define MCF_FEC1_FECRFDR (*(vuint32*)(&__MBAR[0x9984])) +#define MCF_FEC1_FECRFSR (*(vuint32*)(&__MBAR[0x9988])) +#define MCF_FEC1_FECRFCR (*(vuint32*)(&__MBAR[0x998C])) +#define MCF_FEC1_FECRLRFP (*(vuint32*)(&__MBAR[0x9990])) +#define MCF_FEC1_FECRLWFP (*(vuint32*)(&__MBAR[0x9994])) +#define MCF_FEC1_FECRFAR (*(vuint32*)(&__MBAR[0x9998])) +#define MCF_FEC1_FECRFRP (*(vuint32*)(&__MBAR[0x999C])) +#define MCF_FEC1_FECRFWP (*(vuint32*)(&__MBAR[0x99A0])) +#define MCF_FEC1_FECTFDR (*(vuint32*)(&__MBAR[0x99A4])) +#define MCF_FEC1_FECTFSR (*(vuint32*)(&__MBAR[0x99A8])) +#define MCF_FEC1_FECTFCR (*(vuint32*)(&__MBAR[0x99AC])) +#define MCF_FEC1_FECTLRFP (*(vuint32*)(&__MBAR[0x99B0])) +#define MCF_FEC1_FECTLWFP (*(vuint32*)(&__MBAR[0x99B4])) +#define MCF_FEC1_FECTFAR (*(vuint32*)(&__MBAR[0x99B8])) +#define MCF_FEC1_FECTFRP (*(vuint32*)(&__MBAR[0x99BC])) +#define MCF_FEC1_FECTFWP (*(vuint32*)(&__MBAR[0x99C0])) +#define MCF_FEC1_FECFRST (*(vuint32*)(&__MBAR[0x99C4])) +#define MCF_FEC1_FECCTCWR (*(vuint32*)(&__MBAR[0x99C8])) +#define MCF_FEC1_RMON_T_DROP (*(vuint32*)(&__MBAR[0x9A00])) +#define MCF_FEC1_RMON_T_PACKETS (*(vuint32*)(&__MBAR[0x9A04])) +#define MCF_FEC1_RMON_T_BC_PKT (*(vuint32*)(&__MBAR[0x9A08])) +#define MCF_FEC1_RMON_T_MC_PKT (*(vuint32*)(&__MBAR[0x9A0C])) +#define MCF_FEC1_RMON_T_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9A10])) +#define MCF_FEC1_RMON_T_UNDERSIZE (*(vuint32*)(&__MBAR[0x9A14])) +#define MCF_FEC1_RMON_T_OVERSIZE (*(vuint32*)(&__MBAR[0x9A18])) +#define MCF_FEC1_RMON_T_FRAG (*(vuint32*)(&__MBAR[0x9A1C])) +#define MCF_FEC1_RMON_T_JAB (*(vuint32*)(&__MBAR[0x9A20])) +#define MCF_FEC1_RMON_T_COL (*(vuint32*)(&__MBAR[0x9A24])) +#define MCF_FEC1_RMON_T_P64 (*(vuint32*)(&__MBAR[0x9A28])) +#define MCF_FEC1_RMON_T_P65TO127 (*(vuint32*)(&__MBAR[0x9A2C])) +#define MCF_FEC1_RMON_T_P128TO255 (*(vuint32*)(&__MBAR[0x9A30])) +#define MCF_FEC1_RMON_T_P256TO511 (*(vuint32*)(&__MBAR[0x9A34])) +#define MCF_FEC1_RMON_T_P512TO1023 (*(vuint32*)(&__MBAR[0x9A38])) +#define MCF_FEC1_RMON_T_P1024TO2047 (*(vuint32*)(&__MBAR[0x9A3C])) +#define MCF_FEC1_RMON_T_P_GTE2048 (*(vuint32*)(&__MBAR[0x9A40])) +#define MCF_FEC1_RMON_T_OCTETS (*(vuint32*)(&__MBAR[0x9A44])) +#define MCF_FEC1_IEEE_T_DROP (*(vuint32*)(&__MBAR[0x9A48])) +#define MCF_FEC1_IEEE_T_FRAME_OK (*(vuint32*)(&__MBAR[0x9A4C])) +#define MCF_FEC1_IEEE_T_1COL (*(vuint32*)(&__MBAR[0x9A50])) +#define MCF_FEC1_IEEE_T_MCOL (*(vuint32*)(&__MBAR[0x9A54])) +#define MCF_FEC1_IEEE_T_DEF (*(vuint32*)(&__MBAR[0x9A58])) +#define MCF_FEC1_IEEE_T_LCOL (*(vuint32*)(&__MBAR[0x9A5C])) +#define MCF_FEC1_IEEE_T_EXCOL (*(vuint32*)(&__MBAR[0x9A60])) +#define MCF_FEC1_IEEE_T_MACERR (*(vuint32*)(&__MBAR[0x9A64])) +#define MCF_FEC1_IEEE_T_CSERR (*(vuint32*)(&__MBAR[0x9A68])) +#define MCF_FEC1_IEEE_T_SQE (*(vuint32*)(&__MBAR[0x9A6C])) +#define MCF_FEC1_IEEE_T_FDXFC (*(vuint32*)(&__MBAR[0x9A70])) +#define MCF_FEC1_IEEE_T_OCTETS_OK (*(vuint32*)(&__MBAR[0x9A74])) +#define MCF_FEC1_RMON_R_DROP (*(vuint32*)(&__MBAR[0x9A80])) +#define MCF_FEC1_RMON_R_PACKETS (*(vuint32*)(&__MBAR[0x9A84])) +#define MCF_FEC1_RMON_R_BC_PKT (*(vuint32*)(&__MBAR[0x9A88])) +#define MCF_FEC1_RMON_R_MC_PKT (*(vuint32*)(&__MBAR[0x9A8C])) +#define MCF_FEC1_RMON_R_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9A90])) +#define MCF_FEC1_RMON_R_UNDERSIZE (*(vuint32*)(&__MBAR[0x9A94])) +#define MCF_FEC1_RMON_R_OVERSIZE (*(vuint32*)(&__MBAR[0x9A98])) +#define MCF_FEC1_RMON_R_FRAG (*(vuint32*)(&__MBAR[0x9A9C])) +#define MCF_FEC1_RMON_R_JAB (*(vuint32*)(&__MBAR[0x9AA0])) +#define MCF_FEC1_RMON_R_RESVD_0 (*(vuint32*)(&__MBAR[0x9AA4])) +#define MCF_FEC1_RMON_R_P64 (*(vuint32*)(&__MBAR[0x9AA8])) +#define MCF_FEC1_RMON_R_P65TO127 (*(vuint32*)(&__MBAR[0x9AAC])) +#define MCF_FEC1_RMON_R_P128TO255 (*(vuint32*)(&__MBAR[0x9AB0])) +#define MCF_FEC1_RMON_R_P256TO511 (*(vuint32*)(&__MBAR[0x9AB4])) +#define MCF_FEC1_RMON_R_P512TO1023 (*(vuint32*)(&__MBAR[0x9AB8])) +#define MCF_FEC1_RMON_R_P1024TO2047 (*(vuint32*)(&__MBAR[0x9ABC])) +#define MCF_FEC1_RMON_R_P_GTE2048 (*(vuint32*)(&__MBAR[0x9AC0])) +#define MCF_FEC1_RMON_R_OCTETS (*(vuint32*)(&__MBAR[0x9AC4])) +#define MCF_FEC1_IEEE_R_DROP (*(vuint32*)(&__MBAR[0x9AC8])) +#define MCF_FEC1_IEEE_R_FRAME_OK (*(vuint32*)(&__MBAR[0x9ACC])) +#define MCF_FEC1_IEEE_R_CRC (*(vuint32*)(&__MBAR[0x9AD0])) +#define MCF_FEC1_IEEE_R_ALIGN (*(vuint32*)(&__MBAR[0x9AD4])) +#define MCF_FEC1_IEEE_R_MACERR (*(vuint32*)(&__MBAR[0x9AD8])) +#define MCF_FEC1_IEEE_R_FDXFC (*(vuint32*)(&__MBAR[0x9ADC])) +#define MCF_FEC1_IEEE_R_OCTETS_OK (*(vuint32*)(&__MBAR[0x9AE0])) + +#define MCF_FEC_EIR(x) (*(vuint32*)(&__MBAR[0x9004 + ((x)*0x800)])) +#define MCF_FEC_EIMR(x) (*(vuint32*)(&__MBAR[0x9008 + ((x)*0x800)])) +#define MCF_FEC_ECR(x) (*(vuint32*)(&__MBAR[0x9024 + ((x)*0x800)])) +#define MCF_FEC_MMFR(x) (*(vuint32*)(&__MBAR[0x9040 + ((x)*0x800)])) +#define MCF_FEC_MSCR(x) (*(vuint32*)(&__MBAR[0x9044 + ((x)*0x800)])) +#define MCF_FEC_MIBC(x) (*(vuint32*)(&__MBAR[0x9064 + ((x)*0x800)])) +#define MCF_FEC_RCR(x) (*(vuint32*)(&__MBAR[0x9084 + ((x)*0x800)])) +#define MCF_FEC_RHR(x) (*(vuint32*)(&__MBAR[0x9088 + ((x)*0x800)])) +#define MCF_FEC_TCR(x) (*(vuint32*)(&__MBAR[0x90C4 + ((x)*0x800)])) +#define MCF_FEC_PALR(x) (*(vuint32*)(&__MBAR[0x90E4 + ((x)*0x800)])) +#define MCF_FEC_PAHR(x) (*(vuint32*)(&__MBAR[0x90E8 + ((x)*0x800)])) +#define MCF_FEC_OPD(x) (*(vuint32*)(&__MBAR[0x90EC + ((x)*0x800)])) +#define MCF_FEC_IAUR(x) (*(vuint32*)(&__MBAR[0x9118 + ((x)*0x800)])) +#define MCF_FEC_IALR(x) (*(vuint32*)(&__MBAR[0x911C + ((x)*0x800)])) +#define MCF_FEC_GAUR(x) (*(vuint32*)(&__MBAR[0x9120 + ((x)*0x800)])) +#define MCF_FEC_GALR(x) (*(vuint32*)(&__MBAR[0x9124 + ((x)*0x800)])) +#define MCF_FEC_FECTFWR(x) (*(vuint32*)(&__MBAR[0x9144 + ((x)*0x800)])) +#define MCF_FEC_FECRFDR(x) (*(vuint32*)(&__MBAR[0x9184 + ((x)*0x800)])) +#define MCF_FEC_FECRFSR(x) (*(vuint32*)(&__MBAR[0x9188 + ((x)*0x800)])) +#define MCF_FEC_FECRFCR(x) (*(vuint32*)(&__MBAR[0x918C + ((x)*0x800)])) +#define MCF_FEC_FECRLRFP(x) (*(vuint32*)(&__MBAR[0x9190 + ((x)*0x800)])) +#define MCF_FEC_FECRLWFP(x) (*(vuint32*)(&__MBAR[0x9194 + ((x)*0x800)])) +#define MCF_FEC_FECRFAR(x) (*(vuint32*)(&__MBAR[0x9198 + ((x)*0x800)])) +#define MCF_FEC_FECRFRP(x) (*(vuint32*)(&__MBAR[0x919C + ((x)*0x800)])) +#define MCF_FEC_FECRFWP(x) (*(vuint32*)(&__MBAR[0x91A0 + ((x)*0x800)])) +#define MCF_FEC_FECTFDR(x) (*(vuint32*)(&__MBAR[0x91A4 + ((x)*0x800)])) +#define MCF_FEC_FECTFSR(x) (*(vuint32*)(&__MBAR[0x91A8 + ((x)*0x800)])) +#define MCF_FEC_FECTFCR(x) (*(vuint32*)(&__MBAR[0x91AC + ((x)*0x800)])) +#define MCF_FEC_FECTLRFP(x) (*(vuint32*)(&__MBAR[0x91B0 + ((x)*0x800)])) +#define MCF_FEC_FECTLWFP(x) (*(vuint32*)(&__MBAR[0x91B4 + ((x)*0x800)])) +#define MCF_FEC_FECTFAR(x) (*(vuint32*)(&__MBAR[0x91B8 + ((x)*0x800)])) +#define MCF_FEC_FECTFRP(x) (*(vuint32*)(&__MBAR[0x91BC + ((x)*0x800)])) +#define MCF_FEC_FECTFWP(x) (*(vuint32*)(&__MBAR[0x91C0 + ((x)*0x800)])) +#define MCF_FEC_FECFRST(x) (*(vuint32*)(&__MBAR[0x91C4 + ((x)*0x800)])) +#define MCF_FEC_FECCTCWR(x) (*(vuint32*)(&__MBAR[0x91C8 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_DROP(x) (*(vuint32*)(&__MBAR[0x9200 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_PACKETS(x) (*(vuint32*)(&__MBAR[0x9204 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_BC_PKT(x) (*(vuint32*)(&__MBAR[0x9208 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_MC_PKT(x) (*(vuint32*)(&__MBAR[0x920C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(vuint32*)(&__MBAR[0x9210 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(vuint32*)(&__MBAR[0x9214 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OVERSIZE(x) (*(vuint32*)(&__MBAR[0x9218 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_FRAG(x) (*(vuint32*)(&__MBAR[0x921C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_JAB(x) (*(vuint32*)(&__MBAR[0x9220 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_COL(x) (*(vuint32*)(&__MBAR[0x9224 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P64(x) (*(vuint32*)(&__MBAR[0x9228 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P65TO127(x) (*(vuint32*)(&__MBAR[0x922C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P128TO255(x) (*(vuint32*)(&__MBAR[0x9230 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P256TO511(x) (*(vuint32*)(&__MBAR[0x9234 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P512TO1023(x) (*(vuint32*)(&__MBAR[0x9238 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P1024TO2047(x) (*(vuint32*)(&__MBAR[0x923C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P_GTE2048(x) (*(vuint32*)(&__MBAR[0x9240 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OCTETS(x) (*(vuint32*)(&__MBAR[0x9244 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DROP(x) (*(vuint32*)(&__MBAR[0x9248 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(vuint32*)(&__MBAR[0x924C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_1COL(x) (*(vuint32*)(&__MBAR[0x9250 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MCOL(x) (*(vuint32*)(&__MBAR[0x9254 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DEF(x) (*(vuint32*)(&__MBAR[0x9258 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_LCOL(x) (*(vuint32*)(&__MBAR[0x925C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_EXCOL(x) (*(vuint32*)(&__MBAR[0x9260 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MACERR(x) (*(vuint32*)(&__MBAR[0x9264 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_CSERR(x) (*(vuint32*)(&__MBAR[0x9268 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_SQE(x) (*(vuint32*)(&__MBAR[0x926C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FDXFC(x) (*(vuint32*)(&__MBAR[0x9270 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(vuint32*)(&__MBAR[0x9274 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_DROP(x) (*(vuint32*)(&__MBAR[0x9280 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_PACKETS(x) (*(vuint32*)(&__MBAR[0x9284 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_BC_PKT(x) (*(vuint32*)(&__MBAR[0x9288 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_MC_PKT(x) (*(vuint32*)(&__MBAR[0x928C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(vuint32*)(&__MBAR[0x9290 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(vuint32*)(&__MBAR[0x9294 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OVERSIZE(x) (*(vuint32*)(&__MBAR[0x9298 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_FRAG(x) (*(vuint32*)(&__MBAR[0x929C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_JAB(x) (*(vuint32*)(&__MBAR[0x92A0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_RESVD_0(x) (*(vuint32*)(&__MBAR[0x92A4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P64(x) (*(vuint32*)(&__MBAR[0x92A8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P65TO127(x) (*(vuint32*)(&__MBAR[0x92AC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P128TO255(x) (*(vuint32*)(&__MBAR[0x92B0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P256TO511(x) (*(vuint32*)(&__MBAR[0x92B4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P512TO1023(x) (*(vuint32*)(&__MBAR[0x92B8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P1024TO2047(x) (*(vuint32*)(&__MBAR[0x92BC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P_GTE2048(x) (*(vuint32*)(&__MBAR[0x92C0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OCTETS(x) (*(vuint32*)(&__MBAR[0x92C4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_DROP(x) (*(vuint32*)(&__MBAR[0x92C8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(vuint32*)(&__MBAR[0x92CC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_CRC(x) (*(vuint32*)(&__MBAR[0x92D0 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_ALIGN(x) (*(vuint32*)(&__MBAR[0x92D4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_MACERR(x) (*(vuint32*)(&__MBAR[0x92D8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FDXFC(x) (*(vuint32*)(&__MBAR[0x92DC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(vuint32*)(&__MBAR[0x92E0 + ((x)*0x800)])) + + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_RFERR (0x20000) +#define MCF_FEC_EIR_XFERR (0x40000) +#define MCF_FEC_EIR_XFUN (0x80000) +#define MCF_FEC_EIR_RL (0x100000) +#define MCF_FEC_EIR_LC (0x200000) +#define MCF_FEC_EIR_MII (0x800000) +#define MCF_FEC_EIR_TXF (0x8000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) +#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_RFERR (0x20000) +#define MCF_FEC_EIMR_XFERR (0x40000) +#define MCF_FEC_EIMR_XFUN (0x80000) +#define MCF_FEC_EIMR_RL (0x100000) +#define MCF_FEC_EIMR_LC (0x200000) +#define MCF_FEC_EIMR_MII (0x800000) +#define MCF_FEC_EIMR_TXF (0x8000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) +#define MCF_FEC_EIMR_MASK_ALL (0) +#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x1) +#define MCF_FEC_ECR_ETHER_EN (0x2) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10) +#define MCF_FEC_MMFR_TA_10 (0x20000) +#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12) +#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17) +#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E) +#define MCF_FEC_MMFR_ST_01 (0x40000000) + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80) +#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x1) +#define MCF_FEC_RCR_DRT (0x2) +#define MCF_FEC_RCR_MII_MODE (0x4) +#define MCF_FEC_RCR_PROM (0x8) +#define MCF_FEC_RCR_BC_REJ (0x10) +#define MCF_FEC_RCR_FCE (0x20) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_RHR */ +#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18) +#define MCF_FEC_RHR_MULTCAST (0x40000000) +#define MCF_FEC_RHR_FCE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x1) +#define MCF_FEC_TCR_HBC (0x2) +#define MCF_FEC_TCR_FDEN (0x4) +#define MCF_FEC_TCR_TFC_PAUSE (0x8) +#define MCF_FEC_TCR_RFC_PAUSE (0x10) + +/* Bit definitions and macros for MCF_FEC_PALR */ +#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_PAHR */ +#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_IAUR */ +#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IALR */ +#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GAUR */ +#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GALR */ +#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWR */ +#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0) +#define MCF_FEC_FECTFWR_X_WMRK_64 (0) +#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1) +#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2) +#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3) +#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4) +#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5) +#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6) +#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7) +#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8) +#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9) +#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA) +#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB) +#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC) +#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD) +#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE) +#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF) + +/* Bit definitions and macros for MCF_FEC_FECRFDR */ +#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFSR */ +#define MCF_FEC_FECRFSR_EMT (0x10000) +#define MCF_FEC_FECRFSR_ALARM (0x20000) +#define MCF_FEC_FECRFSR_FU (0x40000) +#define MCF_FEC_FECRFSR_FRMRDY (0x80000) +#define MCF_FEC_FECRFSR_OF (0x100000) +#define MCF_FEC_FECRFSR_UF (0x200000) +#define MCF_FEC_FECRFSR_RXW (0x400000) +#define MCF_FEC_FECRFSR_FAE (0x800000) +#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECRFCR */ +#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_FECRFCR_OF_MSK (0x80000) +#define MCF_FEC_FECRFCR_UF_MSK (0x100000) +#define MCF_FEC_FECRFCR_RXW_MSK (0x200000) +#define MCF_FEC_FECRFCR_FAE_MSK (0x400000) +#define MCF_FEC_FECRFCR_IP_MSK (0x800000) +#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_FEC_FECRFCR_FRMEN (0x8000000) +#define MCF_FEC_FECRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_FEC_FECRLRFP */ +#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRLWFP */ +#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFAR */ +#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFRP */ +#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFWP */ +#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFDR */ +#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFSR */ +#define MCF_FEC_FECTFSR_EMT (0x10000) +#define MCF_FEC_FECTFSR_ALARM (0x20000) +#define MCF_FEC_FECTFSR_FU (0x40000) +#define MCF_FEC_FECTFSR_FRMRDY (0x80000) +#define MCF_FEC_FECTFSR_OF (0x100000) +#define MCF_FEC_FECTFSR_UF (0x200000) +#define MCF_FEC_FECTFSR_FAE (0x800000) +#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECTFSR_TXW (0x40000000) +#define MCF_FEC_FECTFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECTFCR */ +#define MCF_FEC_FECTFCR_RESERVED (0x200000) +#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000) +#define MCF_FEC_FECTFCR_TXW_MASK (0x240000) +#define MCF_FEC_FECTFCR_OF_MSK (0x280000) +#define MCF_FEC_FECTFCR_UF_MSK (0x300000) +#define MCF_FEC_FECTFCR_FAE_MSK (0x600000) +#define MCF_FEC_FECTFCR_IP_MSK (0xA00000) +#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000) +#define MCF_FEC_FECTFCR_FRMEN (0x8200000) +#define MCF_FEC_FECTFCR_TIMER (0x10200000) +#define MCF_FEC_FECTFCR_WFR (0x20200000) +#define MCF_FEC_FECTFCR_WCTL (0x40200000) + +/* Bit definitions and macros for MCF_FEC_FECTLRFP */ +#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTLWFP */ +#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFAR */ +#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFRP */ +#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWP */ +#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECFRST */ +#define MCF_FEC_FECFRST_RST_CTL (0x1000000) +#define MCF_FEC_FECFRST_SW_RST (0x2000000) + +/* Bit definitions and macros for MCF_FEC_FECCTCWR */ +#define MCF_FEC_FECCTCWR_TFCW (0x1000000) +#define MCF_FEC_FECCTCWR_CRC (0x2000000) + +/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */ +#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */ +#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */ +#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */ +#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */ +#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */ +#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */ +#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */ +#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */ +#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_COL */ +#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */ +#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */ +#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */ +#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */ +#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */ +#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */ +#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */ +#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */ +#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */ +#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */ +#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */ +#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */ +#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */ +#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */ +#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */ +#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */ +#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */ +#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */ +#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */ +#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */ +#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */ +#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */ +#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */ +#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */ +#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */ +#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */ +#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */ +#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */ +#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */ +#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */ +#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */ +#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */ +#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */ +#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */ +#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */ +#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */ +#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */ +#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */ +#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */ +#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */ +#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */ +#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */ +#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */ +#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */ +#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */ +#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF5475_FEC_H__ */ diff --git a/BaS_GNU/include/MCF5475_GPIO.h b/BaS_GNU/include/MCF5475_GPIO.h new file mode 100644 index 0000000..7ef3dce --- /dev/null +++ b/BaS_GNU/include/MCF5475_GPIO.h @@ -0,0 +1,543 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPIO_H__ +#define __MCF5475_GPIO_H__ + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FBCTL (*(vuint8 *)(&__MBAR[0xA00])) +#define MCF_GPIO_PDDR_FBCTL (*(vuint8 *)(&__MBAR[0xA10])) +#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8 *)(&__MBAR[0xA20])) +#define MCF_GPIO_PCLRR_FBCTL (*(vuint8 *)(&__MBAR[0xA30])) + +#define MCF_GPIO_PODR_FBCS (*(vuint8 *)(&__MBAR[0xA01])) +#define MCF_GPIO_PDDR_FBCS (*(vuint8 *)(&__MBAR[0xA11])) +#define MCF_GPIO_PPDSDR_FBCS (*(vuint8 *)(&__MBAR[0xA21])) +#define MCF_GPIO_PCLRR_FBCS (*(vuint8 *)(&__MBAR[0xA31])) + +#define MCF_GPIO_PODR_DMA (*(vuint8 *)(&__MBAR[0xA02])) +#define MCF_GPIO_PDDR_DMA (*(vuint8 *)(&__MBAR[0xA12])) +#define MCF_GPIO_PPDSDR_DMA (*(vuint8 *)(&__MBAR[0xA22])) +#define MCF_GPIO_PCLRR_DMA (*(vuint8 *)(&__MBAR[0xA32])) + +#define MCF_GPIO_PODR_FEC0H (*(vuint8 *)(&__MBAR[0xA04])) +#define MCF_GPIO_PDDR_FEC0H (*(vuint8 *)(&__MBAR[0xA14])) +#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8 *)(&__MBAR[0xA24])) +#define MCF_GPIO_PCLRR_FEC0H (*(vuint8 *)(&__MBAR[0xA34])) + +#define MCF_GPIO_PODR_FEC0L (*(vuint8 *)(&__MBAR[0xA05])) +#define MCF_GPIO_PDDR_FEC0L (*(vuint8 *)(&__MBAR[0xA15])) +#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8 *)(&__MBAR[0xA25])) +#define MCF_GPIO_PCLRR_FEC0L (*(vuint8 *)(&__MBAR[0xA35])) + +#define MCF_GPIO_PODR_FEC1H (*(vuint8 *)(&__MBAR[0xA06])) +#define MCF_GPIO_PDDR_FEC1H (*(vuint8 *)(&__MBAR[0xA16])) +#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8 *)(&__MBAR[0xA26])) +#define MCF_GPIO_PCLRR_FEC1H (*(vuint8 *)(&__MBAR[0xA36])) + +#define MCF_GPIO_PODR_FEC1L (*(vuint8 *)(&__MBAR[0xA07])) +#define MCF_GPIO_PDDR_FEC1L (*(vuint8 *)(&__MBAR[0xA17])) +#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8 *)(&__MBAR[0xA27])) +#define MCF_GPIO_PCLRR_FEC1L (*(vuint8 *)(&__MBAR[0xA37])) + +#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(&__MBAR[0xA08])) +#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(&__MBAR[0xA18])) +#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(&__MBAR[0xA28])) +#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(&__MBAR[0xA38])) + +#define MCF_GPIO_PODR_PCIBG (*(vuint8 *)(&__MBAR[0xA09])) +#define MCF_GPIO_PDDR_PCIBG (*(vuint8 *)(&__MBAR[0xA19])) +#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8 *)(&__MBAR[0xA29])) +#define MCF_GPIO_PCLRR_PCIBG (*(vuint8 *)(&__MBAR[0xA39])) + +#define MCF_GPIO_PODR_PCIBR (*(vuint8 *)(&__MBAR[0xA0A])) +#define MCF_GPIO_PDDR_PCIBR (*(vuint8 *)(&__MBAR[0xA1A])) +#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8 *)(&__MBAR[0xA2A])) +#define MCF_GPIO_PCLRR_PCIBR (*(vuint8 *)(&__MBAR[0xA3A])) + +#define MCF_GPIO2_PODR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA0C])) +#define MCF_GPIO2_PDDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA1C])) +#define MCF_GPIO2_PPDSDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA2C])) +#define MCF_GPIO2_PCLRR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA3C])) + +#define MCF_GPIO0_PODR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA0D])) +#define MCF_GPIO0_PDDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA1D])) +#define MCF_GPIO0_PPDSDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA2D])) +#define MCF_GPIO0_PCLRR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA3D])) + +#define MCF_GPIO_PODR_DSPI (*(vuint8 *)(&__MBAR[0xA0E])) +#define MCF_GPIO_PDDR_DSPI (*(vuint8 *)(&__MBAR[0xA1E])) +#define MCF_GPIO_PPDSDR_DSPI (*(vuint8 *)(&__MBAR[0xA2E])) +#define MCF_GPIO_PCLRR_DSPI (*(vuint8 *)(&__MBAR[0xA3E])) + + + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ +#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ +#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1) +#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2) +#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4) +#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ +#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */ +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */ +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */ +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */ +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */ +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */ +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */ +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */ +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ +#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) + + +#endif /* __MCF5475_GPIO_H__ */ diff --git a/BaS_GNU/include/MCF5475_GPT.h b/BaS_GNU/include/MCF5475_GPT.h new file mode 100644 index 0000000..ab99d05 --- /dev/null +++ b/BaS_GNU/include/MCF5475_GPT.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPT_H__ +#define __MCF5475_GPT_H__ + + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS (*(vuint32*)(&__MBAR[0x800])) +#define MCF_GPT0_GCIR (*(vuint32*)(&__MBAR[0x804])) +#define MCF_GPT0_GPWM (*(vuint32*)(&__MBAR[0x808])) +#define MCF_GPT0_GSR (*(vuint32*)(&__MBAR[0x80C])) + +#define MCF_GPT1_GMS (*(vuint32*)(&__MBAR[0x810])) +#define MCF_GPT1_GCIR (*(vuint32*)(&__MBAR[0x814])) +#define MCF_GPT1_GPWM (*(vuint32*)(&__MBAR[0x818])) +#define MCF_GPT1_GSR (*(vuint32*)(&__MBAR[0x81C])) + +#define MCF_GPT2_GMS (*(vuint32*)(&__MBAR[0x820])) +#define MCF_GPT2_GCIR (*(vuint32*)(&__MBAR[0x824])) +#define MCF_GPT2_GPWM (*(vuint32*)(&__MBAR[0x828])) +#define MCF_GPT2_GSR (*(vuint32*)(&__MBAR[0x82C])) + +#define MCF_GPT3_GMS (*(vuint32*)(&__MBAR[0x830])) +#define MCF_GPT3_GCIR (*(vuint32*)(&__MBAR[0x834])) +#define MCF_GPT3_GPWM (*(vuint32*)(&__MBAR[0x838])) +#define MCF_GPT3_GSR (*(vuint32*)(&__MBAR[0x83C])) + +#define MCF_GPT_GMS(x) (*(vuint32*)(&__MBAR[0x800 + ((x)*0x10)])) +#define MCF_GPT_GCIR(x) (*(vuint32*)(&__MBAR[0x804 + ((x)*0x10)])) +#define MCF_GPT_GPWM(x) (*(vuint32*)(&__MBAR[0x808 + ((x)*0x10)])) +#define MCF_GPT_GSR(x) (*(vuint32*)(&__MBAR[0x80C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_GPT_GMS */ +#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0) +#define MCF_GPT_GMS_TMS_DISABLE (0) +#define MCF_GPT_GMS_TMS_INCAPT (0x1) +#define MCF_GPT_GMS_TMS_OUTCAPT (0x2) +#define MCF_GPT_GMS_TMS_PWM (0x3) +#define MCF_GPT_GMS_TMS_GPIO (0x4) +#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4) +#define MCF_GPT_GMS_GPIO_INPUT (0) +#define MCF_GPT_GMS_GPIO_OUTLO (0x20) +#define MCF_GPT_GMS_GPIO_OUTHI (0x30) +#define MCF_GPT_GMS_IEN (0x100) +#define MCF_GPT_GMS_OD (0x200) +#define MCF_GPT_GMS_SC (0x400) +#define MCF_GPT_GMS_CE (0x1000) +#define MCF_GPT_GMS_WDEN (0x8000) +#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10) +#define MCF_GPT_GMS_ICT_ANY (0) +#define MCF_GPT_GMS_ICT_RISE (0x10000) +#define MCF_GPT_GMS_ICT_FALL (0x20000) +#define MCF_GPT_GMS_ICT_PULSE (0x30000) +#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14) +#define MCF_GPT_GMS_OCT_FRCLOW (0) +#define MCF_GPT_GMS_OCT_PULSEHI (0x100000) +#define MCF_GPT_GMS_OCT_PULSELO (0x200000) +#define MCF_GPT_GMS_OCT_TOGGLE (0x300000) +#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_GPT_GCIR */ +#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0) +#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GPWM */ +#define MCF_GPT_GPWM_LOAD (0x1) +#define MCF_GPT_GPWM_PWMOP (0x100) +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GSR */ +#define MCF_GPT_GSR_CAPT (0x1) +#define MCF_GPT_GSR_COMP (0x2) +#define MCF_GPT_GSR_PWMP (0x4) +#define MCF_GPT_GSR_TEXP (0x8) +#define MCF_GPT_GSR_PIN (0x100) +#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC) +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_GPT_H__ */ diff --git a/BaS_GNU/include/MCF5475_I2C.h b/BaS_GNU/include/MCF5475_I2C.h new file mode 100644 index 0000000..dbbd626 --- /dev/null +++ b/BaS_GNU/include/MCF5475_I2C.h @@ -0,0 +1,69 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_I2C_H__ +#define __MCF5475_I2C_H__ + + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2ADR (*(vuint8 *)(&__MBAR[0x8F00])) +#define MCF_I2C_I2FDR (*(vuint8 *)(&__MBAR[0x8F04])) +#define MCF_I2C_I2CR (*(vuint8 *)(&__MBAR[0x8F08])) +#define MCF_I2C_I2SR (*(vuint8 *)(&__MBAR[0x8F0C])) +#define MCF_I2C_I2DR (*(vuint8 *)(&__MBAR[0x8F10])) +#define MCF_I2C_I2ICR (*(vuint8 *)(&__MBAR[0x8F20])) + + + +/* Bit definitions and macros for MCF_I2C_I2ADR */ +#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x4) +#define MCF_I2C_I2CR_TXAK (0x8) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x1) +#define MCF_I2C_I2SR_IIF (0x2) +#define MCF_I2C_I2SR_SRW (0x4) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x1) +#define MCF_I2C_I2ICR_RE (0x2) +#define MCF_I2C_I2ICR_TE (0x4) +#define MCF_I2C_I2ICR_BNBE (0x8) + + +#endif /* __MCF5475_I2C_H__ */ diff --git a/BaS_GNU/include/MCF5475_INTC.h b/BaS_GNU/include/MCF5475_INTC.h new file mode 100644 index 0000000..4dfc6d2 --- /dev/null +++ b/BaS_GNU/include/MCF5475_INTC.h @@ -0,0 +1,331 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_INTC_H__ +#define __MCF5475_INTC_H__ + + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IPRH (*(vuint32*)(&__MBAR[0x700])) +#define MCF_INTC_IPRL (*(vuint32*)(&__MBAR[0x704])) +#define MCF_INTC_IMRH (*(vuint32*)(&__MBAR[0x708])) +#define MCF_INTC_IMRL (*(vuint32*)(&__MBAR[0x70C])) +#define MCF_INTC_INTFRCH (*(vuint32*)(&__MBAR[0x710])) +#define MCF_INTC_INTFRCL (*(vuint32*)(&__MBAR[0x714])) +#define MCF_INTC_IRLR (*(vuint8 *)(&__MBAR[0x718])) +#define MCF_INTC_IACKLPR (*(vuint8 *)(&__MBAR[0x719])) +#define MCF_INTC_ICR01 (*(vuint8 *)(&__MBAR[0x741])) +#define MCF_INTC_ICR02 (*(vuint8 *)(&__MBAR[0x742])) +#define MCF_INTC_ICR03 (*(vuint8 *)(&__MBAR[0x743])) +#define MCF_INTC_ICR04 (*(vuint8 *)(&__MBAR[0x744])) +#define MCF_INTC_ICR05 (*(vuint8 *)(&__MBAR[0x745])) +#define MCF_INTC_ICR06 (*(vuint8 *)(&__MBAR[0x746])) +#define MCF_INTC_ICR07 (*(vuint8 *)(&__MBAR[0x747])) +#define MCF_INTC_ICR08 (*(vuint8 *)(&__MBAR[0x748])) +#define MCF_INTC_ICR09 (*(vuint8 *)(&__MBAR[0x749])) +#define MCF_INTC_ICR10 (*(vuint8 *)(&__MBAR[0x74A])) +#define MCF_INTC_ICR11 (*(vuint8 *)(&__MBAR[0x74B])) +#define MCF_INTC_ICR12 (*(vuint8 *)(&__MBAR[0x74C])) +#define MCF_INTC_ICR13 (*(vuint8 *)(&__MBAR[0x74D])) +#define MCF_INTC_ICR14 (*(vuint8 *)(&__MBAR[0x74E])) +#define MCF_INTC_ICR15 (*(vuint8 *)(&__MBAR[0x74F])) +#define MCF_INTC_ICR16 (*(vuint8 *)(&__MBAR[0x750])) +#define MCF_INTC_ICR17 (*(vuint8 *)(&__MBAR[0x751])) +#define MCF_INTC_ICR18 (*(vuint8 *)(&__MBAR[0x752])) +#define MCF_INTC_ICR19 (*(vuint8 *)(&__MBAR[0x753])) +#define MCF_INTC_ICR20 (*(vuint8 *)(&__MBAR[0x754])) +#define MCF_INTC_ICR21 (*(vuint8 *)(&__MBAR[0x755])) +#define MCF_INTC_ICR22 (*(vuint8 *)(&__MBAR[0x756])) +#define MCF_INTC_ICR23 (*(vuint8 *)(&__MBAR[0x757])) +#define MCF_INTC_ICR24 (*(vuint8 *)(&__MBAR[0x758])) +#define MCF_INTC_ICR25 (*(vuint8 *)(&__MBAR[0x759])) +#define MCF_INTC_ICR26 (*(vuint8 *)(&__MBAR[0x75A])) +#define MCF_INTC_ICR27 (*(vuint8 *)(&__MBAR[0x75B])) +#define MCF_INTC_ICR28 (*(vuint8 *)(&__MBAR[0x75C])) +#define MCF_INTC_ICR29 (*(vuint8 *)(&__MBAR[0x75D])) +#define MCF_INTC_ICR30 (*(vuint8 *)(&__MBAR[0x75E])) +#define MCF_INTC_ICR31 (*(vuint8 *)(&__MBAR[0x75F])) +#define MCF_INTC_ICR32 (*(vuint8 *)(&__MBAR[0x760])) +#define MCF_INTC_ICR33 (*(vuint8 *)(&__MBAR[0x761])) +#define MCF_INTC_ICR34 (*(vuint8 *)(&__MBAR[0x762])) +#define MCF_INTC_ICR35 (*(vuint8 *)(&__MBAR[0x763])) +#define MCF_INTC_ICR36 (*(vuint8 *)(&__MBAR[0x764])) +#define MCF_INTC_ICR37 (*(vuint8 *)(&__MBAR[0x765])) +#define MCF_INTC_ICR38 (*(vuint8 *)(&__MBAR[0x766])) +#define MCF_INTC_ICR39 (*(vuint8 *)(&__MBAR[0x767])) +#define MCF_INTC_ICR40 (*(vuint8 *)(&__MBAR[0x768])) +#define MCF_INTC_ICR41 (*(vuint8 *)(&__MBAR[0x769])) +#define MCF_INTC_ICR42 (*(vuint8 *)(&__MBAR[0x76A])) +#define MCF_INTC_ICR43 (*(vuint8 *)(&__MBAR[0x76B])) +#define MCF_INTC_ICR44 (*(vuint8 *)(&__MBAR[0x76C])) +#define MCF_INTC_ICR45 (*(vuint8 *)(&__MBAR[0x76D])) +#define MCF_INTC_ICR46 (*(vuint8 *)(&__MBAR[0x76E])) +#define MCF_INTC_ICR47 (*(vuint8 *)(&__MBAR[0x76F])) +#define MCF_INTC_ICR48 (*(vuint8 *)(&__MBAR[0x770])) +#define MCF_INTC_ICR49 (*(vuint8 *)(&__MBAR[0x771])) +#define MCF_INTC_ICR50 (*(vuint8 *)(&__MBAR[0x772])) +#define MCF_INTC_ICR51 (*(vuint8 *)(&__MBAR[0x773])) +#define MCF_INTC_ICR52 (*(vuint8 *)(&__MBAR[0x774])) +#define MCF_INTC_ICR53 (*(vuint8 *)(&__MBAR[0x775])) +#define MCF_INTC_ICR54 (*(vuint8 *)(&__MBAR[0x776])) +#define MCF_INTC_ICR55 (*(vuint8 *)(&__MBAR[0x777])) +#define MCF_INTC_ICR56 (*(vuint8 *)(&__MBAR[0x778])) +#define MCF_INTC_ICR57 (*(vuint8 *)(&__MBAR[0x779])) +#define MCF_INTC_ICR58 (*(vuint8 *)(&__MBAR[0x77A])) +#define MCF_INTC_ICR59 (*(vuint8 *)(&__MBAR[0x77B])) +#define MCF_INTC_ICR60 (*(vuint8 *)(&__MBAR[0x77C])) +#define MCF_INTC_ICR61 (*(vuint8 *)(&__MBAR[0x77D])) +#define MCF_INTC_ICR62 (*(vuint8 *)(&__MBAR[0x77E])) +#define MCF_INTC_ICR63 (*(vuint8 *)(&__MBAR[0x77F])) +#define MCF_INTC_SWIACK (*(vuint8 *)(&__MBAR[0x7E0])) +#define MCF_INTC_L1IACK (*(vuint8 *)(&__MBAR[0x7E4])) +#define MCF_INTC_L2IACK (*(vuint8 *)(&__MBAR[0x7E8])) +#define MCF_INTC_L3IACK (*(vuint8 *)(&__MBAR[0x7EC])) +#define MCF_INTC_L4IACK (*(vuint8 *)(&__MBAR[0x7F0])) +#define MCF_INTC_L5IACK (*(vuint8 *)(&__MBAR[0x7F4])) +#define MCF_INTC_L6IACK (*(vuint8 *)(&__MBAR[0x7F8])) +#define MCF_INTC_L7IACK (*(vuint8 *)(&__MBAR[0x7FC])) +#define MCF_INTC_ICR(x) (*(vuint8 *)(&__MBAR[0x741 + ((x-1)*0x1)])) +#define MCF_INTC_LIACK(x) (*(vuint8 *)(&__MBAR[0x7E4 + ((x-1)*0x4)])) + + + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x1) +#define MCF_INTC_IPRH_INT33 (0x2) +#define MCF_INTC_IPRH_INT34 (0x4) +#define MCF_INTC_IPRH_INT35 (0x8) +#define MCF_INTC_IPRH_INT36 (0x10) +#define MCF_INTC_IPRH_INT37 (0x20) +#define MCF_INTC_IPRH_INT38 (0x40) +#define MCF_INTC_IPRH_INT39 (0x80) +#define MCF_INTC_IPRH_INT40 (0x100) +#define MCF_INTC_IPRH_INT41 (0x200) +#define MCF_INTC_IPRH_INT42 (0x400) +#define MCF_INTC_IPRH_INT43 (0x800) +#define MCF_INTC_IPRH_INT44 (0x1000) +#define MCF_INTC_IPRH_INT45 (0x2000) +#define MCF_INTC_IPRH_INT46 (0x4000) +#define MCF_INTC_IPRH_INT47 (0x8000) +#define MCF_INTC_IPRH_INT48 (0x10000) +#define MCF_INTC_IPRH_INT49 (0x20000) +#define MCF_INTC_IPRH_INT50 (0x40000) +#define MCF_INTC_IPRH_INT51 (0x80000) +#define MCF_INTC_IPRH_INT52 (0x100000) +#define MCF_INTC_IPRH_INT53 (0x200000) +#define MCF_INTC_IPRH_INT54 (0x400000) +#define MCF_INTC_IPRH_INT55 (0x800000) +#define MCF_INTC_IPRH_INT56 (0x1000000) +#define MCF_INTC_IPRH_INT57 (0x2000000) +#define MCF_INTC_IPRH_INT58 (0x4000000) +#define MCF_INTC_IPRH_INT59 (0x8000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x2) +#define MCF_INTC_IPRL_INT2 (0x4) +#define MCF_INTC_IPRL_INT3 (0x8) +#define MCF_INTC_IPRL_INT4 (0x10) +#define MCF_INTC_IPRL_INT5 (0x20) +#define MCF_INTC_IPRL_INT6 (0x40) +#define MCF_INTC_IPRL_INT7 (0x80) +#define MCF_INTC_IPRL_INT8 (0x100) +#define MCF_INTC_IPRL_INT9 (0x200) +#define MCF_INTC_IPRL_INT10 (0x400) +#define MCF_INTC_IPRL_INT11 (0x800) +#define MCF_INTC_IPRL_INT12 (0x1000) +#define MCF_INTC_IPRL_INT13 (0x2000) +#define MCF_INTC_IPRL_INT14 (0x4000) +#define MCF_INTC_IPRL_INT15 (0x8000) +#define MCF_INTC_IPRL_INT16 (0x10000) +#define MCF_INTC_IPRL_INT17 (0x20000) +#define MCF_INTC_IPRL_INT18 (0x40000) +#define MCF_INTC_IPRL_INT19 (0x80000) +#define MCF_INTC_IPRL_INT20 (0x100000) +#define MCF_INTC_IPRL_INT21 (0x200000) +#define MCF_INTC_IPRL_INT22 (0x400000) +#define MCF_INTC_IPRL_INT23 (0x800000) +#define MCF_INTC_IPRL_INT24 (0x1000000) +#define MCF_INTC_IPRL_INT25 (0x2000000) +#define MCF_INTC_IPRL_INT26 (0x4000000) +#define MCF_INTC_IPRL_INT27 (0x8000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x1) +#define MCF_INTC_IMRH_INT_MASK33 (0x2) +#define MCF_INTC_IMRH_INT_MASK34 (0x4) +#define MCF_INTC_IMRH_INT_MASK35 (0x8) +#define MCF_INTC_IMRH_INT_MASK36 (0x10) +#define MCF_INTC_IMRH_INT_MASK37 (0x20) +#define MCF_INTC_IMRH_INT_MASK38 (0x40) +#define MCF_INTC_IMRH_INT_MASK39 (0x80) +#define MCF_INTC_IMRH_INT_MASK40 (0x100) +#define MCF_INTC_IMRH_INT_MASK41 (0x200) +#define MCF_INTC_IMRH_INT_MASK42 (0x400) +#define MCF_INTC_IMRH_INT_MASK43 (0x800) +#define MCF_INTC_IMRH_INT_MASK44 (0x1000) +#define MCF_INTC_IMRH_INT_MASK45 (0x2000) +#define MCF_INTC_IMRH_INT_MASK46 (0x4000) +#define MCF_INTC_IMRH_INT_MASK47 (0x8000) +#define MCF_INTC_IMRH_INT_MASK48 (0x10000) +#define MCF_INTC_IMRH_INT_MASK49 (0x20000) +#define MCF_INTC_IMRH_INT_MASK50 (0x40000) +#define MCF_INTC_IMRH_INT_MASK51 (0x80000) +#define MCF_INTC_IMRH_INT_MASK52 (0x100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x1000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x2000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x4000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x8000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x1) +#define MCF_INTC_IMRL_INT_MASK1 (0x2) +#define MCF_INTC_IMRL_INT_MASK2 (0x4) +#define MCF_INTC_IMRL_INT_MASK3 (0x8) +#define MCF_INTC_IMRL_INT_MASK4 (0x10) +#define MCF_INTC_IMRL_INT_MASK5 (0x20) +#define MCF_INTC_IMRL_INT_MASK6 (0x40) +#define MCF_INTC_IMRL_INT_MASK7 (0x80) +#define MCF_INTC_IMRL_INT_MASK8 (0x100) +#define MCF_INTC_IMRL_INT_MASK9 (0x200) +#define MCF_INTC_IMRL_INT_MASK10 (0x400) +#define MCF_INTC_IMRL_INT_MASK11 (0x800) +#define MCF_INTC_IMRL_INT_MASK12 (0x1000) +#define MCF_INTC_IMRL_INT_MASK13 (0x2000) +#define MCF_INTC_IMRL_INT_MASK14 (0x4000) +#define MCF_INTC_IMRL_INT_MASK15 (0x8000) +#define MCF_INTC_IMRL_INT_MASK16 (0x10000) +#define MCF_INTC_IMRL_INT_MASK17 (0x20000) +#define MCF_INTC_IMRL_INT_MASK18 (0x40000) +#define MCF_INTC_IMRL_INT_MASK19 (0x80000) +#define MCF_INTC_IMRL_INT_MASK20 (0x100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x1000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x2000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x4000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x8000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x1) +#define MCF_INTC_INTFRCH_INTFRC33 (0x2) +#define MCF_INTC_INTFRCH_INTFRC34 (0x4) +#define MCF_INTC_INTFRCH_INTFRC35 (0x8) +#define MCF_INTC_INTFRCH_INTFRC36 (0x10) +#define MCF_INTC_INTFRCH_INTFRC37 (0x20) +#define MCF_INTC_INTFRCH_INTFRC38 (0x40) +#define MCF_INTC_INTFRCH_INTFRC39 (0x80) +#define MCF_INTC_INTFRCH_INTFRC40 (0x100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x1000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x2000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x4000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x8000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x10000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x20000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x40000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x80000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x2) +#define MCF_INTC_INTFRCL_INTFRC2 (0x4) +#define MCF_INTC_INTFRCL_INTFRC3 (0x8) +#define MCF_INTC_INTFRCL_INTFRC4 (0x10) +#define MCF_INTC_INTFRCL_INTFRC5 (0x20) +#define MCF_INTC_INTFRCL_INTFRC6 (0x40) +#define MCF_INTC_INTFRCL_INTFRC7 (0x80) +#define MCF_INTC_INTFRCL_INTFRC8 (0x100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x1000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x2000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x4000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x8000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x10000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x20000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x40000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x80000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + + +#endif /* __MCF5475_INTC_H__ */ diff --git a/BaS_GNU/include/MCF5475_MMU.h b/BaS_GNU/include/MCF5475_MMU.h new file mode 100644 index 0000000..84d57b9 --- /dev/null +++ b/BaS_GNU/include/MCF5475_MMU.h @@ -0,0 +1,77 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_MMU_H__ +#define __MCF5475_MMU_H__ + + +/********************************************************************* +* +* Memory Management Unit (MMU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_MMU_MMUCR (*(vuint32*)(&__MMUBAR[0])) +#define MCF_MMU_MMUOR (*(vuint32*)(&__MMUBAR[0x4])) +#define MCF_MMU_MMUSR (*(vuint32*)(&__MMUBAR[0x8])) +#define MCF_MMU_MMUAR (*(vuint32*)(&__MMUBAR[0x10])) +#define MCF_MMU_MMUTR (*(vuint32*)(&__MMUBAR[0x14])) +#define MCF_MMU_MMUDR (*(vuint32*)(&__MMUBAR[0x18])) + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + + +#endif /* __MCF5475_MMU_H__ */ diff --git a/BaS_GNU/include/MCF5475_PAD.h b/BaS_GNU/include/MCF5475_PAD.h new file mode 100644 index 0000000..9c0fcf7 --- /dev/null +++ b/BaS_GNU/include/MCF5475_PAD.h @@ -0,0 +1,233 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PAD_H__ +#define __MCF5475_PAD_H__ + + +/********************************************************************* +* +* Common GPIO +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PAD_PAR_FBCTL (*(vuint16*)(&__MBAR[0xA40])) +#define MCF_PAD_PAR_FBCS (*(vuint8 *)(&__MBAR[0xA42])) +#define MCF_PAD_PAR_DMA (*(vuint8 *)(&__MBAR[0xA43])) +#define MCF_PAD_PAR_FECI2CIRQ (*(vuint16*)(&__MBAR[0xA44])) +#define MCF_PAD_PAR_PCIBG (*(vuint16*)(&__MBAR[0xA48])) +#define MCF_PAD_PAR_PCIBR (*(vuint16*)(&__MBAR[0xA4A])) +#define MCF_PAD_PAR_PSC3 (*(vuint8 *)(&__MBAR[0xA4C])) +#define MCF_PAD_PAR_PSC2 (*(vuint8 *)(&__MBAR[0xA4D])) +#define MCF_PAD_PAR_PSC1 (*(vuint8 *)(&__MBAR[0xA4E])) +#define MCF_PAD_PAR_PSC0 (*(vuint8 *)(&__MBAR[0xA4F])) +#define MCF_PAD_PAR_DSPI (*(vuint16*)(&__MBAR[0xA50])) +#define MCF_PAD_PAR_TIMER (*(vuint8 *)(&__MBAR[0xA52])) + + +/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */ +#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3) +#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30) +#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40) +#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100) +#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400) +#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000) +#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000) + +/* Bit definitions and macros for MCF_PAD_PAR_FBCS */ +#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2) +#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4) +#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8) +#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10) +#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20) + +/* Bit definitions and macros for MCF_PAD_PAR_DMA */ +#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3) +#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC) +#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20) +#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30) +#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80) +#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */ +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */ +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */ +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */ +#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4) +#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8) +#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30) +#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */ +#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4) +#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8) +#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30) +#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */ +#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4) +#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8) +#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30) +#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */ +#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4) +#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8) +#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30) +#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_DSPI */ +#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3) +#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8) +#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC) +#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10) +#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20) +#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30) +#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40) +#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80) +#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0) +#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200) +#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300) +#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA) +#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800) +#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00) +#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000) + +/* Bit definitions and macros for MCF_PAD_PAR_TIMER */ +#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6) +#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8) +#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30) + + +#endif /* __MCF5475_PAD_H__ */ diff --git a/BaS_GNU/include/MCF5475_PCI.h b/BaS_GNU/include/MCF5475_PCI.h new file mode 100644 index 0000000..47e9e98 --- /dev/null +++ b/BaS_GNU/include/MCF5475_PCI.h @@ -0,0 +1,376 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCI_H__ +#define __MCF5475_PCI_H__ + + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCI_PCIIDR (*(vuint32*)(&__MBAR[0xB00])) +#define MCF_PCI_PCISCR (*(vuint32*)(&__MBAR[0xB04])) +#define MCF_PCI_PCICCRIR (*(vuint32*)(&__MBAR[0xB08])) +#define MCF_PCI_PCICR1 (*(vuint32*)(&__MBAR[0xB0C])) +#define MCF_PCI_PCIBAR0 (*(vuint32*)(&__MBAR[0xB10])) +#define MCF_PCI_PCIBAR1 (*(vuint32*)(&__MBAR[0xB14])) +#define MCF_PCI_PCICCPR (*(vuint32*)(&__MBAR[0xB28])) +#define MCF_PCI_PCISID (*(vuint32*)(&__MBAR[0xB2C])) +#define MCF_PCI_PCICR2 (*(vuint32*)(&__MBAR[0xB3C])) +#define MCF_PCI_PCIGSCR (*(vuint32*)(&__MBAR[0xB60])) +#define MCF_PCI_PCITBATR0 (*(vuint32*)(&__MBAR[0xB64])) +#define MCF_PCI_PCITBATR1 (*(vuint32*)(&__MBAR[0xB68])) +#define MCF_PCI_PCITCR (*(vuint32*)(&__MBAR[0xB6C])) +#define MCF_PCI_PCIIW0BTAR (*(vuint32*)(&__MBAR[0xB70])) +#define MCF_PCI_PCIIW1BTAR (*(vuint32*)(&__MBAR[0xB74])) +#define MCF_PCI_PCIIW2BTAR (*(vuint32*)(&__MBAR[0xB78])) +#define MCF_PCI_PCIIWCR (*(vuint32*)(&__MBAR[0xB80])) +#define MCF_PCI_PCIICR (*(vuint32*)(&__MBAR[0xB84])) +#define MCF_PCI_PCIISR (*(vuint32*)(&__MBAR[0xB88])) +#define MCF_PCI_PCICAR (*(vuint32*)(&__MBAR[0xBF8])) +#define MCF_PCI_PCITPSR (*(vuint32*)(&__MBAR[0x8400])) +#define MCF_PCI_PCITSAR (*(vuint32*)(&__MBAR[0x8404])) +#define MCF_PCI_PCITTCR (*(vuint32*)(&__MBAR[0x8408])) +#define MCF_PCI_PCITER (*(vuint32*)(&__MBAR[0x840C])) +#define MCF_PCI_PCITNAR (*(vuint32*)(&__MBAR[0x8410])) +#define MCF_PCI_PCITLWR (*(vuint32*)(&__MBAR[0x8414])) +#define MCF_PCI_PCITDCR (*(vuint32*)(&__MBAR[0x8418])) +#define MCF_PCI_PCITSR (*(vuint32*)(&__MBAR[0x841C])) +#define MCF_PCI_PCITFDR (*(vuint32*)(&__MBAR[0x8440])) +#define MCF_PCI_PCITFSR (*(vuint32*)(&__MBAR[0x8444])) +#define MCF_PCI_PCITFCR (*(vuint32*)(&__MBAR[0x8448])) +#define MCF_PCI_PCITFAR (*(vuint32*)(&__MBAR[0x844C])) +#define MCF_PCI_PCITFRPR (*(vuint32*)(&__MBAR[0x8450])) +#define MCF_PCI_PCITFWPR (*(vuint32*)(&__MBAR[0x8454])) +#define MCF_PCI_PCIRPSR (*(vuint32*)(&__MBAR[0x8480])) +#define MCF_PCI_PCIRSAR (*(vuint32*)(&__MBAR[0x8484])) +#define MCF_PCI_PCIRTCR (*(vuint32*)(&__MBAR[0x8488])) +#define MCF_PCI_PCIRER (*(vuint32*)(&__MBAR[0x848C])) +#define MCF_PCI_PCIRNAR (*(vuint32*)(&__MBAR[0x8490])) +#define MCF_PCI_PCIRDCR (*(vuint32*)(&__MBAR[0x8498])) +#define MCF_PCI_PCIRSR (*(vuint32*)(&__MBAR[0x849C])) +#define MCF_PCI_PCIRFDR (*(vuint32*)(&__MBAR[0x84C0])) +#define MCF_PCI_PCIRFSR (*(vuint32*)(&__MBAR[0x84C4])) +#define MCF_PCI_PCIRFCR (*(vuint32*)(&__MBAR[0x84C8])) +#define MCF_PCI_PCIRFAR (*(vuint32*)(&__MBAR[0x84CC])) +#define MCF_PCI_PCIRFRPR (*(vuint32*)(&__MBAR[0x84D0])) +#define MCF_PCI_PCIRFWPR (*(vuint32*)(&__MBAR[0x84D4])) + + +/* Bit definitions and macros for MCF_PCI_PCIIDR */ +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCISCR */ +#define MCF_PCI_PCISCR_IO (0x1) +#define MCF_PCI_PCISCR_M (0x2) +#define MCF_PCI_PCISCR_B (0x4) +#define MCF_PCI_PCISCR_SP (0x8) +#define MCF_PCI_PCISCR_MW (0x10) +#define MCF_PCI_PCISCR_V (0x20) +#define MCF_PCI_PCISCR_PER (0x40) +#define MCF_PCI_PCISCR_ST (0x80) +#define MCF_PCI_PCISCR_S (0x100) +#define MCF_PCI_PCISCR_F (0x200) +#define MCF_PCI_PCISCR_C (0x100000) +#define MCF_PCI_PCISCR_66M (0x200000) +#define MCF_PCI_PCISCR_R (0x400000) +#define MCF_PCI_PCISCR_FC (0x800000) +#define MCF_PCI_PCISCR_DP (0x1000000) +#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCISCR_TS (0x8000000) +#define MCF_PCI_PCISCR_TR (0x10000000) +#define MCF_PCI_PCISCR_MA (0x20000000) +#define MCF_PCI_PCISCR_SE (0x40000000) +#define MCF_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCICCRIR */ +#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8) + +/* Bit definitions and macros for MCF_PCI_PCICR1 */ +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ +#define MCF_PCI_PCIBAR0_IOM (0x1) +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR0_PREF (0x8) +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ +#define MCF_PCI_PCIBAR1_IOM (0x1) +#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR1_PREF (0x8) +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCICCPR */ +#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCISID */ +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCICR2 */ +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIGSCR */ +#define MCF_PCI_PCIGSCR_PR (0x1) +#define MCF_PCI_PCIGSCR_SEE (0x1000) +#define MCF_PCI_PCIGSCR_PEE (0x2000) +#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10) +#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIGSCR_SE (0x10000000) +#define MCF_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ +#define MCF_PCI_PCITBATR0_EN (0x1) +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ +#define MCF_PCI_PCITBATR1_EN (0x1) +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCITCR */ +#define MCF_PCI_PCITCR_P (0x10000) +#define MCF_PCI_PCITCR_LD (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ +#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ +#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ +#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIWCR */ +#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9) +#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800) +#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11) +#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000) +#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500) +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000) +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000) + +/* Bit definitions and macros for MCF_PCI_PCIICR */ +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCIICR_TAE (0x1000000) +#define MCF_PCI_PCIICR_IAE (0x2000000) +#define MCF_PCI_PCIICR_REE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCIISR */ +#define MCF_PCI_PCIISR_TA (0x1000000) +#define MCF_PCI_PCIISR_IA (0x2000000) +#define MCF_PCI_PCIISR_RE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCICAR */ +#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2) +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB) +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICAR_E (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITPSR */ +#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSAR */ +#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITTCR */ +#define MCF_PCI_PCITTCR_DI (0x1) +#define MCF_PCI_PCITTCR_W (0x10) +#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCITER */ +#define MCF_PCI_PCITER_NE (0x10000) +#define MCF_PCI_PCITER_IAE (0x20000) +#define MCF_PCI_PCITER_TAE (0x40000) +#define MCF_PCI_PCITER_RE (0x80000) +#define MCF_PCI_PCITER_SE (0x100000) +#define MCF_PCI_PCITER_FEE (0x200000) +#define MCF_PCI_PCITER_ME (0x1000000) +#define MCF_PCI_PCITER_BE (0x8000000) +#define MCF_PCI_PCITER_CM (0x10000000) +#define MCF_PCI_PCITER_RF (0x40000000) +#define MCF_PCI_PCITER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITNAR */ +#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITLWR */ +#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITDCR */ +#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSR */ +#define MCF_PCI_PCITSR_IA (0x10000) +#define MCF_PCI_PCITSR_TA (0x20000) +#define MCF_PCI_PCITSR_RE (0x40000) +#define MCF_PCI_PCITSR_SE (0x80000) +#define MCF_PCI_PCITSR_FE (0x100000) +#define MCF_PCI_PCITSR_BE1 (0x200000) +#define MCF_PCI_PCITSR_BE2 (0x400000) +#define MCF_PCI_PCITSR_BE3 (0x800000) +#define MCF_PCI_PCITSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCITFDR */ +#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFSR */ +#define MCF_PCI_PCITFSR_EMPTY (0x10000) +#define MCF_PCI_PCITFSR_ALARM (0x20000) +#define MCF_PCI_PCITFSR_FULL (0x40000) +#define MCF_PCI_PCITFSR_FR (0x80000) +#define MCF_PCI_PCITFSR_OF (0x100000) +#define MCF_PCI_PCITFSR_UF (0x200000) +#define MCF_PCI_PCITFSR_RXW (0x400000) +#define MCF_PCI_PCITFSR_FAE (0x800000) +#define MCF_PCI_PCITFSR_TXW (0x40000000) +#define MCF_PCI_PCITFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITFCR */ +#define MCF_PCI_PCITFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCITFCR_OF_MASK (0x80000) +#define MCF_PCI_PCITFCR_UF_MASK (0x100000) +#define MCF_PCI_PCITFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCITFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCITFCR_IP_MASK (0x800000) +#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCITFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITFAR */ +#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFRPR */ +#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFWPR */ +#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRPSR */ +#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSAR */ +#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRTCR */ +#define MCF_PCI_PCIRTCR_DI (0x1) +#define MCF_PCI_PCIRTCR_W (0x10) +#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCIRTCR_FB (0x1000) +#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIRER */ +#define MCF_PCI_PCIRER_NE (0x10000) +#define MCF_PCI_PCIRER_IAE (0x20000) +#define MCF_PCI_PCIRER_TAE (0x40000) +#define MCF_PCI_PCIRER_RE (0x80000) +#define MCF_PCI_PCIRER_SE (0x100000) +#define MCF_PCI_PCIRER_FEE (0x200000) +#define MCF_PCI_PCIRER_ME (0x1000000) +#define MCF_PCI_PCIRER_BE (0x8000000) +#define MCF_PCI_PCIRER_CM (0x10000000) +#define MCF_PCI_PCIRER_FE (0x20000000) +#define MCF_PCI_PCIRER_RF (0x40000000) +#define MCF_PCI_PCIRER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRNAR */ +#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRDCR */ +#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSR */ +#define MCF_PCI_PCIRSR_IA (0x10000) +#define MCF_PCI_PCIRSR_TA (0x20000) +#define MCF_PCI_PCIRSR_RE (0x40000) +#define MCF_PCI_PCIRSR_SE (0x80000) +#define MCF_PCI_PCIRSR_FE (0x100000) +#define MCF_PCI_PCIRSR_BE1 (0x200000) +#define MCF_PCI_PCIRSR_BE2 (0x400000) +#define MCF_PCI_PCIRSR_BE3 (0x800000) +#define MCF_PCI_PCIRSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFDR */ +#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFSR */ +#define MCF_PCI_PCIRFSR_EMPTY (0x10000) +#define MCF_PCI_PCIRFSR_ALARM (0x20000) +#define MCF_PCI_PCIRFSR_FULL (0x40000) +#define MCF_PCI_PCIRFSR_FR (0x80000) +#define MCF_PCI_PCIRFSR_OF (0x100000) +#define MCF_PCI_PCIRFSR_UF (0x200000) +#define MCF_PCI_PCIRFSR_RXW (0x400000) +#define MCF_PCI_PCIRFSR_FAE (0x800000) +#define MCF_PCI_PCIRFSR_TXW (0x40000000) +#define MCF_PCI_PCIRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFCR */ +#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCIRFCR_OF_MASK (0x80000) +#define MCF_PCI_PCIRFCR_UF_MASK (0x100000) +#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCIRFCR_IP_MASK (0x800000) +#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIRFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFAR */ +#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ +#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ +#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + + +#endif /* __MCF5475_PCI_H__ */ diff --git a/BaS_GNU/include/MCF5475_PCIARB.h b/BaS_GNU/include/MCF5475_PCIARB.h new file mode 100644 index 0000000..3e793a1 --- /dev/null +++ b/BaS_GNU/include/MCF5475_PCIARB.h @@ -0,0 +1,43 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCIARB_H__ +#define __MCF5475_PCIARB_H__ + + +/********************************************************************* +* +* PCI Bus Arbiter Module (PCIARB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCIARB_PACR (*(vuint32*)(&__MBAR[0xC00])) +#define MCF_PCIARB_PASR (*(vuint32*)(&__MBAR[0xC04])) + + +/* Bit definitions and macros for MCF_PCIARB_PACR */ +#define MCF_PCIARB_PACR_INTMPRI (0x1) +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1) +#define MCF_PCIARB_PACR_INTMINTEN (0x10000) +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11) +#define MCF_PCIARB_PACR_DS (0x80000000) + +/* Bit definitions and macros for MCF_PCIARB_PASR */ +#define MCF_PCIARB_PASR_ITLMBK (0x10000) +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11) + + +#endif /* __MCF5475_PCIARB_H__ */ diff --git a/BaS_GNU/include/MCF5475_PSC.h b/BaS_GNU/include/MCF5475_PSC.h new file mode 100644 index 0000000..2165c57 --- /dev/null +++ b/BaS_GNU/include/MCF5475_PSC.h @@ -0,0 +1,527 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PSC_H__ +#define __MCF5475_PSC_H__ + + +/********************************************************************* +* +* Programmable Serial Controller (PSC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PSC0_PSCMR2 (*(vuint8 *)(&__MBAR[0x8600])) +#define MCF_PSC0_PSCMR1 (*(vuint8 *)(&__MBAR[0x8600])) +#define MCF_PSC0_PSCCSR (*(vuint8 *)(&__MBAR[0x8604])) +#define MCF_PSC0_PSCSR (*(vuint16*)(&__MBAR[0x8604])) +#define MCF_PSC0_PSCCR (*(vuint8 *)(&__MBAR[0x8608])) +#define MCF_PSC0_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCIPCR (*(vuint8 *)(&__MBAR[0x8610])) +#define MCF_PSC0_PSCACR (*(vuint8 *)(&__MBAR[0x8610])) +#define MCF_PSC0_PSCIMR (*(vuint16*)(&__MBAR[0x8614])) +#define MCF_PSC0_PSCISR (*(vuint16*)(&__MBAR[0x8614])) +#define MCF_PSC0_PSCCTUR (*(vuint8 *)(&__MBAR[0x8618])) +#define MCF_PSC0_PSCCTLR (*(vuint8 *)(&__MBAR[0x861C])) +#define MCF_PSC0_PSCIP (*(vuint8 *)(&__MBAR[0x8634])) +#define MCF_PSC0_PSCOPSET (*(vuint8 *)(&__MBAR[0x8638])) +#define MCF_PSC0_PSCOPRESET (*(vuint8 *)(&__MBAR[0x863C])) +#define MCF_PSC0_PSCSICR (*(vuint8 *)(&__MBAR[0x8640])) +#define MCF_PSC0_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8644])) +#define MCF_PSC0_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8648])) +#define MCF_PSC0_PSCIRSDR (*(vuint8 *)(&__MBAR[0x864C])) +#define MCF_PSC0_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8650])) +#define MCF_PSC0_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8654])) +#define MCF_PSC0_PSCRFCNT (*(vuint16*)(&__MBAR[0x8658])) +#define MCF_PSC0_PSCTFCNT (*(vuint16*)(&__MBAR[0x865C])) +#define MCF_PSC0_PSCRFDR (*(vuint32*)(&__MBAR[0x8660])) +#define MCF_PSC0_PSCRFSR (*(vuint16*)(&__MBAR[0x8664])) +#define MCF_PSC0_PSCRFCR (*(vuint32*)(&__MBAR[0x8668])) +#define MCF_PSC0_PSCRFAR (*(vuint16*)(&__MBAR[0x866E])) +#define MCF_PSC0_PSCRFRP (*(vuint16*)(&__MBAR[0x8672])) +#define MCF_PSC0_PSCRFWP (*(vuint16*)(&__MBAR[0x8676])) +#define MCF_PSC0_PSCRLRFP (*(vuint16*)(&__MBAR[0x867A])) +#define MCF_PSC0_PSCRLWFP (*(vuint16*)(&__MBAR[0x867E])) +#define MCF_PSC0_PSCTFDR (*(vuint32*)(&__MBAR[0x8680])) +#define MCF_PSC0_PSCTFSR (*(vuint16*)(&__MBAR[0x8684])) +#define MCF_PSC0_PSCTFCR (*(vuint32*)(&__MBAR[0x8688])) +#define MCF_PSC0_PSCTFAR (*(vuint16*)(&__MBAR[0x868E])) +#define MCF_PSC0_PSCTFRP (*(vuint16*)(&__MBAR[0x8692])) +#define MCF_PSC0_PSCTFWP (*(vuint16*)(&__MBAR[0x8696])) +#define MCF_PSC0_PSCTLRFP (*(vuint16*)(&__MBAR[0x869A])) +#define MCF_PSC0_PSCTLWFP (*(vuint16*)(&__MBAR[0x869E])) + +#define MCF_PSC1_PSCMR2 (*(vuint8 *)(&__MBAR[0x8700])) +#define MCF_PSC1_PSCMR1 (*(vuint8 *)(&__MBAR[0x8700])) +#define MCF_PSC1_PSCCSR (*(vuint8 *)(&__MBAR[0x8704])) +#define MCF_PSC1_PSCSR (*(vuint16*)(&__MBAR[0x8704])) +#define MCF_PSC1_PSCCR (*(vuint8 *)(&__MBAR[0x8708])) +#define MCF_PSC1_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCIPCR (*(vuint8 *)(&__MBAR[0x8710])) +#define MCF_PSC1_PSCACR (*(vuint8 *)(&__MBAR[0x8710])) +#define MCF_PSC1_PSCIMR (*(vuint16*)(&__MBAR[0x8714])) +#define MCF_PSC1_PSCISR (*(vuint16*)(&__MBAR[0x8714])) +#define MCF_PSC1_PSCCTUR (*(vuint8 *)(&__MBAR[0x8718])) +#define MCF_PSC1_PSCCTLR (*(vuint8 *)(&__MBAR[0x871C])) +#define MCF_PSC1_PSCIP (*(vuint8 *)(&__MBAR[0x8734])) +#define MCF_PSC1_PSCOPSET (*(vuint8 *)(&__MBAR[0x8738])) +#define MCF_PSC1_PSCOPRESET (*(vuint8 *)(&__MBAR[0x873C])) +#define MCF_PSC1_PSCSICR (*(vuint8 *)(&__MBAR[0x8740])) +#define MCF_PSC1_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8744])) +#define MCF_PSC1_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8748])) +#define MCF_PSC1_PSCIRSDR (*(vuint8 *)(&__MBAR[0x874C])) +#define MCF_PSC1_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8750])) +#define MCF_PSC1_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8754])) +#define MCF_PSC1_PSCRFCNT (*(vuint16*)(&__MBAR[0x8758])) +#define MCF_PSC1_PSCTFCNT (*(vuint16*)(&__MBAR[0x875C])) +#define MCF_PSC1_PSCRFDR (*(vuint32*)(&__MBAR[0x8760])) +#define MCF_PSC1_PSCRFSR (*(vuint16*)(&__MBAR[0x8764])) +#define MCF_PSC1_PSCRFCR (*(vuint32*)(&__MBAR[0x8768])) +#define MCF_PSC1_PSCRFAR (*(vuint16*)(&__MBAR[0x876E])) +#define MCF_PSC1_PSCRFRP (*(vuint16*)(&__MBAR[0x8772])) +#define MCF_PSC1_PSCRFWP (*(vuint16*)(&__MBAR[0x8776])) +#define MCF_PSC1_PSCRLRFP (*(vuint16*)(&__MBAR[0x877A])) +#define MCF_PSC1_PSCRLWFP (*(vuint16*)(&__MBAR[0x877E])) +#define MCF_PSC1_PSCTFDR (*(vuint32*)(&__MBAR[0x8780])) +#define MCF_PSC1_PSCTFSR (*(vuint16*)(&__MBAR[0x8784])) +#define MCF_PSC1_PSCTFCR (*(vuint32*)(&__MBAR[0x8788])) +#define MCF_PSC1_PSCTFAR (*(vuint16*)(&__MBAR[0x878E])) +#define MCF_PSC1_PSCTFRP (*(vuint16*)(&__MBAR[0x8792])) +#define MCF_PSC1_PSCTFWP (*(vuint16*)(&__MBAR[0x8796])) +#define MCF_PSC1_PSCTLRFP (*(vuint16*)(&__MBAR[0x879A])) +#define MCF_PSC1_PSCTLWFP (*(vuint16*)(&__MBAR[0x879E])) + +#define MCF_PSC2_PSCMR2 (*(vuint8 *)(&__MBAR[0x8800])) +#define MCF_PSC2_PSCMR1 (*(vuint8 *)(&__MBAR[0x8800])) +#define MCF_PSC2_PSCCSR (*(vuint8 *)(&__MBAR[0x8804])) +#define MCF_PSC2_PSCSR (*(vuint16*)(&__MBAR[0x8804])) +#define MCF_PSC2_PSCCR (*(vuint8 *)(&__MBAR[0x8808])) +#define MCF_PSC2_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCIPCR (*(vuint8 *)(&__MBAR[0x8810])) +#define MCF_PSC2_PSCACR (*(vuint8 *)(&__MBAR[0x8810])) +#define MCF_PSC2_PSCIMR (*(vuint16*)(&__MBAR[0x8814])) +#define MCF_PSC2_PSCISR (*(vuint16*)(&__MBAR[0x8814])) +#define MCF_PSC2_PSCCTUR (*(vuint8 *)(&__MBAR[0x8818])) +#define MCF_PSC2_PSCCTLR (*(vuint8 *)(&__MBAR[0x881C])) +#define MCF_PSC2_PSCIP (*(vuint8 *)(&__MBAR[0x8834])) +#define MCF_PSC2_PSCOPSET (*(vuint8 *)(&__MBAR[0x8838])) +#define MCF_PSC2_PSCOPRESET (*(vuint8 *)(&__MBAR[0x883C])) +#define MCF_PSC2_PSCSICR (*(vuint8 *)(&__MBAR[0x8840])) +#define MCF_PSC2_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8844])) +#define MCF_PSC2_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8848])) +#define MCF_PSC2_PSCIRSDR (*(vuint8 *)(&__MBAR[0x884C])) +#define MCF_PSC2_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8850])) +#define MCF_PSC2_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8854])) +#define MCF_PSC2_PSCRFCNT (*(vuint16*)(&__MBAR[0x8858])) +#define MCF_PSC2_PSCTFCNT (*(vuint16*)(&__MBAR[0x885C])) +#define MCF_PSC2_PSCRFDR (*(vuint32*)(&__MBAR[0x8860])) +#define MCF_PSC2_PSCRFSR (*(vuint16*)(&__MBAR[0x8864])) +#define MCF_PSC2_PSCRFCR (*(vuint32*)(&__MBAR[0x8868])) +#define MCF_PSC2_PSCRFAR (*(vuint16*)(&__MBAR[0x886E])) +#define MCF_PSC2_PSCRFRP (*(vuint16*)(&__MBAR[0x8872])) +#define MCF_PSC2_PSCRFWP (*(vuint16*)(&__MBAR[0x8876])) +#define MCF_PSC2_PSCRLRFP (*(vuint16*)(&__MBAR[0x887A])) +#define MCF_PSC2_PSCRLWFP (*(vuint16*)(&__MBAR[0x887E])) +#define MCF_PSC2_PSCTFDR (*(vuint32*)(&__MBAR[0x8880])) +#define MCF_PSC2_PSCTFSR (*(vuint16*)(&__MBAR[0x8884])) +#define MCF_PSC2_PSCTFCR (*(vuint32*)(&__MBAR[0x8888])) +#define MCF_PSC2_PSCTFAR (*(vuint16*)(&__MBAR[0x888E])) +#define MCF_PSC2_PSCTFRP (*(vuint16*)(&__MBAR[0x8892])) +#define MCF_PSC2_PSCTFWP (*(vuint16*)(&__MBAR[0x8896])) +#define MCF_PSC2_PSCTLRFP (*(vuint16*)(&__MBAR[0x889A])) +#define MCF_PSC2_PSCTLWFP (*(vuint16*)(&__MBAR[0x889E])) + +#define MCF_PSC3_PSCMR2 (*(vuint8 *)(&__MBAR[0x8900])) +#define MCF_PSC3_PSCMR1 (*(vuint8 *)(&__MBAR[0x8900])) +#define MCF_PSC3_PSCCSR (*(vuint8 *)(&__MBAR[0x8904])) +#define MCF_PSC3_PSCSR (*(vuint16*)(&__MBAR[0x8904])) +#define MCF_PSC3_PSCCR (*(vuint8 *)(&__MBAR[0x8908])) +#define MCF_PSC3_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCIPCR (*(vuint8 *)(&__MBAR[0x8910])) +#define MCF_PSC3_PSCACR (*(vuint8 *)(&__MBAR[0x8910])) +#define MCF_PSC3_PSCIMR (*(vuint16*)(&__MBAR[0x8914])) +#define MCF_PSC3_PSCISR (*(vuint16*)(&__MBAR[0x8914])) +#define MCF_PSC3_PSCCTUR (*(vuint8 *)(&__MBAR[0x8918])) +#define MCF_PSC3_PSCCTLR (*(vuint8 *)(&__MBAR[0x891C])) +#define MCF_PSC3_PSCIP (*(vuint8 *)(&__MBAR[0x8934])) +#define MCF_PSC3_PSCOPSET (*(vuint8 *)(&__MBAR[0x8938])) +#define MCF_PSC3_PSCOPRESET (*(vuint8 *)(&__MBAR[0x893C])) +#define MCF_PSC3_PSCSICR (*(vuint8 *)(&__MBAR[0x8940])) +#define MCF_PSC3_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8944])) +#define MCF_PSC3_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8948])) +#define MCF_PSC3_PSCIRSDR (*(vuint8 *)(&__MBAR[0x894C])) +#define MCF_PSC3_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8950])) +#define MCF_PSC3_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8954])) +#define MCF_PSC3_PSCRFCNT (*(vuint16*)(&__MBAR[0x8958])) +#define MCF_PSC3_PSCTFCNT (*(vuint16*)(&__MBAR[0x895C])) +#define MCF_PSC3_PSCRFDR (*(vuint32*)(&__MBAR[0x8960])) +#define MCF_PSC3_PSCRFSR (*(vuint16*)(&__MBAR[0x8964])) +#define MCF_PSC3_PSCRFCR (*(vuint32*)(&__MBAR[0x8968])) +#define MCF_PSC3_PSCRFAR (*(vuint16*)(&__MBAR[0x896E])) +#define MCF_PSC3_PSCRFRP (*(vuint16*)(&__MBAR[0x8972])) +#define MCF_PSC3_PSCRFWP (*(vuint16*)(&__MBAR[0x8976])) +#define MCF_PSC3_PSCRLRFP (*(vuint16*)(&__MBAR[0x897A])) +#define MCF_PSC3_PSCRLWFP (*(vuint16*)(&__MBAR[0x897E])) +#define MCF_PSC3_PSCTFDR (*(vuint32*)(&__MBAR[0x8980])) +#define MCF_PSC3_PSCTFSR (*(vuint16*)(&__MBAR[0x8984])) +#define MCF_PSC3_PSCTFCR (*(vuint32*)(&__MBAR[0x8988])) +#define MCF_PSC3_PSCTFAR (*(vuint16*)(&__MBAR[0x898E])) +#define MCF_PSC3_PSCTFRP (*(vuint16*)(&__MBAR[0x8992])) +#define MCF_PSC3_PSCTFWP (*(vuint16*)(&__MBAR[0x8996])) +#define MCF_PSC3_PSCTLRFP (*(vuint16*)(&__MBAR[0x899A])) +#define MCF_PSC3_PSCTLWFP (*(vuint16*)(&__MBAR[0x899E])) + +#define MCF_PSC_PSCMR(x) (*(vuint8 *)(&__MBAR[0x8600 + ((x)*0x100)])) +#define MCF_PSC_PSCCSR(x) (*(vuint8 *)(&__MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCSR(x) (*(vuint16*)(&__MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCCR(x) (*(vuint8 *)(&__MBAR[0x8608 + ((x)*0x100)])) +#define MCF_PSC_PSCRB_8BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_8BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_16BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_16BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_AC97(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_AC97(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCIPCR(x) (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCACR(x) (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCIMR(x) (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCISR(x) (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCCTUR(x) (*(vuint8 *)(&__MBAR[0x8618 + ((x)*0x100)])) +#define MCF_PSC_PSCCTLR(x) (*(vuint8 *)(&__MBAR[0x861C + ((x)*0x100)])) +#define MCF_PSC_PSCIP(x) (*(vuint8 *)(&__MBAR[0x8634 + ((x)*0x100)])) +#define MCF_PSC_PSCOPSET(x) (*(vuint8 *)(&__MBAR[0x8638 + ((x)*0x100)])) +#define MCF_PSC_PSCOPRESET(x) (*(vuint8 *)(&__MBAR[0x863C + ((x)*0x100)])) +#define MCF_PSC_PSCSICR(x) (*(vuint8 *)(&__MBAR[0x8640 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR1(x) (*(vuint8 *)(&__MBAR[0x8644 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR2(x) (*(vuint8 *)(&__MBAR[0x8648 + ((x)*0x100)])) +#define MCF_PSC_PSCIRSDR(x) (*(vuint8 *)(&__MBAR[0x864C + ((x)*0x100)])) +#define MCF_PSC_PSCIRMDR(x) (*(vuint8 *)(&__MBAR[0x8650 + ((x)*0x100)])) +#define MCF_PSC_PSCIRFDR(x) (*(vuint8 *)(&__MBAR[0x8654 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCNT(x) (*(vuint16*)(&__MBAR[0x8658 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCNT(x) (*(vuint16*)(&__MBAR[0x865C + ((x)*0x100)])) +#define MCF_PSC_PSCRFDR(x) (*(vuint32*)(&__MBAR[0x8660 + ((x)*0x100)])) +#define MCF_PSC_PSCRFSR(x) (*(vuint16*)(&__MBAR[0x8664 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCR(x) (*(vuint32*)(&__MBAR[0x8668 + ((x)*0x100)])) +#define MCF_PSC_PSCRFAR(x) (*(vuint16*)(&__MBAR[0x866E + ((x)*0x100)])) +#define MCF_PSC_PSCRFRP(x) (*(vuint16*)(&__MBAR[0x8672 + ((x)*0x100)])) +#define MCF_PSC_PSCRFWP(x) (*(vuint16*)(&__MBAR[0x8676 + ((x)*0x100)])) +#define MCF_PSC_PSCRLRFP(x) (*(vuint16*)(&__MBAR[0x867A + ((x)*0x100)])) +#define MCF_PSC_PSCRLWFP(x) (*(vuint16*)(&__MBAR[0x867E + ((x)*0x100)])) +#define MCF_PSC_PSCTFDR(x) (*(vuint32*)(&__MBAR[0x8680 + ((x)*0x100)])) +#define MCF_PSC_PSCTFSR(x) (*(vuint16*)(&__MBAR[0x8684 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCR(x) (*(vuint32*)(&__MBAR[0x8688 + ((x)*0x100)])) +#define MCF_PSC_PSCTFAR(x) (*(vuint16*)(&__MBAR[0x868E + ((x)*0x100)])) +#define MCF_PSC_PSCTFRP(x) (*(vuint16*)(&__MBAR[0x8692 + ((x)*0x100)])) +#define MCF_PSC_PSCTFWP(x) (*(vuint16*)(&__MBAR[0x8696 + ((x)*0x100)])) +#define MCF_PSC_PSCTLRFP(x) (*(vuint16*)(&__MBAR[0x869A + ((x)*0x100)])) +#define MCF_PSC_PSCTLWFP(x) (*(vuint16*)(&__MBAR[0x869E + ((x)*0x100)])) + +/* Bit definitions and macros for MCF_PSC_PSCMR */ +#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCMR_TXCTS (0x10) +#define MCF_PSC_PSCMR_TXRTS (0x20) +#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6) +#define MCF_PSC_PSCMR_CM_NORMAL (0) +#define MCF_PSC_PSCMR_CM_ECHO (0x40) +#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80) +#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0) +#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7) +#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8) +#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF) +#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C) +#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18) +#define MCF_PSC_PSCMR_PM_NONE (0x10) +#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC) +#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8) +#define MCF_PSC_PSCMR_PM_ODD (0x4) +#define MCF_PSC_PSCMR_PM_EVEN (0) +#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCMR_BC_5 (0) +#define MCF_PSC_PSCMR_BC_6 (0x1) +#define MCF_PSC_PSCMR_BC_7 (0x2) +#define MCF_PSC_PSCMR_BC_8 (0x3) +#define MCF_PSC_PSCMR_PT (0x4) +#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3) +#define MCF_PSC_PSCMR_ERR (0x20) +#define MCF_PSC_PSCMR_RXIRQ_FU (0x40) +#define MCF_PSC_PSCMR_RXRTS (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCCSR */ +#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4) +#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D) +#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E) +#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F) +#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0) +#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0) +#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0) + +/* Bit definitions and macros for MCF_PSC_PSCSR */ +#define MCF_PSC_PSCSR_ERR (0x40) +#define MCF_PSC_PSCSR_CDE_DEOF (0x80) +#define MCF_PSC_PSCSR_RXRDY (0x100) +#define MCF_PSC_PSCSR_FU (0x200) +#define MCF_PSC_PSCSR_TXRDY (0x400) +#define MCF_PSC_PSCSR_TXEMP_URERR (0x800) +#define MCF_PSC_PSCSR_OE (0x1000) +#define MCF_PSC_PSCSR_PE_CRCERR (0x2000) +#define MCF_PSC_PSCSR_FE_PHYERR (0x4000) +#define MCF_PSC_PSCSR_RB_NEOF (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCR */ +#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCCR_RX_ENABLED (0x1) +#define MCF_PSC_PSCCR_RX_DISABLED (0x2) +#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2) +#define MCF_PSC_PSCCR_TX_ENABLED (0x4) +#define MCF_PSC_PSCCR_TX_DISABLED (0x8) +#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4) +#define MCF_PSC_PSCCR_NONE (0) +#define MCF_PSC_PSCCR_RESET_MR (0x10) +#define MCF_PSC_PSCCR_RESET_RX (0x20) +#define MCF_PSC_PSCCR_RESET_TX (0x30) +#define MCF_PSC_PSCCR_RESET_ERROR (0x40) +#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50) +#define MCF_PSC_PSCCR_START_BREAK (0x60) +#define MCF_PSC_PSCCR_STOP_BREAK (0x70) + +/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */ +#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */ +#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */ +#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */ +#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */ +#define MCF_PSC_PSCRB_AC97_SOF (0x800) +#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */ +#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCIPCR */ +#define MCF_PSC_PSCIPCR_RESERVED (0xC) +#define MCF_PSC_PSCIPCR_CTS (0xD) +#define MCF_PSC_PSCIPCR_D_CTS (0x1C) +#define MCF_PSC_PSCIPCR_SYNC (0x8C) + +/* Bit definitions and macros for MCF_PSC_PSCACR */ +#define MCF_PSC_PSCACR_IEC0 (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCIMR */ +#define MCF_PSC_PSCIMR_ERR (0x40) +#define MCF_PSC_PSCIMR_DEOF (0x80) +#define MCF_PSC_PSCIMR_TXRDY (0x100) +#define MCF_PSC_PSCIMR_RXRDY_FU (0x200) +#define MCF_PSC_PSCIMR_DB (0x400) +#define MCF_PSC_PSCIMR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCISR */ +#define MCF_PSC_PSCISR_ERR (0x40) +#define MCF_PSC_PSCISR_DEOF (0x80) +#define MCF_PSC_PSCISR_TXRDY (0x100) +#define MCF_PSC_PSCISR_RXRDY_FU (0x200) +#define MCF_PSC_PSCISR_DB (0x400) +#define MCF_PSC_PSCISR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCTUR */ +#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCCTLR */ +#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIP */ +#define MCF_PSC_PSCIP_CTS (0x1) +#define MCF_PSC_PSCIP_TGL (0x40) +#define MCF_PSC_PSCIP_LPWR_B (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCOPSET */ +#define MCF_PSC_PSCOPSET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCOPRESET */ +#define MCF_PSC_PSCOPRESET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCSICR */ +#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0) +#define MCF_PSC_PSCSICR_SIM_UART (0) +#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1) +#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2) +#define MCF_PSC_PSCSICR_SIM_AC97 (0x3) +#define MCF_PSC_PSCSICR_SIM_SIR (0x4) +#define MCF_PSC_PSCSICR_SIM_MIR (0x5) +#define MCF_PSC_PSCSICR_SIM_FIR (0x6) +#define MCF_PSC_PSCSICR_SHDIR (0x10) +#define MCF_PSC_PSCSICR_DTS1 (0x20) +#define MCF_PSC_PSCSICR_AWR (0x40) +#define MCF_PSC_PSCSICR_ACRB (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */ +#define MCF_PSC_PSCIRCR1_SPUL (0x1) +#define MCF_PSC_PSCIRCR1_SIPEN (0x2) +#define MCF_PSC_PSCIRCR1_FD (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */ +#define MCF_PSC_PSCIRCR2_NXTEOF (0x1) +#define MCF_PSC_PSCIRCR2_ABORT (0x2) +#define MCF_PSC_PSCIRCR2_SIPREQ (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRSDR */ +#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIRMDR */ +#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0) +#define MCF_PSC_PSCIRMDR_FREQ (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRFDR */ +#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFCNT */ +#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFCNT */ +#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFDR */ +#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFSR */ +#define MCF_PSC_PSCRFSR_EMT (0x1) +#define MCF_PSC_PSCRFSR_ALARM (0x2) +#define MCF_PSC_PSCRFSR_FU (0x4) +#define MCF_PSC_PSCRFSR_FRMRDY (0x8) +#define MCF_PSC_PSCRFSR_OF (0x10) +#define MCF_PSC_PSCRFSR_UF (0x20) +#define MCF_PSC_PSCRFSR_RXW (0x40) +#define MCF_PSC_PSCRFSR_FAE (0x80) +#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCRFSR_TXW (0x4000) +#define MCF_PSC_PSCRFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCRFCR */ +#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCRFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCRFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCRFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCRFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_PSC_PSCRFAR */ +#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFRP */ +#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFWP */ +#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLRFP */ +#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLWFP */ +#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFDR */ +#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFSR */ +#define MCF_PSC_PSCTFSR_EMT (0x1) +#define MCF_PSC_PSCTFSR_ALARM (0x2) +#define MCF_PSC_PSCTFSR_FU (0x4) +#define MCF_PSC_PSCTFSR_FRMRDY (0x8) +#define MCF_PSC_PSCTFSR_OF (0x10) +#define MCF_PSC_PSCTFSR_UF (0x20) +#define MCF_PSC_PSCTFSR_RXW (0x40) +#define MCF_PSC_PSCTFSR_FAE (0x80) +#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCTFSR_TXW (0x4000) +#define MCF_PSC_PSCTFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCTFCR */ +#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCTFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCTFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCTFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCTFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCTFCR_TIMER (0x10000000) +#define MCF_PSC_PSCTFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PSC_PSCTFAR */ +#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFRP */ +#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFWP */ +#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLRFP */ +#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLWFP */ +#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0) + + +#endif /* __MCF5475_PSC_H__ */ diff --git a/BaS_GNU/include/MCF5475_SDRAMC.h b/BaS_GNU/include/MCF5475_SDRAMC.h new file mode 100644 index 0000000..843ac12 --- /dev/null +++ b/BaS_GNU/include/MCF5475_SDRAMC.h @@ -0,0 +1,106 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SDRAMC_H__ +#define __MCF5475_SDRAMC_H__ + + +/********************************************************************* +* +* Synchronous DRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_SDRAMDS (*(vuint32*)(&__MBAR[0x4])) +#define MCF_SDRAMC_CS0CFG (*(vuint32*)(&__MBAR[0x20])) +#define MCF_SDRAMC_CS1CFG (*(vuint32*)(&__MBAR[0x24])) +#define MCF_SDRAMC_CS2CFG (*(vuint32*)(&__MBAR[0x28])) +#define MCF_SDRAMC_CS3CFG (*(vuint32*)(&__MBAR[0x2C])) +#define MCF_SDRAMC_SDMR (*(vuint32*)(&__MBAR[0x100])) +#define MCF_SDRAMC_SDCR (*(vuint32*)(&__MBAR[0x104])) +#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(&__MBAR[0x108])) +#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(&__MBAR[0x10C])) +#define MCF_SDRAMC_CSCFG(x) (*(vuint32*)(&__MBAR[0x20 + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ +#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0) +#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2) +#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4) +#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6) +#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8) +#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0) +#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1) +#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2) +#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3) + +/* Bit definitions and macros for MCF_SDRAMC_CSCFG */ +#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0) +#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0) +#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13) +#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14) +#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15) +#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16) +#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17) +#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18) +#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19) +#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A) +#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B) +#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C) +#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D) +#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E) +#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F) +#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14) +#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000) + +/* Bit definitions and macros for MCF_SDRAMC_SDMR */ +#define MCF_SDRAMC_SDMR_CMD (0x10000) +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12) +#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E) +#define MCF_SDRAMC_SDMR_BK_LMR (0) +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCR */ +#define MCF_SDRAMC_SDCR_IPALL (0x2) +#define MCF_SDRAMC_SDCR_IREF (0x4) +#define MCF_SDRAMC_SDCR_BUFF (0x10) +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10) +#define MCF_SDRAMC_SDCR_DRIVE (0x400000) +#define MCF_SDRAMC_SDCR_AP (0x800000) +#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18) +#define MCF_SDRAMC_SDCR_REF (0x10000000) +#define MCF_SDRAMC_SDCR_DDR (0x20000000) +#define MCF_SDRAMC_SDCR_CKE (0x40000000) +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ +#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4) +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC) +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10) +#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18) +#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10) +#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18) +#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C) + + +#endif /* __MCF5475_SDRAMC_H__ */ diff --git a/BaS_GNU/include/MCF5475_SEC.h b/BaS_GNU/include/MCF5475_SEC.h new file mode 100644 index 0000000..ce02c30 --- /dev/null +++ b/BaS_GNU/include/MCF5475_SEC.h @@ -0,0 +1,398 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SEC_H__ +#define __MCF5475_SEC_H__ + + +/********************************************************************* +* +* Integrated Security Engine (SEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SEC_EUACRH (*(vuint32*)(&__MBAR[0x21000])) +#define MCF_SEC_EUACRL (*(vuint32*)(&__MBAR[0x21004])) +#define MCF_SEC_SIMRH (*(vuint32*)(&__MBAR[0x21008])) +#define MCF_SEC_SIMRL (*(vuint32*)(&__MBAR[0x2100C])) +#define MCF_SEC_SISRH (*(vuint32*)(&__MBAR[0x21010])) +#define MCF_SEC_SISRL (*(vuint32*)(&__MBAR[0x21014])) +#define MCF_SEC_SICRH (*(vuint32*)(&__MBAR[0x21018])) +#define MCF_SEC_SICRL (*(vuint32*)(&__MBAR[0x2101C])) +#define MCF_SEC_SIDR (*(vuint32*)(&__MBAR[0x21020])) +#define MCF_SEC_EUASRH (*(vuint32*)(&__MBAR[0x21028])) +#define MCF_SEC_EUASRL (*(vuint32*)(&__MBAR[0x2102C])) +#define MCF_SEC_SMCR (*(vuint32*)(&__MBAR[0x21030])) +#define MCF_SEC_MEAR (*(vuint32*)(&__MBAR[0x21038])) +#define MCF_SEC_CCCR0 (*(vuint32*)(&__MBAR[0x2200C])) +#define MCF_SEC_CCPSRH0 (*(vuint32*)(&__MBAR[0x22010])) +#define MCF_SEC_CCPSRL0 (*(vuint32*)(&__MBAR[0x22014])) +#define MCF_SEC_CDPR0 (*(vuint32*)(&__MBAR[0x22044])) +#define MCF_SEC_FR0 (*(vuint32*)(&__MBAR[0x2204C])) +#define MCF_SEC_CCCR1 (*(vuint32*)(&__MBAR[0x2300C])) +#define MCF_SEC_CCPSRH1 (*(vuint32*)(&__MBAR[0x23010])) +#define MCF_SEC_CCPSRL1 (*(vuint32*)(&__MBAR[0x23014])) +#define MCF_SEC_CDPR1 (*(vuint32*)(&__MBAR[0x23044])) +#define MCF_SEC_FR1 (*(vuint32*)(&__MBAR[0x2304C])) +#define MCF_SEC_AFRCR (*(vuint32*)(&__MBAR[0x28018])) +#define MCF_SEC_AFSR (*(vuint32*)(&__MBAR[0x28028])) +#define MCF_SEC_AFISR (*(vuint32*)(&__MBAR[0x28030])) +#define MCF_SEC_AFIMR (*(vuint32*)(&__MBAR[0x28038])) +#define MCF_SEC_DRCR (*(vuint32*)(&__MBAR[0x2A018])) +#define MCF_SEC_DSR (*(vuint32*)(&__MBAR[0x2A028])) +#define MCF_SEC_DISR (*(vuint32*)(&__MBAR[0x2A030])) +#define MCF_SEC_DIMR (*(vuint32*)(&__MBAR[0x2A038])) +#define MCF_SEC_MDRCR (*(vuint32*)(&__MBAR[0x2C018])) +#define MCF_SEC_MDSR (*(vuint32*)(&__MBAR[0x2C028])) +#define MCF_SEC_MDISR (*(vuint32*)(&__MBAR[0x2C030])) +#define MCF_SEC_MDIMR (*(vuint32*)(&__MBAR[0x2C038])) +#define MCF_SEC_RNGRCR (*(vuint32*)(&__MBAR[0x2E018])) +#define MCF_SEC_RNGSR (*(vuint32*)(&__MBAR[0x2E028])) +#define MCF_SEC_RNGISR (*(vuint32*)(&__MBAR[0x2E030])) +#define MCF_SEC_RNGIMR (*(vuint32*)(&__MBAR[0x2E038])) +#define MCF_SEC_AESRCR (*(vuint32*)(&__MBAR[0x32018])) +#define MCF_SEC_AESSR (*(vuint32*)(&__MBAR[0x32028])) +#define MCF_SEC_AESISR (*(vuint32*)(&__MBAR[0x32030])) +#define MCF_SEC_AESIMR (*(vuint32*)(&__MBAR[0x32038])) +#define MCF_SEC_CCCRn(x) (*(vuint32*)(&__MBAR[0x2200C + ((x)*0x1000)])) +#define MCF_SEC_CCPSRHn(x) (*(vuint32*)(&__MBAR[0x22010 + ((x)*0x1000)])) +#define MCF_SEC_CCPSRLn(x) (*(vuint32*)(&__MBAR[0x22014 + ((x)*0x1000)])) +#define MCF_SEC_CDPRn(x) (*(vuint32*)(&__MBAR[0x22044 + ((x)*0x1000)])) +#define MCF_SEC_FRn(x) (*(vuint32*)(&__MBAR[0x2204C + ((x)*0x1000)])) + + +/* Bit definitions and macros for MCF_SEC_EUACRH */ +#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1) +#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2) +#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100) +#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200) +#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18) +#define MCF_SEC_EUACRH_RNG_NOASSIGN (0) +#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000) +#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000) + +/* Bit definitions and macros for MCF_SEC_EUACRL */ +#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUACRL_AESU_NOASSIGN (0) +#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000) +#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000) +#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SIMRH */ +#define MCF_SEC_SIMRH_AERR (0x8000000) +#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SIMRL */ +#define MCF_SEC_SIMRL_TEA (0x40) +#define MCF_SEC_SIMRL_DEU_DN (0x100) +#define MCF_SEC_SIMRL_DEU_ERR (0x200) +#define MCF_SEC_SIMRL_AESU_DN (0x1000) +#define MCF_SEC_SIMRL_AESU_ERR (0x2000) +#define MCF_SEC_SIMRL_MDEU_DN (0x10000) +#define MCF_SEC_SIMRL_MDEU_ERR (0x20000) +#define MCF_SEC_SIMRL_AFEU_DN (0x100000) +#define MCF_SEC_SIMRL_AFEU_ERR (0x200000) +#define MCF_SEC_SIMRL_RNG_DN (0x1000000) +#define MCF_SEC_SIMRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SISRH */ +#define MCF_SEC_SISRH_AERR (0x8000000) +#define MCF_SEC_SISRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SISRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SISRL */ +#define MCF_SEC_SISRL_TEA (0x40) +#define MCF_SEC_SISRL_DEU_DN (0x100) +#define MCF_SEC_SISRL_DEU_ERR (0x200) +#define MCF_SEC_SISRL_AESU_DN (0x1000) +#define MCF_SEC_SISRL_AESU_ERR (0x2000) +#define MCF_SEC_SISRL_MDEU_DN (0x10000) +#define MCF_SEC_SISRL_MDEU_ERR (0x20000) +#define MCF_SEC_SISRL_AFEU_DN (0x100000) +#define MCF_SEC_SISRL_AFEU_ERR (0x200000) +#define MCF_SEC_SISRL_RNG_DN (0x1000000) +#define MCF_SEC_SISRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SICRH */ +#define MCF_SEC_SICRH_AERR (0x8000000) +#define MCF_SEC_SICRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SICRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SICRL */ +#define MCF_SEC_SICRL_TEA (0x40) +#define MCF_SEC_SICRL_DEU_DN (0x100) +#define MCF_SEC_SICRL_DEU_ERR (0x200) +#define MCF_SEC_SICRL_AESU_DN (0x1000) +#define MCF_SEC_SICRL_AESU_ERR (0x2000) +#define MCF_SEC_SICRL_MDEU_DN (0x10000) +#define MCF_SEC_SICRL_MDEU_ERR (0x20000) +#define MCF_SEC_SICRL_AFEU_DN (0x100000) +#define MCF_SEC_SICRL_AFEU_ERR (0x200000) +#define MCF_SEC_SICRL_RNG_DN (0x1000000) +#define MCF_SEC_SICRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SIDR */ +#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_EUASRH */ +#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_EUASRL */ +#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SMCR */ +#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4) +#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10) +#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20) +#define MCF_SEC_SMCR_SWR (0x1000000) + +/* Bit definitions and macros for MCF_SEC_MEAR */ +#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCCRn */ +#define MCF_SEC_CCCRn_RST (0x1) +#define MCF_SEC_CCCRn_CDIE (0x2) +#define MCF_SEC_CCCRn_NT (0x4) +#define MCF_SEC_CCCRn_NE (0x8) +#define MCF_SEC_CCCRn_WE (0x10) +#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8) +#define MCF_SEC_CCCRn_BURST_SIZE_2 (0) +#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100) +#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200) +#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300) +#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400) +#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500) +#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600) +#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700) + +/* Bit definitions and macros for MCF_SEC_CCPSRHn */ +#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCPSRLn */ +#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0) +#define MCF_SEC_CCPSRLn_EUERR (0x100) +#define MCF_SEC_CCPSRLn_SERR (0x200) +#define MCF_SEC_CCPSRLn_DERR (0x400) +#define MCF_SEC_CCPSRLn_PERR (0x1000) +#define MCF_SEC_CCPSRLn_TEA (0x2000) +#define MCF_SEC_CCPSRLn_SD (0x10000) +#define MCF_SEC_CCPSRLn_PD (0x20000) +#define MCF_SEC_CCPSRLn_SRD (0x40000) +#define MCF_SEC_CCPSRLn_PRD (0x80000) +#define MCF_SEC_CCPSRLn_SG (0x100000) +#define MCF_SEC_CCPSRLn_PG (0x200000) +#define MCF_SEC_CCPSRLn_SR (0x400000) +#define MCF_SEC_CCPSRLn_PR (0x800000) +#define MCF_SEC_CCPSRLn_MO (0x1000000) +#define MCF_SEC_CCPSRLn_MI (0x2000000) +#define MCF_SEC_CCPSRLn_STAT (0x4000000) + +/* Bit definitions and macros for MCF_SEC_CDPRn */ +#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_FRn */ +#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_AFRCR */ +#define MCF_SEC_AFRCR_SR (0x1000000) +#define MCF_SEC_AFRCR_MI (0x2000000) +#define MCF_SEC_AFRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AFSR */ +#define MCF_SEC_AFSR_RD (0x1000000) +#define MCF_SEC_AFSR_ID (0x2000000) +#define MCF_SEC_AFSR_IE (0x4000000) +#define MCF_SEC_AFSR_OFR (0x8000000) +#define MCF_SEC_AFSR_IFW (0x10000000) +#define MCF_SEC_AFSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AFISR */ +#define MCF_SEC_AFISR_DSE (0x10000) +#define MCF_SEC_AFISR_KSE (0x20000) +#define MCF_SEC_AFISR_CE (0x40000) +#define MCF_SEC_AFISR_ERE (0x80000) +#define MCF_SEC_AFISR_IE (0x100000) +#define MCF_SEC_AFISR_OFU (0x2000000) +#define MCF_SEC_AFISR_IFO (0x4000000) +#define MCF_SEC_AFISR_IFE (0x10000000) +#define MCF_SEC_AFISR_OFE (0x20000000) +#define MCF_SEC_AFISR_AE (0x40000000) +#define MCF_SEC_AFISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AFIMR */ +#define MCF_SEC_AFIMR_DSE (0x10000) +#define MCF_SEC_AFIMR_KSE (0x20000) +#define MCF_SEC_AFIMR_CE (0x40000) +#define MCF_SEC_AFIMR_ERE (0x80000) +#define MCF_SEC_AFIMR_IE (0x100000) +#define MCF_SEC_AFIMR_OFU (0x2000000) +#define MCF_SEC_AFIMR_IFO (0x4000000) +#define MCF_SEC_AFIMR_IFE (0x10000000) +#define MCF_SEC_AFIMR_OFE (0x20000000) +#define MCF_SEC_AFIMR_AE (0x40000000) +#define MCF_SEC_AFIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DRCR */ +#define MCF_SEC_DRCR_SR (0x1000000) +#define MCF_SEC_DRCR_MI (0x2000000) +#define MCF_SEC_DRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_DSR */ +#define MCF_SEC_DSR_RD (0x1000000) +#define MCF_SEC_DSR_ID (0x2000000) +#define MCF_SEC_DSR_IE (0x4000000) +#define MCF_SEC_DSR_OFR (0x8000000) +#define MCF_SEC_DSR_IFW (0x10000000) +#define MCF_SEC_DSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_DISR */ +#define MCF_SEC_DISR_DSE (0x10000) +#define MCF_SEC_DISR_KSE (0x20000) +#define MCF_SEC_DISR_CE (0x40000) +#define MCF_SEC_DISR_ERE (0x80000) +#define MCF_SEC_DISR_IE (0x100000) +#define MCF_SEC_DISR_KPE (0x200000) +#define MCF_SEC_DISR_OFU (0x2000000) +#define MCF_SEC_DISR_IFO (0x4000000) +#define MCF_SEC_DISR_IFE (0x10000000) +#define MCF_SEC_DISR_OFE (0x20000000) +#define MCF_SEC_DISR_AE (0x40000000) +#define MCF_SEC_DISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DIMR */ +#define MCF_SEC_DIMR_DSE (0x10000) +#define MCF_SEC_DIMR_KSE (0x20000) +#define MCF_SEC_DIMR_CE (0x40000) +#define MCF_SEC_DIMR_ERE (0x80000) +#define MCF_SEC_DIMR_IE (0x100000) +#define MCF_SEC_DIMR_KPE (0x200000) +#define MCF_SEC_DIMR_OFU (0x2000000) +#define MCF_SEC_DIMR_IFO (0x4000000) +#define MCF_SEC_DIMR_IFE (0x10000000) +#define MCF_SEC_DIMR_OFE (0x20000000) +#define MCF_SEC_DIMR_AE (0x40000000) +#define MCF_SEC_DIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDRCR */ +#define MCF_SEC_MDRCR_SR (0x1000000) +#define MCF_SEC_MDRCR_MI (0x2000000) +#define MCF_SEC_MDRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_MDSR */ +#define MCF_SEC_MDSR_RD (0x1000000) +#define MCF_SEC_MDSR_ID (0x2000000) +#define MCF_SEC_MDSR_IE (0x4000000) +#define MCF_SEC_MDSR_IFW (0x10000000) +#define MCF_SEC_MDSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_MDISR */ +#define MCF_SEC_MDISR_DSE (0x10000) +#define MCF_SEC_MDISR_KSE (0x20000) +#define MCF_SEC_MDISR_CE (0x40000) +#define MCF_SEC_MDISR_ERE (0x80000) +#define MCF_SEC_MDISR_IE (0x100000) +#define MCF_SEC_MDISR_IFO (0x4000000) +#define MCF_SEC_MDISR_AE (0x40000000) +#define MCF_SEC_MDISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDIMR */ +#define MCF_SEC_MDIMR_DSE (0x10000) +#define MCF_SEC_MDIMR_KSE (0x20000) +#define MCF_SEC_MDIMR_CE (0x40000) +#define MCF_SEC_MDIMR_ERE (0x80000) +#define MCF_SEC_MDIMR_IE (0x100000) +#define MCF_SEC_MDIMR_IFO (0x4000000) +#define MCF_SEC_MDIMR_AE (0x40000000) +#define MCF_SEC_MDIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGRCR */ +#define MCF_SEC_RNGRCR_SR (0x1000000) +#define MCF_SEC_RNGRCR_MI (0x2000000) +#define MCF_SEC_RNGRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_RNGSR */ +#define MCF_SEC_RNGSR_RD (0x1000000) +#define MCF_SEC_RNGSR_IE (0x4000000) +#define MCF_SEC_RNGSR_OFR (0x8000000) +#define MCF_SEC_RNGSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_RNGISR */ +#define MCF_SEC_RNGISR_IE (0x100000) +#define MCF_SEC_RNGISR_OFU (0x2000000) +#define MCF_SEC_RNGISR_AE (0x40000000) +#define MCF_SEC_RNGISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGIMR */ +#define MCF_SEC_RNGIMR_IE (0x100000) +#define MCF_SEC_RNGIMR_OFU (0x2000000) +#define MCF_SEC_RNGIMR_AE (0x40000000) +#define MCF_SEC_RNGIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESRCR */ +#define MCF_SEC_AESRCR_SR (0x1000000) +#define MCF_SEC_AESRCR_MI (0x2000000) +#define MCF_SEC_AESRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AESSR */ +#define MCF_SEC_AESSR_RD (0x1000000) +#define MCF_SEC_AESSR_ID (0x2000000) +#define MCF_SEC_AESSR_IE (0x4000000) +#define MCF_SEC_AESSR_OFR (0x8000000) +#define MCF_SEC_AESSR_IFW (0x10000000) +#define MCF_SEC_AESSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AESISR */ +#define MCF_SEC_AESISR_DSE (0x10000) +#define MCF_SEC_AESISR_KSE (0x20000) +#define MCF_SEC_AESISR_CE (0x40000) +#define MCF_SEC_AESISR_ERE (0x80000) +#define MCF_SEC_AESISR_IE (0x100000) +#define MCF_SEC_AESISR_OFU (0x2000000) +#define MCF_SEC_AESISR_IFO (0x4000000) +#define MCF_SEC_AESISR_IFE (0x10000000) +#define MCF_SEC_AESISR_OFE (0x20000000) +#define MCF_SEC_AESISR_AE (0x40000000) +#define MCF_SEC_AESISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESIMR */ +#define MCF_SEC_AESIMR_DSE (0x10000) +#define MCF_SEC_AESIMR_KSE (0x20000) +#define MCF_SEC_AESIMR_CE (0x40000) +#define MCF_SEC_AESIMR_ERE (0x80000) +#define MCF_SEC_AESIMR_IE (0x100000) +#define MCF_SEC_AESIMR_OFU (0x2000000) +#define MCF_SEC_AESIMR_IFO (0x4000000) +#define MCF_SEC_AESIMR_IFE (0x10000000) +#define MCF_SEC_AESIMR_OFE (0x20000000) +#define MCF_SEC_AESIMR_AE (0x40000000) +#define MCF_SEC_AESIMR_ME (0x80000000) + + +#endif /* __MCF5475_SEC_H__ */ diff --git a/BaS_GNU/include/MCF5475_SIU.h b/BaS_GNU/include/MCF5475_SIU.h new file mode 100644 index 0000000..498aa91 --- /dev/null +++ b/BaS_GNU/include/MCF5475_SIU.h @@ -0,0 +1,52 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SIU_H__ +#define __MCF5475_SIU_H__ + + +/********************************************************************* +* +* System Integration Unit (SIU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SIU_SBCR (*(vuint32*)(&__MBAR[0x10])) +#define MCF_SIU_SECSACR (*(vuint32*)(&__MBAR[0x38])) +#define MCF_SIU_RSR (*(vuint32*)(&__MBAR[0x44])) +#define MCF_SIU_JTAGID (*(vuint32*)(&__MBAR[0x50])) + + +/* Bit definitions and macros for MCF_SIU_SBCR */ +#define MCF_SIU_SBCR_PIN2DSPI (0x8000000) +#define MCF_SIU_SBCR_DMA2CPU (0x10000000) +#define MCF_SIU_SBCR_CPU2DMA (0x20000000) +#define MCF_SIU_SBCR_PIN2DMA (0x40000000) +#define MCF_SIU_SBCR_PIN2CPU (0x80000000) + +/* Bit definitions and macros for MCF_SIU_SECSACR */ +#define MCF_SIU_SECSACR_SEQEN (0x1) + +/* Bit definitions and macros for MCF_SIU_RSR */ +#define MCF_SIU_RSR_RST (0x1) +#define MCF_SIU_RSR_RSTWD (0x2) +#define MCF_SIU_RSR_RSTJTG (0x8) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF5475_SIU_H__ */ diff --git a/BaS_GNU/include/MCF5475_SLT.h b/BaS_GNU/include/MCF5475_SLT.h new file mode 100644 index 0000000..44a74c6 --- /dev/null +++ b/BaS_GNU/include/MCF5475_SLT.h @@ -0,0 +1,59 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SLT_H__ +#define __MCF5475_SLT_H__ + + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SLT0_STCNT (*(vuint32*)(&__MBAR[0x900])) +#define MCF_SLT0_SCR (*(vuint32*)(&__MBAR[0x904])) +#define MCF_SLT0_SCNT (*(vuint32*)(&__MBAR[0x908])) +#define MCF_SLT0_SSR (*(vuint32*)(&__MBAR[0x90C])) + +#define MCF_SLT1_STCNT (*(vuint32*)(&__MBAR[0x910])) +#define MCF_SLT1_SCR (*(vuint32*)(&__MBAR[0x914])) +#define MCF_SLT1_SCNT (*(vuint32*)(&__MBAR[0x918])) +#define MCF_SLT1_SSR (*(vuint32*)(&__MBAR[0x91C])) + +#define MCF_SLT_STCNT(x) (*(vuint32*)(&__MBAR[0x900 + ((x)*0x10)])) +#define MCF_SLT_SCR(x) (*(vuint32*)(&__MBAR[0x904 + ((x)*0x10)])) +#define MCF_SLT_SCNT(x) (*(vuint32*)(&__MBAR[0x908 + ((x)*0x10)])) +#define MCF_SLT_SSR(x) (*(vuint32*)(&__MBAR[0x90C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_SLT_STCNT */ +#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SCR */ +#define MCF_SLT_SCR_TEN (0x1000000) +#define MCF_SLT_SCR_IEN (0x2000000) +#define MCF_SLT_SCR_RUN (0x4000000) + +/* Bit definitions and macros for MCF_SLT_SCNT */ +#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SSR */ +#define MCF_SLT_SSR_ST (0x1000000) +#define MCF_SLT_SSR_BE (0x2000000) + + +#endif /* __MCF5475_SLT_H__ */ diff --git a/BaS_GNU/include/MCF5475_SRAM.h b/BaS_GNU/include/MCF5475_SRAM.h new file mode 100644 index 0000000..7e645fe --- /dev/null +++ b/BaS_GNU/include/MCF5475_SRAM.h @@ -0,0 +1,62 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SRAM_H__ +#define __MCF5475_SRAM_H__ + + +/********************************************************************* +* +* System SRAM Module (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SRAM_SSCR (*(vuint32*)(&__MBAR[0x1FFC0])) +#define MCF_SRAM_TCCR (*(vuint32*)(&__MBAR[0x1FFC4])) +#define MCF_SRAM_TCCRDR (*(vuint32*)(&__MBAR[0x1FFC8])) +#define MCF_SRAM_TCCRDW (*(vuint32*)(&__MBAR[0x1FFCC])) +#define MCF_SRAM_TCCRSEC (*(vuint32*)(&__MBAR[0x1FFD0])) + + +/* Bit definitions and macros for MCF_SRAM_SSCR */ +#define MCF_SRAM_SSCR_INLV (0x10000) + +/* Bit definitions and macros for MCF_SRAM_TCCR */ +#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDR */ +#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDW */ +#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRSEC */ +#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18) + + +#endif /* __MCF5475_SRAM_H__ */ diff --git a/BaS_GNU/include/MCF5475_USB.h b/BaS_GNU/include/MCF5475_USB.h new file mode 100644 index 0000000..da9e6db --- /dev/null +++ b/BaS_GNU/include/MCF5475_USB.h @@ -0,0 +1,554 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_USB_H__ +#define __MCF5475_USB_H__ + + +/********************************************************************* +* +* Universal Serial Bus Interface (USB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_USB_USBAISR (*(vuint8 *)(&__MBAR[0xB000])) +#define MCF_USB_USBAIMR (*(vuint8 *)(&__MBAR[0xB001])) +#define MCF_USB_EPINFO (*(vuint8 *)(&__MBAR[0xB003])) +#define MCF_USB_CFGR (*(vuint8 *)(&__MBAR[0xB004])) +#define MCF_USB_CFGAR (*(vuint8 *)(&__MBAR[0xB005])) +#define MCF_USB_SPEEDR (*(vuint8 *)(&__MBAR[0xB006])) +#define MCF_USB_FRMNUMR (*(vuint16*)(&__MBAR[0xB00E])) +#define MCF_USB_EPTNR (*(vuint16*)(&__MBAR[0xB010])) +#define MCF_USB_IFUR (*(vuint16*)(&__MBAR[0xB014])) +#define MCF_USB_IFR0 (*(vuint16*)(&__MBAR[0xB040])) +#define MCF_USB_IFR1 (*(vuint16*)(&__MBAR[0xB042])) +#define MCF_USB_IFR2 (*(vuint16*)(&__MBAR[0xB044])) +#define MCF_USB_IFR3 (*(vuint16*)(&__MBAR[0xB046])) +#define MCF_USB_IFR4 (*(vuint16*)(&__MBAR[0xB048])) +#define MCF_USB_IFR5 (*(vuint16*)(&__MBAR[0xB04A])) +#define MCF_USB_IFR6 (*(vuint16*)(&__MBAR[0xB04C])) +#define MCF_USB_IFR7 (*(vuint16*)(&__MBAR[0xB04E])) +#define MCF_USB_IFR8 (*(vuint16*)(&__MBAR[0xB050])) +#define MCF_USB_IFR9 (*(vuint16*)(&__MBAR[0xB052])) +#define MCF_USB_IFR10 (*(vuint16*)(&__MBAR[0xB054])) +#define MCF_USB_IFR11 (*(vuint16*)(&__MBAR[0xB056])) +#define MCF_USB_IFR12 (*(vuint16*)(&__MBAR[0xB058])) +#define MCF_USB_IFR13 (*(vuint16*)(&__MBAR[0xB05A])) +#define MCF_USB_IFR14 (*(vuint16*)(&__MBAR[0xB05C])) +#define MCF_USB_IFR15 (*(vuint16*)(&__MBAR[0xB05E])) +#define MCF_USB_IFR16 (*(vuint16*)(&__MBAR[0xB060])) +#define MCF_USB_IFR17 (*(vuint16*)(&__MBAR[0xB062])) +#define MCF_USB_IFR18 (*(vuint16*)(&__MBAR[0xB064])) +#define MCF_USB_IFR19 (*(vuint16*)(&__MBAR[0xB066])) +#define MCF_USB_IFR20 (*(vuint16*)(&__MBAR[0xB068])) +#define MCF_USB_IFR21 (*(vuint16*)(&__MBAR[0xB06A])) +#define MCF_USB_IFR22 (*(vuint16*)(&__MBAR[0xB06C])) +#define MCF_USB_IFR23 (*(vuint16*)(&__MBAR[0xB06E])) +#define MCF_USB_IFR24 (*(vuint16*)(&__MBAR[0xB070])) +#define MCF_USB_IFR25 (*(vuint16*)(&__MBAR[0xB072])) +#define MCF_USB_IFR26 (*(vuint16*)(&__MBAR[0xB074])) +#define MCF_USB_IFR27 (*(vuint16*)(&__MBAR[0xB076])) +#define MCF_USB_IFR28 (*(vuint16*)(&__MBAR[0xB078])) +#define MCF_USB_IFR29 (*(vuint16*)(&__MBAR[0xB07A])) +#define MCF_USB_IFR30 (*(vuint16*)(&__MBAR[0xB07C])) +#define MCF_USB_IFR31 (*(vuint16*)(&__MBAR[0xB07E])) +#define MCF_USB_PPCNT (*(vuint16*)(&__MBAR[0xB080])) +#define MCF_USB_DPCNT (*(vuint16*)(&__MBAR[0xB082])) +#define MCF_USB_CRCECNT (*(vuint16*)(&__MBAR[0xB084])) +#define MCF_USB_BSECNT (*(vuint16*)(&__MBAR[0xB086])) +#define MCF_USB_PIDECNT (*(vuint16*)(&__MBAR[0xB088])) +#define MCF_USB_FRMECNT (*(vuint16*)(&__MBAR[0xB08A])) +#define MCF_USB_TXPCNT (*(vuint16*)(&__MBAR[0xB08C])) +#define MCF_USB_CNTOVR (*(vuint8 *)(&__MBAR[0xB08E])) +#define MCF_USB_EP0ACR (*(vuint8 *)(&__MBAR[0xB101])) +#define MCF_USB_EP0MPSR (*(vuint16*)(&__MBAR[0xB102])) +#define MCF_USB_EP0IFR (*(vuint8 *)(&__MBAR[0xB104])) +#define MCF_USB_EP0SR (*(vuint8 *)(&__MBAR[0xB105])) +#define MCF_USB_BMRTR (*(vuint8 *)(&__MBAR[0xB106])) +#define MCF_USB_BRTR (*(vuint8 *)(&__MBAR[0xB107])) +#define MCF_USB_WVALUER (*(vuint16*)(&__MBAR[0xB108])) +#define MCF_USB_WINDEXR (*(vuint16*)(&__MBAR[0xB10A])) +#define MCF_USB_WLENGTHR (*(vuint16*)(&__MBAR[0xB10C])) +#define MCF_USB_EP1OUTACR (*(vuint8 *)(&__MBAR[0xB131])) +#define MCF_USB_EP1OUTMPSR (*(vuint16*)(&__MBAR[0xB132])) +#define MCF_USB_EP1OUTIFR (*(vuint8 *)(&__MBAR[0xB134])) +#define MCF_USB_EP1OUTSR (*(vuint8 *)(&__MBAR[0xB135])) +#define MCF_USB_EP1OUTSFR (*(vuint16*)(&__MBAR[0xB13E])) +#define MCF_USB_EP1INACR (*(vuint8 *)(&__MBAR[0xB149])) +#define MCF_USB_EP1INMPSR (*(vuint16*)(&__MBAR[0xB14A])) +#define MCF_USB_EP1INIFR (*(vuint8 *)(&__MBAR[0xB14C])) +#define MCF_USB_EP1INSR (*(vuint8 *)(&__MBAR[0xB14D])) +#define MCF_USB_EP1INSFR (*(vuint16*)(&__MBAR[0xB156])) +#define MCF_USB_EP2OUTACR (*(vuint8 *)(&__MBAR[0xB161])) +#define MCF_USB_EP2OUTMPSR (*(vuint16*)(&__MBAR[0xB162])) +#define MCF_USB_EP2OUTIFR (*(vuint8 *)(&__MBAR[0xB164])) +#define MCF_USB_EP2OUTSR (*(vuint8 *)(&__MBAR[0xB165])) +#define MCF_USB_EP2OUTSFR (*(vuint16*)(&__MBAR[0xB16E])) +#define MCF_USB_EP2INACR (*(vuint8 *)(&__MBAR[0xB179])) +#define MCF_USB_EP2INMPSR (*(vuint16*)(&__MBAR[0xB17A])) +#define MCF_USB_EP2INIFR (*(vuint8 *)(&__MBAR[0xB17C])) +#define MCF_USB_EP2INSR (*(vuint8 *)(&__MBAR[0xB17D])) +#define MCF_USB_EP2INSFR (*(vuint16*)(&__MBAR[0xB186])) +#define MCF_USB_EP3OUTACR (*(vuint8 *)(&__MBAR[0xB191])) +#define MCF_USB_EP3OUTMPSR (*(vuint16*)(&__MBAR[0xB192])) +#define MCF_USB_EP3OUTIFR (*(vuint8 *)(&__MBAR[0xB194])) +#define MCF_USB_EP3OUTSR (*(vuint8 *)(&__MBAR[0xB195])) +#define MCF_USB_EP3OUTSFR (*(vuint16*)(&__MBAR[0xB19E])) +#define MCF_USB_EP3INACR (*(vuint8 *)(&__MBAR[0xB1A9])) +#define MCF_USB_EP3INMPSR (*(vuint16*)(&__MBAR[0xB1AA])) +#define MCF_USB_EP3INIFR (*(vuint8 *)(&__MBAR[0xB1AC])) +#define MCF_USB_EP3INSR (*(vuint8 *)(&__MBAR[0xB1AD])) +#define MCF_USB_EP3INSFR (*(vuint16*)(&__MBAR[0xB1B6])) +#define MCF_USB_EP4OUTACR (*(vuint8 *)(&__MBAR[0xB1C1])) +#define MCF_USB_EP4OUTMPSR (*(vuint16*)(&__MBAR[0xB1C2])) +#define MCF_USB_EP4OUTIFR (*(vuint8 *)(&__MBAR[0xB1C4])) +#define MCF_USB_EP4OUTSR (*(vuint8 *)(&__MBAR[0xB1C5])) +#define MCF_USB_EP4OUTSFR (*(vuint16*)(&__MBAR[0xB1CE])) +#define MCF_USB_EP4INACR (*(vuint8 *)(&__MBAR[0xB1D9])) +#define MCF_USB_EP4INMPSR (*(vuint16*)(&__MBAR[0xB1DA])) +#define MCF_USB_EP4INIFR (*(vuint8 *)(&__MBAR[0xB1DC])) +#define MCF_USB_EP4INSR (*(vuint8 *)(&__MBAR[0xB1DD])) +#define MCF_USB_EP4INSFR (*(vuint16*)(&__MBAR[0xB1E6])) +#define MCF_USB_EP5OUTACR (*(vuint8 *)(&__MBAR[0xB1F1])) +#define MCF_USB_EP5OUTMPSR (*(vuint16*)(&__MBAR[0xB1F2])) +#define MCF_USB_EP5OUTIFR (*(vuint8 *)(&__MBAR[0xB1F4])) +#define MCF_USB_EP5OUTSR (*(vuint8 *)(&__MBAR[0xB1F5])) +#define MCF_USB_EP5OUTSFR (*(vuint16*)(&__MBAR[0xB1FE])) +#define MCF_USB_EP5INACR (*(vuint8 *)(&__MBAR[0xB209])) +#define MCF_USB_EP5INMPSR (*(vuint16*)(&__MBAR[0xB20A])) +#define MCF_USB_EP5INIFR (*(vuint8 *)(&__MBAR[0xB20C])) +#define MCF_USB_EP5INSR (*(vuint8 *)(&__MBAR[0xB20D])) +#define MCF_USB_EP5INSFR (*(vuint16*)(&__MBAR[0xB216])) +#define MCF_USB_EP6OUTACR (*(vuint8 *)(&__MBAR[0xB221])) +#define MCF_USB_EP6OUTMPSR (*(vuint16*)(&__MBAR[0xB222])) +#define MCF_USB_EP6OUTIFR (*(vuint8 *)(&__MBAR[0xB224])) +#define MCF_USB_EP6OUTSR (*(vuint8 *)(&__MBAR[0xB225])) +#define MCF_USB_EP6OUTSFR (*(vuint16*)(&__MBAR[0xB22E])) +#define MCF_USB_EP6INACR (*(vuint8 *)(&__MBAR[0xB239])) +#define MCF_USB_EP6INMPSR (*(vuint16*)(&__MBAR[0xB23A])) +#define MCF_USB_EP6INIFR (*(vuint8 *)(&__MBAR[0xB23C])) +#define MCF_USB_EP6INSR (*(vuint8 *)(&__MBAR[0xB23D])) +#define MCF_USB_EP6INSFR (*(vuint16*)(&__MBAR[0xB246])) +#define MCF_USB_USBSR (*(vuint32*)(&__MBAR[0xB400])) +#define MCF_USB_USBCR (*(vuint32*)(&__MBAR[0xB404])) +#define MCF_USB_DRAMCR (*(vuint32*)(&__MBAR[0xB408])) +#define MCF_USB_DRAMDR (*(vuint32*)(&__MBAR[0xB40C])) +#define MCF_USB_USBISR (*(vuint32*)(&__MBAR[0xB410])) +#define MCF_USB_USBIMR (*(vuint32*)(&__MBAR[0xB414])) +#define MCF_USB_EP0STAT (*(vuint32*)(&__MBAR[0xB440])) +#define MCF_USB_EP0ISR (*(vuint32*)(&__MBAR[0xB444])) +#define MCF_USB_EP0IMR (*(vuint32*)(&__MBAR[0xB448])) +#define MCF_USB_EP0FRCFGR (*(vuint32*)(&__MBAR[0xB44C])) +#define MCF_USB_EP0FDR (*(vuint32*)(&__MBAR[0xB450])) +#define MCF_USB_EP0FSR (*(vuint32*)(&__MBAR[0xB454])) +#define MCF_USB_EP0FCR (*(vuint32*)(&__MBAR[0xB458])) +#define MCF_USB_EP0FAR (*(vuint32*)(&__MBAR[0xB45C])) +#define MCF_USB_EP0FRP (*(vuint32*)(&__MBAR[0xB460])) +#define MCF_USB_EP0FWP (*(vuint32*)(&__MBAR[0xB464])) +#define MCF_USB_EP0LRFP (*(vuint32*)(&__MBAR[0xB468])) +#define MCF_USB_EP0LWFP (*(vuint32*)(&__MBAR[0xB46C])) +#define MCF_USB_EP1STAT (*(vuint32*)(&__MBAR[0xB470])) +#define MCF_USB_EP1ISR (*(vuint32*)(&__MBAR[0xB474])) +#define MCF_USB_EP1IMR (*(vuint32*)(&__MBAR[0xB478])) +#define MCF_USB_EP1FRCFGR (*(vuint32*)(&__MBAR[0xB47C])) +#define MCF_USB_EP1FDR (*(vuint32*)(&__MBAR[0xB480])) +#define MCF_USB_EP1FSR (*(vuint32*)(&__MBAR[0xB484])) +#define MCF_USB_EP1FCR (*(vuint32*)(&__MBAR[0xB488])) +#define MCF_USB_EP1FAR (*(vuint32*)(&__MBAR[0xB48C])) +#define MCF_USB_EP1FRP (*(vuint32*)(&__MBAR[0xB490])) +#define MCF_USB_EP1FWP (*(vuint32*)(&__MBAR[0xB494])) +#define MCF_USB_EP1LRFP (*(vuint32*)(&__MBAR[0xB498])) +#define MCF_USB_EP1LWFP (*(vuint32*)(&__MBAR[0xB49C])) +#define MCF_USB_EP2STAT (*(vuint32*)(&__MBAR[0xB4A0])) +#define MCF_USB_EP2ISR (*(vuint32*)(&__MBAR[0xB4A4])) +#define MCF_USB_EP2IMR (*(vuint32*)(&__MBAR[0xB4A8])) +#define MCF_USB_EP2FRCFGR (*(vuint32*)(&__MBAR[0xB4AC])) +#define MCF_USB_EP2FDR (*(vuint32*)(&__MBAR[0xB4B0])) +#define MCF_USB_EP2FSR (*(vuint32*)(&__MBAR[0xB4B4])) +#define MCF_USB_EP2FCR (*(vuint32*)(&__MBAR[0xB4B8])) +#define MCF_USB_EP2FAR (*(vuint32*)(&__MBAR[0xB4BC])) +#define MCF_USB_EP2FRP (*(vuint32*)(&__MBAR[0xB4C0])) +#define MCF_USB_EP2FWP (*(vuint32*)(&__MBAR[0xB4C4])) +#define MCF_USB_EP2LRFP (*(vuint32*)(&__MBAR[0xB4C8])) +#define MCF_USB_EP2LWFP (*(vuint32*)(&__MBAR[0xB4CC])) +#define MCF_USB_EP3STAT (*(vuint32*)(&__MBAR[0xB4D0])) +#define MCF_USB_EP3ISR (*(vuint32*)(&__MBAR[0xB4D4])) +#define MCF_USB_EP3IMR (*(vuint32*)(&__MBAR[0xB4D8])) +#define MCF_USB_EP3FRCFGR (*(vuint32*)(&__MBAR[0xB4DC])) +#define MCF_USB_EP3FDR (*(vuint32*)(&__MBAR[0xB4E0])) +#define MCF_USB_EP3FSR (*(vuint32*)(&__MBAR[0xB4E4])) +#define MCF_USB_EP3FCR (*(vuint32*)(&__MBAR[0xB4E8])) +#define MCF_USB_EP3FAR (*(vuint32*)(&__MBAR[0xB4EC])) +#define MCF_USB_EP3FRP (*(vuint32*)(&__MBAR[0xB4F0])) +#define MCF_USB_EP3FWP (*(vuint32*)(&__MBAR[0xB4F4])) +#define MCF_USB_EP3LRFP (*(vuint32*)(&__MBAR[0xB4F8])) +#define MCF_USB_EP3LWFP (*(vuint32*)(&__MBAR[0xB4FC])) +#define MCF_USB_EP4STAT (*(vuint32*)(&__MBAR[0xB500])) +#define MCF_USB_EP4ISR (*(vuint32*)(&__MBAR[0xB504])) +#define MCF_USB_EP4IMR (*(vuint32*)(&__MBAR[0xB508])) +#define MCF_USB_EP4FRCFGR (*(vuint32*)(&__MBAR[0xB50C])) +#define MCF_USB_EP4FDR (*(vuint32*)(&__MBAR[0xB510])) +#define MCF_USB_EP4FSR (*(vuint32*)(&__MBAR[0xB514])) +#define MCF_USB_EP4FCR (*(vuint32*)(&__MBAR[0xB518])) +#define MCF_USB_EP4FAR (*(vuint32*)(&__MBAR[0xB51C])) +#define MCF_USB_EP4FRP (*(vuint32*)(&__MBAR[0xB520])) +#define MCF_USB_EP4FWP (*(vuint32*)(&__MBAR[0xB524])) +#define MCF_USB_EP4LRFP (*(vuint32*)(&__MBAR[0xB528])) +#define MCF_USB_EP4LWFP (*(vuint32*)(&__MBAR[0xB52C])) +#define MCF_USB_EP5STAT (*(vuint32*)(&__MBAR[0xB530])) +#define MCF_USB_EP5ISR (*(vuint32*)(&__MBAR[0xB534])) +#define MCF_USB_EP5IMR (*(vuint32*)(&__MBAR[0xB538])) +#define MCF_USB_EP5FRCFGR (*(vuint32*)(&__MBAR[0xB53C])) +#define MCF_USB_EP5FDR (*(vuint32*)(&__MBAR[0xB540])) +#define MCF_USB_EP5FSR (*(vuint32*)(&__MBAR[0xB544])) +#define MCF_USB_EP5FCR (*(vuint32*)(&__MBAR[0xB548])) +#define MCF_USB_EP5FAR (*(vuint32*)(&__MBAR[0xB54C])) +#define MCF_USB_EP5FRP (*(vuint32*)(&__MBAR[0xB550])) +#define MCF_USB_EP5FWP (*(vuint32*)(&__MBAR[0xB554])) +#define MCF_USB_EP5LRFP (*(vuint32*)(&__MBAR[0xB558])) +#define MCF_USB_EP5LWFP (*(vuint32*)(&__MBAR[0xB55C])) +#define MCF_USB_EP6STAT (*(vuint32*)(&__MBAR[0xB560])) +#define MCF_USB_EP6ISR (*(vuint32*)(&__MBAR[0xB564])) +#define MCF_USB_EP6IMR (*(vuint32*)(&__MBAR[0xB568])) +#define MCF_USB_EP6FRCFGR (*(vuint32*)(&__MBAR[0xB56C])) +#define MCF_USB_EP6FDR (*(vuint32*)(&__MBAR[0xB570])) +#define MCF_USB_EP6FSR (*(vuint32*)(&__MBAR[0xB574])) +#define MCF_USB_EP6FCR (*(vuint32*)(&__MBAR[0xB578])) +#define MCF_USB_EP6FAR (*(vuint32*)(&__MBAR[0xB57C])) +#define MCF_USB_EP6FRP (*(vuint32*)(&__MBAR[0xB580])) +#define MCF_USB_EP6FWP (*(vuint32*)(&__MBAR[0xB584])) +#define MCF_USB_EP6LRFP (*(vuint32*)(&__MBAR[0xB588])) +#define MCF_USB_EP6LWFP (*(vuint32*)(&__MBAR[0xB58C])) +#define MCF_USB_IFR(x) (*(vuint16*)(&__MBAR[0xB040 + ((x)*0x2)])) +#define MCF_USB_EPOUTACR(x) (*(vuint8 *)(&__MBAR[0xB131 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTMPSR(x) (*(vuint16*)(&__MBAR[0xB132 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTIFR(x) (*(vuint8 *)(&__MBAR[0xB134 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSR(x) (*(vuint8 *)(&__MBAR[0xB135 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSFR(x) (*(vuint16*)(&__MBAR[0xB13E + ((x-1)*0x30)])) +#define MCF_USB_EPINACR(x) (*(vuint8 *)(&__MBAR[0xB149 + ((x-1)*0x30)])) +#define MCF_USB_EPINMPSR(x) (*(vuint16*)(&__MBAR[0xB14A + ((x-1)*0x30)])) +#define MCF_USB_EPINIFR(x) (*(vuint8 *)(&__MBAR[0xB14C + ((x-1)*0x30)])) +#define MCF_USB_EPINSR(x) (*(vuint8 *)(&__MBAR[0xB14D + ((x-1)*0x30)])) +#define MCF_USB_EPINSFR(x) (*(vuint16*)(&__MBAR[0xB156 + ((x-1)*0x30)])) +#define MCF_USB_EPSTAT(x) (*(vuint32*)(&__MBAR[0xB440 + ((x)*0x30)])) +#define MCF_USB_EPISR(x) (*(vuint32*)(&__MBAR[0xB444 + ((x)*0x30)])) +#define MCF_USB_EPIMR(x) (*(vuint32*)(&__MBAR[0xB448 + ((x)*0x30)])) +#define MCF_USB_EPFRCFGR(x) (*(vuint32*)(&__MBAR[0xB44C + ((x)*0x30)])) +#define MCF_USB_EPFDR(x) (*(vuint32*)(&__MBAR[0xB450 + ((x)*0x30)])) +#define MCF_USB_EPFSR(x) (*(vuint32*)(&__MBAR[0xB454 + ((x)*0x30)])) +#define MCF_USB_EPFCR(x) (*(vuint32*)(&__MBAR[0xB458 + ((x)*0x30)])) +#define MCF_USB_EPFAR(x) (*(vuint32*)(&__MBAR[0xB45C + ((x)*0x30)])) +#define MCF_USB_EPFRP(x) (*(vuint32*)(&__MBAR[0xB460 + ((x)*0x30)])) +#define MCF_USB_EPFWP(x) (*(vuint32*)(&__MBAR[0xB464 + ((x)*0x30)])) +#define MCF_USB_EPLRFP(x) (*(vuint32*)(&__MBAR[0xB468 + ((x)*0x30)])) +#define MCF_USB_EPLWFP(x) (*(vuint32*)(&__MBAR[0xB46C + ((x)*0x30)])) + + +/* Bit definitions and macros for MCF_USB_USBAISR */ +#define MCF_USB_USBAISR_SETUP (0x1) +#define MCF_USB_USBAISR_IN (0x2) +#define MCF_USB_USBAISR_OUT (0x4) +#define MCF_USB_USBAISR_EPHALT (0x8) +#define MCF_USB_USBAISR_TRANSERR (0x10) +#define MCF_USB_USBAISR_ACK (0x20) +#define MCF_USB_USBAISR_CTROVFL (0x40) +#define MCF_USB_USBAISR_EPSTALL (0x80) + +/* Bit definitions and macros for MCF_USB_USBAIMR */ +#define MCF_USB_USBAIMR_SETUPEN (0x1) +#define MCF_USB_USBAIMR_INEN (0x2) +#define MCF_USB_USBAIMR_OUTEN (0x4) +#define MCF_USB_USBAIMR_EPHALTEN (0x8) +#define MCF_USB_USBAIMR_TRANSERREN (0x10) +#define MCF_USB_USBAIMR_ACKEN (0x20) +#define MCF_USB_USBAIMR_CTROVFLEN (0x40) +#define MCF_USB_USBAIMR_EPSTALLEN (0x80) + +/* Bit definitions and macros for MCF_USB_EPINFO */ +#define MCF_USB_EPINFO_EPDIR (0x1) +#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1) + +/* Bit definitions and macros for MCF_USB_CFGR */ +#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_CFGAR */ +#define MCF_USB_CFGAR_RESERVED (0xA0) +#define MCF_USB_CFGAR_RMTWKEUP (0xE0) + +/* Bit definitions and macros for MCF_USB_SPEEDR */ +#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0) + +/* Bit definitions and macros for MCF_USB_FRMNUMR */ +#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPTNR */ +#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0) +#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2) +#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4) +#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6) +#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8) +#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA) +#define MCF_USB_EPTNR_EPnT1 (0) +#define MCF_USB_EPTNR_EPnT2 (0x1) +#define MCF_USB_EPTNR_EPnT3 (0x2) + +/* Bit definitions and macros for MCF_USB_IFUR */ +#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_IFR */ +#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_PPCNT */ +#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_DPCNT */ +#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CRCECNT */ +#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_BSECNT */ +#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_PIDECNT */ +#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_FRMECNT */ +#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_TXPCNT */ +#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CNTOVR */ +#define MCF_USB_CNTOVR_PPCNT (0x1) +#define MCF_USB_CNTOVR_DPCNT (0x2) +#define MCF_USB_CNTOVR_CRCECNT (0x4) +#define MCF_USB_CNTOVR_BSECNT (0x8) +#define MCF_USB_CNTOVR_PIDECNT (0x10) +#define MCF_USB_CNTOVR_FRMECNT (0x20) +#define MCF_USB_CNTOVR_TXPCNT (0x40) + +/* Bit definitions and macros for MCF_USB_EP0ACR */ +#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EP0ACR_TTYPE_CTRL (0) +#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1) +#define MCF_USB_EP0ACR_TTYPE_BULK (0x2) +#define MCF_USB_EP0ACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EP0MPSR */ +#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EP0IFR */ +#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EP0SR */ +#define MCF_USB_EP0SR_HALT (0x1) +#define MCF_USB_EP0SR_ACTIVE (0x2) +#define MCF_USB_EP0SR_PSTALL (0x4) +#define MCF_USB_EP0SR_CCOMP (0x8) +#define MCF_USB_EP0SR_TXZERO (0x20) +#define MCF_USB_EP0SR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_BMRTR */ +#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0) +#define MCF_USB_BMRTR_REC_DEVICE (0) +#define MCF_USB_BMRTR_REC_INTERFACE (0x1) +#define MCF_USB_BMRTR_REC_ENDPOINT (0x2) +#define MCF_USB_BMRTR_REC_OTHER (0x3) +#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5) +#define MCF_USB_BMRTR_TYPE_STANDARD (0) +#define MCF_USB_BMRTR_TYPE_CLASS (0x20) +#define MCF_USB_BMRTR_TYPE_VENDOR (0x40) +#define MCF_USB_BMRTR_DIR (0x80) + +/* Bit definitions and macros for MCF_USB_BRTR */ +#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_WVALUER */ +#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WINDEXR */ +#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WLENGTHR */ +#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTACR */ +#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2) +#define MCF_USB_EPOUTACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPOUTMPSR */ +#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPOUTIFR */ +#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTSR */ +#define MCF_USB_EPOUTSR_HALT (0x1) +#define MCF_USB_EPOUTSR_ACTIVE (0x2) +#define MCF_USB_EPOUTSR_PSTALL (0x4) +#define MCF_USB_EPOUTSR_CCOMP (0x8) +#define MCF_USB_EPOUTSR_TXZERO (0x20) +#define MCF_USB_EPOUTSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPOUTSFR */ +#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINACR */ +#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPINACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPINACR_TTYPE_BULK (0x2) +#define MCF_USB_EPINACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPINMPSR */ +#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPINIFR */ +#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINSR */ +#define MCF_USB_EPINSR_HALT (0x1) +#define MCF_USB_EPINSR_ACTIVE (0x2) +#define MCF_USB_EPINSR_PSTALL (0x4) +#define MCF_USB_EPINSR_CCOMP (0x8) +#define MCF_USB_EPINSR_TXZERO (0x20) +#define MCF_USB_EPINSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPINSFR */ +#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_USBSR */ +#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0) +#define MCF_USB_USBSR_SUSP (0x80) + +/* Bit definitions and macros for MCF_USB_USBCR */ +#define MCF_USB_USBCR_RESUME (0x1) +#define MCF_USB_USBCR_APPLOCK (0x2) +#define MCF_USB_USBCR_RST (0x4) +#define MCF_USB_USBCR_RAMEN (0x8) +#define MCF_USB_USBCR_RAMSPLIT (0x20) + +/* Bit definitions and macros for MCF_USB_DRAMCR */ +#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0) +#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10) +#define MCF_USB_DRAMCR_BSY (0x40000000) +#define MCF_USB_DRAMCR_START (0x80000000) + +/* Bit definitions and macros for MCF_USB_DRAMDR */ +#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_USBISR */ +#define MCF_USB_USBISR_ISOERR (0x1) +#define MCF_USB_USBISR_FTUNLCK (0x2) +#define MCF_USB_USBISR_SUSP (0x4) +#define MCF_USB_USBISR_RES (0x8) +#define MCF_USB_USBISR_UPDSOF (0x10) +#define MCF_USB_USBISR_RSTSTOP (0x20) +#define MCF_USB_USBISR_SOF (0x40) +#define MCF_USB_USBISR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_USBIMR */ +#define MCF_USB_USBIMR_ISOERR (0x1) +#define MCF_USB_USBIMR_FTUNLCK (0x2) +#define MCF_USB_USBIMR_SUSP (0x4) +#define MCF_USB_USBIMR_RES (0x8) +#define MCF_USB_USBIMR_UPDSOF (0x10) +#define MCF_USB_USBIMR_RSTSTOP (0x20) +#define MCF_USB_USBIMR_SOF (0x40) +#define MCF_USB_USBIMR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_EPSTAT */ +#define MCF_USB_EPSTAT_RST (0x1) +#define MCF_USB_EPSTAT_FLUSH (0x2) +#define MCF_USB_EPSTAT_DIR (0x80) +#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPISR */ +#define MCF_USB_EPISR_EOF (0x1) +#define MCF_USB_EPISR_EOT (0x4) +#define MCF_USB_EPISR_FIFOLO (0x10) +#define MCF_USB_EPISR_FIFOHI (0x20) +#define MCF_USB_EPISR_ERR (0x40) +#define MCF_USB_EPISR_EMT (0x80) +#define MCF_USB_EPISR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPIMR */ +#define MCF_USB_EPIMR_EOF (0x1) +#define MCF_USB_EPIMR_EOT (0x4) +#define MCF_USB_EPIMR_FIFOLO (0x10) +#define MCF_USB_EPIMR_FIFOHI (0x20) +#define MCF_USB_EPIMR_ERR (0x40) +#define MCF_USB_EPIMR_EMT (0x80) +#define MCF_USB_EPIMR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPFRCFGR */ +#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0) +#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPFDR */ +#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFSR */ +#define MCF_USB_EPFSR_EMT (0x10000) +#define MCF_USB_EPFSR_ALRM (0x20000) +#define MCF_USB_EPFSR_FU (0x40000) +#define MCF_USB_EPFSR_FR (0x80000) +#define MCF_USB_EPFSR_OF (0x100000) +#define MCF_USB_EPFSR_UF (0x200000) +#define MCF_USB_EPFSR_RXW (0x400000) +#define MCF_USB_EPFSR_FAE (0x800000) +#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_USB_EPFSR_TXW (0x40000000) +#define MCF_USB_EPFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFCR */ +#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_USB_EPFCR_TXWMSK (0x40000) +#define MCF_USB_EPFCR_OFMSK (0x80000) +#define MCF_USB_EPFCR_UFMSK (0x100000) +#define MCF_USB_EPFCR_RXWMSK (0x200000) +#define MCF_USB_EPFCR_FAEMSK (0x400000) +#define MCF_USB_EPFCR_IPMSK (0x800000) +#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_USB_EPFCR_FRM (0x8000000) +#define MCF_USB_EPFCR_TMR (0x10000000) +#define MCF_USB_EPFCR_WFR (0x20000000) +#define MCF_USB_EPFCR_SHAD (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFAR */ +#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFRP */ +#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFWP */ +#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLRFP */ +#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLWFP */ +#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0) + + +#endif /* __MCF5475_USB_H__ */ diff --git a/BaS_GNU/include/MCF5475_XLB.h b/BaS_GNU/include/MCF5475_XLB.h new file mode 100644 index 0000000..f13a20c --- /dev/null +++ b/BaS_GNU/include/MCF5475_XLB.h @@ -0,0 +1,101 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_XLB_H__ +#define __MCF5475_XLB_H__ + + +/********************************************************************* +* +* XL Bus Arbiter (XLB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_XLB_XARB_CFG (*(vuint32*)(&__MBAR[0x240])) +#define MCF_XLB_XARB_VER (*(vuint32*)(&__MBAR[0x244])) +#define MCF_XLB_XARB_SR (*(vuint32*)(&__MBAR[0x248])) +#define MCF_XLB_XARB_IMR (*(vuint32*)(&__MBAR[0x24C])) +#define MCF_XLB_XARB_ADRCAP (*(vuint32*)(&__MBAR[0x250])) +#define MCF_XLB_XARB_SIGCAP (*(vuint32*)(&__MBAR[0x254])) +#define MCF_XLB_XARB_ADRTO (*(vuint32*)(&__MBAR[0x258])) +#define MCF_XLB_XARB_DATTO (*(vuint32*)(&__MBAR[0x25C])) +#define MCF_XLB_XARB_BUSTO (*(vuint32*)(&__MBAR[0x260])) +#define MCF_XLB_XARB_PRIEN (*(vuint32*)(&__MBAR[0x264])) +#define MCF_XLB_XARB_PRI (*(vuint32*)(&__MBAR[0x268])) + + +/* Bit definitions and macros for MCF_XLB_XARB_CFG */ +#define MCF_XLB_XARB_CFG_AT (0x2) +#define MCF_XLB_XARB_CFG_DT (0x4) +#define MCF_XLB_XARB_CFG_BA (0x8) +#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5) +#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_CFG_PLDIS (0x80000000) + +/* Bit definitions and macros for MCF_XLB_XARB_VER */ +#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SR */ +#define MCF_XLB_XARB_SR_AT (0x1) +#define MCF_XLB_XARB_SR_DT (0x2) +#define MCF_XLB_XARB_SR_BA (0x4) +#define MCF_XLB_XARB_SR_TTM (0x8) +#define MCF_XLB_XARB_SR_ECW (0x10) +#define MCF_XLB_XARB_SR_TTR (0x20) +#define MCF_XLB_XARB_SR_TTA (0x40) +#define MCF_XLB_XARB_SR_MM (0x80) +#define MCF_XLB_XARB_SR_SEA (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_IMR */ +#define MCF_XLB_XARB_IMR_ATE (0x1) +#define MCF_XLB_XARB_IMR_DTE (0x2) +#define MCF_XLB_XARB_IMR_BAE (0x4) +#define MCF_XLB_XARB_IMR_TTME (0x8) +#define MCF_XLB_XARB_IMR_ECWE (0x10) +#define MCF_XLB_XARB_IMR_TTRE (0x20) +#define MCF_XLB_XARB_IMR_TTAE (0x40) +#define MCF_XLB_XARB_IMR_MME (0x80) +#define MCF_XLB_XARB_IMR_SEAE (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */ +#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */ +#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0) +#define MCF_XLB_XARB_SIGCAP_TBST (0x20) +#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */ +#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_DATTO */ +#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */ +#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */ +#define MCF_XLB_XARB_PRIEN_M0 (0x1) +#define MCF_XLB_XARB_PRIEN_M2 (0x4) +#define MCF_XLB_XARB_PRIEN_M3 (0x8) + +/* Bit definitions and macros for MCF_XLB_XARB_PRI */ +#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0) +#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC) + + +#endif /* __MCF5475_XLB_H__ */ From 5cdf5743aa435121232fb8837995de7d466de55f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 14:57:56 +0000 Subject: [PATCH 010/276] unfinished --- BaS_GNU/sources/sd_card.c | 610 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 610 insertions(+) create mode 100644 BaS_GNU/sources/sd_card.c diff --git a/BaS_GNU/sources/sd_card.c b/BaS_GNU/sources/sd_card.c new file mode 100644 index 0000000..4673854 --- /dev/null +++ b/BaS_GNU/sources/sd_card.c @@ -0,0 +1,610 @@ +/********************************************************************/ +// sd card +/********************************************************************/ + +#define __MBAR 0xff000000 +#define MCF_SLT0_SCNT __MBAR + 0x908 +#define MCF_PSC0_PSCTB_8BIT __MBAR + 0x860C +#define MCF_PAD_PAR_DSPI __MBAR + 0xA50 +#define MCF_DSPI_DMCR __MBAR + 0x8A00 //dspi control + +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 +#define time1us 1320 + + +void wait_10ms(void) +{ + asm + { +warte_10ms: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #1320000,d0 + warte_d6: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d6 + move.l (sp)+,d0 + } +} + +void sd_com(void) // byt senden und holen --------------------- +{ + + asm + { + + move.l d4,dspi_dtfr(a0) +wait_auf_complett: + btst.b #7,dspi_dsr(a0) + beq wait_auf_complett + move.l dspi_drfr(a0),d5 + mov3q.l #-1,dspi_dsr(a0) // clr status register + } +} + +void sd_get_status(void) // status holen ------------------------------- +{ + asm + { +sd_get_status: + move.b #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_get_status + } +} + +void sd_rcv_info(void) // daten holen ---------------------------- +{ + asm + { + moveq #18,d3 // 16 byts + 2 byts crc + move.b #0xff,d4 +sd_rcv_rb_w: + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rcv_rb_w // nein-> +sd_rcv_rd_rb: + bsr sd_com + move.b d5,(a2)+ + subq.l #1,d3 + bne sd_rcv_rd_rb + } +} + +void sd_card_idle(void) +{ + + asm + { +// sd idle +// speed =400kHz + move.l #0x082000ff,d4 // tx vorbesetzen + lea MCF_DSPI_DMCR,a0 + move.l #0x38558897,d0 + move.l d0,dspi_dtar0(a0) // 400kHz + + move.b #0xff,d4 + bsr sd_com // clocks + move.b #0x40,d4 // cmd idle + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + } +} + +int sd_card_init(void) +{ + + long az_sectors; + + asm + { + lea MCF_PSC0_PSCTB_8BIT,a1 + move.l #'SD-C',(a1) + move.l #'ard ',(a1) + + move.l buffer,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) + move.l #0x1fffffff,d0 // normal dspi + move.l d0,MCF_PAD_PAR_DSPI + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) // 8 bit cs off clear fifo + move.l #0x38558897,d0 + move.l d0,dspi_dtar0(a0) // 400kHz + move.l #0x082000ff,d4 // tx vorbesetzen + move.l d4,dspi_dtfr // und setzen + mov3q.l #-1,dspi_dsr(a0) // status register l�schen + + move.l #0xc00d3c00,(a0) // clock on cs ist on + bsr wait_10ms + move.l #0x802d3c00,(a0) // clock off cs off + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + move.l #0x800d3c00,(a0) // cs on + bsr sd_com + bsr sd_com + move.l #0x802d3c00,(a0) // cs off + bsr sd_com + bsr sd_com + bsr wait_10ms + +// sd idle + move.l #100,d6 // 100 versuche + move.l #10,d3 // 10 versuche +sd_idle: + bsr sd_card_idle + + move.l #10,d7 + move.b #0xff,d4 +sd_idle_leeren: + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + subq.l #1,d7 + bne sd_idle_leeren + subq.l #1,d6 + beq sd_not + bra sd_idle +idle_end: + +// cdm 8 +read_ic: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x48,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + move.b #0xaa,d4 + bsr sd_com + move.b #0x87,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #5,d5 + beq sd_v1 + cmp.b #1,d5 + bne read_ic + + bsr sd_com // 4byts zum wegwerfen + bsr sd_com + bsr sd_com + bsr sd_com + cmp.b #0xaa,d5 // pattern zur�ckgekommen? + bne sd_testd3 // nein -> + + move.l #'SDHC',(a1) + move.b #' ',(a1) +sd_v1: + +// cdm 58 +read_ocr: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x7a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + move.l #'Ver1',d6 + cmp.b #5,d5 + beq read_ocr + cmp.b #1,d5 + bne read_ocr + + bsr sd_com // 4 byts zum wegwerfen + bsr sd_com + bsr sd_com + bsr sd_com + +// acdm 41 + move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen +wait_of_aktiv: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x77,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x05,d5 + beq wait_of_aktiv + +wait_of_aktiv2: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x69,d4 + bsr sd_com + move.b #0x40,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq wait_of_aktiv2 + subq.l #1,d6 + bne wait_of_aktiv +sd_testd3: + subq.l #1,d3 + bne sd_idle + bra sd_error + +sd_init_ok: +// fullspeed + move.l #0x38551120,d0 // 22Mbit/sec + move.l d0,dspi_dtar0(a0) // setzen + +// cdm 10 +read_cid: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x4a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + move.l a5,a2 // adresse setzen + bsr sd_rcv_info + +// name ausgeben + lea 1(a5),a2 + moveq #7,d7 +sd_nam_loop: + move.b (a2)+,(a1) + subq.l #1,d7 + bne sd_nam_loop + move.b #' ',(a1) + +// cdm 9 +read_csd: + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x49,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + move.l a5,a2 // adresse setzen + bsr sd_rcv_info + + mvz.b (a5),d0 + lsr.l #6,d0 + + bne sd_csd2 // format v2 + move.l 6(a5),d1 + moveq #14,d0 // bit 73..62 c_size + lsr.l d0,d1 // bits extrahieren + and.l #0xfff,d1 // 12 bits + addq.l #1,d1 + mvz.w 9(a5),d0 + lsr.l #7,d0 // bits 49..47 + and.l #0x7,d0 // 3 bits + moveq.l #8,d2 // x256 (dif v1 v2) + sub.l d0,d2 + lsr.l d2,d1 + bra sd_print_size +sd_csd2: + mvz.w 8(a5),d1 + addq.l #1,d1 +sd_print_size: + swap d1 + move.l d1,d3 + lsr.l #6,d3 //x65636 /64 -> anzahl sectors + move.l d3,az_sectors + lsl.l #1,d1 + bcc sd_16G + move.l #'32GB',(a1) + bra sd_ok +sd_16G: + lsl.l #1,d1 + bcc sd_8G + move.l #'16GB',(a1) + bra sd_ok +sd_8G: + lsl.l #1,d1 + bcc sd_4G + move.l #' 8GB',(a1) + bra sd_ok +sd_4G: + lsl.l #1,d1 + bcc sd_2G + move.l #' 4GB',(a1) + bra sd_ok +sd_2G: + lsl.l #1,d1 + bcc sd_1G + move.l #' 2GB',(a1) + bra sd_ok +sd_1G: + lsl.l #1,d1 + bcc sd_512M + move.l #' 1GB',(a1) + bra sd_ok +sd_512M: + lsl.l #1,d1 + bcc sd_256M + move.b #'5',(a1) + move.l #'12MB',(a1) + bra sd_ok +sd_256M: + lsl.l #1,d1 + bcc sd_128M + move.b #'2',(a1) + move.l #'56MB',(a1) + bra sd_ok +sd_128M: + lsl.l #1,d1 + bcc sd_64M + move.b #'1',(a1) + move.l #'28MB',(a1) + bra sd_ok +sd_64M: + lsl.l #1,d1 + bcc sd_32M + move.l #'64MB',(a1) + bra sd_ok +sd_32M: + lsl.l #1,d1 + bcc sd_16M + move.l #'32MB',(a1) + bra sd_ok +sd_16M: + lsl.l #1,d1 + bcc sd_8M + move.l #'16MB',(a1) + bra sd_ok +sd_8M: + move.l #'<9MB',(a1) +sd_ok: + move.l #' OK!',(a1) + move.l #0x0a0d,(a1) + bra sd_c_ok +// subs ende ------------------------------- +sd_error: + move.l #'Erro',(a1) + move.l #'r!',(a1) + move.l #0x0a0d,(a1) + bra sd_c_error +sd_not: + move.l #'non!',(a1) + move.l #0x0a0d,(a1) + bra sd_c_not +buffer: dc.l 0,0,0,0,0,0,0,0 + } +sd_c_ok: + return az_sectors; +sd_c_not: + return -2; +sd_c_error: + return -1; +} + +void sd_rcv_sector(void) // 1 sector daten holen ---------------------------- +{ + if (sd_get_status() == 0xfe) + { + for (i = 0; i < 512; i++) + } + } + asm + { + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rs_end // nein-> error + move.l #512,d3 // sonst 512 byts abholen +sd_rs_loop: + bsr sd_com + move.b d5,(a2)+ + subq.l #1,d3 + bne sd_rs_loop +// crc holen + bsr sd_com + bsr sd_com + clr.l d5 // alles ok +sd_rs_end: + } +} + +int sd_card_sector_read(long sec_nr,long buf_adr) +{ + int status ; + asm + { + lea MCF_DSPI_DMCR,a0 + move.l #0x082000ff,d4 // tx vorbesetzen + + move.l sec_nr,d0 + move.l buf_adr,a2 + + lsl.l #8,d0 + add.l d0,d0 // x 512 ! + move.l d0,d1 // byts kehren + swap d1 + move.l d1,d2 + lsr.l #8,d1 + + move.b #0xff,d4 // clocks + bsr sd_com + + move.b #0x51,d4 + bsr sd_com + move.b d1,d4 + bsr sd_com + move.b d2,d4 + bsr sd_com + move.l d0,d2 + lsr.l #8,d2 + move.b d2,d4 + bsr sd_com + move.b d0,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + clr.l d5 // alles auf no error + clr.l status + + bsr sd_get_status // status holen + tst.b d5 + bne sd_csr_end // wenn nicht ok -> weg +// sector holen + bsr sd_rcv_sector +sd_csr_end: + tst.b d5 + beq sd_csr_ok + neg.l d5 // wenn nicht ok status auf negativ + move.l d5,status +sd_csr_ok: + } + return status; +} + +void sd_send_sector(void) // 1 sector daten senden ---------------------------- +{ + asm + { + move.l #512,d3 + move.b #0xfe,d4 // start token + bsr sd_com // senden +sd_send_wr_wb: + move.b (a2)+,d4 // data + bsr sd_com // senden + subq.l #1,d3 + bne sd_send_wr_wb +// send crc + move.b #1,d4 + bsr sd_com // crc 1.byt + move.b #1,d4 + bsr sd_com // crc 2.byt +sd_send_wr_ww: + bsr sd_get_status + and.l #0x1f,d5 + clr.l d6 //status auf OK + cmp.b #5,d5 //data accepted? + beq sd_send_end //ja -> + move.l d5,d6 //sonst status sichern +sd_send_end: + bsr sd_com + tst.b d5 // warte auf geschrieben + beq sd_send_end + move.l d6,d5 // status zur�ck + } +} + +int sd_card_sector_write(long sec_nr,long buf_adr) +{ + int status; + asm + { + lea MCF_DSPI_DMCR,a0 + move.l #0x082000ff,d4 // tx vorbesetzen + + move.l sec_nr,d0 + move.l buf_adr,a2 + + lsl.l #8,d0 + add.l d0,d0 // x 512 ! + move.l d0,d1 // byts kehren + swap d1 + move.l d1,d2 + lsr.l #8,d1 + + move.b #0xff,d4 // clocks + bsr sd_com + move.b #0x58,d4 + bsr sd_com + move.b d1,d4 + bsr sd_com + move.b d2,d4 + bsr sd_com + move.l d0,d2 + lsr.l #8,d2 + move.b d2,d4 + bsr sd_com + move.b d0,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + clr.l d5 // alles auf no error + clr.l status + bsr sd_get_status // status holen + tst.b d5 + bne sd_csw_end // wenn nicht ok -> weg +// sector schreiben + bsr sd_send_sector +sd_csw_end: + tst.b d5 + beq sd_csw_ok + neg.l d5 // wenn nicht ok status auf negativ + move.l d5,status +sd_csw_ok: + } + return status; +} From c979d82fbaddece273d26e63ee1b25cbddc8548e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 18:39:35 +0000 Subject: [PATCH 011/276] removed C++ #ifdefs --- BaS_GNU/sources/sysinit.h | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/BaS_GNU/sources/sysinit.h b/BaS_GNU/sources/sysinit.h index 70bc6da..b7a6c50 100644 --- a/BaS_GNU/sources/sysinit.h +++ b/BaS_GNU/sources/sysinit.h @@ -1,6 +1,6 @@ /* * File: sysinit.h - * Purpose: COLDARI Power-on Reset configuration + * Purpose: Firebee Power-on Reset configuration * * Notes: * @@ -9,11 +9,6 @@ #ifndef __SYSINIT_H__ #define __SYSINIT_H__ -#ifdef __cplusplus -extern "C" { -#endif - - #if ENABLE_UART_SUPPORT==1 /* @@ -76,12 +71,6 @@ void __initialize_hardware(void); */ void __initialize_system(void); - - -#ifdef __cplusplus -} -#endif - #endif /* __SYSINIT_H__ */ From df6b80e67ea4da697cb22cbe5d5f905926f26f0d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 19:55:28 +0000 Subject: [PATCH 012/276] conversion finished -> compiles --- BaS_GNU/sources/BaS.c | 235 ++++++++++++++++++------------------------ 1 file changed, 98 insertions(+), 137 deletions(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index fe925a6..0475d7b 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -8,15 +8,12 @@ #include "MCF5475_SLT.h" #include "startcf.h" -extern unsigned long far __SP_AFTER_RESET[]; -extern unsigned long far __Bas_base[]; +extern unsigned long __Bas_base[]; /* imported routines */ extern int mmu_init(); -extern int mmutr_miss(); extern int vec_init(); extern int illegal_table_make(); -extern int cf68k_initialize(); /* * warte_routinen @@ -70,6 +67,8 @@ void BaS(void) int sd_status,i; uint8_t *src; uint8_t *dst; + uint32_t *adr; + az_sectors = sd_card_init(); if(az_sectors>0) @@ -98,7 +97,7 @@ void BaS(void) { /* copy EMUTOS */ src = (uint8_t *) 0xe0600000L; - while (src < 0xe0700000L) + while (src < (uint8_t *) 0xe0700000L) { *dst++ = *src++; } @@ -106,159 +105,121 @@ void BaS(void) else { /* copy FireTOS */ - src = 0xe0400000L; - while (src < 0xe0500000L) + src = (uint8_t *) 0xe0400000L; + while (src < (uint8_t *) 0xe0500000L) { *dst++ = *src++; } } - if (!DIP_SWITCH & (1 << 6)) + if (!DIP_SWITCH & (1 << 6)) /* switch #6 on ? */ { - + if (MCF_PSC3_PSCRB_8BIT == 0x81) + { + for (i = 0; i < 64; i++) + { + * (uint8_t *) 0xffff8963 = MCF_PSC3_PSCRB_8BIT; /* TODO: what are we doing here ? */ + } + } } -/***************************************************************/ -/* div inits -/***************************************************************/ -div_inits: - move.b DIP_SWITCH,d0 // dip schalter adresse - btst.b #6,d0 - beq video_setup -// rtc daten, mmu set, etc nur wenn switch 6 = off - lea 0xffff8961,a0 - clr.l d1 - moveq #64,d2 - move.b (a4),d0 - cmp.b #0x81,d0 - bne not_rtc -loop_sr: - move.b (a4),d0 - move.b d1,(a0) - move.b d0,2(a0) - addq.l #1,d1 - cmp.b d1,d2 - bne loop_sr -/* +#ifdef _NOT_USED_ + /* + * set the NVRAM checksum as invalid + */ // Set the NVRAM checksum as invalid move.b #63,(a0) move.b 2(a0),d0 add #1,d0 move.b d0,2(a0) -*/ -not_rtc: - bsr mmu_init - bsr vec_init - bsr illegal_table_make +#endif /* NOT_USED */ + + mmu_init(); + vec_init(); + illegal_table_make(); -// interrupts - clr.l 0xf0010004 // disable all interrupts - lea MCF_EPORT_EPPAR,a0 - move.w #0xaaa8,(a0) // falling edge all, + /* interrupts */ -// timer 0 on mit int -> video change ------------------------------------------- - move.l #MCF_GPT_GMS_ICT(1)|MCF_GPT_GMS_IEN|MCF_GPT_GMS_TMS(1),d0 //caputre mit int on rising edge - move.l d0,MCF_GPT0_GMS - moveq.l #0x3f,d0 // max prority interrutp - move.b d0,MCF_INTC_ICR62 // setzen -// ------------------------------------------------- - move.b #0xfe,d0 - move.b d0,0xf0010004 // enable int 1-7 - nop - lea MCF_EPORT_EPIER,a0 - move.b #0xfe,(a0) // int 1-7 on - nop - lea MCF_EPORT_EPFR,a0 - move.b #0xff,(a0) // alle pending interrupts l�schen - nop - lea MCF_INTC_IMRL,a0 - move.l #0xFFFFFF00,(a0) // int 1-7 on - lea MCF_INTC_IMRH,a0 - move.l #0xBFFFFFFE,(a0) // psc3 and timer 0 int on + * (uint32_t *) 0xf0010004 = 0L; /* disable all interrupts */ + MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */ - move.l #MCF_MMU_MMUCR_EN,d0 - move.l d0,MCF_MMU_MMUCR // mmu on - nop - nop -/********************************************************************/ -/* IDE reset -/********************************************************************/ - lea 0xffff8802,a0 - move.b #14,-2(a0) - move.b #0x80,(a0) - bsr warte_1ms - clr.b (a0) -/********************************************************************/ -/* video setup -/********************************************************************/ -video_setup: - lea 0xf0000410,a0 -// 25MHz - move.l #0x032002ba,(a0)+ // horizontal 640x480 - move.l #0x020c020a,(a0)+ // vertikal 640x480 - move.l #0x0190015d,(a0)+ // horizontal 320x240 - move.l #0x020C020A,(a0)+ // vertikal 320x240 */ -/* + MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */ + MCF_GPT_GMS_IEN | + MCF_GPT_GMS(1); + MCF_INTC_ICR62 = 0x3f; + + * (uint8_t *) 0xf0010004 = 0xfe; /* enable int 1-7 */ + MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */ + MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */ + MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */ + MCF_INTC_IMRH = 0x9ffffffe; /* psc3 and timer 0 int on */ + + MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */ + + /* IDE reset */ + * (uint8_t *) (0xffff8802 - 2) = 14; + * (uint8_t *) (0xffff8802 - 0) = 0x80; + warte_1ms(); + + * (uint8_t *) (0xffff8802 - 0) = 0; + + /* + * video setup (25MHz) + */ + * (uint32_t *) (0xf0000410 + 0) = 0x032002ba; /* horizontal 640x480 */ + * (uint32_t *) (0xf0000410 + 4) = 0x020c020a; /* vertical 640x480 */ + * (uint32_t *) (0xf0000410 + 8) = 0x0190015d; /* horizontal 320x240 */ + * (uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */ + +#ifdef _NOT_USED_ // 32MHz move.l #0x037002ba,(a0)+ // horizontal 640x480 move.l #0x020d020a,(a0)+ // vertikal 640x480 move.l #0x02A001e0,(a0)+ // horizontal 320x240 move.l #0x05a00160,(a0)+ // vertikal 320x240 -*/ - lea -0x20(a0),a0 - move.l #0x01070002,(a0) // fifo on, refresh on, ddrcs und cke on, video dac on, -/********************************************************************/ -/* memory setup -/********************************************************************/ - lea 0x400,a0 - lea 0x800,a1 -mem_clr_loop: - clr.l (a0)+ - clr.l (a0)+ - clr.l (a0)+ - clr.l (a0)+ - cmp.l a0,a1 - bgt mem_clr_loop +#endif /* _NOT_USED_ */ - moveq #0x48,d0 - move.b d0,0xffff8007 -// stram - move.l #0xe00000,d0 // ende stram - move.l d0,0x42e - move.l #0x752019f3,d0 // memvalid - move.l d0,0x420 - move.l #0x237698aa,d0 // memval2 - move.l d0,0x43a - move.l #0x5555aaaa,d0 // memval3 - move.l d0,0x51a -// ttram - move.l #__Bas_base,d0 // ende ttram - move.l d0,0x5a4 - move.l #0x1357bd13,d0 // ramvalid - move.l d0,0x5a8 - -// init acia - moveq #3,d0 - move.b d0,0xfffffc00 - nop - move.b d0,0xfffffc04 - nop - moveq #0x96,d0 - move.b d0,0xfffffc00 - moveq #-1,d0 - nop - move.b d0,0xfffffa0f - nop - move.b d0,0xfffffa11 - nop - -// test auf protect mode --------------------- - move.b DIP_SWITCH,d0 - btst #7,d0 - beq no_protect // nein-> - move.w #0x0700,sr -no_protect: - jmp 0xe00030 + /* fifo on, refresh on, ddrcs and cke on, video dac on */ + * (uint32_t *) (0xf0000410 - 0x20) = 0x01070002; -} + /* + * memory setup + */ + for (adr = 0x400; adr < 0x800; adr += 32) { + *adr = 0x0L; + *adr = 0x0L; + *adr = 0x0L; + *adr = 0x0L; + } + + * (uint8_t *) 0xffff8007 = 0x48; /* FIXME: what's that ? */ + + /* ST RAM */ + + * (uint32_t *) 0x42e = 0xe00000; /* phystop TOS system variable */ + * (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */ + * (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */ + * (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */ + + /* TT-RAM */ + + * (uint32_t *) 0x5a4 = __Bas_base; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ + + /* init ACIA */ + * (uint8_t *) 0xfffffc00 = 3; + asm("nop"); + * (uint8_t *) 0xfffffc04 = 3; + asm("nop"); + * (uint8_t *) 0xfffffc00 = 0x96; + asm("nop"); + * (uint8_t *) 0xfffffa0f = 0; + asm("nop"); + * (uint8_t *) 0xfffffa11 = 0; + asm("nop"); + + if (DIP_SWITCH & (1 << 7)) { + asm("move.w #0x0700,sr"); + } + asm("jmp 0xe00030"); } From 9f1d7bdc21331fbcb681c2685888042694837056 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 19:58:39 +0000 Subject: [PATCH 013/276] get rid (#undef) far and __declspec --- BaS_GNU/include/MCF5475.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/BaS_GNU/include/MCF5475.h b/BaS_GNU/include/MCF5475.h index 8feab2d..ed275cb 100644 --- a/BaS_GNU/include/MCF5475.h +++ b/BaS_GNU/include/MCF5475.h @@ -46,6 +46,16 @@ extern "C" { * linker symbols must be defined in the linker command file. */ +#ifdef __GNUC__ +/* get rid of the __declspec() keyword */ +#undef __declspec +#define __declspec(a) /* */ + +/* the same for "far" */ +#undef far +#define far /* */ +#endif + extern __declspec(system) uint8 __MBAR[]; extern __declspec(system) uint8 __MMUBAR[]; extern __declspec(system) uint8 __RAMBAR0[]; From d86b666577bbf5a8a682c42607bd58d97b80c6b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 21:10:42 +0000 Subject: [PATCH 014/276] further translated ASM to C --- BaS_GNU/sources/sysinit.c | 136 ++++++++++++++++++++------------------ 1 file changed, 73 insertions(+), 63 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index da17073..e7e5092 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -206,91 +206,99 @@ void init_fbcs() MCF_PSC0_PSCTB_8BIT = 0x0a0d; } -#ifdef _NOT_USED_ /* - * FPGA LADEN + * load FPGA */ void init_fpga(void) { + register uint8_t *fpga_data; + register int i; + uart_out_word('FPGA'); MCF_GPIO_PODR_FEC1L |= (1 << 1); MCF_GPIO_PODR_FEC1L |= (1 << 2); - while ((!MCF_GPIO_PPDSDR_FEC1L & (1 << 0)) && (!MCF_GPIO_PDDSDR_FEC1L & (1 << 5))); + while ((!MCF_GPIO_PPDSDR_FEC1L & (1 << 0)) && (!MCF_GPIO_PPDSDR_FEC1L & (1 << 5))); warte_10us(); MCF_GPIO_PODR_FEC1L |= (1 << 2); warte_10us(); - start = 0xe0700000; + while (!MCF_GPIO_PPDSDR_FEC1L & (1 << 0)) + { + warte10us(); + } + /* + * excerpt from the Altera configuration manual: + * The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The + * configuration cycle consists of 3 stagesÑreset, configuration, and initialization. + * While nCONFIG is low, the device is in reset. When the device comes out of reset, + * nCONFIG must be at a logic high level in order for the device to release the open-drain + * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA + * is ready to receive configuration data. Before and during configuration, all user I/O pins + * are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors + * on the I/O pins which are on, before and during configuration. + * + * To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay + * configuration by holding the nCONFIG low. The device receives configuration data on its + * DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After + * the FPGA has received all configuration data successfully, it releases the CONF_DONE pin, + * which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates + * configuration is complete and initialization of the device can begin. + */ + fpga_data = (uint8_t *) 0xe0700000L; + do + { + uint8_t value = *fpga_data++; + for (i = 0; i < 8; i++) + { - asm { - lea MCF_GPIO_PODR_FEC1L, a1 // register adresse:write - lea MCF_GPIO_PPDSDR_FEC1L, a2 // reads - bclr #1,(a1) // clk auf low - bclr #2,(a1) // #config=low - test_nSTATUS: - btst #0,(a2) // nSTATUS==0 - bne test_nSTATUS // nein-> - btst #5,(a2) // conf done==0 - bne test_nSTATUS // nein-> - jsr warte_10us // warten - bset #2,(a1) // #config=high - jsr warte_10us // warten - test_STATUS: - btst #0,(a2) // status high? - beq test_STATUS // nein-> - jsr warte_10us // warten - lea 0xE0700000, a0 // startadresse fpga daten - word_send_loop: - cmp.l #0xE0800000,a0 - bgt fpga_error - move.b (a0)+, d0 // 32 bit holen - moveq #8,d1 // 32 bit ausgeben - bit_send_loop: - lsr.l -#1,d0 // bit rausschieben - bcs bit_is_1 bclr -#3,(a1) - bra bit_send bit_is_1: - bset -#3,(a1) - bit_send: - bset -#1,(a1) // clock=high - bclr -#1,(a1) // clock=low - subq.l -#1,d1 - bne bit_send_loop // wiederholen bis fertig - btst -#5,(a2) // fpga fertig, conf_done=high? - beq word_send_loop // nein, next word-> - move.l -#4000,d1 - overclk: - bset -#1,(a1) // clock=high - nop bclr -#1,(a1) // clock=low - subq.l -#1,d1 - bne overclk // weiter bis fertig - bra init_fpga_end + if ((value << i) & 0b10000000) + { + /* bit set -> toggle DATA0 to high */ + MCF_GPIO_PODR_FEC1L |= (1 << 3); + } + else + { + /* bit is cleared -> toggle DATA0 to low */ + MCF_GPIO_PODR_FEC1L &= ~(1 << 3); + } + /* toggle DCLK -> FPGA reads the bit */ + MCF_GPIO_PODR_FEC1L |= 1; + MCF_GPIO_PODR_FEC1L &= ~1; + } + } while ((!MCF_GPIO_PPDSDR_FEC1L & (1 << 5)) && (fpga_data < (uint8_t *) 0xE0800000)); + + for (fpga_data = 0; fpga_data < 4000; fpga_data++) + { + /* toggle a little more since it's fun ;) */ + MCF_GPIO_PODR_FEC1L |= 1; + MCF_GPIO_PODR_FEC1L &= ~1; + } + + bra init_fpga_end //--------------------------------------------------------- wait_pll: - lea MCF_SLT0_SCNT, a3 move.l(a3), d0 move.l -#100000,d6 // ca 1ms + lea MCF_SLT0_SCNT, a3 + move.l (a3),d0 + move.l #100000,d6 // ca 1ms wait_pll_loop: - tst.w(a1) - bpl wait_pll_ok move.l(a3), d1 sub.l d0, d1 add.l d6, d1 bpl wait_pll_loop wait_pll_ok: + tst.w (a1) + bpl wait_pll_ok + move.l (a3), d1 + sub.l d0, d1 + add.l d6, d1 + bpl wait_pll_loop +wait_pll_ok: rts // fertig fpga_error: - } - MCF_PSC0_PSCTB_8BIT = ' NOT'; init_fpga_end: + } + + MCF_PSC0_PSCTB_8BIT = ' NOT'; +init_fpga_end: MCF_PSC0_PSCTB_8BIT = ' OK!'; MCF_PSC0_PSCTB_8BIT = 0x0a0d; // init pll MCF_PSC0_PSCTB_8BIT = 'PLL '; asm { @@ -322,6 +330,8 @@ void init_fpga(void) } MCF_PSC0_PSCTB_8BIT = 'SET!'; MCF_PSC0_PSCTB_8BIT = 0x0a0d;} +#ifdef _NOT_USED_ + /* * INIT VIDEO DDR RAM */ From afd183a866f5816c9c1178412ef95ecb0d12ddfd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 21:15:58 +0000 Subject: [PATCH 015/276] not finished yet --- BaS_GNU/sources/sd_card.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/BaS_GNU/sources/sd_card.c b/BaS_GNU/sources/sd_card.c index 4673854..d8e206d 100644 --- a/BaS_GNU/sources/sd_card.c +++ b/BaS_GNU/sources/sd_card.c @@ -1,12 +1,8 @@ -/********************************************************************/ -// sd card -/********************************************************************/ +/* + * sd card + */ -#define __MBAR 0xff000000 -#define MCF_SLT0_SCNT __MBAR + 0x908 -#define MCF_PSC0_PSCTB_8BIT __MBAR + 0x860C -#define MCF_PAD_PAR_DSPI __MBAR + 0xA50 -#define MCF_DSPI_DMCR __MBAR + 0x8A00 //dspi control +#include #define dspi_dtar0 0x0c #define dspi_dsr 0x2c @@ -14,21 +10,8 @@ #define dspi_drfr 0x38 #define time1us 1320 +extern void wait_10ms(void); -void wait_10ms(void) -{ - asm - { -warte_10ms: - move.l d0,-(sp) - move.l MCF_SLT0_SCNT,d0 - sub.l #1320000,d0 - warte_d6: - cmp.l MCF_SLT0_SCNT,d0 - bcs warte_d6 - move.l (sp)+,d0 - } -} void sd_com(void) // byt senden und holen --------------------- { From eff76690e89f5d521c25224d1a22d9b87fddb97b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 22:03:47 +0000 Subject: [PATCH 016/276] --- BaS_GNU/sources/sysinit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index e7e5092..aa7c0f4 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -271,7 +271,7 @@ void init_fpga(void) } } while ((!MCF_GPIO_PPDSDR_FEC1L & (1 << 5)) && (fpga_data < (uint8_t *) 0xE0800000)); - for (fpga_data = 0; fpga_data < 4000; fpga_data++) + for (i = 0; i < 4000; i++) { /* toggle a little more since it's fun ;) */ MCF_GPIO_PODR_FEC1L |= 1; From 29293ec3f0f2b7eaba1274a84f6410eb17dafcce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 22:12:09 +0000 Subject: [PATCH 017/276] function rename German -> English --- BaS_GNU/sources/BaS.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 0475d7b..7e9a2cf 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -10,7 +10,7 @@ extern unsigned long __Bas_base[]; - /* imported routines */ +/* imported routines */ extern int mmu_init(); extern int vec_init(); extern int illegal_table_make(); @@ -18,42 +18,42 @@ extern int illegal_table_make(); /* * warte_routinen */ -void warte_10ms(void) +void wait_10ms(void) { register uint32_t target = MCF_SLT_SCNT(0) - 1320000; while (MCF_SLT_SCNT(0) > target); } -void warte_1ms(void) +void wait_1ms(void) { register uint32_t target = MCF_SLT_SCNT(0) - 132000; while (MCF_SLT_SCNT(0) > target); } -void warte_100us(void) +void wait_100us(void) { register uint32_t target = MCF_SLT_SCNT(0) - 13200; while (MCF_SLT_SCNT(0) > target); } -void warte_50us(void) +void wait_50us(void) { register uint32_t target = MCF_SLT_SCNT(0) - 6600; while (MCF_SLT_SCNT(0) > target); } -void warte_10us(void) +void wait_10us(void) { register uint32_t target = MCF_SLT_SCNT(0) - 1320; while (MCF_SLT_SCNT(0) > target); } -void warte_1us(void) +void wait_1us(void) { register uint32_t target = MCF_SLT_SCNT(0) - 132; @@ -82,7 +82,7 @@ void BaS(void) } MCF_PSC3_PSCTB_8BIT = 'ACPF'; - warte_10ms(); + wait_10ms(); MCF_PSC0_PSCTB_8BIT = 'PIC '; @@ -159,7 +159,7 @@ void BaS(void) /* IDE reset */ * (uint8_t *) (0xffff8802 - 2) = 14; * (uint8_t *) (0xffff8802 - 0) = 0x80; - warte_1ms(); + wait_1ms(); * (uint8_t *) (0xffff8802 - 0) = 0; @@ -185,7 +185,7 @@ void BaS(void) /* * memory setup */ - for (adr = 0x400; adr < 0x800; adr += 32) { + for (adr = 0x400L; adr < 0x800L; adr += 32) { *adr = 0x0L; *adr = 0x0L; *adr = 0x0L; From 160eba2134e413f1f79b0d8146426346bab199d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 11 Oct 2012 22:13:28 +0000 Subject: [PATCH 018/276] formatted --- BaS_GNU/sources/sysinit.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index aa7c0f4..8259609 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -15,10 +15,10 @@ extern unsigned long _Bas_base; extern unsigned long BaS; extern unsigned long _BOOT_FLASH[]; extern int copy_end(); -extern int warte_10us(); -extern int warte_1ms(); -extern int warte_10ms(); -extern int warte_50us(); +extern int wait_10us(); +extern int wait_1ms(); +extern int wait_10ms(); +extern int wait_50us(); extern unsigned long rt_cacr; @@ -221,9 +221,9 @@ void init_fpga(void) while ((!MCF_GPIO_PPDSDR_FEC1L & (1 << 0)) && (!MCF_GPIO_PPDSDR_FEC1L & (1 << 5))); - warte_10us(); + wait_10us(); MCF_GPIO_PODR_FEC1L |= (1 << 2); - warte_10us(); + wait_10us(); while (!MCF_GPIO_PPDSDR_FEC1L & (1 << 0)) { @@ -277,6 +277,9 @@ void init_fpga(void) MCF_GPIO_PODR_FEC1L |= 1; MCF_GPIO_PODR_FEC1L &= ~1; } +} + +#ifdef _NOT_USED_ bra init_fpga_end //--------------------------------------------------------- @@ -330,7 +333,6 @@ init_fpga_end: } MCF_PSC0_PSCTB_8BIT = 'SET!'; MCF_PSC0_PSCTB_8BIT = 0x0a0d;} -#ifdef _NOT_USED_ /* * INIT VIDEO DDR RAM @@ -651,7 +653,7 @@ i2c_ok: MCF_I2C_I2SR &= 0xfd; MCF_I2C_I2CR |= 0x08; // txak=1 - warte_50us(); + wait_50us(); RBYT = MCF_I2C_I2DR; @@ -725,7 +727,7 @@ void init_ac97(void) { { MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0 } - warte_50us(); + wait_50us(); va = MCF_PSC2_PSCTB_AC97; if ((va & 0x80000fff) == 0x80000800) { From 7f729fa8eccc7e4c397a84890358065c6436e4f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 06:13:44 +0000 Subject: [PATCH 019/276] rather optimize for size than speed for now --- BaS_GNU/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index d503b1f..cac202f 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -15,7 +15,7 @@ CC=$(TCPREFIX)gcc LD=$(TCPREFIX)ld INCLUDE=-Iinclude -CFLAGS=-mcfv4e -Wno-multichar -O1 -fomit-frame-pointer +CFLAGS=-mcfv4e -Wno-multichar -Os -fomit-frame-pointer #CFLAGS=-mcfv4e -Wno-multichar -S -O3 -fomit-frame-pointer SRCDIR=sources From 10e31d172be4779f7aeed85872c499328ab958f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 06:15:28 +0000 Subject: [PATCH 020/276] refactored some hardcoded constants --- BaS_GNU/sources/sysinit.c | 69 ++++++++++++++++++++------------------- 1 file changed, 35 insertions(+), 34 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 8259609..e1e70a7 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -10,6 +10,10 @@ #include "MCF5475.h" #include "startcf.h" + +static const uint8_t *FPGA_FLASH_DATA = (uint8_t *) 0xe0700000L; +static const uint8_t *FPGA_FLASH_DATA_END = (uint8_t *) 0xe0800000L; + extern unsigned long _VRAM; extern unsigned long _Bas_base; extern unsigned long BaS; @@ -125,10 +129,10 @@ void init_serial(void) /********************************************************************/ /* Initialize DDR DIMMs on the EVB board */ /********************************************************************/ - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ +/* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ void init_ddram(void) { MCF_PSC0_PSCTB_8BIT = 'DDRA'; @@ -231,7 +235,7 @@ void init_fpga(void) } /* - * excerpt from the Altera configuration manual: + * excerpt from an Altera configuration manual: * The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The * configuration cycle consists of 3 stagesÑreset, configuration, and initialization. * While nCONFIG is low, the device is in reset. When the device comes out of reset, @@ -248,7 +252,7 @@ void init_fpga(void) * which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates * configuration is complete and initialization of the device can begin. */ - fpga_data = (uint8_t *) 0xe0700000L; + fpga_data = (uint8_t *) FPGA_FLASH_DATA; do { uint8_t value = *fpga_data++; @@ -269,40 +273,37 @@ void init_fpga(void) MCF_GPIO_PODR_FEC1L |= 1; MCF_GPIO_PODR_FEC1L &= ~1; } - } while ((!MCF_GPIO_PPDSDR_FEC1L & (1 << 5)) && (fpga_data < (uint8_t *) 0xE0800000)); + } while ((!MCF_GPIO_PPDSDR_FEC1L & (1 << 5)) && (fpga_data < FPGA_FLASH_DATA_END)); - for (i = 0; i < 4000; i++) + if (fpga_data < FPGA_FLASH_DATA_END) { - /* toggle a little more since it's fun ;) */ - MCF_GPIO_PODR_FEC1L |= 1; - MCF_GPIO_PODR_FEC1L &= ~1; + for (i = 0; i < 4000; i++) + { + /* toggle a little more since it's fun ;) */ + MCF_GPIO_PODR_FEC1L |= 1; + MCF_GPIO_PODR_FEC1L &= ~1; + } } + else + { + MCF_PSC0_PSCTB_8BIT = ' NOT'; + } + MCF_PSC0_PSCTB_8BIT = 'OK! '; + MCF_PSC0_PSCTB_8BIT = 0x0d0a; +} + +void wait_pll(void) +{ + do { + wait1ms(); + } while (! * (uint16_t *) 0xf0000800); +} + +void init_pll(void) +{ } #ifdef _NOT_USED_ - - bra init_fpga_end -//--------------------------------------------------------- - wait_pll: - lea MCF_SLT0_SCNT, a3 - move.l (a3),d0 - move.l #100000,d6 // ca 1ms - wait_pll_loop: - tst.w (a1) - bpl wait_pll_ok - move.l (a3), d1 - sub.l d0, d1 - add.l d6, d1 - bpl wait_pll_loop -wait_pll_ok: - rts -// fertig - fpga_error: - } - - MCF_PSC0_PSCTB_8BIT = ' NOT'; -init_fpga_end: - MCF_PSC0_PSCTB_8BIT = ' OK!'; MCF_PSC0_PSCTB_8BIT = 0x0a0d; // init pll MCF_PSC0_PSCTB_8BIT = 'PLL '; asm { lea 0xf0000600, a0 lea 0xf0000800, a1 bsr wait_pll move.w From 93fdb88e6dd311e744079908b9b66fe80a7c71a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 06:16:50 +0000 Subject: [PATCH 021/276] fixed typo (assembler sources weren't initialized correctly) --- BaS_GNU/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index cac202f..0533d19 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -27,7 +27,7 @@ CSRCS= \ $(SRCDIR)/sd_card.c \ $(SRCDIR)/last.c -ARCS= \ +ASRCS= \ $(SRCDIR)/startcf.S \ $(SRCDIR)/mmu.S \ $(SRCDIR)/exceptions.S \ From 5ac0c061d1892e460faba1e3c8fac9255e450b49 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 06:35:02 +0000 Subject: [PATCH 022/276] generate object files into objs directory --- BaS_GNU/Makefile | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 0533d19..99e6247 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -18,6 +18,7 @@ INCLUDE=-Iinclude CFLAGS=-mcfv4e -Wno-multichar -Os -fomit-frame-pointer #CFLAGS=-mcfv4e -Wno-multichar -S -O3 -fomit-frame-pointer SRCDIR=sources +OBJDIR=objs EXEC=bas.hex @@ -35,8 +36,8 @@ ASRCS= \ $(SRCDIR)/ewf.S \ $(SRCDIR)/illegal_instruction.S -COBJS=$(CSRCS:.c=.o) -AOBJS=$(ASRCS:.S=.o) +COBJS=$(patsubst $(SRCDIR),$(OBJDIR),$(patsubst %.c,%.o,$(CSRCS))) +AOBJS=$(patsubst $(SRCDIR),$(OBJDIR),$(patsubst %.S,%.o,$(ASRCS))) OBJS=$(COBJS) $(SOBJS) @@ -49,7 +50,7 @@ clean: rm $(EXEC) *.o .c.o: - $(CC) -c $(CFLAGS) $(INCLUDE) $< + $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ .S.o: - $(CC) -c $(CFLAGS) $(INCLUDE) $< + $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ From ee08924964e811eede4a720b3d008dbb28bc24f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 06:43:48 +0000 Subject: [PATCH 023/276] Fixed typo (SOBJS instead of AOBJS) --- BaS_GNU/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 99e6247..1159e1e 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -39,7 +39,7 @@ ASRCS= \ COBJS=$(patsubst $(SRCDIR),$(OBJDIR),$(patsubst %.c,%.o,$(CSRCS))) AOBJS=$(patsubst $(SRCDIR),$(OBJDIR),$(patsubst %.S,%.o,$(ASRCS))) -OBJS=$(COBJS) $(SOBJS) +OBJS=$(COBJS) $(AOBJS) all: $(EXEC) From a9d1a24e184b9f44b981154e7813dbcebbaadf18 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 06:49:15 +0000 Subject: [PATCH 024/276] no objects really go to the objs directory --- BaS_GNU/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 1159e1e..71c4e21 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -36,11 +36,11 @@ ASRCS= \ $(SRCDIR)/ewf.S \ $(SRCDIR)/illegal_instruction.S -COBJS=$(patsubst $(SRCDIR),$(OBJDIR),$(patsubst %.c,%.o,$(CSRCS))) -AOBJS=$(patsubst $(SRCDIR),$(OBJDIR),$(patsubst %.S,%.o,$(ASRCS))) +COBJS=$(patsubst $(SRCDIR)/%.o,$(OBJDIR)/%.o,$(patsubst %.c,%.o,$(CSRCS))) +AOBJS=$(patsubst $(SRCDIR)/%.o,$(OBJDIR)/%.o,$(patsubst %.S,%.o,$(ASRCS))) OBJS=$(COBJS) $(AOBJS) - + all: $(EXEC) $(EXEC): $(OBJS) From 6d23105563c6400d5b8196bda8f3a2c20bb6c53a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 06:55:17 +0000 Subject: [PATCH 025/276] fixed pattern rules --- BaS_GNU/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 71c4e21..5593a74 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -49,8 +49,8 @@ $(EXEC): $(OBJS) clean: rm $(EXEC) *.o -.c.o: +$(OBJDIR)/%.o:$(SRCDIR)/%.c $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ -.S.o: +$(OBJDIR)/%.o:$(SRCDIR)/%.S $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ From 55895a0c15bde18584c80a70a7acfb73e43f58b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 08:38:15 +0000 Subject: [PATCH 026/276] --- BaS_GNU/include/MCF5475.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/BaS_GNU/include/MCF5475.h b/BaS_GNU/include/MCF5475.h index ed275cb..be18fec 100644 --- a/BaS_GNU/include/MCF5475.h +++ b/BaS_GNU/include/MCF5475.h @@ -40,6 +40,16 @@ extern "C" { #pragma define_section system ".system" far_absolute RW +/* get rid of __declspec */ +#if __GNUC__ +#undef __declspec +/* the following should work if we had an ELF capable toolchain. Unfortunately, it doesn't + * for the current m68k-atari-mint aoutx toolchain since it does not support the + * __attribute__ ((section("x"))) syntax. + */ +/* #define __declspec(a) __attribute__ ((section ("a"))) */ +#define __declspec(a) /* */ + /*** * MCF5475 Derivative Memory map definitions from linker command files: * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE From 001f009327dfa5fcee3fa5a9b37a6833d94620b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 08:40:42 +0000 Subject: [PATCH 027/276] added objs dir From 5ad8338a959ecb6f09136b36e3c164fae23dc041 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 09:13:57 +0000 Subject: [PATCH 028/276] Fixed case mismatch in include file name which wasn't catched on (non case sensitive) MacOS X filesystem --- BaS_GNU/sources/sd_card.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/sources/sd_card.c b/BaS_GNU/sources/sd_card.c index d8e206d..2fd7bb0 100644 --- a/BaS_GNU/sources/sd_card.c +++ b/BaS_GNU/sources/sd_card.c @@ -2,7 +2,7 @@ * sd card */ -#include +#include #define dspi_dtar0 0x0c #define dspi_dsr 0x2c From f09737a92a87ab040a9f6b7b0d6b73d3f68ab737 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 09:16:15 +0000 Subject: [PATCH 029/276] added missing source files from original code --- BaS_GNU/sources/div.s | 1326 +++++++++++++++++++++ BaS_GNU/sources/ewf.s | 1565 +++++++++++++++++++++++++ BaS_GNU/sources/exceptions.s | 799 +++++++++++++ BaS_GNU/sources/ii_add.h | 581 +++++++++ BaS_GNU/sources/ii_and.h | 441 +++++++ BaS_GNU/sources/ii_dbcc.h | 117 ++ BaS_GNU/sources/ii_ewf.h | 181 +++ BaS_GNU/sources/ii_exg.h | 120 ++ BaS_GNU/sources/ii_func.h | 945 +++++++++++++++ BaS_GNU/sources/ii_jmp.h | 59 + BaS_GNU/sources/ii_lea.h | 105 ++ BaS_GNU/sources/ii_macro.h | 144 +++ BaS_GNU/sources/ii_move.h | 1271 ++++++++++++++++++++ BaS_GNU/sources/ii_movem.h | 374 ++++++ BaS_GNU/sources/ii_movep.h | 179 +++ BaS_GNU/sources/ii_op.h | 661 +++++++++++ BaS_GNU/sources/ii_opc.h | 263 +++++ BaS_GNU/sources/ii_or.h | 442 +++++++ BaS_GNU/sources/ii_pea.h | 74 ++ BaS_GNU/sources/ii_shd.h | 247 ++++ BaS_GNU/sources/ii_shift.h | 687 +++++++++++ BaS_GNU/sources/ii_sub.h | 584 +++++++++ BaS_GNU/sources/illegal_instruction.s | 328 ++++++ BaS_GNU/sources/last.c | 11 + BaS_GNU/sources/last.s | 10 + BaS_GNU/sources/macro.h | 10 + BaS_GNU/sources/mmu.s | 196 ++++ BaS_GNU/sources/movem.h | 256 ++++ BaS_GNU/sources/sd_card.s | 406 +++++++ BaS_GNU/sources/sd_ide.c | 543 +++++++++ BaS_GNU/sources/sd_ide.s | 458 ++++++++ BaS_GNU/sources/startcf.S | 82 ++ BaS_GNU/sources/startcf.h | 47 + BaS_GNU/sources/supervisor.s | 585 +++++++++ 34 files changed, 14097 insertions(+) create mode 100644 BaS_GNU/sources/div.s create mode 100644 BaS_GNU/sources/ewf.s create mode 100644 BaS_GNU/sources/exceptions.s create mode 100644 BaS_GNU/sources/ii_add.h create mode 100644 BaS_GNU/sources/ii_and.h create mode 100644 BaS_GNU/sources/ii_dbcc.h create mode 100644 BaS_GNU/sources/ii_ewf.h create mode 100644 BaS_GNU/sources/ii_exg.h create mode 100644 BaS_GNU/sources/ii_func.h create mode 100644 BaS_GNU/sources/ii_jmp.h create mode 100644 BaS_GNU/sources/ii_lea.h create mode 100644 BaS_GNU/sources/ii_macro.h create mode 100644 BaS_GNU/sources/ii_move.h create mode 100644 BaS_GNU/sources/ii_movem.h create mode 100644 BaS_GNU/sources/ii_movep.h create mode 100644 BaS_GNU/sources/ii_op.h create mode 100644 BaS_GNU/sources/ii_opc.h create mode 100644 BaS_GNU/sources/ii_or.h create mode 100644 BaS_GNU/sources/ii_pea.h create mode 100644 BaS_GNU/sources/ii_shd.h create mode 100644 BaS_GNU/sources/ii_shift.h create mode 100644 BaS_GNU/sources/ii_sub.h create mode 100644 BaS_GNU/sources/illegal_instruction.s create mode 100644 BaS_GNU/sources/last.c create mode 100644 BaS_GNU/sources/last.s create mode 100644 BaS_GNU/sources/macro.h create mode 100644 BaS_GNU/sources/mmu.s create mode 100644 BaS_GNU/sources/movem.h create mode 100644 BaS_GNU/sources/sd_card.s create mode 100644 BaS_GNU/sources/sd_ide.c create mode 100644 BaS_GNU/sources/sd_ide.s create mode 100644 BaS_GNU/sources/startcf.S create mode 100644 BaS_GNU/sources/startcf.h create mode 100644 BaS_GNU/sources/supervisor.s diff --git a/BaS_GNU/sources/div.s b/BaS_GNU/sources/div.s new file mode 100644 index 0000000..f5f151c --- /dev/null +++ b/BaS_GNU/sources/div.s @@ -0,0 +1,1326 @@ + +/********************************************************************/ +// sd card +/********************************************************************/ +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 + +sd_test: + lea 0x40000,a5 // basis addresse + move.l #0x1fffffff,d0 // normal dspi + move.l d0,MCF_PAD_PAR_DSPI + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) // 8 bit 4MHz + move.l #0x38551120,d0 + move.l d0,dspi_dtar0(a0) // + move.l #0x08200000,d4 // tx vorbesetzen + mov3q.l #-1,dspi_dsr(a0) + + move.b #0xc0,(a0) // 8 bit 4MHz + bsr warte_1ms + move.b #0x80,(a0) // 8 bit 4MHz +// sd idle + moveq.l #100,d6 // 100 versuche +sd_idle: + bsr sd_16clk + move.b #0x40,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x01,d5 + beq wait_of_aktiv + subq.l #1,d6 + beq sd_not + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + move.b #0x77,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x05,d5 + beq wait_of_aktiv + + +wait_of_aktiv2: + bsr sd_16clk + move.b #0x69,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x02,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq wait_of_aktiv2 + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + move.b #0x50,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #02,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + move.b #0x51,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_rb + + move.l a5,a4 // adresse setzen + bsr sd_rcv_block + +// write block +sd_wb: + bsr sd_16clk + move.b #0x58,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_wb + + bsr sd_send_block + +// read block 2 +sd_rb2: + bsr sd_16clk + move.b #0x51,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_rb + + bsr sd_rcv_block + clr.l d0 + halt + halt + rts +// status holen ------------------------------- +sd_not: + moveq.l #-1,d0 + halt + halt + rts + +// status holen ------------------------------- +sd_get_status: + move.b #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_get_status + rts +// byt senden und holen --------------------- +sd_com: + move.l d4,dspi_dtfr(a0) +wait_auf_complett: + btst.b #7,dspi_dsr(a0) + beq wait_auf_complett + move.l dspi_drfr(a0),d5 + mov3q.l #-1,dspi_dsr(a0) // clr status register + rts + +// daten holen ---------------------------- +sd_rcv_block: + move.l #512,d3 // 512 byts + 2 ccr byts + move.b #0xff,d4 +sd_rcv_rb_w: + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rcv_rb_w // nein-> +sd_rcv_rd_rb: + bsr sd_com + move.b d5,(a4)+ + subq.l #1,d3 + bne sd_rcv_rd_rb +// crc holen + bsr sd_com // crc 1.byt + move.b d5,d1 + bsr sd_com // crc 2.byt + move.b d5,d2 + rts + +// daten schreiben ----------------------- +sd_send_block: + move.l #512,d3 + move.b #0xfe,d4 // start token + bsr sd_com // senden +sd_send_wr_wb: + move.b #0xc7,d4 // data + bsr sd_com // senden + subq.l #1,d3 + bne sd_send_wr_wb +// send crc + move.b d1,d4 + bsr sd_com // crc 1.byt + move.b d2,d4 + bsr sd_com // crc 2.byt +sd_send_wr_ww: + bsr sd_get_status + and.l #0x1f,d5 + cmp.b #0x05,d5 + bne sd_send_wr_ww +sd_sendwait_wr_f: + bsr sd_com + cmp.b #0xff,d5 + bne sd_sendwait_wr_f + rts +// clock einfügen ------------------------------------- +sd_16clk: + move.b #0xc0,(a0) // 8 bit 4MHz + nop + move.b #0x80,(a0) // 8 bit 4MHz + rts +// cdm 58 +read_ocr: + bsr sd_16clk + move.b #0x7a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + move.b #0xaa,d4 + bsr sd_com + move.b #0x87,d4 + bsr sd_com + + bsr sd_get_status + + halt + + move.l #'Ver1',d6 + cmp.b #5,d5 + beq sd_v1 + cmp.b #1,d5 + bne read_csd + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com +/******************************************/ +#include "MCF5475.h" +#include "startcf.h" + +extern unsigned long far __SP_AFTER_RESET[]; +extern unsigned long far __Bas_base[]; + + /* imported routines */ +//extern int warten_20ms(); +//extern int warten_200us(); +//extern int warten_10us(); + +/********************************************************************/ +void asm sd_test(void) +{ + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} + + +/**************************************************/ +void asm ide_test(void) +{ + lea MCF_PAD_PAR_DSPI,a0 + move.w #0x1fff,(a0) + lea MCF_DSPI_DCTAR0,a0 + move.l #0x38a644e4,(a0) + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) + clr.l MCF_DSPI_DTCR + bsr warten_20ms + lea MCF_DSPI_DTFR,a0 + lea MCF_DSPI_DRFR,a1 + + moveq #10,d0 +sd_reset: + move.l #0x000100ff,(a0) + bsr warten_20ms + and.l (a1),d0 + subq.l #1,d0 + bne sd_reset + + moveq #10,d1 +sd_loop1: + bsr warten_20ms + moveq #-1,d0 +// cmd 0 set to idle + move.l #0x00200040,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200095,(a0) + bsr warten_20ms + and.l (a1),d0 + cmp.w #0x0001,d0 + beq sd_loop2 + subq.l #1,d1 + bne sd_loop1 + moveq #10,d1 + bra sd_test +sd_loop2: + moveq #-1,d0 +// cmd 41 + move.l #0x00200069,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200001,(a0) + bsr warten_20ms + and.l (a1),d0 + tst.w d0 + bne sd_loop2 + + nop + nop +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst.b #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} +/********************************************************************/ +//.include "startcf.h" + +//.extern ___MBAR +//#define MCF_SLT0_SCNT ___MBAR+0x908 + +//.global ide_test + +.text +/********************************************************************/ +// sd card +/********************************************************************/ +sd_test: + lea 0x40000,a5 // basis addresse + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + move.l a5,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + move.l #513,d7 + moveq.l #0xbb,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0xbb,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + +halt +halt + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) // nCS=0 +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + bclr.b #0,(a1) // default 0 bit senden + btst d2,d4 // ist 0? + beq sd_com2 // ja-> + bset.b #0,(a1) // sonst auf 1 +sd_com2: + bsr sd_clk // clocken + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) // nCS=1 + bset.b #0,(a1) // daten = 0 + bsr warten_200us + rts +// clocken +sd_clk: + tst.b 0xfffff700 // wait + tst.b 0xfffff700 + bset.b #2,(a1) // clock high + tst.b 0xfffff700 // wait + tst.b 0xfffff700 // wait + move.b (a2),d3 // bit holen + bclr.b #2,(a1) // clock low + rts + +sd_16clk: + move.l #160,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +/********************************************************************/ +// video pll +/********************************************************************/ + lea 0xf0000800,a1 + + lea 0xf0000600,a0 + move.l #128,d0 +clr_pll: + bsr wait_pll + clr.w (a0) + addq.l #4,a0 + subq.l #1,d0 + bne clr_pll + + lea 0xf0000600,a0 + bsr wait_pll + move.w #27,0x48(a0) // loopfilter r + bsr wait_pll + move.w #1,0x08(a0) // charge pump I + bsr wait_pll + move.w #12,0x0(a0) // N counter high = 12 + bsr wait_pll + move.w #12,0x40(a0) // N counter low = 12 + bsr wait_pll + move.w #1,0x114(a0) // ck1 bypass + bsr wait_pll + move.w #1,0x118(a0) // ck2 bypass + bsr wait_pll + move.w #1,0x11c(a0) // ck3 bypass + bsr wait_pll + move.w #1,0x10(a0) // ck0 high = 1 + bsr wait_pll + move.w #1,0x50(a0) // ck0 low = 1 + + bsr wait_pll + move.w #1,0x144(a0) // M odd division + bsr wait_pll + move.w #1,0x44(a0) // M low = 1 + + bsr wait_pll + move.w #99,0x04(a0) // M high = 100 + + bsr wait_pll + clr.b (a1) // set + +set_pll: + bsr read_pll + halt + move.w d0,(a0) + bsr wait_pll + clr.b (a1) + bra set_pll + +read_pll: + lea 0xf0000600,a3 + lea 0x10000,a2 + move.l #128,d3 +read1_pll: + bsr wait_pll + move.w (a3),d1 + bsr wait_pll + move.w (a3),(a2) + addq.l #4,a3 + addq.l #4,a2 + subq.l #1,d3 + bne read1_pll + rts +wait_pll: + tst.w (a1) + bmi wait_pll + rts + +/********************************************************************/ +void ide_test(void) +/********************************************************************/ +{ + asm + { + halt + lea 0xfff00000,a0 + lea 0x80000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rxl +// read sector normal + move.b #1,seccnt(a0) // 1 sector 0x200 + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rxl +// write pattern 0x400 + move.l a1,a4 //a4=400 + move.l #256,d0 + clr.l d1 +ide_test_loop3: + move.w d1,(a1)+ + addq.l #1,d1 + subq.l #1,d0 + bne ide_test_loop3 + move.l a4,a1 +// write testpattern sector 0x400 + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait + bsr ds_txl + bsr wait_int + move.l a1,a2 //a2=600 + move.l #256,d4 +loop_rw: +// read testpattern sector 0x600 + move.l a2,a1 +// halt + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rxl +// verändere testpattern + move.l a2,a1 +// halt + move.l #256,d0 + move.l #0x100,d1 +verae_loop: + move.w (a1),d2 + add.l d1,d2 + move.w d2,(a1)+ + subq.l #1,d0 + bne verae_loop +// write testpattern sector 0x600 + move.l a2,a1 +// halt + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait + bsr ds_txl + bsr wait_int + subq.l #1,d4 +// bra verae_loop + bne loop_rw +// sector vergleichen +// halt + move.l #128,d0 + moveq.l #-1,d1 +verg_loop: + move.l (a2)+,d2 + cmp.l (a4)+,d2 + bne error + subq.l #1,d0 + bne verg_loop + clr.l d1 +error: + halt + rts +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_txl + + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben long +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts + } +} +/********************************************************************/ diff --git a/BaS_GNU/sources/ewf.s b/BaS_GNU/sources/ewf.s new file mode 100644 index 0000000..7f5a644 --- /dev/null +++ b/BaS_GNU/sources/ewf.s @@ -0,0 +1,1565 @@ +/*************************************************************************************************/ +// extension word format: a0 zeigt auf code, in a1 ist ay, d0/d1 wird zerstört +//------------------------------------------------------------------------------ + +.include "ii_macro.h" + +.global ewf +//----------------------------------------------------------- +.text +ewferr: + nop + halt + nop +//----------------------------------------------------------- +ewf: + mvz.b (a0)+,d1 // 1. byt ewf + mvs.w ewf_table-*-2(pc,d1*2),d1 + jmp ewf_table-*-2(pc,d1) +ewf_table: + .short ewf_00-ewf_table,ewf_01-ewf_table,ewf_02-ewf_table,ewf_03-ewf_table + .short ewf_04-ewf_table,ewf_05-ewf_table,ewf_06-ewf_table,ewf_07-ewf_table + .short ewferr-ewf_table,ewf_09-ewf_table,ewferr-ewf_table,ewf_0b-ewf_table + .short ewferr-ewf_table,ewf_0d-ewf_table,ewferr-ewf_table,ewf_0f-ewf_table + .short ewf_10-ewf_table,ewf_11-ewf_table,ewf_12-ewf_table,ewf_13-ewf_table + .short ewf_14-ewf_table,ewf_15-ewf_table,ewf_16-ewf_table,ewf_17-ewf_table + .short ewferr-ewf_table,ewf_19-ewf_table,ewferr-ewf_table,ewf_1b-ewf_table + .short ewferr-ewf_table,ewf_1d-ewf_table,ewferr-ewf_table,ewf_1f-ewf_table + .short ewf_20-ewf_table,ewf_21-ewf_table,ewf_22-ewf_table,ewf_23-ewf_table + .short ewf_24-ewf_table,ewf_25-ewf_table,ewf_26-ewf_table,ewf_27-ewf_table + .short ewferr-ewf_table,ewf_29-ewf_table,ewferr-ewf_table,ewf_2b-ewf_table + .short ewferr-ewf_table,ewf_2d-ewf_table,ewferr-ewf_table,ewf_2f-ewf_table + .short ewf_30-ewf_table,ewf_31-ewf_table,ewf_32-ewf_table,ewf_33-ewf_table + .short ewf_34-ewf_table,ewf_35-ewf_table,ewf_36-ewf_table,ewf_37-ewf_table + .short ewferr-ewf_table,ewf_39-ewf_table,ewferr-ewf_table,ewf_3b-ewf_table + .short ewferr-ewf_table,ewf_3d-ewf_table,ewferr-ewf_table,ewf_3f-ewf_table + .short ewf_40-ewf_table,ewf_41-ewf_table,ewf_42-ewf_table,ewf_43-ewf_table + .short ewf_44-ewf_table,ewf_45-ewf_table,ewf_46-ewf_table,ewf_47-ewf_table + .short ewferr-ewf_table,ewf_49-ewf_table,ewferr-ewf_table,ewf_4b-ewf_table + .short ewferr-ewf_table,ewf_4d-ewf_table,ewferr-ewf_table,ewf_4f-ewf_table + .short ewf_50-ewf_table,ewf_51-ewf_table,ewf_52-ewf_table,ewf_53-ewf_table + .short ewf_54-ewf_table,ewf_55-ewf_table,ewf_56-ewf_table,ewf_57-ewf_table + .short ewferr-ewf_table,ewf_59-ewf_table,ewferr-ewf_table,ewf_5b-ewf_table + .short ewferr-ewf_table,ewf_5d-ewf_table,ewferr-ewf_table,ewf_5f-ewf_table + .short ewf_60-ewf_table,ewf_61-ewf_table,ewf_62-ewf_table,ewf_63-ewf_table + .short ewf_64-ewf_table,ewf_65-ewf_table,ewf_66-ewf_table,ewf_67-ewf_table + .short ewferr-ewf_table,ewf_69-ewf_table,ewferr-ewf_table,ewf_6b-ewf_table + .short ewferr-ewf_table,ewf_6d-ewf_table,ewferr-ewf_table,ewf_6f-ewf_table + .short ewf_70-ewf_table,ewf_71-ewf_table,ewf_72-ewf_table,ewf_73-ewf_table + .short ewf_74-ewf_table,ewf_75-ewf_table,ewf_76-ewf_table,ewf_77-ewf_table + .short ewferr-ewf_table,ewf_79-ewf_table,ewferr-ewf_table,ewf_7b-ewf_table + .short ewferr-ewf_table,ewf_7d-ewf_table,ewferr-ewf_table,ewf_7f-ewf_table + .short ewf_80-ewf_table,ewf_81-ewf_table,ewf_82-ewf_table,ewf_83-ewf_table + .short ewf_84-ewf_table,ewf_85-ewf_table,ewf_86-ewf_table,ewf_87-ewf_table + .short ewferr-ewf_table,ewf_89-ewf_table,ewferr-ewf_table,ewf_8b-ewf_table + .short ewferr-ewf_table,ewf_8d-ewf_table,ewferr-ewf_table,ewf_8f-ewf_table + .short ewf_90-ewf_table,ewf_91-ewf_table,ewf_92-ewf_table,ewf_93-ewf_table + .short ewf_94-ewf_table,ewf_95-ewf_table,ewf_96-ewf_table,ewf_97-ewf_table + .short ewferr-ewf_table,ewf_99-ewf_table,ewferr-ewf_table,ewf_9b-ewf_table + .short ewferr-ewf_table,ewf_9d-ewf_table,ewferr-ewf_table,ewf_9f-ewf_table + .short ewf_a0-ewf_table,ewf_a1-ewf_table,ewf_a2-ewf_table,ewf_a3-ewf_table + .short ewf_a4-ewf_table,ewf_a5-ewf_table,ewf_a6-ewf_table,ewf_a7-ewf_table + .short ewferr-ewf_table,ewf_a9-ewf_table,ewferr-ewf_table,ewf_ab-ewf_table + .short ewferr-ewf_table,ewf_ad-ewf_table,ewferr-ewf_table,ewf_af-ewf_table + .short ewf_b0-ewf_table,ewf_b1-ewf_table,ewf_b2-ewf_table,ewf_b3-ewf_table + .short ewf_b4-ewf_table,ewf_b5-ewf_table,ewf_b6-ewf_table,ewf_b7-ewf_table + .short ewferr-ewf_table,ewf_b9-ewf_table,ewferr-ewf_table,ewf_bb-ewf_table + .short ewferr-ewf_table,ewf_bd-ewf_table,ewferr-ewf_table,ewf_bf-ewf_table + .short ewf_c0-ewf_table,ewf_c1-ewf_table,ewf_c2-ewf_table,ewf_c3-ewf_table + .short ewf_c4-ewf_table,ewf_c5-ewf_table,ewf_c6-ewf_table,ewf_c7-ewf_table + .short ewferr-ewf_table,ewf_c9-ewf_table,ewferr-ewf_table,ewf_cb-ewf_table + .short ewferr-ewf_table,ewf_cd-ewf_table,ewferr-ewf_table,ewf_cf-ewf_table + .short ewf_d0-ewf_table,ewf_d1-ewf_table,ewf_d2-ewf_table,ewf_d3-ewf_table + .short ewf_d4-ewf_table,ewf_d5-ewf_table,ewf_d6-ewf_table,ewf_d7-ewf_table + .short ewferr-ewf_table,ewf_d9-ewf_table,ewferr-ewf_table,ewf_db-ewf_table + .short ewferr-ewf_table,ewf_dd-ewf_table,ewferr-ewf_table,ewf_df-ewf_table + .short ewf_e0-ewf_table,ewf_e1-ewf_table,ewf_e2-ewf_table,ewf_e3-ewf_table + .short ewf_e4-ewf_table,ewf_e5-ewf_table,ewf_e6-ewf_table,ewf_e7-ewf_table + .short ewferr-ewf_table,ewf_e9-ewf_table,ewferr-ewf_table,ewf_eb-ewf_table + .short ewferr-ewf_table,ewf_ed-ewf_table,ewferr-ewf_table,ewf_ef-ewf_table + .short ewf_f0-ewf_table,ewf_f1-ewf_table,ewf_f2-ewf_table,ewf_f3-ewf_table + .short ewf_f4-ewf_table,ewf_f5-ewf_table,ewf_f6-ewf_table,ewf_f7-ewf_table + .short ewferr-ewf_table,ewf_f9-ewf_table,ewferr-ewf_table,ewf_fb-ewf_table + .short ewferr-ewf_table,ewf_fd-ewf_table,ewferr-ewf_table,ewf_ff-ewf_table +//d0.w * 1 +ewf_00: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_01: + mvs.w d0_off+6(a7),d0 + bra ewf_full +//d0.w * 2 +ewf_02: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_03: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d0.w * 4 +ewf_04: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_05: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d0.w * 8 +ewf_06: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_07: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 1 +ewf_09: + move.l d0_off+4(a7),d0 + bra ewf_full +//d0.l * 2 +ewf_0b: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 4 +ewf_0d: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 8 +ewf_0f: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 1 +ewf_10: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_11: + mvs.w d1_off+6(a7),d0 + bra ewf_full +//d1.w * 2 +ewf_12: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_13: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 4 +ewf_14: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_15: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 8 +ewf_16: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_17: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 1 +ewf_19: + move.l d1_off+4(a7),d0 + bra ewf_full +//d1.l * 2 +ewf_1b: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 4 +ewf_1d: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 8 +ewf_1f: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 1 +ewf_20: + mvs.b (a0)+,d1 + mvs.w d2,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_21: + mvs.w d2,d0 + bra ewf_full +//d2.w * 2 +ewf_22: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_23: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 4 +ewf_24: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_25: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 8 +ewf_26: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_27: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 1 +ewf_29: + move.l d2,d0 + bra ewf_full +//d2.l * 2 +ewf_2b: + move.l d2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 4 +ewf_2d: + move.l d2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 8 +ewf_2f: + move.l d2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 1 +ewf_30: + mvs.b (a0)+,d1 + mvs.w d3,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_31: + mvs.w d3,d0 + bra ewf_full +//d3.w * 2 +ewf_32: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_33: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 4 +ewf_34: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_35: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 8 +ewf_36: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_37: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 1 +ewf_39: + move.l d3,d0 + bra ewf_full +//d3.l * 3 +ewf_3b: + move.l d3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 4 +ewf_3d: + move.l d3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 8 +ewf_3f: + move.l d3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 1 +ewf_40: + mvs.b (a0)+,d1 + mvs.w d4,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_41: + mvs.w d4,d0 + bra ewf_full +//d4.w * 2 +ewf_42: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_43: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 4 +ewf_44: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_45: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 8 +ewf_46: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_47: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 1 +ewf_49: + move.l d4,d0 + bra ewf_full +//d4.l * 4 +ewf_4b: + move.l d4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 4 +ewf_4d: + move.l d4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 8 +ewf_4f: + move.l d4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 1 +ewf_50: + mvs.b (a0)+,d1 + mvs.w d5,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_51: + mvs.w d5,d0 + bra ewf_full +//d5.w * 2 +ewf_52: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_53: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 4 +ewf_54: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_55: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 8 +ewf_56: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_57: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 1 +ewf_59: + move.l d5,d0 + bra ewf_full +//d5.l * 5 +ewf_5b: + move.l d5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 4 +ewf_5d: + move.l d5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 8 +ewf_5f: + move.l d5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 1 +ewf_60: + mvs.b (a0)+,d1 + mvs.w d6,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_61: + mvs.w d6,d0 + bra ewf_full +//d6.w * 2 +ewf_62: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_63: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 4 +ewf_64: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_65: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 8 +ewf_66: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_67: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 1 +ewf_69: + move.l d6,d0 + bra ewf_full +//d6.l * 6 +ewf_6b: + move.l d6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 4 +ewf_6d: + move.l d6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 8 +ewf_6f: + move.l d6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 1 +ewf_70: + mvs.b (a0)+,d1 + mvs.w d7,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_71: + mvs.w d7,d0 + bra ewf_full +//d7.w * 2 +ewf_72: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_73: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 4 +ewf_74: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_75: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 8 +ewf_76: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_77: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 1 +ewf_79: + move.l d7,d0 + bra ewf_full +//d7.l * 7 +ewf_7b: + move.l d7,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 4 +ewf_7d: + move.l d7,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 8 +ewf_7f: + move.l d7,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 1 +ewf_80: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_81: + mvs.w a0_off+6(a7),d0 + bra ewf_full +//a0.w * 2 +ewf_82: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_83: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 4 +ewf_84: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_85: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 8 +ewf_86: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_87: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 1 +ewf_89: + move.l a0_off+4(a7),d0 + bra ewf_full +//a0.l * 2 +ewf_8b: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 4 +ewf_8d: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 8 +ewf_8f: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 1 +ewf_90: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_91: + mvs.w a1_off+6(a7),d0 + bra ewf_full +//a1.w * 2 +ewf_92: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_93: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 4 +ewf_94: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_95: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 8 +ewf_96: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_97: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 1 +ewf_99: + move.l a1_off+4(a7),d0 + bra ewf_full +//a1.l * 2 +ewf_9b: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 4 +ewf_9d: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 8 +ewf_9f: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 1 +ewf_a0: + mvs.b (a0)+,d1 + mvs.w a2,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_a1: + mvs.w a2,d0 + bra ewf_full +//a2.w * 2 +ewf_a2: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_a3: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 4 +ewf_a4: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_a5: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 8 +ewf_a6: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_a7: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 1 +ewf_a9: + move.l a2,d0 + bra ewf_full +//a2.l * 2 +ewf_ab: + move.l a2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 4 +ewf_ad: + move.l a2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 8 +ewf_af: + move.l a2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 1 +ewf_b0: + mvs.b (a0)+,d1 + mvs.w a3,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_b1: + mvs.w a3,d0 + bra ewf_full +//a3.w * 2 +ewf_b2: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_b3: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 4 +ewf_b4: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_b5: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 8 +ewf_b6: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_b7: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 1 +ewf_b9: + move.l a3,d0 + bra ewf_full +//a3.l * 3 +ewf_bb: + move.l a3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 4 +ewf_bd: + move.l a3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 8 +ewf_bf: + move.l a3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 1 +ewf_c0: + mvs.b (a0)+,d1 + mvs.w a4,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_c1: + mvs.w a4,d0 + bra ewf_full +//a4.w * 2 +ewf_c2: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_c3: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 4 +ewf_c4: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_c5: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 8 +ewf_c6: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_c7: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 1 +ewf_c9: + move.l a4,d0 + bra ewf_full +//a4.l * 4 +ewf_cb: + move.l a4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 4 +ewf_cd: + move.l a4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 8 +ewf_cf: + move.l a4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 1 +ewf_d0: + mvs.b (a0)+,d1 + mvs.w a5,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_d1: + mvs.w a5,d0 + bra ewf_full +//a5.w * 2 +ewf_d2: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_d3: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 4 +ewf_d4: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_d5: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 8 +ewf_d6: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_d7: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 1 +ewf_d9: + move.l a5,d0 + bra ewf_full +//a5.l * 5 +ewf_db: + move.l a5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 4 +ewf_dd: + move.l a5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 8 +ewf_df: + move.l a5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 1 +ewf_e0: + mvs.b (a0)+,d1 + mvs.w a6,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_e1: + mvs.w a6,d0 + bra ewf_full +//a6.w * 2 +ewf_e2: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_e3: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 4 +ewf_e4: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_e5: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 8 +ewf_e6: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_e7: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 1 +ewf_e9: + move.l a6,d0 + bra ewf_full +//a6.l * 6 +ewf_eb: + move.l a6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 4 +ewf_ed: + move.l a6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 8 +ewf_ef: + move.l a6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 1 +ewf_f0: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + add.l d1,a1 + rts +ewf_f1: + move.l a1,-(a7) + move.l usp,a1 + mvs.w a1,d0 + move.l (a7)+,a1 + bra ewf_full +//usp.w * 2 +ewf_f2: + mvs.b (a0)+,d1 + move.l usp,a1 + mvs.w a1,d0 + move.l (a7)+,a1 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_f3: + move.l usp,a1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 4 +ewf_f4: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_f5: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 8 +ewf_f6: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_f7: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 1 +ewf_f9: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + bra ewf_full +//usp.l * 7 +ewf_fb: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 4 +ewf_fd: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 8 +ewf_ff: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//----------------------------------------------------------------------------------- +// extension full format rest von ewf +//-------------------------------------------------------------------- +ewf_full: + mvz.b (a0)+,d1 + mvs.w ewff_table-*-2(pc,d1*2),d1 + jmp ewff_table-*-2(pc,d1) +ewff_table: + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //00 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //10 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsw-ewff_table,ewff_w0v-ewff_table,ewff_wwv-ewff_table,ewff_wlv-ewff_table //20 + .short ewff_end-ewff_table,ewff_w0n-ewff_table,ewff_wwn-ewff_table,ewff_wln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsl-ewff_table,ewff_l0v-ewff_table,ewff_lwv-ewff_table,ewff_llv-ewff_table //30 + .short ewff_end-ewff_table,ewff_l0n-ewff_table,ewff_lwn-ewff_table,ewff_lln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //40 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //50 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsw-ewff_table,ewff_wi0-ewff_table,ewff_wiw-ewff_table,ewff_wil-ewff_table //60 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsl-ewff_table,ewff_li0-ewff_table,ewff_liw-ewff_table,ewff_lil-ewff_table //70 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //80 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //90 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //a0 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //b0 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //c0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //d0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //e0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //f0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table +ewff_end: + rts +ewff_bsw: + mvs.w (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_bsl: + move.l (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_i0v: + add.l d0,a1 + move.l (a1),a1 + rts +ewff_iwv: + add.l d0,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_ilv: + add.l d0,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_i0n: + move.l (a1),a1 + add.l d0,a1 + rts +ewff_iwn: + move.l (a1),a1 + add.l d0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_iln: + move.l (a1),a1 + add.l d0,a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_mi0: + add.l d0,a1 + rts +ewff_miw: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_mil: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_wi0: + mvs.w (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_wiw: + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_wil: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_li0: + move.l (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_liw: + move.l (a0)+,d1 + add.l d1,a1 + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_lil: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_w0v: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + rts +ewff_wwv: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_wlv: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_l0v: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + rts +ewff_lwv: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_llv: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_w0n: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + add.l d0,a1 + rts +ewff_wwn: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_wln: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_l0n: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + add.l d0,a1 + rts +ewff_lwn: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_lln: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +/**************************************************************************************************************** + diff --git a/BaS_GNU/sources/exceptions.s b/BaS_GNU/sources/exceptions.s new file mode 100644 index 0000000..e0494c0 --- /dev/null +++ b/BaS_GNU/sources/exceptions.s @@ -0,0 +1,799 @@ +/********************************************************/ +/* exception vectoren intialisieren +/********************************************************/ + +.include "startcf.h" + +.extern ___Bas_base +.extern ___SUP_SP +.extern ___BOOT_FLASH +.extern ___RAMBAR0 +.extern _rt_cacr +.extern _rt_mod +.extern _rt_ssp +.extern _rt_usp +.extern _rt_vbr +.extern _illegal_instruction +.extern _privileg_violation +.extern _mmutr_miss +.extern ___MBAR +.extern ___MMUBAR +.extern _video_tlb +.extern _video_sbt +.extern cpusha + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + +#define MCF_EPORT_EPPAR ___MBAR+0xF00 +#define MCF_EPORT_EPDDR ___MBAR+0xF04 +#define MCF_EPORT_EPIER ___MBAR+0xF05 +#define MCF_EPORT_EPDR ___MBAR+0xF08 +#define MCF_EPORT_EPPDR ___MBAR+0xF09 +#define MCF_EPORT_EPFR ___MBAR+0xF0C + +#define MCF_GPIO_PODR_FEC1L ___MBAR+0xA07 + +#define MCF_PSC0_PSCTB_8BIT ___MBAR+0x860C + +#define MCF_PSC3_PSCRB_8BIT ___MBAR+0x890C +#define MCF_PSC3_PSCTB_8BIT ___MBAR+0x890C + +.public _vec_init + +//mmu --------------------------------------------------- +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + +#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V) +#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +//--------------------------------------------------- +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS ___MBAR+0x800 + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +#define MCF_SLT0_SCNT ___MBAR+0x908 + +/**********************************************************/ +// macros +/**********************************************************/ +irq: .macro vector,int_mask,clr_int + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern + lea MCF_EPORT_EPFR,a5 + move.b #clr_int,(a5) // clear int pending +// test auf protect mode --------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne @irq_protect // ja-> +// ------------------------------------------- + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + move.l vector,-(a7) + move #0x2\200,sr + rts +@irq_protect: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne @sev_supint // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben +#endif + bra @irq_end +@sev_supint: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec + bset #5,2(a5) // auf super setzen +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif +@irq_end: + move.l a5,usp // usp setzen + lea vector,a5 + adda.l _rt_vbr,a5 + move.l (a5),12(a7) // vectoradresse eintragen + move.b #int_mask,10(a7) // intmaske setzen + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg + .endm +/*********************************************************/ +.text +_vec_init: + mov3q.l #-1,_rt_mod // rt_mod auf super + clr.l _rt_ssp + clr.l _rt_usp + clr.l _rt_vbr + move.l #___RAMBAR0,d0 // sind in rambar0 + movec d0,VBR + move.l d0,a0 + move.l a0,a2 +init_vec: + move.l #256,d0 + lea std_exc_vec(pc),a1 // standard vector +init_vec_loop: + move.l a1,(a2)+ // mal standard vector für alle setzen + subq.l #1,d0 + bne init_vec_loop + + move.l #___SUP_SP,(a0) + lea reset_vector(pc),a1 + move.l a1,0x04(a0) + lea acess(pc),a1 + move.l a1,0x08(a0) + + move.b DIP_SWITCHa,d0 // ++ vr + btst #7,d0 + beq no_protect_vectors + + lea _illegal_instruction(pc),a1 + move.l a1,0x0c(a0) + lea _illegal_instruction(pc),a1 + move.l a1,0x10(a0) + lea zero_divide(pc),a1 + move.l a1,0x14(a0) + lea _privileg_violation(pc),a1 + move.l a1,0x20(a0) + lea linea(pc),a1 + move.l a1,0x28(a0) + lea linef(pc),a1 + move.l a1,0x2c(a0) + lea format(pc),a1 + move.l a1,0x38(a0) + + // floating point overflow + lea flpoow(pc),a1 + move.l a1,0xc0(a0) + lea flpoow(pc),a1 + move.l a1,0xc4(a0) + lea flpoow(pc),a1 + move.l a1,0xc8(a0) + lea flpoow(pc),a1 + move.l a1,0xcc(a0) + lea flpoow(pc),a1 + move.l a1,0xd0(a0) + lea flpoow(pc),a1 + move.l a1,0xd4(a0) + lea flpoow(pc),a1 + move.l a1,0xd8(a0) + lea flpoow(pc),a1 + move.l a1,0xdc(a0) +no_protect_vectors: + + +// int 1-7 + lea irq1(pc),a1 + move.l a1,0x104(a0) + lea irq2(pc),a1 + move.l a1,0x108(a0) + lea irq3(pc),a1 + move.l a1,0x10c(a0) + lea irq4(pc),a1 + move.l a1,0x110(a0) + lea irq5(pc),a1 + move.l a1,0x114(a0) + lea irq6(pc),a1 + move.l a1,0x118(a0) + lea irq7(pc),a1 + move.l a1,0x11c(a0) +//psc_vectors + lea psc3(pc),a1 + move.l a1,0x180(a0) +//timer 1 vectors + lea timer0(pc),a1 + move.l a1,0x1f8(a0) + rts +/********************************************************/ +/* exception vector routinen +/********************************************************/ +vector_table_start: +std_exc_vec: + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern +// test auf protect mode ------------------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne stv_protect // ja-> +//------------------------------------------------------ + move.w 8(a7),d0 // vector holen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),d0 + move.l 4(a7),a5 // a5 zurück + move.l d0,4(a7) + move.w 10(a7),d0 + bset #13,d0 // super + move.w d0,sr // orginal sr wert in super setzen + move.l (a7)+,d0 // d0 zurück + rts +stv_protect: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_sup // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),d0 // sr holen + move.l d0,-(a5) // sr transferieren + swap d0 // vec -> lw +#else + move.w 8(a7),d0 // vector holen + move.w d0,-(a5) // ablegen + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren +#endif + move.l a5,usp // usp setzen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),12(a7) // hier geht's weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg +sev_sup: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),d0 // sr holen + bset #13,d0 // war aus rt super + move.l d0,-(a5) // sr transferieren + swap d0 // vec -> lw +#else + move.w 8(a7),d0 // vector holen + move.w d0,-(a5) // ablegen + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren + bset #5,(a5) // war aus super +#endif + move.l a5,usp // usp setzen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),12(a7) // hier geht's weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg +//******************************************* +reset_vector: + move.w #0x2700,sr // disable interrupt + move.l #0x31415926,d0 + cmp.l 0x426,d0 // reset vector gültg? + beq std_exc_vec // ja-> + jmp ___BOOT_FLASH // sonst kaltstart +acess: + move.w #0x2700,sr // disable interrupt + move.l d0,-(sp) // ++ vr + move.w 4(sp),d0 + andi.l #0x0c03,d0 + cmpi.l #0x0401,d0 + beq access_mmu + cmpi.l #0x0402,d0 + beq access_mmu + cmpi.l #0x0802,d0 + beq access_mmu + cmpi.l #0x0c02,d0 + beq access_mmu + bra bus_error +access_mmu: + move.l MCF_MMU_MMUSR,d0 + btst #1,d0 + bne bus_error + move.l MCF_MMU_MMUAR,d0 + cmp.l #___Bas_base,d0 // max User RAM Bereich + bge bus_error // grösser -> bus error + bra _mmutr_miss +bus_error: + move.l (sp)+,d0 + bra std_exc_vec + +zero_divide: + move.w #0x2700,sr // disable interrupt + move.l a0,-(a7) + move.l d0,-(a7) + move.l 12(a7),a0 // pc + move.w (a0)+,d0 // befehlscode + btst #7,d0 // long? + beq zd_word // nein-> + addq.l #2,a0 +zd_word: + and.l 0x3f,d0 // ea ausmaskieren + cmp.w #0x08,d0 // -(ax) oder weniger + ble zd_end + addq.l #2,a0 + cmp.w #0x39,d0 // xxx.L + bne zd_nal + addq.l #2,a0 + bra zd_end +zd_nal: cmp.w #0x3c,d0 // immediate? + bne zd_end // nein-> + btst #7,d0 // long? + beq zd_end // nein + addq.l #2,a0 +zd_end: + move.l a0,12(a7) + move.l (a7)+,d0 + move.l (a7)+,a0 + rte + +linea: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +linef: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +format: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +//floating point +flpoow: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +irq1: + irq 0x64,1,0x02 +irq2: // hbl + // move.b #3,2(a7) + // rte + irq 0x68,2,0x04 +irq3: + irq 0x6c,3,0x08 +irq4: // vbl + irq 0x70,4,0x10 +irq5: // acp + irq 0x74,5,0x20 +irq6: // mfp + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern + lea MCF_EPORT_EPFR,a5 + move.b #0x40,(a5) // clear int6 +// test auf timeout screen adr change ------------------------------------------------------- + move.l _video_sbt,d0 + beq irq6_non_sca // wenn 0 nichts zu tun + sub.l #0x70000000,d0 // 14 sec abzählen + lea MCF_SLT0_SCNT,a5 + cmp.l (a5),d0 // aktuelle zeit weg + ble irq6_non_sca // noch nicht abgelaufen + lea -28(a7),a7 + movem.l d0-d4/a0-a1,(a7) // register sichern + clr.l d3 // beginn mit 0 + bsr cpusha // cache leeren + // eintrag suchen + irq6_next_sca: + move.l d3,d0 + move.l d0,MCF_MMU_MMUAR // addresse + move.l #0x106,d4 + move.l d4,MCF_MMU_MMUOR // suchen -> + nop + move.l MCF_MMU_MMUOR,d4 + clr.w d4 + swap d4 + move.l d4,MCF_MMU_MMUAR + mvz.w #0x10e,d4 + move.l d4,MCF_MMU_MMUOR // einträge holen aus mmu + nop + move.l MCF_MMU_MMUTR,d4 // ID holen + lsr.l #2,d4 // bit 9 bis 2 + cmp.w #sca_page_ID,d4 // ist screen change ID? + bne irq6_sca_pn // nein -> page keine screen area next +// eintrag ändern + add.l #std_mmutr,d0 + move.l d3,d1 // page 0? + beq irq6_sca_pn0 // ja -> + add.l #cb_mmudr,d1 // sonst page cb + bra irq6_sca_pn1c +irq6_sca_pn0: + add.l #wt_mmudr|MCF_MMU_MMUDR_LK,d1 // page wt and locked +irq6_sca_pn1c: + mvz.w #0x10b,d2 // MMU update + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setze tlb data only + nop +// page copy + move.l d3,a0 + add.l #0x60000000,a0 + move.l d3,a1 + move.l #0x10000,d4 // die ganze page +irq6_vcd0_loop: + move.l (a0)+,(a1)+ // page copy + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + subq.l #1,d4 + bne irq6_vcd0_loop + nop +irq6_sca_pn: + add.l #0x00100000,d3 // next + cmp.l #0x00d00000,d3 // ende? + blt irq6_next_sca // nein-> + + move.l #0x2000,d0 + move.l d0,_video_tlb // anfangszustand wieder herstellen + clr.l _video_sbt // zeit löschen + + movem.l (a7),d0-d4/a0-a1 // register zurück + lea 28(a7),a7 +irq6_non_sca: +// test auf acsi dma ----------------------------------------------------------------- + lea 0xfffffa0b,a5 + bset #7,-4(a5) // int ena + btst.b #7,(a5) // acsi dma int? + beq non_acsi_dma + bsr acsi_dma +non_acsi_dma: +// ---------------------------------------------------------------------------------- + tst.b (a5) + bne irq6_1 + tst.b 2(a5) + bne irq6_1 + movem.l (a7),d0/a5 + addq.l #8,a7 + rte +irq6_1: + lea MCF_GPIO_PODR_FEC1L,a5 + bclr.b #4,(a5) // led on + lea blinker(pc),a5 + addq.l #1,(a5) // +1 + move.l (a5),d0 + and.l #0x80,d0 + bne irq6_2 + lea MCF_GPIO_PODR_FEC1L,a5 + bset.b #4,(a5) // led off +irq6_2: +// test auf protect mode --------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne irq6_3 // ja-> +// ------------------------------------------- + move.l 0xF0020000,a5 // vector holen + add.l _rt_vbr,a5 // basis + move.l (a5),d0 // vector holen + move.l 4(a7),a5 // a5 zurück + move.l d0,4(a7) // vector eintragen + move.l (a7)+,d0 // d0 zurück + move #0x2600,sr + rts +irq6_3: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_sup6 // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr transferieren +#else + move.w 8(a7),-(a5) // vector transferieren + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren +#endif + move.l a5,usp // usp setzen + move.l 0xF0020000,a5 // vector holen: intack routine + add.l _rt_vbr,a5 // virtuelle VBR des Systems + move.l (a5),12(a7) // hier gehts weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + move.b #6,2(a7) // intmaske setzen + rte // und weg +sev_sup6: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec + bset #5,2(a5) // auf super setzen +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif + move.l a5,usp // usp setzen + move.l 0xF0020000,a5 // vector holen: intack routine + add.l _rt_vbr,a5 // virtuelle VBR des Systems + move.l (a5),12(a7) // hier gehts weiter + movem.l (a7),d0/a5 // register zurück + rts +blinker:.long 0 +/**************************************************/ +/* pseudo dma */ +/**************************************************/ +acsi_dma: // atari dma + move.l a1,-(a7) + move.l d1,-(a7) + + lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr + move.l #'DMA ',(a1) + move.l #'INT!',(a1) + + lea 0xf0020110,a5 // fifo daten +acsi_dma_start: + move.l -12(a5),a1 // dma adresse + move.l -8(a5),d0 // byt counter + ble acsi_dma_end + btst.b #0,-16(a5) // write? (dma modus reg) + bne acsi_dma_wl // ja-> +acsi_dma_rl: + tst.b -4(a5) // dma req? + bpl acsi_dma_fertig // nein-> + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + + moveq #'.',d1 + move.b d1,MCF_PSC0_PSCTB_8BIT + + sub.l #16,d0 // byt counter -16 + bpl acsi_dma_rl + bra acsi_dma_fertig +acsi_dma_wl: + tst.b -4(a5) // dma req? + bpl acsi_dma_fertig // nein-> + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + + moveq #'.',d1 + move.b d1,MCF_PSC0_PSCTB_8BIT + + sub.l #16,d0 // byt counter -16 + bpl acsi_dma_wl +acsi_dma_fertig: + move.l a1,-12(a5) // adresse zurück + move.l d0,-8(a5) // byt counter zurück +acsi_dma_end: + tst.b -4(a5) // dma req? + bmi acsi_dma_start // ja-> + lea 0xfffffa0b,a5 + bclr.b #7,4(a5) // clear int in service mfp + bclr.b #7,(a5) // clear int pending mfp 0xfffffa0b + + move.w #0x0d0a,d1 + move.w d1,MCF_PSC0_PSCTB_8BIT + + move.l (a7)+,d1 + move.l (a7)+,a1 + rts +/**************************************************/ +/* irq 7 = pseudo bus error */ +/**************************************************/ +irq7: + lea -12(sp),sp + movem.l d0/a0,(sp) + + move.l ___RAMBAR0+0x008,a0 // Real Access Error handler + move.l a0,8(sp) // This will be the return address for rts + + move.w 12(sp),d0 // Format/Vector word + andi.l #0xf000,d0 // Keep only the Format + ori.l #2*4,d0 // Simulate Vector #2, no Fault + move.w d0,12(sp) + + // TODO: Inside an interrupt handler, 16(sp) is the return address. + // For an Access Error, it should be the address of the fault instruction instead + + lea MCF_EPORT_EPFR,a0 + move.b #0x80,(a0) // clear int7 + move.l (sp)+,d0 + move.l (sp)+,a0 + rts // Forward to the Access Error handler + +/**************************************************/ +/* psc3 com PIC MCF */ +/**************************************************/ +psc3: + move.w #0x2700,sr // disable interrupt + lea -20(a7),a7 + movem.l d0-d2/a0/a3,(a7) + lea MCF_PSC3_PSCRB_8BIT,a3 + move.b (a3),d1 + cmp.b #2,d1 // anforderung rtc daten? + bne psc3_fertig + + lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr + move.l #'PIC ',(a0) + move.l #'INT ',(a0) + move.l #'RTC!',(a0) + move.l #0x0d0a,(a0) + + lea 0xffff8961,a0 + lea MCF_PSC3_PSCTB_8BIT,a3 + clr.l d1 + moveq #64,d2 + move.b #0x82,(a3) // header: rtcd mcf->pic +loop_sr2: + move.b d1,(a0) + move.b 2(a0),d0 + move.b d0,(a3) + addq.l #1,d1 + cmp.b d1,d2 + bne loop_sr2 +psc3_fertig: + movem.l (a7),d0-d2/a0/a3 // register zurück + lea 20(a7),a7 + RTE +/**************************************************/ +/* timer 0: video change later also others +/**************************************************/ +timer0: + move #0x2700,sr +// halt + lea -28(a7),a7 + movem.l d0-d4/a0-a1,(a7) + mvz.b 0xffff8201,d0 // löschen und high byt + cmp.w #2,d0 + blt video_chg_end + cmp.w #0xd0,d0 // normale addresse + blt sca_other // nein-> + lea MCF_SLT0_SCNT,a0 + move.l (a0),d4 + move.l d4,_video_sbt // time sichern +sca_other: + lsl.l #8,d0 + move.b 0xffff8203,d0 // mid byt + lsl.l #8,d0 + move.b 0xffff820d,d0 // low byt + move.l d0,d3 +video_chg_1page: +// test ob page schon gesetzt + moveq #20,d4 + move.l d0,d2 + lsr.l d4,d2 // neue page + move.l _video_tlb,d4 + bset.l d2,d4 // setzen als geändert + bne video_chg_2page // schon gesetzt gewesen? ja->weg + move.l d4,_video_tlb + bsr cpusha // cache leeren +// daten copieren +video_copy_data: + move.l d4,_video_tlb + and.l #0x00f00000,d0 + move.l d0,a0 + move.l a0,a1 + add.l #0x60000000,a1 + move.l #0x10000,d4 // die ganze page +video_copy_data_loop: + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + subq.l #1,d4 + bne video_copy_data_loop +// eintrag suchen + move.l d0,MCF_MMU_MMUAR // addresse + move.l #0x106,d4 + move.l d4,MCF_MMU_MMUOR // suchen -> schlägt neuen vor wenn keiner + nop + move.l MCF_MMU_MMUOR,d4 + clr.w d4 + swap d4 + move.l d4,MCF_MMU_MMUAR + move.l d0,d1 + add.l #MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 + add.l #0x60000000|wt_mmudr|MCF_MMU_MMUDR_LK,d1 + mvz.w #0x10b,d2 // MMU update + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen vidoe maped to 60xxx only data + nop +video_chg_2page: +// test ob evt. anschliessende page gesetzt werden muss + move.l d3,d0 + mvz.w 0xffff8210,d4 // byts pro zeile + mvz.w 0xffff82aa,d2 // zeilen ende + mvz.w 0xffff82a8,d1 // zeilenstart + sub.l d1,d2 // differenz = anzahl zeilen + mulu d2,d4 // maximal 480 zeilen + add.l d4,d0 // video grösse + cmp.l #0xe00000,d0 // maximale addresse + bge video_chg_end // wenn gleich oder grösser -> fertig + moveq #20,d4 + move.l d0,d2 + lsr.l d4,d2 // neue page + move.l _video_tlb,d4 + bset.l d2,d4 // setzen als geändert + beq video_copy_data // nein nochmal +video_chg_end: +// int pending löschen + lea MCF_GPT0_GMS,a0 + bclr.b #0,3(a0) + nop + bset.b #0,3(a0) + + movem.l (a7),d0-d4/a0-a1 + lea 28(a7),a7 +//-------------------------------------------------------------------------------------------------------- + RTE + diff --git a/BaS_GNU/sources/ii_add.h b/BaS_GNU/sources/ii_add.h new file mode 100644 index 0000000..bc23f63 --- /dev/null +++ b/BaS_GNU/sources/ii_add.h @@ -0,0 +1,581 @@ +//-------------------------------------------------------------------- +// add +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// add.b #im,dx +//-------------------------------------------------------------------- +addbir_macro:.macro + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + add.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add ea,dx +//-------------------------------------------------------------------- +adddd:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add ea,dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddd:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add (ea),dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +adddda:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add (ay)+,dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddai:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add -(ay),dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d16(ay),dx +//-------------------------------------------------------------------- +addd16ad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d8(ay,dy),dx +//-------------------------------------------------------------------- +addd8ad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add xxx.w,dx +//-------------------------------------------------------------------- +addxwd:.macro +#ifdef halten_add + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add xxx.l,dx +//-------------------------------------------------------------------- +addxld:.macro +#ifdef halten_add + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d16(pc),dx +//-------------------------------------------------------------------- +addd16pcd:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d8(pc,dy),dx +//-------------------------------------------------------------------- +addd8pcd:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// add dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // add dx,(ay) (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addeda:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,(ay)+ (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addedai:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,(ay)+ +//-------------------------------------------------------------------- +addedaid:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,-(ay) +//-------------------------------------------------------------------- +addedad:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,-(ay) +//-------------------------------------------------------------------- +addedadd:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,d16(ay) +//-------------------------------------------------------------------- +adde16ad:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add.w d8(ay,dy),dx +//-------------------------------------------------------------------- +adde8ad:.macro +#ifdef halten_add + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,xxx.w +//-------------------------------------------------------------------- +addxwe:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,xxx.l +//-------------------------------------------------------------------- +addxle:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// // adda.w ea,ax (ea = dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addaw:.macro +#ifdef halten_add + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + mvs.w \1,d0 + adda.l d0,\2 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// add.w ea,usp +//-------------------------------------------------------------------- +addawa7:.macro +#ifdef halten_add + halt +#endif + mvs.w \1,d0 + move.l usp,a1 + add.l d0,a1 + move.l a1,usp + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w ea,usp (ea = dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addawu:.macro +#ifdef halten_add + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + move.l a7,_a7_save + move.l usp,a7 + move.l \1,d0 + adda.l d0,\2 + move.l a7,usp + move.l _a7_save,a7 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// // adda.w ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addawua7:.macro + addawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // adda.w d16(ay),ax +//-------------------------------------------------------------------- +addawd16a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + adda.l d0,a1 + mvs.w (a1),d0 + move.l \2,a1 + add.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d8(ay,dy),ax +//-------------------------------------------------------------------- +addawd8a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + add.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w xxx.w,ax +//-------------------------------------------------------------------- +addawxwax:.macro +#ifdef halten_add + halt +#endif + move.w \1,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w xxx.l,ax +//-------------------------------------------------------------------- +addawxlax:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d16(pc),ax +//-------------------------------------------------------------------- +addawd16pcax:.macro +#ifdef halten_add + halt +#endif + move.w \1,a1 + adda.l a0,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d8(pc,dy),ax +//-------------------------------------------------------------------- +addawd8pcax:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w #im,ax +//-------------------------------------------------------------------- +addawim:.macro +#ifdef halten_add + halt +#endif + mvs.w \1,d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.l d8(ay,dy),ax +//-------------------------------------------------------------------- +addald8a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.l d8(pc,dy),ax +//-------------------------------------------------------------------- +addakd8pcax:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//***************************************************************************************** +// addx +//***************************************************************************************** +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +adddx:.macro +#ifdef halten_add + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + mvs.\3 \2,d0 + mvs.\3 \1,d1 + addx.l d0,d1 + set_cc0 + move.\3 d1,\1 + ii_end + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +adddax:.macro +#ifdef halten_add + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + move.l \1,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d0 +.endif + move.l \2,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d1 +.endif + addx.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_and.h b/BaS_GNU/sources/ii_and.h new file mode 100644 index 0000000..f74afde --- /dev/null +++ b/BaS_GNU/sources/ii_and.h @@ -0,0 +1,441 @@ +//-------------------------------------------------------------------- +// and +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// and.b #im,dx +//-------------------------------------------------------------------- +andbir_macro:.macro + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + and.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea,dx +//-------------------------------------------------------------------- +anddd:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +andddd:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and (ea)->dy,dx +//-------------------------------------------------------------------- +anddda:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +andddai:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea->ay,-(ay),dx +//-------------------------------------------------------------------- +andddad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d16(ay),dx +//-------------------------------------------------------------------- +andd16ad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d8(ay,dy),dx +//-------------------------------------------------------------------- +andd8ad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and xxx.w,dx +//-------------------------------------------------------------------- +andxwd:.macro +#ifdef halten_and + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and xxx.l,dx +//-------------------------------------------------------------------- +andxld:.macro +#ifdef halten_and + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d16(pc),dx +//-------------------------------------------------------------------- +andd16pcd:.macro +#ifdef halten_and + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d8(pc,dy),dx +//-------------------------------------------------------------------- +andd8pcd:.macro +#ifdef halten_and + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// and dx,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // and dx,(ea)->dy +//-------------------------------------------------------------------- +andeda:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +andedai:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +andedaid:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +andedad:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +andedadd:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,d16(ay) +//-------------------------------------------------------------------- +ande16ad:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and.w dx,d8(ay,dy) +//-------------------------------------------------------------------- +ande8ad:.macro +#ifdef halten_and + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,xxx.w +//-------------------------------------------------------------------- +andxwe:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,xxx.l +//-------------------------------------------------------------------- +andxle:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // anda.w ea,ax +//-------------------------------------------------------------------- +andaw:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// and.w ea,usp +//-------------------------------------------------------------------- +andawa7:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w usp?,ax +//-------------------------------------------------------------------- +andawu:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w usp?,usp +//-------------------------------------------------------------------- +andawua7:.macro + andawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // anda.w d16(ay),ax +//-------------------------------------------------------------------- +andawd16a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d8(ay,dy),ax +//-------------------------------------------------------------------- +andawd8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w xxx.w,ax +//-------------------------------------------------------------------- +andawxwax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w xxx.l,ax +//-------------------------------------------------------------------- +andawxlax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d16(pc),ax +//-------------------------------------------------------------------- +andawd16pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d8(pc,dy),ax +//-------------------------------------------------------------------- +andawd8pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w #im,ax +//-------------------------------------------------------------------- +andawim:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.l d8(ay,dy),ax +//-------------------------------------------------------------------- +andald8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.l d8(pc,dy),ax +//-------------------------------------------------------------------- +andald8pcax:.macro + jmp ii_error + .endm; +//***************************************************************************************** +// spezial addx subx etc. +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +anddx:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +anddax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_dbcc.h b/BaS_GNU/sources/ii_dbcc.h new file mode 100644 index 0000000..652cdbe --- /dev/null +++ b/BaS_GNU/sources/ii_dbcc.h @@ -0,0 +1,117 @@ +//-------------------------------------------------------------------- +// dbcc,trapcc +//-------------------------------------------------------------------- +.text +ii_lset_dbcc:.macro +// dbra + ii_lset_opeau 51,c + ii_lset_opeau 52,c + ii_lset_opeau 53,c + ii_lset_opeau 54,c + ii_lset_opeau 55,c + ii_lset_opeau 56,c + ii_lset_opeau 57,c + ii_lset_opeau 58,c + ii_lset_opeau 59,c + ii_lset_opeau 5a,c + ii_lset_opeau 5b,c + ii_lset_opeau 5c,c + ii_lset_opeau 5d,c + ii_lset_opeau 5e,c + ii_lset_opeau 5f,c +.endm + +ii_dbcc_func:.macro +ii_0x51c8: + dbra_macro d0_off+2(a7) +ii_0x51c9: + dbra_macro d1_off+2(a7) +ii_0x51ca: + dbra_macro d2 +ii_0x51cb: + dbra_macro d3 +ii_0x51cc: + dbra_macro d4 +ii_0x51cd: + dbra_macro d5 +ii_0x51ce: + dbra_macro d6 +ii_0x51cf: + dbra_macro d7 +//--------------------------------------------------------------------------------------------- +// dbcc dx +//--------------------------------------------------------------------------------------------- + ii_dbcc 2,hi + ii_dbcc 3,ls + ii_dbcc 4,cc + ii_dbcc 5,cs + ii_dbcc 6,ne + ii_dbcc 7,eq + ii_dbcc 8,vc + ii_dbcc 9,vs + ii_dbcc a,pl + ii_dbcc b,mi + ii_dbcc c,ge + ii_dbcc d,lt + ii_dbcc e,gt + ii_dbcc f,le +.endm +//--------------------------------------------------------------------------------------------- +// dbra dx +//--------------------------------------------------------------------------------------------- +dbra_macro:.macro +#ifdef halten_dbcc + halt +#endif + mvz.w \1,d1 // dx holen + subq.l #1,d1 // dx-1 + bcc dbra\@ // bra if plus? + addq.l #2,a0 // offset überspringen + move.w d1,\1 // dx sichern + ii_end +dbra\@: + move.w (a0),a1 // offset (wird auf long erweitert) + add.l a1,a0 // dazuadieren + move.w d1,\1 // dx sichern + ii_end +.endm +//--------------------------------------------------------------------------------------------- +// dbcc dx +//--------------------------------------------------------------------------------------------- +dbcc_macro:.macro +#ifdef halten_dbcc + halt +#endif + b\2 dbncc\@ + mvz.w \1,d1 // dx holen + subq.l #1,d1 // dx-1 + bcc dbcc\@ // bra if plus? +dbncc\@: + addq.l #2,a0 // offset überspringen + move.w d1,\1 // dx sichern + ii_end +dbcc\@: + move.w (a0),a1 // offset (wird auf long erweitert) + add.l a1,a0 // dazuadieren + move.w d1,\1 // dx sichern + ii_end +.endm +//db +ii_dbcc:.macro +ii_0x5\1c8: + dbcc_macro d0_off+2(a7),\2 +ii_0x5\1c9: + dbcc_macro d1_off+2(a7),\2 +ii_0x5\1ca: + dbcc_macro d2,\2 +ii_0x5\1cb: + dbcc_macro d3,\2 +ii_0x5\1cc: + dbcc_macro d4,\2 +ii_0x5\1cd: + dbcc_macro d5,\2 +ii_0x5\1ce: + dbcc_macro d6,\2 +ii_0x5\1cf: + dbcc_macro d7,\2 +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_ewf.h b/BaS_GNU/sources/ii_ewf.h new file mode 100644 index 0000000..34d2483 --- /dev/null +++ b/BaS_GNU/sources/ii_ewf.h @@ -0,0 +1,181 @@ +//-------------------------------------------------------------------- +// extension word format missing +//-------------------------------------------------------------------- +.text +ii_ewf_lset:.macro +// pea + ii_lset_opeag 48,7 + ii_lset 0x487b +// jmp + ii_lset_opeag 4e,f + ii_lset 0x4efb +// jsr + ii_lset_opeag 4e,b + ii_lset 0x4ebb +// tas + ii_lset_opeag 4a,f + ii_lset 0x4ebb +// tst.b + ii_lset_opeag 4a,3 + ii_lset 0x4ebb +// tst.w + ii_lset_opeag 4a,7 + ii_lset 0x4ebb +// tst.l + ii_lset_opeag 4a,b + ii_lset 0x4ebb +// clr.b + ii_lset_opeag 42,3 + ii_lset 0x423b +// clr.w + ii_lset_opeag 42,7 + ii_lset 0x423b +// clr.l + ii_lset_opeag 42,b + ii_lset 0x423b +.endm +//--------------------------------------------------------------------------------------------- +ii_ewf_func:.macro + ewf_func_macro pea,487 + ewf_func_macro jmp,4ef + ewf_func_macro jsr,4eb + ewf_func_macro tas,4af + ewf_func_macro tstb,4a3 + ewf_func_macro tstw,4a7 + ewf_func_macro tstl,4ab + ewf_func_macro clrb,423 + ewf_func_macro clrw,427 + ewf_func_macro clrl,42b +.endm +//--------------------------------------------------------------------------------------------- +pea_macro:.macro + jsr ewf + move.l (a1),d0 + move.l usp,a1 + move.l d0,-(a1) + move.l a1,usp + ii_end +.endm + +jmp_macro:.macro + jsr ewf + move.l a1,a0 + ii_end +.endm + +jsr_macro:.macro + jsr ewf + move.l a1,d0 + move.l usp,a1 + move.l a0,-(a1) + move.l a1,usp + move.l d0,a0 + ii_end +.endm + +tas_macro:.macro + jsr ewf + tas (a1) + set_cc0 + ii_end +.endm + +tstb_macro:.macro + jsr ewf + tst.b (a1) + set_cc0 + ii_end +.endm + +tstw_macro:.macro + jsr ewf + tst.w (a1) + set_cc0 + ii_end +.endm + +tstl_macro:.macro + jsr ewf + tst.l (a1) + set_cc0 + ii_end +.endm + +clrb_macro:.macro + jsr ewf + clr.b (a1) + set_cc0 + ii_end +.endm + +clrw_macro:.macro + jsr ewf + clr.w (a1) + set_cc0 + ii_end +.endm + +clrl_macro:.macro + jsr ewf + clr.l (a1) + set_cc0 + ii_end +.endm +//-------------------------------------------------------------------- +ewf_func_macro:.macro //1=art 2=code +ii_0x\20: +#ifdef halten_ewf + halt +#endif + move.l a0_off(a7),a1 + \1_macro +ii_0x\21: +#ifdef halten_ewf + halt +#endif + move.l a1_off(a7),a1 + \1_macro +ii_0x\22: +#ifdef halten_ewf + halt +#endif + move.l a2,a1 + \1_macro +ii_0x\23: +#ifdef halten_ewf + halt +#endif + move.l a3,a1 + \1_macro +ii_0x\24: +#ifdef halten_ewf + halt +#endif + move.l a4,a1 + \1_macro +ii_0x\25: +#ifdef halten_ewf + halt +#endif + move.l a5,a1 + \1_macro +ii_0x\26: +#ifdef halten_ewf + halt +#endif + move.l a6,a1 + \1_macro +ii_0x\27: +#ifdef halten_ewf + halt +#endif + move.l usp,a1 + \1_macro +ii_0x\2b: +#ifdef halten_ewf + halt +#endif + move.l a0,a1 + \1_macro +.endm + diff --git a/BaS_GNU/sources/ii_exg.h b/BaS_GNU/sources/ii_exg.h new file mode 100644 index 0000000..a0544af --- /dev/null +++ b/BaS_GNU/sources/ii_exg.h @@ -0,0 +1,120 @@ +//-------------------------------------------------------------------- +// exg +//-------------------------------------------------------------------- +.text +ii_exg_lset:.macro +/* ii_lset_dxu c,40 //dx,d0 + ii_lset_dxu c,41 //dx,d1 + ii_lset_dxu c,42 //dx,d2 + ii_lset_dxu c,43 //dx,d3 + ii_lset_dxu c,44 //dx,d4 + ii_lset_dxu c,45 //dx,d5 + ii_lset_dxu c,46 //dx,d6 + ii_lset_dxu c,47 //dx,d7 + ii_lset_dxu c,48 //ax,a0 + ii_lset_dxu c,49 //ax,a1 + ii_lset_dxu c,4a //ax,a2 + ii_lset_dxu c,4b //ax,a3 + ii_lset_dxu c,4c //ax,a4 + ii_lset_dxu c,4d //ax,a5 + ii_lset_dxu c,4e //ax,a6 + ii_lset_dxu c,4f //ax,a7 */ -->setting by "and" + ii_lset_dxu c,88 //dx,a0 + ii_lset_dxu c,89 //dx,a1 + ii_lset_dxu c,8a //dx,a2 + ii_lset_dxu c,8b //dx,a3 + ii_lset_dxu c,8c //dx,a4 + ii_lset_dxu c,8d //dx,a5 + ii_lset_dxu c,8e //dx,a6 + ii_lset_dxu c,8f //dx,a7 +.endm +//--------------------------------------------------------------------------------------------- +ii_exg_func:.macro +// exg dx,dy + ii_exg_dx_dx 14,d0_off(a7) + ii_exg_dx_dx 34,d1_off(a7) + ii_exg_dx_dx 54,d2 + ii_exg_dx_dx 74,d3 + ii_exg_dx_dx 94,d4 + ii_exg_dx_dx b4,d5 + ii_exg_dx_dx d4,d6 + ii_exg_dx_dx f4,d7 +// exg ax,ay + ii_exg_to_ax 14,a0_off(a7) + ii_exg_to_ax 34,a1_off(a7) + ii_exg_to_ax 54,a2 + ii_exg_to_ax 74,a3 + ii_exg_to_ax 94,a4 + ii_exg_to_ax b4,a5 + ii_exg_to_ax d4,a6 + ii_exg_to_ax f4,usp +// exg dx,ay + ii_exg_to_ax 18,d0_off(a7) + ii_exg_to_ax 38,d1_off(a7) + ii_exg_to_ax 58,d2 + ii_exg_to_ax 78,d3 + ii_exg_to_ax 98,d4 + ii_exg_to_ax b8,d5 + ii_exg_to_ax d8,d6 + ii_exg_to_ax f8,d7 +.endm +//--------------------------------------------------------------------------------------------- +exg_macro:.macro +#ifdef halten_exg + halt +#endif + move.l \1,a1 +.ifc \2,usp + move.l a1,d0 + move.l \2,a1 + move.l a1,\1 + move.l d0,a1 +.else + .ifc \1,usp + move.l a1,d0 + move.l \2,a1 + move.l a1,\1 + move.l d0,a1 + .else + move.l \2,\1 + .endif +.endif + move.l a1,\2 + ii_end +.endm +ii_exg_dx_dx:.macro +ii_0xc\10: + exg_macro \2,d0_off(a7) +ii_0xc\11: + exg_macro \2,d1_off(a7) +ii_0xc\12: + exg_macro \2,d2 +ii_0xc\13: + exg_macro \2,d3 +ii_0xc\14: + exg_macro \2,d4 +ii_0xc\15: + exg_macro \2,d5 +ii_0xc\16: + exg_macro \2,d6 +ii_0xc\17: + exg_macro \2,d7 +.endm +ii_exg_to_ax:.macro +ii_0xc\18: + exg_macro \2,a0_off(a7) +ii_0xc\19: + exg_macro \2,a1_off(a7) +ii_0xc\1a: + exg_macro \2,a2 +ii_0xc\1b: + exg_macro \2,a3 +ii_0xc\1c: + exg_macro \2,a4 +ii_0xc\1d: + exg_macro \2,a5 +ii_0xc\1e: + exg_macro \2,a6 +ii_0xc\1f: + exg_macro \2,usp +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_func.h b/BaS_GNU/sources/ii_func.h new file mode 100644 index 0000000..f545f47 --- /dev/null +++ b/BaS_GNU/sources/ii_func.h @@ -0,0 +1,945 @@ +//-------------------------------------------------------------------- +// functionen macros +//-------------------------------------------------------------------- +ii_lset_func:.macro +/******************************************************/ +// byt +/******************************************************/ +// func.b dy,dx + ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,01 + ii_lset_dx \1,02 + ii_lset_dx \1,03 + ii_lset_dx \1,04 + ii_lset_dx \1,05 + ii_lset_dx \1,06 + ii_lset_dx \1,07 +// func.b ax,dx + ii_lset_dxu \1,08 + ii_lset_dxu \1,09 + ii_lset_dxu \1,0a + ii_lset_dxu \1,0b + ii_lset_dxu \1,0c + ii_lset_dxu \1,0d + ii_lset_dxu \1,0e + ii_lset_dxu \1,0f +// func.b (ax),dx + ii_lset_dx \1,10 + ii_lset_dx \1,11 + ii_lset_dx \1,12 + ii_lset_dx \1,13 + ii_lset_dx \1,14 + ii_lset_dx \1,15 + ii_lset_dx \1,16 + ii_lset_dx \1,17 +// func.b (ax)+,dx + ii_lset_dx \1,18 + ii_lset_dx \1,19 + ii_lset_dx \1,1a + ii_lset_dx \1,1b + ii_lset_dx \1,1c + ii_lset_dx \1,1d + ii_lset_dx \1,1e + ii_lset_dx \1,1f +// func.b -(ax),dx + ii_lset_dx \1,20 + ii_lset_dx \1,21 + ii_lset_dx \1,22 + ii_lset_dx \1,23 + ii_lset_dx \1,24 + ii_lset_dx \1,25 + ii_lset_dx \1,26 + ii_lset_dx \1,27 +// func.b d16(ax),dx + ii_lset_dx \1,28 + ii_lset_dx \1,29 + ii_lset_dx \1,2a + ii_lset_dx \1,2b + ii_lset_dx \1,2c + ii_lset_dx \1,2d + ii_lset_dx \1,2e + ii_lset_dx \1,2f +// func.b dd8(ax,dy),dx + ii_lset_dx \1,30 + ii_lset_dx \1,31 + ii_lset_dx \1,32 + ii_lset_dx \1,33 + ii_lset_dx \1,34 + ii_lset_dx \1,35 + ii_lset_dx \1,36 + ii_lset_dx \1,37 +// func.b xxx.w,dx + ii_lset_dx \1,38 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b xxx.l,dx + ii_lset_dx \1,39 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b d16(pc),dx + ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b d8(pc,dy),dx + ii_lset_dxg \1,3b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b #im,dx + ii_lset_dxg \1,3c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// word +/******************************************************/ +// func.w dy,dx + ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,41 + ii_lset_dx \1,42 + ii_lset_dx \1,43 + ii_lset_dx \1,44 + ii_lset_dx \1,45 + ii_lset_dx \1,46 + ii_lset_dx \1,47 +// func.w ax,dx + ii_lset_dx \1,48 + ii_lset_dx \1,49 + ii_lset_dx \1,4a + ii_lset_dx \1,4b + ii_lset_dx \1,4c + ii_lset_dx \1,4d + ii_lset_dx \1,4e + ii_lset_dx \1,4f +// func.w (ax),dx + ii_lset_dx \1,50 + ii_lset_dx \1,51 + ii_lset_dx \1,52 + ii_lset_dx \1,53 + ii_lset_dx \1,54 + ii_lset_dx \1,55 + ii_lset_dx \1,56 + ii_lset_dx \1,57 +// func.w (ax)+,dx + ii_lset_dx \1,58 + ii_lset_dx \1,59 + ii_lset_dx \1,5a + ii_lset_dx \1,5b + ii_lset_dx \1,5c + ii_lset_dx \1,5d + ii_lset_dx \1,5e + ii_lset_dx \1,5f +// func.w -(ax),dx + ii_lset_dx \1,60 + ii_lset_dx \1,61 + ii_lset_dx \1,62 + ii_lset_dx \1,63 + ii_lset_dx \1,64 + ii_lset_dx \1,65 + ii_lset_dx \1,66 + ii_lset_dx \1,67 +// func.w d16(ax),dx + ii_lset_dx \1,68 + ii_lset_dx \1,69 + ii_lset_dx \1,6a + ii_lset_dx \1,6b + ii_lset_dx \1,6c + ii_lset_dx \1,6d + ii_lset_dx \1,6e + ii_lset_dx \1,6f +// func.w d8(ax,dy),dx + ii_lset_dx \1,70 + ii_lset_dx \1,71 + ii_lset_dx \1,72 + ii_lset_dx \1,73 + ii_lset_dx \1,74 + ii_lset_dx \1,75 + ii_lset_dx \1,76 + ii_lset_dx \1,77 +// func.w xxx.w,dx + ii_lset_dx \1,78 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w xxx.l,dx + ii_lset_dx \1,79 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w d16(pc),dx + ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w d8(pc,dy),dx + ii_lset_dxg \1,7b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w #im,dx + ii_lset_dxg \1,7c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// long +/******************************************************/ +// func.l ax,dx -> -(ay),-(ax) + ii_lset_dxu \1,c8 + ii_lset_dxu \1,c9 + ii_lset_dxu \1,ca + ii_lset_dxu \1,cb + ii_lset_dxu \1,cc + ii_lset_dxu \1,cd + ii_lset_dxu \1,ce + ii_lset_dxu \1,cf +// func.w d8(ax,dy),dx + ii_lset_dx \1,b0 + ii_lset_dx \1,b1 + ii_lset_dx \1,b2 + ii_lset_dx \1,b3 + ii_lset_dx \1,b4 + ii_lset_dx \1,b5 + ii_lset_dx \1,b6 + ii_lset_dx \1,b7 +// func.l d8(pc,dy),dx + ii_lset_dxg \1,bb // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// adress register +/******************************************************/ +//func.w dy,ax + ii_lset_dxg \1,c0 + ii_lset_dxg \1,c1 + ii_lset_dxg \1,c2 + ii_lset_dxg \1,c3 + ii_lset_dxg \1,c4 + ii_lset_dxg \1,c5 + ii_lset_dxg \1,c6 + ii_lset_dxg \1,c7 +//func.w ay,ax + ii_lset_dxg \1,c8 + ii_lset_dxg \1,c9 + ii_lset_dxg \1,ca + ii_lset_dxg \1,cb + ii_lset_dxg \1,cc + ii_lset_dxg \1,cd + ii_lset_dxg \1,ce + ii_lset_dxg \1,cf +//func.w (ay),ax + ii_lset_dxg \1,d0 + ii_lset_dxg \1,d1 + ii_lset_dxg \1,d2 + ii_lset_dxg \1,d3 + ii_lset_dxg \1,d4 + ii_lset_dxg \1,d5 + ii_lset_dxg \1,d6 + ii_lset_dxg \1,d7 +//func.w (ay)+,ax + ii_lset_dxg \1,d8 + ii_lset_dxg \1,d9 + ii_lset_dxg \1,da + ii_lset_dxg \1,db + ii_lset_dxg \1,dc + ii_lset_dxg \1,dd + ii_lset_dxg \1,de + ii_lset_dxg \1,df +//func.w -(ay),ax + ii_lset_dxg \1,e0 + ii_lset_dxg \1,e1 + ii_lset_dxg \1,e2 + ii_lset_dxg \1,e3 + ii_lset_dxg \1,e4 + ii_lset_dxg \1,e5 + ii_lset_dxg \1,e6 + ii_lset_dxg \1,e7 +//func.w d16(ay),ax + ii_lset_dxg \1,e8 + ii_lset_dxg \1,e9 + ii_lset_dxg \1,ea + ii_lset_dxg \1,eb + ii_lset_dxg \1,ec + ii_lset_dxg \1,ed + ii_lset_dxg \1,ee + ii_lset_dxg \1,ef +//func.w d8(ay,dy),ax + ii_lset_dxg \1,f0 + ii_lset_dxg \1,f1 + ii_lset_dxg \1,f2 + ii_lset_dxg \1,f3 + ii_lset_dxg \1,f4 + ii_lset_dxg \1,f5 + ii_lset_dxg \1,f6 + ii_lset_dxg \1,f7 +// func.w xxx.w,ax + ii_lset_dxg \1,f8 +// func.w xxx.l,ax + ii_lset_dxg \1,f9 +// func.w d16(pc),ax + ii_lset_dxg \1,fa +// func.w d8(pc,dy),ax + ii_lset_dxg \1,fb +// func.w #im,ax + ii_lset_dxg \1,fc +//-------------------------------------------------------------------- +// ende + .endm; +/*****************************************************************************************/ +ii_func:.macro +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.b ds,dx +//-------------------------------------------------------------------- + funcbeadx \1,00,\2dd,d0_off+3(a7) + funcbeadx \1,01,\2dd,d1_off+3(a7) + funcbeadx \1,02,\2dd,d2 + funcbeadx \1,03,\2dd,d3 + funcbeadx \1,04,\2dd,d4 + funcbeadx \1,05,\2dd,d5 + funcbeadx \1,06,\2dd,d6 + funcbeadx \1,07,\2dd,d7 +//-------------------------------------------------------------------- +// func.b (ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,10,\2dda,a0_off(a7) + funcbeadx \1,11,\2dda,a1_off(a7) + funcbeadx \1,12,\2dd,(a2) + funcbeadx \1,13,\2dd,(a3) + funcbeadx \1,14,\2dd,(a4) + funcbeadx \1,15,\2dd,(a5) + funcbeadx \1,16,\2dd,(a6) + funcbeadx \1,17,\2dda,usp +//-------------------------------------------------------------------- +// func.b (ax)+,dx +//-------------------------------------------------------------------- + funcbeadx \1,18,\2ddai,a0_off(a7) + funcbeadx \1,19,\2ddai,a1_off(a7) + funcbeadx \1,1a,\2dd,(a2)+ + funcbeadx \1,1b,\2dd,(a3)+ + funcbeadx \1,1c,\2dd,(a4)+ + funcbeadx \1,1d,\2dd,(a5)+ + funcbeadx \1,1e,\2dd,(a6)+ + funcbeadx \1,1f,\2ddai,usp +//-------------------------------------------------------------------- +// func.b -(ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,20,\2ddad,a0_off(a7) + funcbeadx \1,21,\2ddad,a1_off(a7) + funcbeadx \1,22,\2dd,-(a2) + funcbeadx \1,23,\2dd,-(a3) + funcbeadx \1,24,\2dd,-(a4) + funcbeadx \1,25,\2dd,-(a5) + funcbeadx \1,26,\2dd,-(a6) + funcbeadx \1,27,\2ddad,usp +//-------------------------------------------------------------------- +// func.b d16(ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,28,\2d16ad,a0_off(a7) + funcbeadx \1,29,\2d16ad,a1_off(a7) + funcbeadx \1,2a,\2d16ad,a2 + funcbeadx \1,2b,\2d16ad,a3 + funcbeadx \1,2c,\2d16ad,a4 + funcbeadx \1,2d,\2d16ad,a5 + funcbeadx \1,2e,\2d16ad,a6 + funcbeadx \1,2f,\2d16ad,usp +//-------------------------------------------------------------------- +// func.b d8(ax,dy),dx +//-------------------------------------------------------------------- + funcbeadx \1,30,\2d8ad,a0_off(a7) + funcbeadx \1,31,\2d8ad,a1_off(a7) + funcbeadx \1,32,\2d8ad,a2 + funcbeadx \1,33,\2d8ad,a3 + funcbeadx \1,34,\2d8ad,a4 + funcbeadx \1,35,\2d8ad,a5 + funcbeadx \1,36,\2d8ad,a6 + funcbeadx \1,37,\2d8ad,usp +//-------------------------------------------------------------------- +// func.b xxx.w,dx +//-------------------------------------------------------------------- + funcbeadx \1,38,\2xwd,(a0)+ +//-------------------------------------------------------------------- +// func.b xxx.w,dx +//-------------------------------------------------------------------- + funcbeadx \1,39,\2xld,(a0)+ +//-------------------------------------------------------------------- +// func.b d16(pc),dx +//-------------------------------------------------------------------- + funcbeadx \1,3a,\2d16pcd,(a0)+ +//-------------------------------------------------------------------- +// func.b d8(pc,dy),dx +//-------------------------------------------------------------------- + funcbeadx \1,3b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.b #im,dx +//-------------------------------------------------------------------- + funcbeadx \1,3c,\2bir_macro,(a0)+ +//-------------------------------------------------------------------- +// func.b dy,ea +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.b dx,dd -> addx subx etc. src und dest vertauscht! +//-------------------------------------------------------------------- + funcbdxea \1,00,\2dx,d0_off+3(a7) + funcbdxea \1,01,\2dx,d1_off+3(a7) + funcbdxea \1,02,\2dx,d2 + funcbdxea \1,03,\2dx,d3 + funcbdxea \1,04,\2dx,d4 + funcbdxea \1,05,\2dx,d5 + funcbdxea \1,06,\2dx,d6 + funcbdxea \1,07,\2dx,d7 +//-------------------------------------------------------------------- +// func.b -(ax),-(ay) addx subx etc. src und dest vertauscht! +//-------------------------------------------------------------------- + funcaxay \1,08,\2dax,a0_off(a7),b + funcaxay \1,09,\2dax,a1_off(a7).b + funcaxay \1,0a,\2dax,a2,b + funcaxay \1,0b,\2dax,a3,b + funcaxay \1,0c,\2dax,a4,b + funcaxay \1,0d,\2dax,a5,b + funcaxay \1,0e,\2dax,a6,b + funcaxay \1,0f,\2dax,usp,b +//-------------------------------------------------------------------- +// func.b dy,(ax) +//-------------------------------------------------------------------- + funcbdxea \1,10,\2eda,a0_off(a7) + funcbdxea \1,11,\2eda,a1_off(a7) + funcbdxea \1,12,\2dd,(a2) + funcbdxea \1,13,\2dd,(a3) + funcbdxea \1,14,\2dd,(a4) + funcbdxea \1,15,\2dd,(a5) + funcbdxea \1,16,\2dd,(a6) + funcbdxea \1,17,\2eda,usp +//-------------------------------------------------------------------- +// func.b dy,(ax)+ +//-------------------------------------------------------------------- + funcbdxea \1,18,\2edai,a0_off(a7) + funcbdxea \1,19,\2edai,a1_off(a7) + funcbdxea \1,1a,\2edaid,(a2) + funcbdxea \1,1b,\2edaid,(a3) + funcbdxea \1,1c,\2edaid,(a4) + funcbdxea \1,1d,\2edaid,(a5) + funcbdxea \1,1e,\2edaid,(a6) + funcbdxea \1,1f,\2edai,usp +//-------------------------------------------------------------------- +// func.b dy,-(ax) +//-------------------------------------------------------------------- + funcbdxea \1,20,\2edad,a0_off(a7) + funcbdxea \1,21,\2edad,a1_off(a7) + funcbdxea \1,22,\2edadd,(a2) + funcbdxea \1,23,\2edadd,(a3) + funcbdxea \1,24,\2edadd,(a4) + funcbdxea \1,25,\2edadd,(a5) + funcbdxea \1,26,\2edadd,(a6) + funcbdxea \1,27,\2edad,usp +//-------------------------------------------------------------------- +// func.b dy,d16(ax) +//-------------------------------------------------------------------- + funcbdxea \1,28,\2e16ad,a0_off(a7) + funcbdxea \1,29,\2e16ad,a1_off(a7) + funcbdxea \1,2a,\2e16ad,a2 + funcbdxea \1,2b,\2e16ad,a3 + funcbdxea \1,2c,\2e16ad,a4 + funcbdxea \1,2d,\2e16ad,a5 + funcbdxea \1,2e,\2e16ad,a6 + funcbdxea \1,2f,\2e16ad,usp +//-------------------------------------------------------------------- +// func.b dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcbdxea \1,30,\2e8ad,a0_off(a7) + funcbdxea \1,31,\2e8ad,a1_off(a7) + funcbdxea \1,32,\2e8ad,a2 + funcbdxea \1,33,\2e8ad,a3 + funcbdxea \1,34,\2e8ad,a4 + funcbdxea \1,35,\2e8ad,a5 + funcbdxea \1,36,\2e8ad,a6 + funcbdxea \1,37,\2e8ad,usp +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,38,\2xwe,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,39,\2xld,(a0)+ +/*****************************************************************************************/ +// word +/*****************************************************************************************/ +// func.w ds,dx +//-------------------------------------------------------------------- + funcweadx \1,40,\2dd,d0_off+2(a7) + funcweadx \1,41,\2dd,d1_off+2(a7) + funcweadx \1,42,\2dd,d2 + funcweadx \1,43,\2dd,d3 + funcweadx \1,44,\2dd,d4 + funcweadx \1,45,\2dd,d5 + funcweadx \1,46,\2dd,d6 + funcweadx \1,47,\2dd,d7 +//-------------------------------------------------------------------- +// func.w ax,dx +//-------------------------------------------------------------------- + funcweadx \1,48,\2dd,a0_off+2(a7) + funcweadx \1,49,\2dd,a1_off+2(a7) + funcweadx \1,4a,\2dd,a2 + funcweadx \1,4b,\2dd,a3 + funcweadx \1,4c,\2dd,a4 + funcweadx \1,4d,\2dd,a5 + funcweadx \1,4e,\2dd,a6 + funcweadx \1,4f,\2ddd,usp +//-------------------------------------------------------------------- +// func.w (ax),dx +//-------------------------------------------------------------------- + funcweadx \1,50,\2dda,a0_off(a7) + funcweadx \1,51,\2dda,a1_off(a7) + funcweadx \1,52,\2dd,(a2) + funcweadx \1,53,\2dd,(a3) + funcweadx \1,54,\2dd,(a4) + funcweadx \1,55,\2dd,(a5) + funcweadx \1,56,\2dd,(a6) + funcweadx \1,57,\2dda,usp +//-------------------------------------------------------------------- +// func.w (ax)+,dx +//-------------------------------------------------------------------- + funcweadx \1,58,\2ddai,a0_off(a7) + funcweadx \1,59,\2ddai,a1_off(a7) + funcweadx \1,5a,\2dd,(a2)+ + funcweadx \1,5b,\2dd,(a3)+ + funcweadx \1,5c,\2dd,(a4)+ + funcweadx \1,5d,\2dd,(a5)+ + funcweadx \1,5e,\2dd,(a6)+ + funcweadx \1,5f,\2ddai,usp +//-------------------------------------------------------------------- +// func.w -(ax),dx +//-------------------------------------------------------------------- + funcweadx \1,60,\2ddad,a0_off(a7) + funcweadx \1,61,\2ddad,a1_off(a7) + funcweadx \1,62,\2dd,-(a2) + funcweadx \1,63,\2dd,-(a3) + funcweadx \1,64,\2dd,-(a4) + funcweadx \1,65,\2dd,-(a5) + funcweadx \1,66,\2dd,-(a6) + funcweadx \1,67,\2ddad,usp +//-------------------------------------------------------------------- +// func.w d16(ax),dx +//-------------------------------------------------------------------- + funcweadx \1,68,\2d16ad,a0_off(a7) + funcweadx \1,69,\2d16ad,a1_off(a7) + funcweadx \1,6a,\2d16ad,a2 + funcweadx \1,6b,\2d16ad,a3 + funcweadx \1,6c,\2d16ad,a4 + funcweadx \1,6d,\2d16ad,a5 + funcweadx \1,6e,\2d16ad,a6 + funcweadx \1,6f,\2d16ad,usp +//-------------------------------------------------------------------- +// func.w d8(ax,dy),dx +//-------------------------------------------------------------------- + funcweadx \1,70,\2d8ad,a0_off(a7) + funcweadx \1,71,\2d8ad,a1_off(a7) + funcweadx \1,72,\2d8ad,a2 + funcweadx \1,73,\2d8ad,a3 + funcweadx \1,74,\2d8ad,a4 + funcweadx \1,75,\2d8ad,a5 + funcweadx \1,76,\2d8ad,a6 + funcweadx \1,77,\2d8ad,usp +//-------------------------------------------------------------------- +// func.w xxx.w,dx +//-------------------------------------------------------------------- + funcweadx \1,78,\2xwd,(a0)+ +//-------------------------------------------------------------------- +// func.w xxx.w,dx +//-------------------------------------------------------------------- + funcweadx \1,79,\2xld,(a0)+ +//-------------------------------------------------------------------- +// func.w d16(pc),dx +//-------------------------------------------------------------------- + funcweadx \1,7a,\2d16pcd,(a0)+ +//-------------------------------------------------------------------- +// func.w d8(pc,dy),dx +//-------------------------------------------------------------------- + funcweadx \1,7b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.w #im,dx +//-------------------------------------------------------------------- + funcweadx \1,7c,\2dd,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,ea +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.w dx,dd -> addx subx etc. +//-------------------------------------------------------------------- +.ifnc \2,and //platz für exg + funcwdxea \1,40,\2dx,d0_off+2(a7) + funcwdxea \1,41,\2dx,d1_off+2(a7) + funcwdxea \1,42,\2dx,d2 + funcwdxea \1,43,\2dx,d3 + funcwdxea \1,44,\2dx,d4 + funcwdxea \1,45,\2dx,d5 + funcwdxea \1,46,\2dx,d6 + funcwdxea \1,47,\2dx,d7 +//-------------------------------------------------------------------- +// func.w -(ax),-(ay) -> addx,subx +//-------------------------------------------------------------------- + funcaxay \1,48,\2dax,a0_off(a7),w + funcaxay \1,49,\2dax,a1_off(a7).w + funcaxay \1,4a,\2dax,a2,w + funcaxay \1,4b,\2dax,a3,w + funcaxay \1,4c,\2dax,a4,w + funcaxay \1,4d,\2dax,a5,w + funcaxay \1,4e,\2dax,a6,w + funcaxay \1,4f,\2dax,usp,w +.endif +//-------------------------------------------------------------------- +// func.w dy,(ax) +//-------------------------------------------------------------------- + funcwdxea \1,50,\2eda,a0_off(a7) + funcwdxea \1,51,\2eda,a1_off(a7) + funcwdxea \1,52,\2dd,(a2) + funcwdxea \1,53,\2dd,(a3) + funcwdxea \1,54,\2dd,(a4) + funcwdxea \1,55,\2dd,(a5) + funcwdxea \1,56,\2dd,(a6) + funcwdxea \1,57,\2eda,usp +//-------------------------------------------------------------------- +// func.w dy,(ax)+ +//-------------------------------------------------------------------- + funcwdxea \1,58,\2edai,a0_off(a7) + funcwdxea \1,59,\2edai,a1_off(a7) + funcwdxea \1,5a,\2edaid,(a2) + funcwdxea \1,5b,\2edaid,(a3) + funcwdxea \1,5c,\2edaid,(a4) + funcwdxea \1,5d,\2edaid,(a5) + funcwdxea \1,5e,\2edaid,(a6) + funcwdxea \1,5f,\2edai,usp +//-------------------------------------------------------------------- +// func.w dy,-(ax) +//-------------------------------------------------------------------- + funcwdxea \1,60,\2edad,a0_off(a7) + funcwdxea \1,61,\2edad,a1_off(a7) + funcwdxea \1,62,\2edadd,(a2) + funcwdxea \1,63,\2edadd,(a3) + funcwdxea \1,64,\2edadd,(a4) + funcwdxea \1,65,\2edadd,(a5) + funcwdxea \1,66,\2edadd,(a6) + funcwdxea \1,67,\2edad,usp +//-------------------------------------------------------------------- +// func.w dy,d16(ax) +//-------------------------------------------------------------------- + funcwdxea \1,68,\2e16ad,a0_off(a7) + funcwdxea \1,69,\2e16ad,a1_off(a7) + funcwdxea \1,6a,\2e16ad,a2 + funcwdxea \1,6b,\2e16ad,a3 + funcwdxea \1,6c,\2e16ad,a4 + funcwdxea \1,6d,\2e16ad,a5 + funcwdxea \1,6e,\2e16ad,a6 + funcwdxea \1,6f,\2e16ad,usp +//-------------------------------------------------------------------- +// func.w dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcwdxea \1,70,\2e8ad,a0_off(a7) + funcwdxea \1,71,\2e8ad,a1_off(a7) + funcwdxea \1,72,\2e8ad,a2 + funcwdxea \1,73,\2e8ad,a3 + funcwdxea \1,74,\2e8ad,a4 + funcwdxea \1,75,\2e8ad,a5 + funcwdxea \1,76,\2e8ad,a6 + funcwdxea \1,77,\2e8ad,usp +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,78,\2xwe,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,79,\2xld,(a0)+ +/*****************************************************************************************/ +// long +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// func.l -(ax),-(ay) +//-------------------------------------------------------------------- + funcaxay \1,c8,\2dax,a0_off(a7),l + funcaxay \1,c9,\2dax,a1_off(a7).l + funcaxay \1,ca,\2dax,a2,l + funcaxay \1,cb,\2dax,a3,l + funcaxay \1,cc,\2dax,a4,l + funcaxay \1,cd,\2dax,a5,l + funcaxay \1,ce,\2dax,a6,l + funcaxay \1,cf,\2dax,usp,l +//-------------------------------------------------------------------- +// func.l d8(ax,dy),dx +//-------------------------------------------------------------------- + funcleadx \1,b0,\2d8ad,a0_off(a7) + funcleadx \1,b1,\2d8ad,a1_off(a7) + funcleadx \1,b2,\2d8ad,a2 + funcleadx \1,b3,\2d8ad,a3 + funcleadx \1,b4,\2d8ad,a4 + funcleadx \1,b5,\2d8ad,a5 + funcleadx \1,b6,\2d8ad,a6 + funcleadx \1,b7,\2d8ad,usp +//-------------------------------------------------------------------- +// func.l d8(pc,dy),dx +//-------------------------------------------------------------------- + funcleadx \1,bb,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.l dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcldxea \1,b0,\2e8ad,a0_off(a7) + funcldxea \1,b1,\2e8ad,a1_off(a7) + funcldxea \1,b2,\2e8ad,a2 + funcldxea \1,b3,\2e8ad,a3 + funcldxea \1,b4,\2e8ad,a4 + funcldxea \1,b5,\2e8ad,a5 + funcldxea \1,b6,\2e8ad,a6 + funcldxea \1,b7,\2e8ad,usp +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// func.w ea,ax +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// func.w dx,ax +//-------------------------------------------------------------------- + funcweaax \1,c0,\2aw,d0 + funcweaax \1,c1,\2aw,d1 + funcweaax \1,c2,\2aw,d2 + funcweaax \1,c3,\2aw,d3 + funcweaax \1,c4,\2aw,d4 + funcweaax \1,c5,\2aw,d5 + funcweaax \1,c6,\2aw,d6 + funcweaax \1,c7,\2aw,d7 +//-------------------------------------------------------------------- +// func.w ay,ax +//-------------------------------------------------------------------- + funcweaax \1,c8,\2aw,a0 + funcweaax \1,c9,\2aw,a1 + funcweaax \1,ca,\2aw,a2 + funcweaax \1,cb,\2aw,a3 + funcweaax \1,cc,\2aw,a4 + funcweaax \1,cd,\2aw,a5 + funcweaax \1,ce,\2aw,a6 + funcweaax \1,cf,\2awu,a7 +//-------------------------------------------------------------------- +// func.w (ay),ax +//-------------------------------------------------------------------- + funcweaax \1,d0,\2aw,(a0) + funcweaax \1,d1,\2aw,(a1) + funcweaax \1,d2,\2aw,(a2) + funcweaax \1,d3,\2aw,(a3) + funcweaax \1,d4,\2aw,(a4) + funcweaax \1,d5,\2aw,(a5) + funcweaax \1,d6,\2aw,(a6) + funcweaax \1,d7,\2awu,(a7) +//-------------------------------------------------------------------- +// func.w (ay)+,ax +//-------------------------------------------------------------------- + funcweaax \1,d8,\2aw,(a0)+ + funcweaax \1,d9,\2aw,(a1)+ + funcweaax \1,da,\2aw,(a2)+ + funcweaax \1,db,\2aw,(a3)+ + funcweaax \1,dc,\2aw,(a4)+ + funcweaax \1,dd,\2aw,(a5)+ + funcweaax \1,de,\2aw,(a6)+ + funcweaax \1,df,\2awu,(a7)+ +//-------------------------------------------------------------------- +// func.w -(ay),ax +//-------------------------------------------------------------------- + funcweaax \1,e0,\2aw,-(a0) + funcweaax \1,e1,\2aw,-(a1) + funcweaax \1,e2,\2aw,-(a2) + funcweaax \1,e3,\2aw,-(a3) + funcweaax \1,e4,\2aw,-(a4) + funcweaax \1,e5,\2aw,-(a5) + funcweaax \1,e6,\2aw,-(a6) + funcweaax \1,e7,\2awu,-(a7) +//-------------------------------------------------------------------- +// func.w d16(ay),ax +//-------------------------------------------------------------------- + funcweaaxn \1,e8,\2awd16a,a0_off(a7) + funcweaaxn \1,e9,\2awd16a,a1_off(a7) + funcweaaxn \1,ea,\2awd16a,a2 + funcweaaxn \1,eb,\2awd16a,a3 + funcweaaxn \1,ec,\2awd16a,a4 + funcweaaxn \1,ed,\2awd16a,a5 + funcweaaxn \1,ee,\2awd16a,a6 + funcweaaxn \1,ef,\2awd16a,usp +//-------------------------------------------------------------------- +// func.w d8(ay,dy),ax +//-------------------------------------------------------------------- + funcweaaxn \1,f0,\2awd8a,a0_off(a7) + funcweaaxn \1,f1,\2awd8a,a1_off(a7) + funcweaaxn \1,f2,\2awd8a,a2 + funcweaaxn \1,f3,\2awd8a,a3 + funcweaaxn \1,f4,\2awd8a,a4 + funcweaaxn \1,f5,\2awd8a,a5 + funcweaaxn \1,f6,\2awd8a,a6 + funcweaaxn \1,f7,\2awd8a,usp +//-------------------------------------------------------------------- +// func.w xxx.w,ax +//-------------------------------------------------------------------- + funcweaaxn \1,f8,\2awxwax,(a0)+ +//-------------------------------------------------------------------- +// func.w xxxlw,ax +//-------------------------------------------------------------------- + funcweaaxn \1,f9,\2awxlax,(a0)+ +//-------------------------------------------------------------------- +// func.w d16(pc),ax +//-------------------------------------------------------------------- + funcweaaxn \1,fa,\2awd16pcax,(a0)+ +//-------------------------------------------------------------------- +// func.w d8(pc,dy),ax +//-------------------------------------------------------------------- + funcweaaxn \1,fb,\2awd8pcax,(a0)+ //(a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.w #im,ax +//-------------------------------------------------------------------- + funcweaaxn \1,fc,\2awim,(a0)+ +//-------------------------------------------------------------------- +// ende + .endm; +//-------------------------------------------------------------------- +// byt +funcbeadx:.macro // function byt: im,dx +ii_0x\10\2: + \3 \4,d0_off+3(a7),b +ii_0x\12\2: + \3 \4,d1_off+3(a7),b +ii_0x\14\2: + \3 \4,d2,b +ii_0x\16\2: + \3 \4,d3,b +ii_0x\18\2: + \3 \4,d4,b +ii_0x\1a\2: + \3 \4,d5,b +ii_0x\1c\2: + \3 \4,d6,b +ii_0x\1e\2: + \3 \4,d7,b + .endm; +funcbdxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off+3(a7),\4,b +ii_0x\13\2: + \3 d1_off+3(a7),\4,b +ii_0x\15\2: + \3 d2,\4,b +ii_0x\17\2: + \3 d3,\4,b +ii_0x\19\2: + \3 d4,\4,b +ii_0x\1b\2: + \3 d5,\4,b +ii_0x\1d\2: + \3 d6,\4,b +ii_0x\1f\2: + \3 d7,\4,b + .endm; +//-------------------------------------------------------------------- +// word +funcweadx:.macro // dx function(\3) ea(\4) -> dx +ii_0x\10\2: + \3 \4,d0_off+2(a7),w +ii_0x\12\2: + \3 \4,d1_off+2(a7),w +ii_0x\14\2: + \3 \4,d2,w +ii_0x\16\2: + \3 \4,d3,w +ii_0x\18\2: + \3 \4,d4,w +ii_0x\1a\2: + \3 \4,d5,w +ii_0x\1c\2: + \3 \4,d6,w +ii_0x\1e\2: + \3 \4,d7,w + .endm; +funcwdxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off+2(a7),\4,w +ii_0x\13\2: + \3 d1_off+2(a7),\4,w +ii_0x\15\2: + \3 d2,\4,w +ii_0x\17\2: + \3 d3,\4,w +ii_0x\19\2: + \3 d4,\4,w +ii_0x\1b\2: + \3 d5,\4,w +ii_0x\1d\2: + \3 d6,\4,w +ii_0x\1f\2: + \3 d7,\4,w + .endm; +//-------------------------------------------------------------------- +// long +funcleadx:.macro // dx function(\3) ea(\4) -> dx +ii_0x\10\2: + \3 \4,d0_off(a7),w +ii_0x\12\2: + \3 \4,d1_off(a7),w +ii_0x\14\2: + \3 \4,d2,w +ii_0x\16\2: + \3 \4,d3,w +ii_0x\18\2: + \3 \4,d4,w +ii_0x\1a\2: + \3 \4,d5,w +ii_0x\1c\2: + \3 \4,d6,w +ii_0x\1e\2: + \3 \4,d7,w + .endm; +funcldxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off(a7),\4,w +ii_0x\13\2: + \3 d1_off(a7),\4,w +ii_0x\15\2: + \3 d2,\4,w +ii_0x\17\2: + \3 d3,\4,w +ii_0x\19\2: + \3 d4,\4,w +ii_0x\1b\2: + \3 d5,\4,w +ii_0x\1d\2: + \3 d6,\4,w +ii_0x\1f\2: + \3 d7,\4,w + .endm; +//-------------------------------------------------------------- +// address +funcweaax:.macro // ax function(\3) ea(\4)(ext long!) -> ax +ii_0x\10\2: + \3 \4,a0 +ii_0x\12\2: + \3 \4,a1 +ii_0x\14\2: + \3 \4,a2 +ii_0x\16\2: + \3 \4,a3 +ii_0x\18\2: + \3 \4,a4 +ii_0x\1a\2: + \3 \4,a5 +ii_0x\1c\2: + \3 \4,a6 +ii_0x\1e\2: + \3a7 \4,a7 // "a7" beachten wegen usp + .endm; +funcweaaxn:.macro // ax function(\3) ea(\4)(ext long!) -> ax +ii_0x\10\2: + \3 \4,a0_off(a7) +ii_0x\12\2: + \3 \4,a1_off(a7) +ii_0x\14\2: + \3 \4,a2 +ii_0x\16\2: + \3 \4,a3 +ii_0x\18\2: + \3 \4,a4 +ii_0x\1a\2: + \3 \4,a5 +ii_0x\1c\2: + \3 \4,a6 +ii_0x\1e\2: + \3 \4,usp + .endm; +//-------------------------------------------------------------- +// byt, word, long +//-------------------------------------------------------------- +funcaxay:.macro // ea(\4) function(\3) dx -> ea,\5 = size +ii_0x\11\2: + \3 a0_off(a7),\4,\5 +ii_0x\13\2: + \3 a1_off(a7),\4,\5 +ii_0x\15\2: + \3 a2,\4,\5 +ii_0x\17\2: + \3 a3,\4,\5 +ii_0x\19\2: + \3 a4,\4,\5 +ii_0x\1b\2: + \3 a5,\4,\5 +ii_0x\1d\2: + \3 a6,\4,\5 +ii_0x\1f\2: + \3 usp,\4,\5 + .endm; diff --git a/BaS_GNU/sources/ii_jmp.h b/BaS_GNU/sources/ii_jmp.h new file mode 100644 index 0000000..1896118 --- /dev/null +++ b/BaS_GNU/sources/ii_jmp.h @@ -0,0 +1,59 @@ +//-------------------------------------------------------------------- +// extension word format missing +//-------------------------------------------------------------------- +ii_\1_func:.macro +ii_0x\20: +#ifdef halten_\1 + halt +#endif + move.l a0_off(a7),a1 + \1_macro +ii_0x\21: +#ifdef halten_\1 + halt +#endif + move.l a1_off(a7),a1 + \1_macro +ii_0x\22: +#ifdef halten_\1 + halt +#endif + move.l a2,a1 + \1_macro +ii_0x\23: +#ifdef halten_\1 + halt +#endif + move.l a3,a1 + \1_macro +ii_0x\24: +#ifdef halten_\1 + halt +#endif + move.l a4,a1 + \1_macro +ii_0x\25: +#ifdef halten_\1 + halt +#endif + move.l a5,a1 + \1_macro +ii_0x\26: +#ifdef halten_\1 + halt +#endif + move.l a6,a1 + \1_macro +ii_0x\27: +#ifdef halten_\1 + halt +#endif + move.l usp,a1 + \1_macro +ii_0x\2b: +#ifdef halten_\1 + halt +#endif + move.l a0,a1 + \1_macro +.endm diff --git a/BaS_GNU/sources/ii_lea.h b/BaS_GNU/sources/ii_lea.h new file mode 100644 index 0000000..7a422a7 --- /dev/null +++ b/BaS_GNU/sources/ii_lea.h @@ -0,0 +1,105 @@ +//------------------------------------------------------------------- +// lea +//------------------------------------------------------------------- +.text +ii_lea_lset:.macro + ii_lset_dxu 4,f0 // lea d8(a0,dy.w),a0-a7 + ii_lset_dxu 4,f1 // lea d8(a1,dy.w),a0-a7 + ii_lset_dxu 4,f2 // lea d8(a2,dy.w),a0-a7 + ii_lset_dxu 4,f3 // lea d8(a3,dy.w),a0-a7 + ii_lset_dxu 4,f4 // lea d8(a4,dy.w),a0-a7 + ii_lset_dxu 4,f5 // lea d8(a5,dy.w),a0-a7 + ii_lset_dxu 4,f6 // lea d8(a6,dy.w),a0-a7 + ii_lset_dxu 4,f7 // lea d8(a7,dy.w),a0-a7 + ii_lset_dxu 4,fb // lea d8(pc,dy.w),a0-a7 +.endm + +//--------------------------------------------------------------------------------------------- +// function +//--------------------------------------------------------------------------------------------- +ii_lea_sub:.macro +ii_0x4\1\2: +#ifdef halten_lea + halt +#endif + move.l \4,a1 + jsr ewf + move.l a1,\3 + ii_end +.endm +ii_lea_func:.macro +//lea d8(ax,dy.w),a0-a7 + ii_lea_sub 1,f0,a0_off(a7),a0_off(a7) + ii_lea_sub 1,f1,a0_off(a7),a1_off(a7) + ii_lea_sub 1,f2,a0_off(a7),a2 + ii_lea_sub 1,f3,a0_off(a7),a3 + ii_lea_sub 1,f4,a0_off(a7),a4 + ii_lea_sub 1,f5,a0_off(a7),a5 + ii_lea_sub 1,f6,a0_off(a7),a6 + ii_lea_sub 1,f7,a0_off(a7),usp + ii_lea_sub 3,f0,a1_off(a7),a0_off(a7) + ii_lea_sub 3,f1,a1_off(a7),a1_off(a7) + ii_lea_sub 3,f2,a1_off(a7),a2 + ii_lea_sub 3,f3,a1_off(a7),a3 + ii_lea_sub 3,f4,a1_off(a7),a4 + ii_lea_sub 3,f5,a1_off(a7),a5 + ii_lea_sub 3,f6,a1_off(a7),a6 + ii_lea_sub 3,f7,a1_off(a7),usp + ii_lea_sub 5,f0,a2,a0_off(a7) + ii_lea_sub 5,f1,a2,a1_off(a7) + ii_lea_sub 5,f2,a2,a2 + ii_lea_sub 5,f3,a2,a3 + ii_lea_sub 5,f4,a2,a4 + ii_lea_sub 5,f5,a2,a5 + ii_lea_sub 5,f6,a2,a6 + ii_lea_sub 5,f7,a2,usp + ii_lea_sub 7,f0,a3,a0_off(a7) + ii_lea_sub 7,f1,a3,a1_off(a7) + ii_lea_sub 7,f2,a3,a2 + ii_lea_sub 7,f3,a3,a3 + ii_lea_sub 7,f4,a3,a4 + ii_lea_sub 7,f5,a3,a5 + ii_lea_sub 7,f6,a3,a6 + ii_lea_sub 7,f7,a3,usp + ii_lea_sub 9,f0,a4,a0_off(a7) + ii_lea_sub 9,f1,a4,a1_off(a7) + ii_lea_sub 9,f2,a4,a2 + ii_lea_sub 9,f3,a4,a3 + ii_lea_sub 9,f4,a4,a4 + ii_lea_sub 9,f5,a4,a5 + ii_lea_sub 9,f6,a4,a6 + ii_lea_sub 9,f7,a4,usp + ii_lea_sub b,f0,a5,a0_off(a7) + ii_lea_sub b,f1,a5,a1_off(a7) + ii_lea_sub b,f2,a5,a2 + ii_lea_sub b,f3,a5,a3 + ii_lea_sub b,f4,a5,a4 + ii_lea_sub b,f5,a5,a5 + ii_lea_sub b,f6,a5,a6 + ii_lea_sub b,f7,a6,usp + ii_lea_sub d,f0,a6,a0_off(a7) + ii_lea_sub d,f1,a6,a1_off(a7) + ii_lea_sub d,f2,a6,a2 + ii_lea_sub d,f3,a6,a3 + ii_lea_sub d,f4,a6,a4 + ii_lea_sub d,f5,a6,a5 + ii_lea_sub d,f6,a6,a6 + ii_lea_sub d,f7,a6,usp + ii_lea_sub f,f0,usp,a0_off(a7) + ii_lea_sub f,f1,usp,a1_off(a7) + ii_lea_sub f,f2,usp,a2 + ii_lea_sub f,f3,usp,a3 + ii_lea_sub f,f4,usp,a4 + ii_lea_sub f,f5,usp,a5 + ii_lea_sub f,f6,usp,a6 + ii_lea_sub f,f7,usp,usp +// lea d8(pc,dy.w),az + ii_lea_sub 1,fb,a0_off(a7),a0 + ii_lea_sub 3,fb,a1_off(a7),a0 + ii_lea_sub 5,fb,a2,a0 + ii_lea_sub 7,fb,a3,a0 + ii_lea_sub 9,fb,a4,a0 + ii_lea_sub b,fb,a5,a0 + ii_lea_sub d,fb,a6,a0 + ii_lea_sub f,fb,usp,a0 +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_macro.h b/BaS_GNU/sources/ii_macro.h new file mode 100644 index 0000000..5db7460 --- /dev/null +++ b/BaS_GNU/sources/ii_macro.h @@ -0,0 +1,144 @@ +/*******************************************************/ +// constanten +/*******************************************************/ +.extern ___RAMBAR1 +.extern _rt_cacr +.extern _rt_mod +.extern _rt_ssp +.extern _rt_usp +.extern _rt_vbr +.extern _d0_save +.extern _a7_save + +ii_ss = 16 +d0_off = 0 +d1_off = 4 +a0_off = 8 +a1_off = 12 +format_off = 16 +sr_off = 18 +ccr_off = 19 +pc_off = 20 + +#define table 0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle -> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle + +/*******************************************************/ +// allgemeine macros +/*******************************************************/ +ii_end: .macro + move.l a0,pc_off(a7) + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 + rte + .endm; + +set_cc0:.macro + move.w ccr,d0 + move.b d0,ccr_off(a7) + .endm; + +ii_esr: .macro // geht nicht!!?? + movem.l (a7),d0/d1/a0/a1 + lea ii_ss+8(a7),a7 // stack erhöhen + move.w d0,_d0_save // d0.w sicheren + move.w -6(a7),d0 // sr holen + move.w d0,sr // sr setzen + nop + move.w _d0_save,d0 // d0.w zurück + .endm; + +ii_end_mvm:.macro + move.l a0_off(a7),a0 + lea 16(a7),a7 + rte + .endm; + +ii_endj:.macro + movem.l (a7),d0/d1/a0/a1 // register zurück + lea ii_ss(a7),a7 // korr + rte // ende + .endm; + +set_nzvc:.macro // set ccr bits nzvc + move.w ccr,d1 + bclr #4,d1 + btst #4,ccr_off(a7) + beq snzvc2\@ + bset #4,d1 +snzvc2\@: + move.b d1,ccr_off(a7) + .endm; + +set_cc1:.macro + move.w ccr,d1 + move.b d1,ccr_off(a7) + .endm; + +set_cc_b:.macro + move.w ccr,d1 + btst #7,d0 // byt negativ? + beq set_cc_b2\@ + bset #3,d1 // make negativ +set_cc_b2\@: + move.b d1,ccr_off(a7) + .endm; + +set_cc_w:.macro + move.w ccr,d1 + btst #15,d0 // byt negativ? + beq set_cc_w2\@ + bset #3,d1 // make negativ +set_cc_w2\@: + move.b d1,ccr_off(a7) + .endm; + +get_pc: .macro + lea.l (a0),a1 + .endm; + +//-------------------------------------------------------------------- +ii_lset:.macro + lea table+\1*4,a0 + move.l #ii_\1,(a0) + .endm; +ii_lset_dx:.macro // 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 + ii_lset_dxg \1,\2 + ii_lset_dxu \1,\2 + .endm; +ii_lset_dxg:.macro // gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 + lea table+0x\10\2*4,a0 + move.l #ii_0x\10\2,(a0) + lea 0x800(a0),a0 // 4 * 0x200 + move.l #ii_0x\12\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\14\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\16\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\18\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1a\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1c\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1e\2,(a0) + .endm; +ii_lset_dxu:.macro // ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40 + lea table+0x\11\2*4,a0 + move.l #ii_0x\11\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\13\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\15\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\17\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\19\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1b\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1d\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1f\2,(a0) + .endm; + diff --git a/BaS_GNU/sources/ii_move.h b/BaS_GNU/sources/ii_move.h new file mode 100644 index 0000000..1ae8213 --- /dev/null +++ b/BaS_GNU/sources/ii_move.h @@ -0,0 +1,1271 @@ +//------------------------------------------------------------------- +// move +//------------------------------------------------------------------- +.extern ewf + +.text +ii_move_lset:.macro +//------------------------------------------------------------------------- +// 0x1000 move.b +//------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 11,e +// move.x d16(ax),xxx.l + ii_lset_opeau 13,e +// move.x d16(pc),xxx.w + ii_lset 0x11fa +// move.x d16(pc),xxx.l + ii_lset 0x13fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 1,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 1,79 +// move.x #xx,d16(ax) + ii_lset_dxu 1,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x11f8 +// move.x xxx.l,xxx.w + ii_lset 0x11f9 +// move.x xxx.w,xxx.l + ii_lset 0x13f8 +// move.x xxx.l,xxx.l + ii_lset 0x13f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x11fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x13fc +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 11,8 + ii_lset_opeag 13,8 + ii_lset_opeag 15,8 + ii_lset_opeag 17,8 + ii_lset_opeag 19,8 + ii_lset_opeag 1b,8 + ii_lset_opeag 1d,8 + ii_lset_opeag 1f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 11,9 + ii_lset_opea 13,9 + ii_lset_opea 15,9 + ii_lset_opea 17,9 + ii_lset_opea 19,9 + ii_lset_opea 1b,9 + ii_lset_opea 1d,9 + ii_lset_opea 1f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 11,a + ii_lset_opeag 13,a + ii_lset_opeag 15,a + ii_lset_opeag 17,a + ii_lset_opeag 19,a + ii_lset_opeag 1b,a + ii_lset_opeag 1d,a + ii_lset_opeag 1f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) + ii_lset_opeag 17,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 17,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 17,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 10,3 + ii_lset_opeag 12,3 + ii_lset_opeag 14,3 + ii_lset_opeag 16,3 + ii_lset_opeag 18,3 + ii_lset_opeag 1a,3 + ii_lset_opeag 1c,3 + ii_lset_opeag 1e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 10,7 + ii_lset_opeag 12,7 + ii_lset_opeag 14,7 + ii_lset_opeag 16,7 + ii_lset_opeag 18,7 + ii_lset_opeag 1a,7 + ii_lset_opeag 1c,7 + ii_lset_opeag 1e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 10,b + ii_lset_opeag 12,b + ii_lset_opeag 14,b + ii_lset_opeag 16,b + ii_lset_opeag 18,b + ii_lset_opeag 1a,b + ii_lset_opeag 1c,b + ii_lset_opeag 1e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 10,f + ii_lset_opeag 12,f + ii_lset_opeag 14,f + ii_lset_opeag 16,f + ii_lset_opeag 18,f + ii_lset_opeag 1a,f + ii_lset_opeag 1c,f + ii_lset_opeag 1e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 11,3 + ii_lset_opeag 13,3 + ii_lset_opeag 15,3 + ii_lset_opeag 17,3 + ii_lset_opeag 19,3 + ii_lset_opeag 1b,3 + ii_lset_opeag 1d,3 + ii_lset_opeag 1f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 1,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 1,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 1,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 1,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 1,3b +//------------------------------------------------------------------------- +// 0x2000 move.l +//------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 21,e +// move.x d16(ax),xxx.l + ii_lset_opeau 23,e +// move.x d16(pc),xxx.w + ii_lset 0x21fa +// move.x d16(pc),xxx.l + ii_lset 0x23fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 2,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 2,79 +// move.x #xx,d16(ax) + ii_lset_dxu 2,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x21f8 +// move.x xxx.l,xxx.w + ii_lset 0x21f9 +// move.x xxx.w,xxx.l + ii_lset 0x23f8 +// move.x xxx.l,xxx.l + ii_lset 0x23f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x21fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x23fc +// move.x ea,d8(ax,dy) ------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 21,8 + ii_lset_opeag 23,8 + ii_lset_opeag 25,8 + ii_lset_opeag 27,8 + ii_lset_opeag 29,8 + ii_lset_opeag 2b,8 + ii_lset_opeag 2d,8 + ii_lset_opeag 2f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 21,9 + ii_lset_opea 23,9 + ii_lset_opea 25,9 + ii_lset_opea 27,9 + ii_lset_opea 29,9 + ii_lset_opea 2b,9 + ii_lset_opea 2d,9 + ii_lset_opea 2f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 21,a + ii_lset_opeag 23,a + ii_lset_opeag 25,a + ii_lset_opeag 27,a + ii_lset_opeag 29,a + ii_lset_opeag 2b,a + ii_lset_opeag 2d,a + ii_lset_opeag 2f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) +// move.x ax,d8(pc,dy) + ii_lset_opea 27,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 27,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 27,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 20,3 + ii_lset_opeag 22,3 + ii_lset_opeag 24,3 + ii_lset_opeag 26,3 + ii_lset_opeag 28,3 + ii_lset_opeag 2a,3 + ii_lset_opeag 2c,3 + ii_lset_opeag 2e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 20,7 + ii_lset_opeag 22,7 + ii_lset_opeag 24,7 + ii_lset_opeag 26,7 + ii_lset_opeag 28,7 + ii_lset_opeag 2a,7 + ii_lset_opeag 2c,7 + ii_lset_opeag 2e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 20,b + ii_lset_opeag 22,b + ii_lset_opeag 24,b + ii_lset_opeag 26,b + ii_lset_opeag 28,b + ii_lset_opeag 2a,b + ii_lset_opeag 2c,b + ii_lset_opeag 2e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 20,f + ii_lset_opeag 22,f + ii_lset_opeag 24,f + ii_lset_opeag 26,f + ii_lset_opeag 28,f + ii_lset_opeag 2a,f + ii_lset_opeag 2c,f + ii_lset_opeag 2e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 21,3 + ii_lset_opeag 23,3 + ii_lset_opeag 25,3 + ii_lset_opeag 27,3 + ii_lset_opeag 29,3 + ii_lset_opeag 2b,3 + ii_lset_opeag 2d,3 + ii_lset_opeag 2f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 2,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 2,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 2,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 2,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 2,3b +//------------------------------------------------------------------------- +// 0x3000 move.w +///------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 31,e +// move.x d16(ax),xxx.l + ii_lset_opeau 33,e +// move.x d16(pc),xxx.w + ii_lset 0x31fa +// move.x d16(pc),xxx.l + ii_lset 0x33fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 3,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 3,79 +// move.x #xx,d16(ax) + ii_lset_dxu 3,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x31f8 +// move.x xxx.l,xxx.w + ii_lset 0x31f9 +// move.x xxx.w,xxx.l + ii_lset 0x33f8 +// move.x xxx.l,xxx.l + ii_lset 0x33f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x31fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x33fc +// move.x ea,d8(ax,dy) ------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 31,8 + ii_lset_opeag 33,8 + ii_lset_opeag 35,8 + ii_lset_opeag 37,8 + ii_lset_opeag 39,8 + ii_lset_opeag 3b,8 + ii_lset_opeag 3d,8 + ii_lset_opeag 3f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 31,9 + ii_lset_opea 33,9 + ii_lset_opea 35,9 + ii_lset_opea 37,9 + ii_lset_opea 39,9 + ii_lset_opea 3b,9 + ii_lset_opea 3d,9 + ii_lset_opea 3f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 31,a + ii_lset_opeag 33,a + ii_lset_opeag 35,a + ii_lset_opeag 37,a + ii_lset_opeag 39,a + ii_lset_opeag 3b,a + ii_lset_opeag 3d,a + ii_lset_opeag 3f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) +// move.x ax,d8(pc,dy) + ii_lset_opea 37,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 37,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 37,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 30,3 + ii_lset_opeag 32,3 + ii_lset_opeag 34,3 + ii_lset_opeag 36,3 + ii_lset_opeag 38,3 + ii_lset_opeag 3a,3 + ii_lset_opeag 3c,3 + ii_lset_opeag 3e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 30,7 + ii_lset_opeag 32,7 + ii_lset_opeag 34,7 + ii_lset_opeag 36,7 + ii_lset_opeag 38,7 + ii_lset_opeag 3a,7 + ii_lset_opeag 3c,7 + ii_lset_opeag 3e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 30,b + ii_lset_opeag 32,b + ii_lset_opeag 34,b + ii_lset_opeag 36,b + ii_lset_opeag 38,b + ii_lset_opeag 3a,b + ii_lset_opeag 3c,b + ii_lset_opeag 3e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 30,f + ii_lset_opeag 32,f + ii_lset_opeag 34,f + ii_lset_opeag 36,f + ii_lset_opeag 38,f + ii_lset_opeag 3a,f + ii_lset_opeag 3c,f + ii_lset_opeag 3e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 31,3 + ii_lset_opeag 33,3 + ii_lset_opeag 35,3 + ii_lset_opeag 37,3 + ii_lset_opeag 39,3 + ii_lset_opeag 3b,3 + ii_lset_opeag 3d,3 + ii_lset_opeag 3f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 3,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 3,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 3,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 3,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 3,3b +.endm +//--------------------------------------------------------------------------------------------- +// function +//--------------------------------------------------------------------------------------------- +ii_move_op:.macro +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_move_d16ax_xxx 1e8,a0_off(a7),w + ii_move_d16ax_xxx 1e9,a1_off(a7),w + ii_move_d16ax_xxx 1ea,a2,w + ii_move_d16ax_xxx 1eb,a3,w + ii_move_d16ax_xxx 1ec,a4,w + ii_move_d16ax_xxx 1ed,a5,w + ii_move_d16ax_xxx 1ee,a6,w + ii_move_d16ax_xxx 1ef,usp,w +// move.x d16(ax),xxx.l + ii_move_d16ax_xxx 3e8,a0_off(a7),l + ii_move_d16ax_xxx 3e9,a1_off(a7),l + ii_move_d16ax_xxx 3ea,a2,l + ii_move_d16ax_xxx 3eb,a3,l + ii_move_d16ax_xxx 3ec,a4,l + ii_move_d16ax_xxx 3ed,a5,l + ii_move_d16ax_xxx 3ee,a6,l + ii_move_d16ax_xxx 3ef,usp,l +// move.x d16(pc),xxx.w + ii_move_d16ax_xxx 1fa,a0,w +// move.x d16(pc),xxx.l + ii_move_d16ax_xxx 3fa,a0,l +// move.x xxx.w,d16(ax) +// move.x xxx.l,d16(ax) +// move.x #xx,d16(ax) + ii_move_xxx_d16ax 1,a0_off(a7) + ii_move_xxx_d16ax 3,a1_off(a7) + ii_move_xxx_d16ax 5,a2 + ii_move_xxx_d16ax 7,a3 + ii_move_xxx_d16ax 9,a4 + ii_move_xxx_d16ax b,a5 + ii_move_xxx_d16ax d,a6 + ii_move_xxx_d16ax f,usp +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_move_xxx_xxx b,w,w,11f8 + ii_move_xxx_xxx l,w,w,21f8 + ii_move_xxx_xxx w,w,w,31f8 +// move.x xxx.l,xxx.w + ii_move_xxx_xxx b,l,w,11f9 + ii_move_xxx_xxx l,l,w,21f9 + ii_move_xxx_xxx w,l,w,31f9 +// move.x xxx.w,xxx.l + ii_move_xxx_xxx b,w,l,13f8 + ii_move_xxx_xxx l,w,l,23f8 + ii_move_xxx_xxx w,w,l,33f8 +// move.x xxx.l,xxx.l + ii_move_xxx_xxx b,l,l,13f9 + ii_move_xxx_xxx l,l,l,23f9 + ii_move_xxx_xxx w,l,l,33f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_move_im_xxx b,w,11fc + ii_move_im_xxx l,w,21fc + ii_move_im_xxx w,w,31fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_move_im_xxx b,l,13fc + ii_move_im_xxx l,l,23fc + ii_move_im_xxx w,l,33fc +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(ax/pc,dy) + ii_move_dxxia d0_off(a7),80,id,d,c0 + ii_move_dxxia d1_off(a7),81,id,d,c1 + ii_move_dxxia d2,82,d,d,c2 + ii_move_dxxia d3,83,d,d,c3 + ii_move_dxxia d4,84,d,d,c4 + ii_move_dxxia d5,85,d,d,c5 + ii_move_dxxia d6,86,d,d,c6 + ii_move_dxxia d7,87,d,d,c7 +// move.x ax,d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),88,id,d,c8 + ii_move_dxxia a1_off(a7),89,id,d,c9 + ii_move_dxxia a2,8a,d,da,ca + ii_move_dxxia a3,8b,d,da,cb + ii_move_dxxia a4,8c,d,da,cc + ii_move_dxxia a5,8d,d,da,cd + ii_move_dxxia a6,8e,d,da,ce + ii_move_dxxia a7,8f,a7,da,cf +// move.x (ax),d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),90,ia,d,d0 + ii_move_dxxia a1_off(a7),91,ia,d,d1 + ii_move_dxxia (a2),92,d,d,d2 + ii_move_dxxia (a3),93,d,d,d3 + ii_move_dxxia (a4),94,d,d,d4 + ii_move_dxxia (a5),95,d,d,d5 + ii_move_dxxia (a6),96,d,d,d6 + ii_move_dxxia (a7),97,a7,d,d7 +// move.x (ax)+,d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),98,iap,d,d8 + ii_move_dxxia a1_off(a7),99,iap,d,d9 + ii_move_dxxia (a2)+,9a,d,d,da + ii_move_dxxia (a3)+,9b,d,d,db + ii_move_dxxia (a4)+,9c,d,d,dc + ii_move_dxxia (a5)+,9d,d,d,dd + ii_move_dxxia (a6)+,9e,d,d,de + ii_move_dxxia (a7)+,9f,a7,d,df +// move.x -(ax),d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),a0,iam,d,e0 + ii_move_dxxia a1_off(a7),a1,iam,d,e1 + ii_move_dxxia -(a2),a2,d,d,e2 + ii_move_dxxia -(a3),a3,d,d,e3 + ii_move_dxxia -(a4),a4,d,d,e4 + ii_move_dxxia -(a5),a5,d,d,e5 + ii_move_dxxia -(a6),a6,d,d,e6 + ii_move_dxxia -(a7),a7,a7,d,e7 +//--------------------------------------------------------------------- +// move.x d8(ax/pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax/pc,dy),dz + ii_move_d8_dest d0,id,03,dx + ii_move_d8_dest d1,id,23,dx + ii_move_d8_dest d2,d,43,dx + ii_move_d8_dest d3,d,63,dx + ii_move_d8_dest d4,d,83,dx + ii_move_d8_dest d5,d,a3,dx + ii_move_d8_dest d6,d,c3,dx + ii_move_d8_dest d7,d,e3,dx +// move.x d8(ax/pc,dy),az + ii_move_d8_dest a0,id,07,ax + ii_move_d8_dest a1,id,27,ax + ii_move_d8_dest a2,d,47,ax + ii_move_d8_dest a3,d,67,ax + ii_move_d8_dest a4,d,87,ax + ii_move_d8_dest a5,d,a7,ax + ii_move_d8_dest a6,d,c7,ax + ii_move_d8_dest usp,id,e7,ax +// move.x d8(ax/pc,dy),(az) + ii_move_d8_dest a0_off(a7),id,0b,ia + ii_move_d8_dest a1_off(a7),id,2b,ia + ii_move_d8_dest (a2),d,4b,ia + ii_move_d8_dest (a3),d,6b,ia + ii_move_d8_dest (a4),d,8b,ia + ii_move_d8_dest (a5),d,ab,ia + ii_move_d8_dest (a6),d,cb,ia + ii_move_d8_dest usp,id,eb,ia +// move.x d8(ax/pc,dy),(az)+ + ii_move_d8_dest a0_off(a7),id,0f,iap + ii_move_d8_dest a1_off(a7),id,2f,iap + ii_move_d8_dest (a2)+,d,4f,iap + ii_move_d8_dest (a3)+,d,6f,iap + ii_move_d8_dest (a4)+,d,8f,iap + ii_move_d8_dest (a5)+,d,af,iap + ii_move_d8_dest (a6)+,d,cf,iap + ii_move_d8_dest usp,id,ef,iap +// move.x d8(ax/pc,dy),-(az) + ii_move_d8_dest a0_off(a7),id,13,iam + ii_move_d8_dest a1_off(a7),id,33,iam + ii_move_d8_dest -(a2),d,53,iam + ii_move_d8_dest -(a3),d,73,iam + ii_move_d8_dest -(a4),d,93,iam + ii_move_d8_dest -(a5),d,b3,iam + ii_move_d8_dest -(a6),d,d3,iam + ii_move_d8_dest usp,id,f3,iam +.endm //end function +//==================================================================== +// subs ---------------------------------------------------------- +//==================================================================== +// move.x d16(ax),xxx.w/l 1=code 2=adress register 3=dest adr size +ii_move_d16ax_xxx:.macro +ii_0x1\1: //byt: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.b (a1),d0 + move.\3 (a0)+,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x2\1: //long: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.l (a1),d0 + move.\3 (a0)+,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x3\1: //word: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.w (a1),d0 + move.\3 (a0)+,a1 + move.w d0,(a1) + set_cc0 + ii_end +.endm +//---------------------------------------- +// move.x xxx.w,d16(ax) +// move.x xxx.l,d16(ax) +// move.x #xx,d16(ax) +ii_move_xxx_d16ax:.macro //1=code 2=adress register +ii_0x1\178: //byt xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.b (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x1\179: //byt xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.b (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x1\17c: //byt #x +#ifdef halten_move + halt +#endif + mvs.b (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x2\178: //long xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.l (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x2\179: //long xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.l (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x2\17c: //long #x +#ifdef halten_move + halt +#endif + move.l (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end + ii_end +ii_0x3\178: //word xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.w (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +ii_0x3\179: //word xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.w (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +ii_0x3\17c: //word #x +#ifdef halten_move + halt +#endif + move.w (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +.endm +// move.x xxx,xxx +ii_move_xxx_xxx:.macro //1=size 2=size source adr 3=size dest adr 4=code +ii_0x\4: +#ifdef halten_move + halt +#endif + move.\2 (a0)+,a1 + move.\1 (a1),d0 + move.\3 (a0)+,d1 + move.\1 d0,(a1) + set_cc0 + ii_end +.endm +// move.x im,xxx +ii_move_im_xxx:.macro //1=size 2=size dest adr 3=code +ii_0x\3: +#ifdef halten_move + halt +#endif +.ifc 1,b + move.w (a0)+,d0 +.else + move.\1 (a0)+,d0 +.endif + move.\2 (a0)+,a1 + move.\1 d0,(a1) + set_cc0 + ii_end +.endm +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// ea=dx,ax,(ax),(ax)+,-(ax) +//--------------------------------------------------------------------- +ii_move_dxxia:.macro //1=source 2=code 1.stelle 3=code 2 letzte Stellen 4=art 5=code d8(pc,dy) +.ifc \3,id + ii_move_dxxi b,\1+3,1,\2,\3,\5 + ii_move_dxxi w,\1+2,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 +.else + .ifc \4,da + ii_move_dxxi w,\1,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 + .else + ii_move_dxxi b,\1,1,\2,\3,\5 + ii_move_dxxi w,\1,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 + .endif +.endif +.endm + +ii_move_dxxi:.macro +ii_0x\31\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + move_end \1,\2,\5 +ii_0x\33\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + move_end \1,\2,\5 +ii_0x\35\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a2,a1 + move_end \1,\2,\5 +ii_0x\37\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a3,a1 + move_end \1,\2,\5 +ii_0x\39\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a4,a1 + move_end \1,\2,\5 +ii_0x\3b\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a5,a1 + move_end \1,\2,\5 +ii_0x\3d\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a6,a1 + move_end \1,\2,\5 +ii_0x\3f\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l usp,a1 + move_end \1,\2,\5 +ii_0x\37\6: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a0,a1 + move_end \1,\2,\5 +.endm +//------------------------------------ +move_end:.macro + jsr ewf +.ifc 3,a7 + move.l a7,d1 // a7 sichern + move.l usp,a7 // a7 holen +.endif +.ifc 3,ia + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 (a2),(a1) + move.l d1,a2 // a2 zurück +.else + .ifc 3,iap + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 (a2)+,(a1) + .else + .ifc 3,iam + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 -(a2),(a1) + .else + move.\1 \2,(a1) + .endif + .endif +.endif +.ifc 3,a7 + movea.l a7,usp // a7 zurück + movea.l d1,a7 // a7 setzen +.endif + set_cc0 +.ifc 3,iap + move.l d1,a2 // a2 zurück +.endif +.ifc 3,iam + move.l d1,a2 // a2 zurück +.endif + ii_end +.endm +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) +//--------------------------------------------------------------------- + +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea --------------------------------------------- +//--------------------------------------------------------------------- +ii_move_d8_dest:.macro //1=dest 2=art 3=code 2.+3.stelle 4=art adresse +//byt +ii_0x1\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + moveb_a1_src\4 \1,\2 +ii_0x1\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + moveb_a1_src\4 \1,\2 +ii_0x1\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +//long +ii_0x2\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + movel_a1_src\4 \1,\2 +ii_0x2\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + movel_a1_src\4 \1,\2 +ii_0x2\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + movel_a1_src\4 \1,\2 +ii_0x2\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + movel_a1_src\4 \1,\2 +ii_0x2\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + movel_a1_src\4 \1,\2 +ii_0x2\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + movel_a1_src\4 \1,\2 +ii_0x2\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + movel_a1_src\4 \1,\2 +ii_0x2\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + movel_a1_src\4 \1,\2 +ii_0x2\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +//word +ii_0x3\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + movew_a1_src\4 \1,\2 +ii_0x3\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + movew_a1_src\4 \1,\2 +ii_0x3\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + movew_a1_src\4 \1,\2 +ii_0x3\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + movew_a1_src\4 \1,\2 +ii_0x3\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + movew_a1_src\4 \1,\2 +ii_0x3\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + movew_a1_src\4 \1,\2 +ii_0x3\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + movew_a1_src\4 \1,\2 +ii_0x3\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + movew_a1_src\4 \1,\2 +ii_0x3\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +.endm +//--------------------------------------------------------------------- +//dx +moveb_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.b (a1),\1_off+3(a7) +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.l (a1),\1_off(a7) +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.w (a1),\1_off+2(a7) +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// ax +moveb_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.w (a1),a1 + move.l a1,usp + .else + move.w (a1),\1_off+2(a7) + .endif +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.l (a1),a1 + move.l a1,usp + .else + move.l (a1),\1_off(a7) + .endif +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.w (a1),a1 + move.l a1,usp + .else + move.w (a1),\1_off+2(a7) + .endif +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// (ax) +moveb_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,(a1) +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,(a1) +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,(a1) +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// (ax)+ +moveb_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,(a1)+ + move.l a1,\1 +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,(a1)+ + move.l a1,\1 +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,(a1)+ + move.l a1,\1 +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// -(ax) +moveb_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,-(a1) + move.l a1,\1 +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,-(a1) + move.l a1,\1 +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,-(a1) + move.l a1,\1 +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm + +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea +//--------------------------------------------------------------------- + + + +/*============================================================ +// move.w dx,(a0,dx.w*SF) + ii_lset 0x3180 + ii_lset 0x3181 + ii_lset 0x3182 + ii_lset 0x3183 + ii_lset 0x3184 + ii_lset 0x3185 + ii_lset 0x3186 + ii_lset 0x3187 + +//-------------------------------------------------------------------- +// // move.w dx,d(ay,dz.w*sf) +//-------------------------------------------------------------------- +movew_ewfw:.macro + move.l \2,a1 + jsr ewf + move.w \1,(a1) + set_cc0 + ii_end + .endm +ii_0x3180: + movew_ewfw d0_off+2(a7),a0_off(a7) +ii_0x3181: + movew_ewfw d0_off+2(a7),a0_off(a7) +ii_0x3182: + movew_ewfw d2,a0_off(a7) +ii_0x3183: + movew_ewfw d3,a0_off(a7) +ii_0x3184: + movew_ewfw d4,a0_off(a7) +ii_0x3185: + movew_ewfw d5,a0_off(a7) +ii_0x3186: + movew_ewfw d6,a0_off(a7) +ii_0x3187: + movew_ewfw d7,a0_off(a7) diff --git a/BaS_GNU/sources/ii_movem.h b/BaS_GNU/sources/ii_movem.h new file mode 100644 index 0000000..5e8a470 --- /dev/null +++ b/BaS_GNU/sources/ii_movem.h @@ -0,0 +1,374 @@ +//***********************************************************************************/ +// movem +//***********************************************************************************/ +ii_movem_lset: .macro +// movem.l rx,xxx.L + ii_lset 0x48f9 +// movem.l xxx.L,rx + ii_lset 0x4cf9 +// movem.w rx,xxx.L + ii_lset 0x48b9 +// movem.w xxx.L,rx + ii_lset 0x4cb9 +// movem.l rx,-(ax) + ii_lset 0x48e0 + ii_lset 0x48e1 + ii_lset 0x48e2 + ii_lset 0x48e3 + ii_lset 0x48e4 + ii_lset 0x48e5 + ii_lset 0x48e6 + ii_lset 0x48e7 +// movem.l (ax)+,rx + ii_lset 0x4cd8 + ii_lset 0x4cd9 + ii_lset 0x4cda + ii_lset 0x4cdb + ii_lset 0x4cdc + ii_lset 0x4cdd + ii_lset 0x4cde + ii_lset 0x4cdf +.endm +//***********************************************************************************/ +ii_movem_func: .macro +//------------------------------------------------------------------- +// movem.l +//-------------------------------------------------------------------- +// movem.l (ax)+,reg +//-------------------------------------------------------------------- + .long 0 +az_reg_table: + .byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70 + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0 + .byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0 +//------------------------------------------------------------------------------- +ii_0x48e0: // movem.l reglist,-(a0) + mvm_mem_macro 0x48d0,a0_off(a7),2 +ii_0x48e1: // movem.l reglist,-(a1) + mvm_mem_macro 0x48d1,a1_off(a7),2 +ii_0x48e2: // movem.l reglist,-(a2) + mvm_mem_macro 0x48d2,a2,2 +ii_0x48e3: // movem.l reglist,-(a3) + mvm_mem_macro 0x48d3,a3,2 +ii_0x48e4: // movem.l reglist,-(a4) + mvm_mem_macro 0x48d4,a4,2 +ii_0x48e5: // movem.l reglist,-(a5) + mvm_mem_macro 0x48d5,a5,2 +ii_0x48e6: // movem.l reglist,-(a6) + mvm_mem_macro 0x48d6,a6,2 +ii_0x48e7: // movem.l reglist,-(a7) + mvm_mem_macro 0x48d7,usp,2 +//------------------------------------------------------------------------------- +ii_0x4cd8: // movem.l (a0)+,reglist + mvm_reg_macro 0x4cd0,0x41e8,2 +ii_0x4cd9: // movem.l (a1)+,reglist + mvm_reg_macro 0x4cd1,0x43e9,2 +ii_0x4cda: // movem.l (a2)+,reglist + mvm_reg_macro 0x4cd2,0x45ea,2 +ii_0x4cdb: // movem.l (a3)+,reglist + mvm_reg_macro 0x4cd3,0x47eb,2 +ii_0x4cdc: // movem.l (a4)+,reglist + mvm_reg_macro 0x4cd4,0x49ec,2 +ii_0x4cdd: // movem.l (a5)+,reglist + mvm_reg_macro 0x4cd5,0x4bed,2 +ii_0x4cde: // movem.l (a6)+,reglist + mvm_reg_macro 0x4cd6,0x4dee,2 +ii_0x4cdf: // movem.l (a7)+,reglist + mvm_reg_macro 0x4cd7,0x4fef,2 +//---------------------------------------------------------------------------- +ii_0x48f9: // movem.l reg,xxx.L +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro l +//--------------------------------------------------------------------------------------------- +ii_0x4cf9: // movem.l xxx.L,reg +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro l +//---------------------------------------------------------------------------- +ii_0x48b9: // movem.w reg,xxx.L +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro w +//--------------------------------------------------------------------------------------------- +ii_0x4cb9: // movem.w xxx.L,reg +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro w +.endm +//============================================================== +mvm_mem_macro:.macro +#ifdef halten_movem + halt +#endif + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lsl.l #\3,d1 // * anzahl byts pro wert + move.l \2,a1 + sub.l d1,a1 // ax-anzahl byts + move.l a1,\2 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x reg_list,-(a7) + move.w (a0)+,(a1)+ // register list + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte +.endm +//--------------------------------------------------------------------------------- +mvm_reg_macro:.macro +#ifdef halten_movem + halt +#endif + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x (ax),reg_list + move.w (a0)+,(a1)+ // register list + move.w #\2,(a1)+ // lea 0(ax),ax + lsl.l #\3,d1 // * anzahl byts pro wert + move.w d1,(a1)+ // offset von lea + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte +.endm +//--------------------------------------------------------------------------------- +movemrm_macro:.macro // in d0 register liste, in a1 zieladresse +#ifdef halten_movem + halt +#endif + tst.b d0 // datenregister zu verschieben? + bne mrm_dx\@ // ja-> + lsr.l #8,d0 // sonst zu addressregister + jmp mmrm_nd7\@ // -> +mrm_dx\@: + lsr.l #1,d0 + bcc mmrm_nd0\@ +.ifc 1,l + move.l d0_off(a7),(a1)+ +.else + move.w d0_off+2(a7),(a1)+ +.endif +mmrm_nd0\@: + lsr.l #1,d0 + bcc mmrm_nd1\@ +.ifc 1,l + move.l d1_off(a7),(a1)+ +.else + move.w d1_off+2(a7),(a1)+ +.endif +mmrm_nd1\@: + lsr.l #1,d0 + bcc mmrm_nd2\@ + move.\1 d2,(a1)+ +mmrm_nd2\@: + lsr.l #1,d0 + bcc mmrm_nd3\@ + move.\1 d3,(a1)+ +mmrm_nd3\@: + lsr.l #1,d0 + bcc mmrm_nd4\@ + move.\1 d4,(a1)+ +mmrm_nd4\@: + lsr.l #1,d0 + bcc mmrm_nd5\@ + move.\1 d5,(a1)+ +mmrm_nd5\@: + lsr.l #1,d0 + bcc mmrm_nd6\@ + move.l d6,(a1)+ +mmrm_nd6\@: + lsr.l #1,d0 + bcc mmrm_nd7\@ + move.\1 d7,(a1)+ +mmrm_nd7\@: + tst.b d0 // addressregister zu verschieben? + beq mmrm_na7\@ + lsr.l #1,d0 + bcc mmrm_na0\@ +.ifc 1,l + move.l a0_off(a7),(a1)+ +.else + move.w a0_off+2(a7),(a1)+ +.endif +mmrm_na0\@: + lsr.l #1,d0 + bcc mmrm_na1\@ +.ifc 1,l + move.l a1_off(a7),(a1)+ +.else + move.w a1_off+2(a7),(a1)+ +.endif +mmrm_na1\@: + lsr.l #1,d0 + bcc mmrm_na2\@ + move.\1 a2,(a1)+ +mmrm_na2\@: + lsr.l #1,d0 + bcc mmrm_na3\@ + move.\1 a3,(a1)+ +mmrm_na3\@: + lsr.l #1,d0 + bcc mmrm_na4\@ + move.\1 a4,(a1)+ +mmrm_na4\@: + lsr.l #1,d0 + bcc mmrm_na5\@ + move.\1 a5,(a1)+ +mmrm_na5\@: + lsr.l #1,d0 + bcc mmrm_na6\@ + move.\1 a6,(a1)+ +mmrm_na6\@: + lsr.l #1,d0 + bcc mmrm_na7\@ + move.l a0,d1 // sichern + move.l usp,a0 // ist ja usp + move.\1 a0,(a1)+ // nach a0 + move.l d1,a0 // pc zurück +mmrm_na7\@: + ii_end + .endm +//--------------------------------------------------------------------------------------------- +movemmr_macro:.macro // in d0 register liste, in a1 source adr +#ifdef halten_movem + halt +#endif + tst.b d0 // datenregister zu verschieben? + bne mmr_dx\@ // ja-> + lsr.l #8,d0 // sonst zu addressregister + bra mmmr_nd7\@ // -> +mmr_dx\@: + lsr.l #1,d0 + bcc mmmr_nd0\@ +.ifc 1,l + move.l (a1)+,d0_off(a7) +.else + move.w (a1)+,d0_off+2(a7) +.endif +mmmr_nd0\@: + lsr.l #1,d0 + bcc mmmr_nd1\@ +.ifc 1,l + move.l (a1)+,d1_off(a7) +.else + move.w (a1)+,d1_off+2(a7) +.endif +mmmr_nd1\@: + lsr.l #1,d0 + bcc mmmr_nd2\@ + move.\1 (a1)+,d2 +mmmr_nd2\@: + lsr.l #1,d0 + bcc mmmr_nd3\@ + move.\1 (a1)+,d3 +mmmr_nd3\@: + lsr.l #1,d0 + bcc mmmr_nd4\@ + move.\1 (a1)+,d4 +mmmr_nd4\@: + lsr.l #1,d0 + bcc mmmr_nd5\@ + move.\1 (a1)+,d5 +mmmr_nd5\@: + lsr.l #1,d0 + bcc mmmr_nd6\@ + move.\1 (a1)+,d6 +mmmr_nd6\@: + lsr.l #1,d0 + bcc mmmr_nd7\@ + move.\1 (a1)+,d7 +mmmr_nd7\@: + tst.b d0 // addressregister zu verschieben? + beq mmmr_na7\@ // nein-> + lsr.l #1,d0 + bcc mmmr_na0\@ +.ifc 1,l + move.l (a1)+,a0_off(a7) +.else + move.w (a1)+,a0_off+2(a7) +.endif +mmmr_na0\@: + lsr.l #1,d0 + bcc mmmr_na1\@ +.ifc 1,l + move.l (a1)+,a1_off(a7) +.else + move.w (a1)+,a1_off+2(a7) +.endif +mmmr_na1\@: + lsr.l #1,d0 + bcc mmmr_na2\@ + move.\1 (a1)+,a2 +mmmr_na2\@: + lsr.l #1,d0 + bcc mmmr_na3\@ + move.\1 (a1)+,a3 +mmmr_na3\@: + lsr.l #1,d0 + bcc mmmr_na4\@ + move.\1 (a1)+,a4 +mmmr_na4\@: + lsr.l #1,d0 + bcc mmmr_na5\@ + move.\1 (a1)+,a5 +mmmr_na5\@: + lsr.l #1,d0 + bcc mmmr_na6\@ + move.\1 (a1)+,a6 +mmmr_na6\@: + lsr.l #1,d0 + bcc mmmr_na7\@ + move.\1 (a1)+,a1 // nach a0 + move.l a1,usp // war ja usp +mmmr_na7\@: + ii_end + .endm diff --git a/BaS_GNU/sources/ii_movep.h b/BaS_GNU/sources/ii_movep.h new file mode 100644 index 0000000..830fdf7 --- /dev/null +++ b/BaS_GNU/sources/ii_movep.h @@ -0,0 +1,179 @@ +//-------------------------------------------------------------------- +// movep +//-------------------------------------------------------------------- +.text +ii_movep_lset:.macro + ii_lset_opeau 01,0 //movep.w d(a0-7),d0 + ii_lset_opeau 03,0 //movep.w d(a0-7),d1 + ii_lset_opeau 05,0 //movep.w d(a0-7),d2 + ii_lset_opeau 07,0 //movep.w d(a0-7),d3 + ii_lset_opeau 09,0 //movep.w d(a0-7),d4 + ii_lset_opeau 0b,0 //movep.w d(a0-7),d5 + ii_lset_opeau 0d,0 //movep.w d(a0-7),d6 + ii_lset_opeau 0f,0 //movep.w d(a0-7),d7 + + ii_lset_opeau 01,4 //movep.w d0,d(a0-7) + ii_lset_opeau 03,4 //movep.w d1,d(a0-7) + ii_lset_opeau 05,4 //movep.w d2,d(a0-7) + ii_lset_opeau 07,4 //movep.w d3,d(a0-7) + ii_lset_opeau 09,4 //movep.w d4,d(a0-7) + ii_lset_opeau 0b,4 //movep.w d5,d(a0-7) + ii_lset_opeau 0d,4 //movep.w d6,d(a0-7) + ii_lset_opeau 0f,4 //movep.w d7,d(a0-7) + + ii_lset_opeau 01,8 //movep.l d(a0-7),d0 + ii_lset_opeau 03,8 //movep.l d(a0-7),d1 + ii_lset_opeau 05,8 //movep.l d(a0-7),d2 + ii_lset_opeau 07,8 //movep.l d(a0-7),d3 + ii_lset_opeau 09,8 //movep.l d(a0-7),d4 + ii_lset_opeau 0b,8 //movep.l d(a0-7),d5 + ii_lset_opeau 0d,8 //movep.l d(a0-7),d6 + ii_lset_opeau 0f,8 //movep.l d(a0-7),d7 + + ii_lset_opeau 01,c //movep.l d0,d(a0-7) + ii_lset_opeau 03,c //movep.l d1,d(a0-7) + ii_lset_opeau 05,c //movep.l d2,d(a0-7) + ii_lset_opeau 07,c //movep.l d3,d(a0-7) + ii_lset_opeau 09,c //movep.l d4,d(a0-7) + ii_lset_opeau 0b,c //movep.l d5,d(a0-7) + ii_lset_opeau 0d,c //movep.l d6,d(a0-7) + ii_lset_opeau 0f,c //movep.l d7,d(a0-7) +.endm +//--------------------------------------------------------------------------------------------- +ii_movep_func:.macro +//movep.w d(a0-7),d0-7 + ii_movep 010,d0_off(a7),wad + ii_movep 030,d1_off(a7),wad + ii_movep 050,d2,wad + ii_movep 070,d3,wad + ii_movep 090,d4,wad + ii_movep 0b0,d5,wad + ii_movep 0d0,d6,wad + ii_movep 0f0,d7,wad +//movep.w d0-7,d(a0-7) + ii_movep 014,d0_off(a7),wda + ii_movep 034,d1_off(a7),wda + ii_movep 054,d2,wda + ii_movep 074,d3,wda + ii_movep 094,d4,wda + ii_movep 0b4,d5,wda + ii_movep 0d4,d6,wda + ii_movep 0f4,d7,wda +//movep.l d(a0-7),d0-7 + ii_movep 018,d0_off(a7),lad + ii_movep 038,d1_off(a7),lad + ii_movep 058,d2,lad + ii_movep 078,d3,lad + ii_movep 098,d4,lad + ii_movep 0b8,d5,lad + ii_movep 0d8,d6,lad + ii_movep 0f8,d7,lad +//movep.l d0-7,d(a0-7) + ii_movep 01c,d0_off(a7),lda + ii_movep 03c,d1_off(a7),lda + ii_movep 05c,d2,lda + ii_movep 07c,d3,lda + ii_movep 09c,d4,lda + ii_movep 0bc,d5,lda + ii_movep 0dc,d6,lda + ii_movep 0fc,d7,lda +.endm +//--------------------------------------------------------------------------------------------- +ii_movep:.macro //1=code ziffer 1-3 2=register 3=art +ii_0x\18: +#ifdef halten_movep + halt +#endif + move.l a0_off(a7),a1 + ii_movep\3_up1 \2 +ii_0x\19: +#ifdef halten_movep + halt +#endif + move.l a1_off(a7),a1 + ii_movep\3_up1 \2 +ii_0x\1a: +#ifdef halten_movep + halt +#endif + move.l a2,a1 + ii_movep\3_up1 \2 +ii_0x\1b: +#ifdef halten_movep + halt +#endif + move.l a3,a1 + ii_movep\3_up1 \2 +ii_0x\1c: +#ifdef halten_movep + halt +#endif + move.l a4,a1 + ii_movep\3_up1 \2 +ii_0x\1d: +#ifdef halten_movep + halt +#endif + move.l a5,a1 + ii_movep\3_up1 \2 +ii_0x\1e: +#ifdef halten_movep + halt +#endif + move.l a6,a1 + ii_movep\3_up1 \2 +ii_0x\1f: +#ifdef halten_movep + halt +#endif + move.l usp,a1 + ii_movep\3_up1 \2 +.endm + +ii_movepwad_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.b (a1),d0 + lsl.l #8,d0 + move.b 2(a1,d1.l),d0 + move.w d0,\1 + ii_end +.endm + +ii_movepwda_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.w \1,d0 + move.b d0,2(a1) + lsr.l #8,d0 + move.b d0,(a1) + ii_end +.endm + +ii_moveplad_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.b (a1),d0 + lsl.l #8,d0 + move.b 2(a1),d0 + lsl.l #8,d0 + move.b 4(a1),d0 + lsl.l #8,d0 + move.b 6(a1),d0 + move.l d0,\1 + ii_end +.endm + +ii_moveplda_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.l \1,d0 + move.b d0,6(a1) + lsr.l #8,d0 + move.b d0,4(a1) + lsr.l #8,d0 + move.b d0,2(a1) + lsr.l #8,d0 + move.b d0,(a1) + ii_end +.endm diff --git a/BaS_GNU/sources/ii_op.h b/BaS_GNU/sources/ii_op.h new file mode 100644 index 0000000..a3fc0cf --- /dev/null +++ b/BaS_GNU/sources/ii_op.h @@ -0,0 +1,661 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_lset_op:.macro +//byt + ii_lset_opea \1,0 // dx,ax + ii_lset_opea \1,1 // (ax), (ax)+ + ii_lset_opea \1,2 // -(ax),d16(ax) + ii_lset_opeag \1,3 // d8(ax,dy) + lea table+0x\1\238*4,a0 + move.l #ii_0x\138,(a0)+ // xxx.w + move.l #ii_0x\139,(a0)+ // xxx.l +//word + ii_lset_opea \1,4 // dx,ax + ii_lset_opea \1,5 // (ax), (ax)+ + ii_lset_opea \1,6 // -(ax),d16(ax) + ii_lset_opeag \1,7 // d8(ax,dy) + lea table+0x\178*4,a0 + move.l #ii_0x\178,(a0)+ // xxx.w + move.l #ii_0x\179,(a0)+ // xxx.l +//long + ii_lset_opea \1,8 // dx,ax + ii_lset_opea \1,9 // (ax), (ax)+ + ii_lset_opea \1,a // -(ax),d16(ax) + ii_lset_opeag \1,b // d8(ax,dy) + lea table+0x\1b8*4,a0 + move.l #ii_0x\1b8,(a0)+ // xxx.w + move.l #ii_0x\1b9,(a0)+ // xxx.l + .endm + +ii_lset_opeag:.macro // 0x1120-0x1127 + lea table+0x\1\20*4,a0 + move.l #ii_0x\1\20,(a0)+ + move.l #ii_0x\1\21,(a0)+ + move.l #ii_0x\1\22,(a0)+ + move.l #ii_0x\1\23,(a0)+ + move.l #ii_0x\1\24,(a0)+ + move.l #ii_0x\1\25,(a0)+ + move.l #ii_0x\1\26,(a0)+ + move.l #ii_0x\1\27,(a0)+ + .endm; + +ii_lset_opeau:.macro // 0x1128-0x112f + lea table+0x\1\28*4,a0 + move.l #ii_0x\1\28,(a0)+ + move.l #ii_0x\1\29,(a0)+ + move.l #ii_0x\1\2a,(a0)+ + move.l #ii_0x\1\2b,(a0)+ + move.l #ii_0x\1\2c,(a0)+ + move.l #ii_0x\1\2d,(a0)+ + move.l #ii_0x\1\2e,(a0)+ + move.l #ii_0x\1\2f,(a0)+ + .endm; + +ii_lset_opea:.macro + ii_lset_opeag \1,\2 + ii_lset_opeau \1,\2 + .endm +/******************************************************/ +ii_op:.macro // 1=code 2=operation 3 = normal oder immediat/quick +// byt + opdx \1,\2,b,0,\3 // dx,ax + opia \1,\2,b,1,\3 // (ax),(ax)+ + opdia \1,\2,b,2,\3 // -(ax),d16(ax) + opd8a \1,\2,b,3,\3 // d8(ax),xxx +// word + opdx \1,\2,w,4,\3 // dx,ax + opia \1,\2,w,5,\3 // (ax),(ax)+ + opdia \1,\2,w,6,\3 // -(ax),d16(ax) + opd8a \1,\2,w,7,\3 // d8(ax),xxx +// long + opdx \1,\2,l,8,\3 // dx,ax + opia \1,\2,l,9,\3 // (ax),(ax)+ + opdia \1,\2,l,a,\3 // -(ax),d16(ax) + opd8a \1,\2,l,b,\3 // d8(ax),xxx + .endm +/******************************************************/ +// byt word long +/******************************************************/ +opdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + .ifc \3,b + op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 + .else + op\5smd \2,d0_off(a7),d0_off(a7),\3 + .endif + .endif +ii_0x\1\41: + .ifc \3,b + op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 + .else + op\5smd \2,d1_off(a7),d1_off(a7),\3 + .endif +.endif +ii_0x\1\42: + op\5smd \2,d2,d2,\3 +ii_0x\1\43: + op\5smd \2,d3,d3,\3 +ii_0x\1\44: + op\5smd \2,d4,d4,\3 +ii_0x\1\45: + op\5smd \2,d5,d5,\3 +ii_0x\1\46: + op\5smd \2,d6,d6,\3 +ii_0x\1\47: + op\5smd \2,d7,d7,\3 +//ax +ii_0x\1\48: + opa\5smd \2,a0_off(a7),a0_off(a7),\3 +ii_0x\1\49: + opa\5smd \2,a1_off(a7),a1_off(a7),\3 +ii_0x\1\4a: + opa\5smd \2,a2,a2,\3 +ii_0x\1\4b: + opa\5smd \2,a3,a3,\3 +ii_0x\1\4c: + opa\5smd \2,a4,a4,\3 +ii_0x\1\4d: + opa\5smd \2,a5,a5,\3 +ii_0x\1\4e: + opa\5smd \2,a6,a6,\3 +ii_0x\1\4f: + opa\5smd \2,usp,usp,\3 +.endm; +//----------------------------------------------- +opia: .macro // (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +//(ax) +ii_0x\1\40: + op\5sia \2,a0_off(a7),(a1),(a1),\3 +ii_0x\1\41: + op\5sia \2,a1_off(a7),(a1),(a1),\3 +ii_0x\1\42: + op\5smd \2,(a2),(a2),\3 +ii_0x\1\43: + op\5smd \2,(a3),(a3),\3 +ii_0x\1\44: + op\5smd \2,(a4),(a4),\3 +ii_0x\1\45: + op\5smd \2,(a5),(a5),\3 +ii_0x\1\46: + op\5smd \2,(a6),(a6),\3 +ii_0x\1\47: + op\5sia \2,usp,(a1),(a1),\3 +//(ax)+ +ii_0x\1\48: + op\5sia \2,a0_off(a7),(a1),(a1)+,\3 +ii_0x\1\49: + op\5sia \2,a1_off(a7),(a1),(a1)+,\3 +ii_0x\1\4a: + op\5smd \2,(a2),(a2)+,\3 +ii_0x\1\4b: + op\5smd \2,(a3),(a3)+,\3 +ii_0x\1\4c: + op\5smd \2,(a4),(a4)+,\3 +ii_0x\1\4d: + op\5smd \2,(a5),(a5)+,\3 +ii_0x\1\4e: + op\5smd \2,(a6),(a6)+,\3 +ii_0x\1\4f: + op\5sia \2,usp,(a1),(a1)+,\3 +.endm; +//----------------------------------------------- +opdia: .macro // -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + op\5sia \2,a0_off(a7),-(a1),(a1),\3 +ii_0x\1\41: + op\5sia \2,a1_off(a7),-(a1),(a1),\3 +ii_0x\1\42: + op\5smd \2,-(a2),(a2),\3 +ii_0x\1\43: + op\5smd \2,-(a3),(a3),\3 +ii_0x\1\44: + op\5smd \2,-(a4),(a4),\3 +ii_0x\1\45: + op\5smd \2,-(a5),(a5),\3 +ii_0x\1\46: + op\5smd \2,-(a6),(a6),\3 +ii_0x\1\47: + op\5sia \2,usp,-(a1),(a1),\3 + +ii_0x\1\48: + op\5sd16a \2,a0_off(a7),\3 +ii_0x\1\49: + op\5sd16a \2,a1_off(a7),\3 +ii_0x\1\4a: + op\5sd16a \2,a2,\3 +ii_0x\1\4b: + op\5sd16a \2,a3,\3 +ii_0x\1\4c: + op\5sd16a \2,a4,\3 +ii_0x\1\4d: + op\5sd16a \2,a5,\3 +ii_0x\1\4e: + op\5sd16a \2,a6,\3 +ii_0x\1\4f: + op\5sd16a \2,usp,\3 +.endm; +//----------------------------------------------- +opd8a: .macro // d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + op\5sd8a \2,a0_off(a7),\3 +ii_0x\1\41: + op\5sd8a \2,a1_off(a7),\3 +ii_0x\1\42: + op\5sd8a \2,a2,\3 +ii_0x\1\43: + op\5sd8a \2,a3,\3 +ii_0x\1\44: + op\5sd8a \2,a4,\3 +ii_0x\1\45: + op\5sd8a \2,a5,\3 +ii_0x\1\46: + op\5sd8a \2,a6,\3 +ii_0x\1\47: + op\5sd8a \2,usp,\3 + +ii_0x\1\48: + op\5sxx \2,\3,w +ii_0x\1\49: + op\5sxx \2,\3,l +.endm; +//----------------------------------------------- +opnsmd:.macro // direct dx: 1=operation 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opansmd:.macro // direct ax: 1=operation 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d1 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end +.endm; + +opnsia:.macro // indirect: 1=operation 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opnsd16a:.macro // indirect: 1=operation 2=adress register 3=size +#ifdef halten_op + halt +#endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opnsd8a:.macro // indirect: 1=operation 2=adress register 3=size +#ifdef halten_op + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opnsxx:.macro // indirect: 1=operation 2=size 3=size adresse +#ifdef halten_op + halt +#endif + +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif + move.\3 (a0)+,a1 + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; +//*******************************************************************************3 +opismd:.macro // immediate dx: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\4 d1,\3 +.endif + ii_end +.endm; + +opaismd:.macro // immediate ax: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d0,d1 +.ifnc \1,cmp.l +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif +.endif + ii_end +.endm; + +opisia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + +.ifc \5,l + move.l (a0)+,d0 +.else + .ifc \5,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\5 d1,\4 +.endif + ii_end +.endm; + +opisd16a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + +.ifc \3,l + move.l (a0)+,d0 +.else + .ifc \3,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\3 d1,(a1) +.endif + ii_end + .endm; + +opisd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + +.ifc \3,l + move.l (a0)+,d0 +.else + .ifc \3,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\3 d1,(a1) +.endif + ii_end + .endm; + +opisxx:.macro // immediate: 1=opieration 2=size 3=size adresse +.ifc \2,l + move.l (a0)+,d0 +.else + .ifc \2,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\2 d1,(a1) +.endif + ii_end + .endm; +//*******************************************************************************3 +opqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opaqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 ,d1 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end + .endm; + +opqsia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opqsd16a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opqsd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opqsxx:.macro // quick: 1=opieration 2=size 3=size adresse +#ifdef halten_op + halt +#endif + + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; diff --git a/BaS_GNU/sources/ii_opc.h b/BaS_GNU/sources/ii_opc.h new file mode 100644 index 0000000..8b887ce --- /dev/null +++ b/BaS_GNU/sources/ii_opc.h @@ -0,0 +1,263 @@ +/*****************************************************************************************/ +// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax +// zusammen mit op.h +/*****************************************************************************************/ +ii_lset_opc:.macro + ii_lset_opeag \1,c // dx,ax + ii_lset_opea \1,d // (ax), (ax)+ + ii_lset_opea \1,e // -(ax),d16(ax) + ii_lset_opeag \1,f // d8(ax,dy) + lea table+0x\1b8*4,a0 + move.l #ii_0x\1b8,(a0)+ // xxx.w + move.l #ii_0x\1b9,(a0)+ // xxx.l + .endm + +/******************************************************/ +ii_opc:.macro // 1=code 2=operation 3 = normal oder immediat + opcdx \1,\2,l,c,\3 // dx,ax + opia \1,\2,l,d,\3 // (ax),(ax)+ + opdia \1,\2,l,e,\3 // -(ax),d16(ax) + opd8a \1,\2,l,f,\3 // d8(ax),xxx + .endm +//*******************************************************************************3 +/******************************************************/ +// byt word long +/******************************************************/ +opcdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: +#ifdef halten_opc + halt +#endif + .ifc \3,b + op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 + .else + op\5smd \2,d0_off(a7),d0_off(a7),\3 + .endif + .endif +ii_0x\1\41: + .ifc \3,b + op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 + .else + op\5smd \2,d1_off(a7),d1_off(a7),\3 + .endif +.endif +ii_0x\1\42: + op\5smd \2,d2,d2,\3 +ii_0x\1\43: + op\5smd \2,d3,d3,\3 +ii_0x\1\44: + op\5smd \2,d4,d4,\3 +ii_0x\1\45: + op\5smd \2,d5,d5,\3 +ii_0x\1\46: + op\5smd \2,d6,d6,\3 +ii_0x\1\47: + op\5smd \2,d7,d7,\3 +.endm +//----------------------------------------------------- +opcsmd:.macro // dx: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opacsmd:.macro // ax: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d1 + set_cc0 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end + .endm; + +opcsia:.macro // (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opcsd16a:.macro // d16(ax): 1=opieration 2=adress register 3=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opcsd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opcsxx:.macro // indirect: 1=opieration 2=size 3=size adresse +#ifdef halten_opc + halt +#endif + +.ifc \2,l + move.l (a0)+,d0 +.else + .ifc \2,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; diff --git a/BaS_GNU/sources/ii_or.h b/BaS_GNU/sources/ii_or.h new file mode 100644 index 0000000..dfe4450 --- /dev/null +++ b/BaS_GNU/sources/ii_or.h @@ -0,0 +1,442 @@ +//-------------------------------------------------------------------- +// or +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// or.b #im,dx +//-------------------------------------------------------------------- +orbir_macro:.macro +#ifdef halten_or + halt +#endif + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + or.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea,dx +//-------------------------------------------------------------------- +ordd:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +orddd:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or (ea)->dy,dx +//-------------------------------------------------------------------- +ordda:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +orddai:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea->ay,-(ay),dx +//-------------------------------------------------------------------- +orddad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d16(ay),dx +//-------------------------------------------------------------------- +ord16ad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d8(ay,dy),dx +//-------------------------------------------------------------------- +ord8ad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or xxx.w,dx +//-------------------------------------------------------------------- +orxwd:.macro +#ifdef halten_or + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or xxx.l,dx +//-------------------------------------------------------------------- +orxld:.macro +#ifdef halten_or + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d16(pc),dx +//-------------------------------------------------------------------- +ord16pcd:.macro + halt + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d8(pc,dy),dx +//-------------------------------------------------------------------- +ord8pcd:.macro +#ifdef halten_or + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// or dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // or (ea)->dy,dx +//-------------------------------------------------------------------- +oreda:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +oredai:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +oredaid:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +oredad:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +oredadd:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,d16(ay) +//-------------------------------------------------------------------- +ore16ad:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or.w dx,d8(ay,dy) +//-------------------------------------------------------------------- +ore8ad:.macro +#ifdef halten_or + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,xxx.w +//-------------------------------------------------------------------- +orxwe:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,xxx.l +//-------------------------------------------------------------------- +orxle:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // ora.w ea,ax +//-------------------------------------------------------------------- +oraw:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// or.w ea,usp +//-------------------------------------------------------------------- +orawa7:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w usp?,ax +//-------------------------------------------------------------------- +orawu:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w usp?,usp +//-------------------------------------------------------------------- +orawua7:.macro + orawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // ora.w d16(ay),ax +//-------------------------------------------------------------------- +orawd16a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d8(ay,dy),ax +//-------------------------------------------------------------------- +orawd8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w xxx.w,ax +//-------------------------------------------------------------------- +orawxwax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w xxx.l,ax +//-------------------------------------------------------------------- +orawxlax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d16(pc),ax +//-------------------------------------------------------------------- +orawd16pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d8(pc,dy),ax +//-------------------------------------------------------------------- +orawd8pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w #im,ax +//-------------------------------------------------------------------- +orawim:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.l d8(ay,dy),ax +//-------------------------------------------------------------------- +orald8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.l d8(pc,dy),ax +//-------------------------------------------------------------------- +orald8pcax:.macro + jmp ii_error + .endm; +//***************************************************************************************** +// spezial addx subx etc. +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +ordx:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +ordax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_pea.h b/BaS_GNU/sources/ii_pea.h new file mode 100644 index 0000000..69f69d0 --- /dev/null +++ b/BaS_GNU/sources/ii_pea.h @@ -0,0 +1,74 @@ +//-------------------------------------------------------------------- +// pea +//-------------------------------------------------------------------- +.text +ii_pea_lset:.macro + ii_lset_opeag 48,7 + ii_lset 0x487b +.endm +//--------------------------------------------------------------------------------------------- +ii_pea_func:.macro +ii_0x4870: +#ifdef halten_pea + halt +#endif + move.l a0_off(a7),a1 + pea_macro +ii_0x4871: +#ifdef halten_pea + halt +#endif + move.l a1_off(a7),a1 + pea_macro +ii_0x4872: +#ifdef halten_pea + halt +#endif + move.l a2,a1 + pea_macro +ii_0x4873: +#ifdef halten_pea + halt +#endif + move.l a3,a1 + pea_macro +ii_0x4874: +#ifdef halten_pea + halt +#endif + move.l a4,a1 + pea_macro +ii_0x4875: +#ifdef halten_pea + halt +#endif + move.l a5,a1 + pea_macro +ii_0x4876: +#ifdef halten_pea + halt +#endif + move.l a6,a1 + pea_macro +ii_0x4877: +#ifdef halten_pea + halt +#endif + move.l usp,a1 + pea_macro +ii_0x487b: +#ifdef halten_pea + halt +#endif + move.l a0,a1 + pea_macro +.endm +//--------------------------------------------------------------------------------------------- +pea_macro:.macro + jsr ewf + move.l (a1),d0 + move.l usp,a1 + move.l d0,-(a1) + move.l a1,usp + ii_end +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_shd.h b/BaS_GNU/sources/ii_shd.h new file mode 100644 index 0000000..ecace29 --- /dev/null +++ b/BaS_GNU/sources/ii_shd.h @@ -0,0 +1,247 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_lset_shd:.macro + ii_lset_shdx e0 //r d0 + ii_lset_shdx e2 //r d1 + ii_lset_shdx e4 //r d2 + ii_lset_shdx e6 //r d3 + ii_lset_shdx e8 //r d4 + ii_lset_shdx ea //r d5 + ii_lset_shdx ec //r d6 + ii_lset_shdx ee //r d7 + + ii_lset_shdx e1 //l d0 + ii_lset_shdx e3 //l d1 + ii_lset_shdx e4 //l d2 + ii_lset_shdx e5 //l d3 + ii_lset_shdx e9 //l d4 + ii_lset_shdx eb //l d5 + ii_lset_shdx ed //l d6 + ii_lset_shdx ef //l d7 + .endm + +ii_lset_shdx:.macro +//byt + ii_lset_opea \1,0 // as,ls #im,dx + ii_lset_opea \1,1 // rox,ro #im,dx + ii_lset_opea \1,2 // as,ls dy,dx + ii_lset_opea \1,3 // rox,ro dy,dx +//word + ii_lset_opea \1,4 // as,ls #im,dx + ii_lset_opea \1,5 // rox,ro #im,dx + ii_lset_opea \1,6 // as,ls dy,dx + ii_lset_opea \1,7 // rox,ro dy,dx +//long +// ii_lset_opea \1,8 // as,ls #im,dx -> vorhanden + ii_lset_opea \1,9 // rox,ro #im,dx +// ii_lset_opea \1,a // as,ls dy,dx -> vorhanden + ii_lset_opea \1,b // rox,ro dy,dx + .endm +/******************************************************/ +ii_shd:.macro // 1=code 2=operation 3 = normal, direct oder immediat +// byt + opdx \1,\2,b,0,\3 // dx +// word + opdx \1,\2,w,4,\3 // dx +// long + opdx \1,\2,l,8,\3 // dx + .endm +/******************************************************/ +// byt word long routinen +/******************************************************/ +sh_asr: .macro // asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvs.\4 \2,d1 + sh_shal \1,\2,\3,\4 + .endm + +sh_lsr: .macro // asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvz.\4 \2,d1 + sh_shal \1,\2,\3,\4 + .endm + +sh_shal:.macro + move.w \3,d0 + \1.l d0,d1 + set_cc0 + move.\4 d1,\2 + .endm + +sh_all: .macro // asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvz.\4 \2,d1 +.ifc \4,b + byterev.l d1 +.else + swap.w d1 +.endif + sh_asr \1,\2,\3,\4 + .endm + +sh_ror: .macro // ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + move.\4 \2,d1 / + move.w \3,d0 +.ifc \4,b + lsl.l #8,d1 + move.b \2,d1 + and.l #0x7,d0 + lsr.l d0,d1 +.else + .ifc \4,w + swap.w d1 + move.w \2,d1 + and.l #0xf,d0 + lsr.l d0,d1 + .else + and.l #0x1f,d0 + lsr.l d0,d1 + move.l d1,a1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsl.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + move.w ccr,d0 + and.l #1,d1 // ist auch carry bit + or.l d1,d0 + move.b d0,ccr_off(a7) + .endm + +sh_rol: .macro // rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + move.\4 \2,d1 + move.w \3,d0 +.ifc \4,b + lsl.l #8,d1 + move.b \2,d1 + and.l #0x7,d0 + lsl.l d0,d1 + lsr.l #8,d1 + moveq #7,d0 +.else + .ifc \4,w + swap.w d1 + move.w \2,d1 + and.l #0xf,d0 + lsr.l d0,d1 + swap.w d1 + moveq #15,d0 + .else + and.l #0x1f,d0 + lsl.l d0,d1 + move.l d1,a1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsr.l d0,d1 + add.l a1,d1 + moveq #31,d0 + .endif +.endif + move.\4 d1,\2 + lsr.l d0,d1 // carry bit schieben + move.w ccr,d0 + and.l #1,d1 + or.l d1,d0 + move.b d0,ccr_off(a7) + .endm + +sh_roxr: .macro // roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + clr.l d0 + addx.l d0,d0 +ifc \4,b + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + move.b \2,d1 + move.w \3,d0 + and.l #0x7,d0 + lsr.l d0,d1 + set_cc0 +else + .ifc \4,w + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + lsl.l #8,d1 + move.w \2,d1 + move.w \3,d0 + and.l #0xf,d0 + lsr.l d0,d1 + set_cc0 + .else + bitrev.l d0 + move.l \2,d1 + lsr.l #1,d1 + add.l d0,d1 + move.w \3,d0 + subq.l #1,d0 + and.l #0x1f,d0 + lsr.l d0,d1 + move.l d1,a1 + set_cc1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsl.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + .endm + +sh_roxl: .macro // roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + clr.l d0 + addx.l d0,d0 +ifc \4,b + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + move.b \2,d1 + lsl.l #8,d1 + lsl.l #7,d1 + move.w \3,d0 + and.l #0x7,d0 + lsl.l d0,d1 + set_cc0 + byterev.l d1 +else + .ifc \4,w + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + lsl.l #7,d1 + mvz.w \2,d0 + lsr.l #1,d0 + add.l d0,d1 + move.w \3,d0 + and.l #0xf,d0 + lsl.l d0,d1 + set_cc0 + swap.w d1 + .else + move.l \2,d1 + lsl.l #1,d1 + add.l d0,d1 + move.w \3,d0 + subq.l #1,d0 + and.l #0x1f,d0 + lsl.l d0,d1 + move.l d1,a1 + set_cc1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsr.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + .endm + + \ No newline at end of file diff --git a/BaS_GNU/sources/ii_shift.h b/BaS_GNU/sources/ii_shift.h new file mode 100644 index 0000000..f83bfcb --- /dev/null +++ b/BaS_GNU/sources/ii_shift.h @@ -0,0 +1,687 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_shift_lset:.macro +/******************************************************/ +// byt +/******************************************************/ +// asx.b #,dx + ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,01 + ii_lset_dx \1,02 + ii_lset_dx \1,03 + ii_lset_dx \1,04 + ii_lset_dx \1,05 + ii_lset_dx \1,06 + ii_lset_dx \1,07 +// lsx.b #,dx + ii_lset_dxu \1,08 + ii_lset_dxu \1,09 + ii_lset_dxu \1,0a + ii_lset_dxu \1,0b + ii_lset_dxu \1,0c + ii_lset_dxu \1,0d + ii_lset_dxu \1,0e + ii_lset_dxu \1,0f +// roxx.b #,dx + ii_lset_dx \1,10 + ii_lset_dx \1,11 + ii_lset_dx \1,12 + ii_lset_dx \1,13 + ii_lset_dx \1,14 + ii_lset_dx \1,15 + ii_lset_dx \1,16 + ii_lset_dx \1,17 +// rox.b #,dx + ii_lset_dx \1,18 + ii_lset_dx \1,19 + ii_lset_dx \1,1a + ii_lset_dx \1,1b + ii_lset_dx \1,1c + ii_lset_dx \1,1d + ii_lset_dx \1,1e + ii_lset_dx \1,1f +// asx.b dy,dx + ii_lset_dx \1,20 + ii_lset_dx \1,21 + ii_lset_dx \1,22 + ii_lset_dx \1,23 + ii_lset_dx \1,24 + ii_lset_dx \1,25 + ii_lset_dx \1,26 + ii_lset_dx \1,27 +// lsx.b dy,dx + ii_lset_dx \1,28 + ii_lset_dx \1,29 + ii_lset_dx \1,2a + ii_lset_dx \1,2b + ii_lset_dx \1,2c + ii_lset_dx \1,2d + ii_lset_dx \1,2e + ii_lset_dx \1,2f +// roxx.dy,dx + ii_lset_dx \1,30 + ii_lset_dx \1,31 + ii_lset_dx \1,32 + ii_lset_dx \1,33 + ii_lset_dx \1,34 + ii_lset_dx \1,35 + ii_lset_dx \1,36 + ii_lset_dx \1,37 +// rox.b dy,dx + ii_lset_dx \1,38 + ii_lset_dx \1,39 + ii_lset_dx \1,3a + ii_lset_dx \1,3b + ii_lset_dx \1,3c + ii_lset_dx \1,3d + ii_lset_dx \1,3e + ii_lset_dx \1,3f +/******************************************************/ +// word +/******************************************************/ +// asx.w #x,dx + ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,41 + ii_lset_dx \1,42 + ii_lset_dx \1,43 + ii_lset_dx \1,44 + ii_lset_dx \1,45 + ii_lset_dx \1,46 + ii_lset_dx \1,47 +// lsx.w #,dx + ii_lset_dx \1,48 + ii_lset_dx \1,49 + ii_lset_dx \1,4a + ii_lset_dx \1,4b + ii_lset_dx \1,4c + ii_lset_dx \1,4d + ii_lset_dx \1,4e + ii_lset_dx \1,4f +// roxx.w #,dx + ii_lset_dx \1,50 + ii_lset_dx \1,51 + ii_lset_dx \1,52 + ii_lset_dx \1,53 + ii_lset_dx \1,54 + ii_lset_dx \1,55 + ii_lset_dx \1,56 + ii_lset_dx \1,57 +// rox.w #xdx + ii_lset_dx \1,58 + ii_lset_dx \1,59 + ii_lset_dx \1,5a + ii_lset_dx \1,5b + ii_lset_dx \1,5c + ii_lset_dx \1,5d + ii_lset_dx \1,5e + ii_lset_dx \1,5f +// asx.w dy,dx + ii_lset_dx \1,60 + ii_lset_dx \1,61 + ii_lset_dx \1,62 + ii_lset_dx \1,63 + ii_lset_dx \1,64 + ii_lset_dx \1,65 + ii_lset_dx \1,66 + ii_lset_dx \1,67 +// lsx.w dy,dx + ii_lset_dx \1,68 + ii_lset_dx \1,69 + ii_lset_dx \1,6a + ii_lset_dx \1,6b + ii_lset_dx \1,6c + ii_lset_dx \1,6d + ii_lset_dx \1,6e + ii_lset_dx \1,6f +// roxx.w dy,dx + ii_lset_dx \1,70 + ii_lset_dx \1,71 + ii_lset_dx \1,72 + ii_lset_dx \1,73 + ii_lset_dx \1,74 + ii_lset_dx \1,75 + ii_lset_dx \1,76 + ii_lset_dx \1,77 +// rox.w dy,dx + ii_lset_dx \1,78 + ii_lset_dx \1,79 + ii_lset_dx \1,7a + ii_lset_dx \1,7b + ii_lset_dx \1,7c + ii_lset_dx \1,7d + ii_lset_dx \1,7e + ii_lset_dx \1,7f +/******************************************************/ +// long +/******************************************************/ +// roxx.l #,dx + ii_lset_dx \1,90 + ii_lset_dx \1,91 + ii_lset_dx \1,92 + ii_lset_dx \1,93 + ii_lset_dx \1,94 + ii_lset_dx \1,95 + ii_lset_dx \1,96 + ii_lset_dx \1,97 +// rox.l #xdx + ii_lset_dx \1,98 + ii_lset_dx \1,99 + ii_lset_dx \1,9a + ii_lset_dx \1,9b + ii_lset_dx \1,9c + ii_lset_dx \1,9d + ii_lset_dx \1,9e + ii_lset_dx \1,9f +// roxx.l dy,dx + ii_lset_dx \1,b0 + ii_lset_dx \1,b1 + ii_lset_dx \1,b2 + ii_lset_dx \1,b3 + ii_lset_dx \1,b4 + ii_lset_dx \1,b5 + ii_lset_dx \1,b6 + ii_lset_dx \1,b7 +// rox.l dy,dx + ii_lset_dx \1,b8 + ii_lset_dx \1,b9 + ii_lset_dx \1,ba + ii_lset_dx \1,bb + ii_lset_dx \1,bc + ii_lset_dx \1,bd + ii_lset_dx \1,be + ii_lset_dx \1,bf +//-------------------------------------------------------------------- +// asr.w ea + ii_lset_opea \10,d // (ax), (ax)+ + ii_lset_opea \10,e // -(ax),d16(ax) + ii_lset_opeag \10,f // d8(ax,dy) + lea table+0x\10\2f8*4,a0 + move.l #ii_0x\10f8,(a0)+ // xxx.w + move.l #ii_0x\10f9,(a0)+ // xxx.l +// asl.w ea + ii_lset_opea \11,d // (ax), (ax)+ + ii_lset_opea \11,e // -(ax),d16(ax) + ii_lset_opeag \11,f // d8(ax,dy) + lea table+0x\11\2f8*4,a0 + move.l #ii_0x\11f8,(a0)+ // xxx.w + move.l #ii_0x\11f9,(a0)+ // xxx.l +// lsr.w ea + ii_lset_opea \12,d // (ax), (ax)+ + ii_lset_opea \12,e // -(ax),d16(ax) + ii_lset_opeag \12,f // d8(ax,dy) + lea table+0x\12\2f8*4,a0 + move.l #ii_0x\12f8,(a0)+ // xxx.w + move.l #ii_0x\12f9,(a0)+ // xxx.l +// lsr.w ea + ii_lset_opea \13,d // (ax), (ax)+ + ii_lset_opea \13,e // -(ax),d16(ax) + ii_lset_opeag \13,f // d8(ax,dy) + lea table+0x\13\2f8*4,a0 + move.l #ii_0x\13f8,(a0)+ // xxx.w + move.l #ii_0x\13f9,(a0)+ // xxx.l +// roxr.w ea + ii_lset_opea \14,d // (ax), (ax)+ + ii_lset_opea \14,e // -(ax),d16(ax) + ii_lset_opeag \14,f // d8(ax,dy) + lea table+0x\14\2f8*4,a0 + move.l #ii_0x\14f8,(a0)+ // xxx.w + move.l #ii_0x\14f9,(a0)+ // xxx.l +// roxl.w ea + ii_lset_opea \15,e // (ax), (ax)+ + ii_lset_opea \15,e // -(ax),d16(ax) + ii_lset_opeag \15,f // d8(ax,dy) + lea table+0x\15\2f8*4,a0 + move.l #ii_0x\15f8,(a0)+ // xxx.w + move.l #ii_0x\15f9,(a0)+ // xxx.l +// ror.w ea + ii_lset_opea \16,d // (ax), (ax)+ + ii_lset_opea \16,e // -(ax),d16(ax) + ii_lset_opeag \16,f // d8(ax,dy) + lea table+0x\16\2f8*4,a0 + move.l #ii_0x\16f8,(a0)+ // xxx.w + move.l #ii_0x\16f9,(a0)+ // xxx.l +// rol.w ea + ii_lset_opea \17,d // (ax), (ax)+ + ii_lset_opea \17,e // -(ax),d16(ax) + ii_lset_opeag \17,f // d8(ax,dy) + lea table+0x\17\2f8*4,a0 + move.l #ii_0x\17f8,(a0)+ // xxx.w + move.l #ii_0x\17f9,(a0)+ // xxx.l +// ende +.endm; +/******************************************************/ +ii_shift_op:.macro // 1=code +//byt------------------------------- +//asx.b #x,dx + ii_shift_op2agb 0,as,a +//lsx.b #x,dx + ii_shift_op2aub 0,ls,a +//roxx.b #x,dx + ii_shift_op2agb 1,rox,a +//rox.b #x,dx + ii_shift_op2aub 1,ro,a +//asx.b dy,dx + ii_shift_op2agb 2,as,b +//lsx.b dy,dx + ii_shift_op2aub 2,ls,b +//roxx.b dy,dx + ii_shift_op2agb 3,rox,b +//rox.b dy,dx + ii_shift_op2aub 3,ro,b +// word --------------------------------------- +//asx.w #x,dx + ii_shift_op2agw 4,as,a +//lsx.w #x,dx + ii_shift_op2auw 4,ls,a +//roxx.w #x,dx + ii_shift_op2agw 5,rox,a +//rox.w #x,dx + ii_shift_op2auw 5,ro,a +//asx.w dy,dx + ii_shift_op2agw 6,as,b +//lsx.w dy,dx + ii_shift_op2auw 6,ls,b +//roxx.w dy,dx + ii_shift_op2agw 7,rox,b +//rox.w dy,dx + ii_shift_op2auw 7,ro,b +// long --------------------------------------- +//roxx.l #x,dx + ii_shift_op2agw 9,rox,a +//rox.l #x,dx + ii_shift_op2auw 9,ro,a +//roxx.l dy,dx + ii_shift_op2agw b,rox,b +//rox.l dy,dx + ii_shift_op2auw b,ro,b +// ea --------------------------------------- +//asr.w #1,ea + ii_shift_op2ea 0,asr +//asl.w #1,ea + ii_shift_op2ea 1,asl +//lsr.w #1,ea + ii_shift_op2ea 2,lsr, +//lsl.w #1,ea + ii_shift_op2ea 3,lsl +//roxr.w #1,ea + ii_shift_op2ea 4,roxr +//roxl.w #1,ea + ii_shift_op2ea 5,roxl +//ror.w #1,ea + ii_shift_op2ea 6,ror +//rol.w #1,ea + ii_shift_op2ea 7,rol +.endm +//byt ============================================ +ii_shift_op2agb:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3b \1,0,\2,d0_off+3(a7) + ii_shift_op1\3b \1,1,\2,d1_off+3(a7) + ii_shift_op1\3b \1,2,\2,d2 + ii_shift_op1\3b \1,3,\2,d3 + ii_shift_op1\3b \1,4,\2,d4 + ii_shift_op1\3b \1,5,\2,d5 + ii_shift_op1\3b \1,6,\2,d6 + ii_shift_op1\3b \1,7,\2,d7 +.endm + +ii_shift_op2aub:.macro //byt: 1=code 2=operation + ii_shift_op1\3b \1,8,\2,d0_off+3(a7) + ii_shift_op1\3b \1,9,\2,d1_off+3(a7) + ii_shift_op1\3b \1,a,\2,d2 + ii_shift_op1\3b \1,b,\2,d3 + ii_shift_op1\3b \1,c,\2,d4 + ii_shift_op1\3b \1,d,\2,d5 + ii_shift_op1\3b \1,e,\2,d6 + ii_shift_op1\3b \1,f,\2,d7 +.endm + +ii_shift_op1ab:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,b,\3r,#8,\4 + ii_shift_op0 2\1\2,b,\3r,#1,\4 + ii_shift_op0 4\1\2,b,\3r,#2,\4 + ii_shift_op0 6\1\2,b,\3r,#3,\4 + ii_shift_op0 8\1\2,b,\3r,#4,\4 + ii_shift_op0 a\1\2,b,\3r,#5,\4 + ii_shift_op0 c\1\2,b,\3r,#6,\4 + ii_shift_op0 e\1\2,b,\3r,#7,\4 + ii_shift_op0 1\1\2,b,\3l,#8,\4 + ii_shift_op0 3\1\2,b,\3l,#1,\4 + ii_shift_op0 5\1\2,b,\3l,#2,\4 + ii_shift_op0 7\1\2,b,\3l,#3,\4 + ii_shift_op0 9\1\2,b,\3l,#4,\4 + ii_shift_op0 b\1\2,b,\3l,#5,\4 + ii_shift_op0 d\1\2,b,\3l,#6,\4 + ii_shift_op0 f\1\2,b,\3l,#7,\4 +.endm + +ii_shift_op1bb:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,b,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,b,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,b,\3r,d2,\4 + ii_shift_op0 6\1\2,b,\3r,d3,\4 + ii_shift_op0 8\1\2,b,\3r,d4,\4 + ii_shift_op0 a\1\2,b,\3r,d5,\4 + ii_shift_op0 c\1\2,b,\3r,d6,\4 + ii_shift_op0 e\1\2,b,\3r,d7,\4 + ii_shift_op0b 1\1\2,b,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,b,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,b,\3l,d2,\4 + ii_shift_op0 7\1\2,b,\3l,d3,\4 + ii_shift_op0 9\1\2,b,\3l,d4,\4 + ii_shift_op0 b\1\2,b,\3l,d5,\4 + ii_shift_op0 d\1\2,b,\3l,d6,\4 + ii_shift_op0 f\1\2,b,\3l,d7,\4 +.endm +// word --------------------------------------- +ii_shift_op2agw:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3w \1,0,\2,d0_off+2(a7) + ii_shift_op1\3w \1,1,\2,d1_off+2(a7) + ii_shift_op1\3w \1,2,\2,d2 + ii_shift_op1\3w \1,3,\2,d3 + ii_shift_op1\3w \1,4,\2,d4 + ii_shift_op1\3w \1,5,\2,d5 + ii_shift_op1\3w \1,6,\2,d6 + ii_shift_op1\3w \1,7,\2,d7 +.endm + +ii_shift_op2auw:.macro //byt: 1=code 2=operation + ii_shift_op1\3w \1,8,\2,d0_off+2(a7) + ii_shift_op1\3w \1,9,\2,d1_off+2(a7) + ii_shift_op1\3w \1,a,\2,d2 + ii_shift_op1\3w \1,b,\2,d3 + ii_shift_op1\3w \1,c,\2,d4 + ii_shift_op1\3w \1,d,\2,d5 + ii_shift_op1\3w \1,e,\2,d6 + ii_shift_op1\3w \1,f,\2,d7 +.endm + +ii_shift_op1aw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,w,\3r,#8,\4 + ii_shift_op0 2\1\2,w,\3r,#1,\4 + ii_shift_op0 4\1\2,w,\3r,#2,\4 + ii_shift_op0 6\1\2,w,\3r,#3,\4 + ii_shift_op0 8\1\2,w,\3r,#4,\4 + ii_shift_op0 a\1\2,w,\3r,#5,\4 + ii_shift_op0 c\1\2,w,\3r,#6,\4 + ii_shift_op0 e\1\2,w,\3r,#7,\4 + ii_shift_op0 1\1\2,w,\3l,#8,\4 + ii_shift_op0 3\1\2,w,\3l,#1,\4 + ii_shift_op0 5\1\2,w,\3l,#2,\4 + ii_shift_op0 7\1\2,w,\3l,#3,\4 + ii_shift_op0 9\1\2,w,\3l,#4,\4 + ii_shift_op0 b\1\2,w,\3l,#5,\4 + ii_shift_op0 d\1\2,w,\3l,#6,\4 + ii_shift_op0 f\1\2,w,\3l,#7,\4 +.endm + +ii_shift_op1bw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,w,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,w,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,w,\3r,d2,\4 + ii_shift_op0 6\1\2,w,\3r,d3,\4 + ii_shift_op0 8\1\2,w,\3r,d4,\4 + ii_shift_op0 a\1\2,w,\3r,d5,\4 + ii_shift_op0 c\1\2,w,\3r,d6,\4 + ii_shift_op0 e\1\2,w,\3r,d7,\4 + ii_shift_op0b 1\1\2,w,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,w,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,w,\3l,d2,\4 + ii_shift_op0 7\1\2,w,\3l,d3,\4 + ii_shift_op0 9\1\2,w,\3l,d4,\4 + ii_shift_op0 b\1\2,w,\3l,d5,\4 + ii_shift_op0 d\1\2,w,\3l,d6,\4 + ii_shift_op0 f\1\2,w,\3l,d7,\4 +.endm +// long --------------------------------------- +ii_shift_op2agl:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3l \1,0,\2,d0_off(a7) + ii_shift_op1\3l \1,1,\2,d1_off(a7) + ii_shift_op1\3l \1,2,\2,d2 + ii_shift_op1\3l \1,3,\2,d3 + ii_shift_op1\3l \1,4,\2,d4 + ii_shift_op1\3l \1,5,\2,d5 + ii_shift_op1\3l \1,6,\2,d6 + ii_shift_op1\3l \1,7,\2,d7 +.endm + +ii_shift_op2aul:.macro //byt: 1=code 2=operation + ii_shift_op1\3l \1,8,\2,d0_off(a7) + ii_shift_op1\3l \1,9,\2,d1_off(a7) + ii_shift_op1\3l \1,a,\2,d2 + ii_shift_op1\3l \1,b,\2,d3 + ii_shift_op1\3l \1,c,\2,d4 + ii_shift_op1\3l \1,d,\2,d5 + ii_shift_op1\3l \1,e,\2,d6 + ii_shift_op1\3l \1,f,\2,d7 +.endm + +ii_shift_op1al:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,l,\3r,#8,\4 + ii_shift_op0 2\1\2,l,\3r,#1,\4 + ii_shift_op0 4\1\2,l,\3r,#2,\4 + ii_shift_op0 6\1\2,l,\3r,#3,\4 + ii_shift_op0 8\1\2,l,\3r,#4,\4 + ii_shift_op0 a\1\2,l,\3r,#5,\4 + ii_shift_op0 c\1\2,l,\3r,#6,\4 + ii_shift_op0 e\1\2,l,\3r,#7,\4 + ii_shift_op0 1\1\2,l,\3l,#8,\4 + ii_shift_op0 3\1\2,l,\3l,#1,\4 + ii_shift_op0 5\1\2,l,\3l,#2,\4 + ii_shift_op0 7\1\2,l,\3l,#3,\4 + ii_shift_op0 9\1\2,l,\3l,#4,\4 + ii_shift_op0 b\1\2,l,\3l,#5,\4 + ii_shift_op0 d\1\2,l,\3l,#6,\4 + ii_shift_op0 f\1\2,l,\3l,#7,\4 +.endm + +ii_shift_op1bl:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,l,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,l,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,l,\3r,d2,\4 + ii_shift_op0 6\1\2,l,\3r,d3,\4 + ii_shift_op0 8\1\2,l,\3r,d4,\4 + ii_shift_op0 a\1\2,l,\3r,d5,\4 + ii_shift_op0 c\1\2,l,\3r,d6,\4 + ii_shift_op0 e\1\2,l,\3r,d7,\4 + ii_shift_op0b 1\1\2,l,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,l,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,l,\3l,d2,\4 + ii_shift_op0 7\1\2,l,\3l,d3,\4 + ii_shift_op0 9\1\2,l,\3l,d4,\4 + ii_shift_op0 b\1\2,l,\3l,d5,\4 + ii_shift_op0 d\1\2,l,\3l,d6,\4 + ii_shift_op0 f\1\2,l,\3l,d7,\4 +.endm +// .word ea ============================================ +ii_shift_op2ea:.macro //1=code 2.ziffer 2=shiftart +// (a0) bis (a7) ---------------------------- +ii_0xe\1d0: + move.l a0_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d1: + move.l a1_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d2: + ii_shift_typ w,\2,#1,(a2),(a2). +ii_0xe\1d3: + ii_shift_typ w,\2,#1,(a3),(a3). +ii_0xe\1d4: + ii_shift_typ w,\2,#1,(a4),(a4). +ii_0xe\1d5: + ii_shift_typ w,\2,#1,(a5),(a5). +ii_0xe\1d6: + ii_shift_typ w,\2,#1,(a6),(a6). +ii_0xe\1d7: + move.l usp,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// (a0)+ bis (a7)+ ----------------------------- +ii_0xe\1d8: + move.l a0_off(a7),a1 + addq.l #2,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d9: + move.l a1_off(a7),a1 + addq.l #2,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1da: + ii_shift_typ w,\2,#1,(a2),(a2)+. +ii_0xe\1db: + ii_shift_typ w,\2,#1,(a3),(a3)+ +ii_0xe\1dc: + ii_shift_typ w,\2,#1,(a4),(a4)+ +ii_0xe\1dd: + ii_shift_typ w,\2,#1,(a5),(a5)+ +ii_0xe\1de: + ii_shift_typ w,\2,#1,(a6),(a6)+ +ii_0xe\1df: + move.l usp,a1 + addq.l #2,a1 + move.l a1,usp + subq.l #2,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// -(a0) bis -(a7) ----------------------------- +ii_0xe\1e0: + move.l a0_off(a7),a1 + subq.l #2,a1 + move.l a1,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e1: + move.l a1_off(a7),a1 + subq.l #2,a1 + move.l a1,a1_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e2: + ii_shift_typ w,\2,#1,-(a2),(a2). +ii_0xe\1e3: + ii_shift_typ w,\2,#1,-(a3),(a3) +ii_0xe\1e4: + ii_shift_typ w,\2,#1,-(a4),(a4) +ii_0xe\1e5: + ii_shift_typ w,\2,#1,-(a5),(a5) +ii_0xe\1e6: + ii_shift_typ w,\2,#1,-(a6),(a6) +ii_0xe\1e7: + move.l usp,a1 + subq.l #2,a1 + move.l a1,usp + ii_shift_typ w,\2,#1,(a1),(a1). +// d16(a0) bis d16(a7) ----------------------------- +ii_0xe\1e8: + move.w (a0)+,a1 + add.l a0_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e9: + move.w (a0)+,a1 + add.l a1_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1ea: + move.w (a0)+,a1 + add.l a2,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1eb: + move.w (a0)+,a1 + add.l a3,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ec: + move.w (a0)+,a1 + add.l a4,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ed: + move.w (a0)+,a1 + add.l a5,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ee: + move.w (a0)+,a1 + add.l a6,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ef: + mvs.w (a0)+,d0 + move.l usp,a1 + add.l d0,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// d8(a0,dy) bis d8(a7,dy) ----------------------------- +ii_0xe\1f0: + move.l a0_off(a0),a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f1: + move.l a1_off(a0),a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f2: + move.l a2,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f3: + move.l a3,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f4: + move.l a4,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f5: + move.l a5,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f6: + move.l a6,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f7: + move.l usp,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +// xxx.w xxx.l +ii_0xe\1f8: + move.w (a0)+,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f9: + move.l (a0)+,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +.endm +//============================================================================ +//subroutine +//------------------------------ +ii_shift_op0:.macro // shift: 1=code 2=size 3=shift art 4=shift wert 5=ea +ii_0xe\1: + ii_shift_typ \2,\3,\4,\5,\5 +.endm + +ii_shift_op0b:.macro // shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea +ii_0xe\1: + move.l \4,d0 + ii_shift_typ \2,\3,d0,\5,\5 +.endm + +ii_shift_typ:.macro //1=size 2=shift art 3=shift wert 4=source 5=dest +#ifdef halten + halt +#endif +.ifc asr,\2 + mvs.\1 \4,d1 +.else + mvz.\1 \4,d1 +.endif +.ifc roxr,\2 + nop +.else + .ifc roxl,\2 + nop + .else + .ifc ror,\2 + nop + .else + .ifc rol,\2 + nop + .else + \2.l \3,d1 + .endif + .endif + .endif +.endif + set_cc0 + move.\1 d1,\5 + ii_end +.endm diff --git a/BaS_GNU/sources/ii_sub.h b/BaS_GNU/sources/ii_sub.h new file mode 100644 index 0000000..1405e1a --- /dev/null +++ b/BaS_GNU/sources/ii_sub.h @@ -0,0 +1,584 @@ +//-------------------------------------------------------------------- +// sub +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// sub.b #im,dx +//-------------------------------------------------------------------- +subbir_macro:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + sub.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea,dx +//-------------------------------------------------------------------- +subdd:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +subddd:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub (ea)->dy,dx +//-------------------------------------------------------------------- +subdda:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +subddai:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea->ay,-(ay),dx +//-------------------------------------------------------------------- +subddad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d16(ay),dx +//-------------------------------------------------------------------- +subd16ad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d8(ay,dy),dx +//-------------------------------------------------------------------- +subd8ad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub xxx.w,dx +//-------------------------------------------------------------------- +subxwd:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub xxx.l,dx +//-------------------------------------------------------------------- +subxld:.macro +#ifdef halten_sub + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d16(pc),dx +//-------------------------------------------------------------------- +subd16pcd:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d8(pc,dy),dx +//-------------------------------------------------------------------- +subd8pcd:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// sub dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // sub (ea)->dy,dx +//-------------------------------------------------------------------- +subeda:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +subedai:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +subedaid:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +subedad:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +subedadd:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,d16(ay) +//-------------------------------------------------------------------- +sube16ad:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,d8(ay,dy) +//-------------------------------------------------------------------- +sube8ad:.macro +#ifdef halten_sub + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,xxx.w +//-------------------------------------------------------------------- +subxwe:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,xxx.l +//-------------------------------------------------------------------- +subxle:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// // suba.w ea,ax +//-------------------------------------------------------------------- +subaw:.macro +#ifdef halten_sub + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + mvs.w \1,d0 + suba.l d0,\2 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// sub.w ea,usp +//-------------------------------------------------------------------- +subawa7:.macro +#ifdef halten_sub + halt +#endif + mvs.w \1,d0 + move.l usp,a1 + sub.l d0,a1 + move.l a1,usp + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w usp?,ax +//-------------------------------------------------------------------- +subawu:.macro +#ifdef halten_sub + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + move.l a7,_a7_save + move.l usp,a7 + move.l \1,d0 + suba.l d0,\2 + move.l a7,usp + move.l _a7_save,a7 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// // suba.w usp?,usp +//-------------------------------------------------------------------- +subawua7:.macro + subawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // suba.w d16(ay),ax +//-------------------------------------------------------------------- +subawd16a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + adda.l d0,a1 + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d8(ay,dy),ax +//-------------------------------------------------------------------- +subawd8a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w xxx.w,ax +//-------------------------------------------------------------------- +subawxwax:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w xxx.l,ax +//-------------------------------------------------------------------- +subawxlax:.macro +#ifdef halten_sub + halt +#endif + move.l (a0)+,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d16(pc),ax +//-------------------------------------------------------------------- +subawd16pcax:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + adda.l a0,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d8(pc,dy),ax +//-------------------------------------------------------------------- +subawd8pcax:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w #im,ax +//-------------------------------------------------------------------- +subawim:.macro +#ifdef halten_sub + halt +#endif + mvs.w \1,d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.l d8(ay,dy),ax +//-------------------------------------------------------------------- +subald8a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.l d8(pc,dy),ax +//-------------------------------------------------------------------- +subakd8pcax:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//***************************************************************************************** +// subx +//***************************************************************************************** +//-------------------------------------------------------------------- +// // subx dy,dx +//-------------------------------------------------------------------- +subdx:.macro +#ifdef halten_sub + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + mvs.\3 \2,d0 + mvs.\3 \1,d1 + subx.l d0,d1 + set_cc0 + move.\3 d1,\1 + ii_end + .endm; +//-------------------------------------------------------------------- +// // subx -(ay),-(ax) +//-------------------------------------------------------------------- +subdax:.macro +#ifdef halten_sub + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + move.l \1,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d0 +.endif + move.l \2,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d1 +.endif + subx.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/illegal_instruction.s b/BaS_GNU/sources/illegal_instruction.s new file mode 100644 index 0000000..21461b3 --- /dev/null +++ b/BaS_GNU/sources/illegal_instruction.s @@ -0,0 +1,328 @@ +.public _illegal_instruction +.public _illegal_table_make + +.include "startcf.h" +.include "ii_macro.h" +.include "ii_func.h" +.include "ii_op.h" +.include "ii_opc.h" +.include "ii_add.h" +.include "ii_sub.h" +.include "ii_or.h" +.include "ii_and.h" +.include "ii_dbcc.h" +.include "ii_shd.h" +.include "ii_movem.h" +.include "ii_lea.h" +.include "ii_shift.h" +.include "ii_exg.h" +.include "ii_movep.h" +.include "ii_ewf.h" +.include "ii_move.h" + +.extern _ii_shift_vec +.extern ewf + +/*******************************************************/ +.text +ii_error: + nop + halt + nop + nop + +_illegal_instruction: +#ifdef ii_on + move.w #0x2700,sr + lea -ii_ss(a7),a7 + movem.l d0/d1/a0/a1,(a7) + move.l pc_off(a7),a0 // pc + mvz.w (a0)+,d0 // code + lea table,a1 + move.l 0(a1,d0*4),a1 + jmp (a1) +/*************************************************************************************************/ +#endif +_illegal_table_make: +#ifdef ii_on + lea table,a0 + moveq #0,d0 +_itm_loop: + move.l #ii_error,(a0)+ + addq.l #1,d0 + cmp.l #0xF000,d0 + bne _itm_loop +//------------------------------------------------------------------------- + ii_ewf_lset // diverse fehlende adressierungn +//------------------------------------------------------------------------- +// 0x0000 +// ori + ii_lset_op 00 +// andi + ii_lset_op 02 +// subi + ii_lset_op 04 +// addi + ii_lset_op 06 +// eori + ii_lset_op 0a +// cmpi + ii_lset_op 0c +// movep + ii_movep_lset +//------------------------------------------------------------------------- +// 0x1000 move.b +// 0x2000 move.l +// 0x3000 move.w + ii_move_lset +//------------------------------------------------------------------------- +// 0x4000 +//------------------------------------------------------------------------- +// negx + ii_lset_op 40 +// neg + ii_lset_op 44 +// not + ii_lset_op 46 +//--------------------------------------------------------------------------------------------- +// lea d8(ax,dy.w),az; d8(pc,dy.w),az +//------------------------------------------------------------------- + ii_lea_lset +//------------------------------------------------------------------- +// movem +//------------------------------------------------------------------- + ii_movem_lset +//------------------------------------------------------------------------- +// 0x5000 +//------------------------------------------------------------------------- +// addq, subq + ii_lset_op 50 + ii_lset_op 51 + ii_lset_op 52 + ii_lset_op 53 + ii_lset_op 54 + ii_lset_op 55 + ii_lset_op 56 + ii_lset_op 57 + ii_lset_op 58 + ii_lset_op 59 + ii_lset_op 5a + ii_lset_op 5b + ii_lset_op 5c + ii_lset_op 5d + ii_lset_op 5e + ii_lset_op 5f +// dbcc + ii_lset_dbcc +// scc + ii_lset_opc 50 + ii_lset_opc 51 + ii_lset_opc 52 + ii_lset_opc 53 + ii_lset_opc 54 + ii_lset_opc 55 + ii_lset_opc 56 + ii_lset_opc 57 + ii_lset_opc 58 + ii_lset_opc 59 + ii_lset_opc 5a + ii_lset_opc 5b + ii_lset_opc 5c + ii_lset_opc 5d + ii_lset_opc 5e + ii_lset_opc 5f +//------------------------------------------------------------------------- +// 0x8000 or +//------------------------------------------------------------------------- + ii_lset_func 8 +//------------------------------------------------------------------------- +// 0x9000 sub +//------------------------------------------------------------------------- + ii_lset_func 9 +//------------------------------------------------------------------------- +// 0xb000 +//------------------------------------------------------------------------- +// eor + ii_lset_op b1 + ii_lset_op b3 + ii_lset_op b5 + ii_lset_op b7 + ii_lset_op b9 + ii_lset_op bb + ii_lset_op bd + ii_lset_op bf +//------------------------------------------------------------------------- +// 0xc000 +//------------------------------------------------------------------------- +// and + ii_lset_func c +// exg + ii_exg_lset +//------------------------------------------------------------------------- +// 0xd000 add +//------------------------------------------------------------------------- + ii_lset_func d +//------------------------------------------------------------------------- +// 0xe000 +//------------------------------------------------------------------------- +// shift register + ii_shift_lset e +//------------------------------------------------- +// differenz zwischen orginal und gemoved korrigieren + lea ii_error(pc),a1 + move.l a1,d1 + sub.l #ii_error,d1 + lea table,a0 + moveq #0,d0 +_itkorr_loop: + add.l d1,(a0)+ + addq.l #1,d0 + cmp.l #0xF000,d0 + bne _itkorr_loop +#endif + rts +#ifdef ii_on +//***********************************************************************************/ +//------------------------------------------------------------------------- + ii_ewf_func // diverse fehlende adressierungn +//------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x0000 +//-------------------------------------------------------------------- +// ori 00 + ii_op 00,or.l,i +//-------------------------------------------------------------------- +// andi 02 + ii_op 02,and.l,i +//-------------------------------------------------------------------- +// subi 04 + ii_op 04,and.l,i +//-------------------------------------------------------------------- +// addi 06 + ii_op 06,add.l,i +//-------------------------------------------------------------------- +// eori 0a + ii_op 0a,eor.l,i +//-------------------------------------------------------------------- +// cmpi 0c + ii_op 0c,cmp.l,i +//-------------------------------------------------------------------- +// movep + ii_movep_func +///--------------------------------------------------------------------------------------------- +// 0x1000 move.b +// 0x2000 move.l +// 0x3000 move.w + ii_move_op +//--------------------------------------------------------------------------------------------- +// 0x4000 +//--------------------------------------------------------------------------------------------- +// neg 0x40.. + ii_op 40,negx.l,n +//--------------------------------------------------------------------------------------------- +// neg 0x44.. + ii_op 44,neg.l,n +//--------------------------------------------------------------------------------------------- +// not 0x46.. + ii_op 46,not.l,n +//--------------------------------------------------------------------------------------------- +// lea d8(ax,dy.w),az; d8(pc,dy.w),az +//------------------------------------------------------------------- + ii_lea_func +//------------------------------------------------------------------- +// movem +//-------------------------------------------------------------------- +ii_movem_func +//--------------------------------------------------------------------------------------------- +// 0x5000 +//--------------------------------------------------------------------------------------------- +//dbcc + ii_dbcc_func +// addq 0x5... + ii_op 50,addq.l #8,q + ii_op 52,addq.l #1,q + ii_op 54,addq.l #2,q + ii_op 56,addq.l #3,q + ii_op 58,addq.l #4,q + ii_op 5a,addq.l #5,q + ii_op 5c,addq.l #6,q + ii_op 5e,addq.l #7,q +//--------------------------------------------------------------------------------------------- +// subq 0x5... + ii_op 51,subq.l #8,q + ii_op 53,subq.l #1,q + ii_op 55,subq.l #2,q + ii_op 57,subq.l #3,q + ii_op 59,subq.l #4,q + ii_op 5b,subq.l #5,q + ii_op 5d,subq.l #6,q + ii_op 5f,subq.l #7,q +//--------------------------------------------------------------------------------------------- +// 0x5... scc + ii_opc 50,st,c + ii_opc 51,sf,c + ii_opc 52,shi,c + ii_opc 53,sls,c + ii_opc 54,scc,c + ii_opc 55,scs,c + ii_opc 56,sne,c + ii_opc 57,seq,c + ii_opc 58,svc,c + ii_opc 59,svs,c + ii_opc 5a,spl,c + ii_opc 5b,smi,c + ii_opc 5c,sge,c + ii_opc 5d,slt,c + ii_opc 5e,sgt,c + ii_opc 5f,sle,c +//--------------------------------------------------------------------------------------------- +// 0x6000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x7000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x8000 +//--------------------------------------------------------------------------------------------- +// or + ii_func 8,or +//--------------------------------------------------------------------------------------------- +// 0x9000 +//--------------------------------------------------------------------------------------------- +// sub + ii_func 9,sub +//--------------------------------------------------------------------------------------------- +// 0xa000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0xb000 +//--------------------------------------------------------------------------------------------- +// eor + ii_op b1,eor.l d0,q + ii_op b3,eor.l d1,q + ii_op b5,eor.l d2,q + ii_op b7,eor.l d3,q + ii_op b9,eor.l d4,q + ii_op bb,eor.l d5,q + ii_op bd,eor.l d6,q + ii_op bf,eor.l d7,q +//--------------------------------------------------------------------------------------------- +// 0xc000 +//--------------------------------------------------------------------------------------------- +// and + ii_func c,and +// exg + ii_exg_func +//--------------------------------------------------------------------------------------------- +// 0xd000 +//--------------------------------------------------------------------------------------------- +// add + ii_func d,add +//--------------------------------------------------------------------------------------------- +// 0xe000 shift +//-------------------------------------------------------------------- + ii_shift_op +//-------------------------------------------------------------------- +// 0xf000 +//-------------------------------------------------------------------- +#endif \ No newline at end of file diff --git a/BaS_GNU/sources/last.c b/BaS_GNU/sources/last.c new file mode 100644 index 0000000..0cb3a3e --- /dev/null +++ b/BaS_GNU/sources/last.c @@ -0,0 +1,11 @@ +// letztes file der liste +// wichtig als endpunkt des kopierens + +void copy_end(void) +{ + asm + { +copy_end: + nop + } +} \ No newline at end of file diff --git a/BaS_GNU/sources/last.s b/BaS_GNU/sources/last.s new file mode 100644 index 0000000..c9dfe7a --- /dev/null +++ b/BaS_GNU/sources/last.s @@ -0,0 +1,10 @@ +// letztes file der liste +// wichtig als endpunkt des kopierens + +.global copy_end + +.text + nop +copy_end: + nop +.asciz 'ende copy'; \ No newline at end of file diff --git a/BaS_GNU/sources/macro.h b/BaS_GNU/sources/macro.h new file mode 100644 index 0000000..2afa44e --- /dev/null +++ b/BaS_GNU/sources/macro.h @@ -0,0 +1,10 @@ +/*******************************************************/ +// allgemeine macros +/*******************************************************/ +.text +wait_pll: .macro +wait1_pll\@: + tst.w (a1) + bmi wait1_pll\@ + rts +.endm diff --git a/BaS_GNU/sources/mmu.s b/BaS_GNU/sources/mmu.s new file mode 100644 index 0000000..0d3fade --- /dev/null +++ b/BaS_GNU/sources/mmu.s @@ -0,0 +1,196 @@ +/********************************************************************/ + /* INIT ACR und MMU /* +/********************************************************************/ + +.include "startcf.h" + +.extern _rt_vbr +.extern _rt_cacr +.extern _rt_asid +.extern _rt_acr0 +.extern _rt_acr1 +.extern _rt_acr2 +.extern _rt_acr3 +.extern _rt_mmubar +.extern ___MMUBAR +.extern cpusha +.extern _video_tlb +.extern _video_sbt + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + +#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V) +#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) + +.public _mmu_init +.public _mmutr_miss + +.text +_mmu_init: + clr.l d0 + movec d0,ASID // ASID allways 0 + move.l d0,_rt_asid // sichern + movec d0,cacr // cache aus + move.l d0,_rt_cacr // sichern + nop + + move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff + movec d0,ACR0 + move.l d0,_rt_acr0 // sichern + + move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff + movec d0,ACR1 + move.l d0,_rt_acr1 // sichern + + move.l #0xe007C400,d0 // instruction r wt e000'0000-e07f'ffff + movec d0,ACR2 + move.l d0,_rt_acr2 // sichern + + clr.l d0 // acr3 aus + movec d0,ACR3 + move.l d0,_rt_acr3 // sichern + + move.l #___MMUBAR+1,d0 + movec d0,MMUBAR //mmubar setzen + move.l d0,_rt_mmubar // sichern + + nop + + move.l #MCF_MMU_MMUOR_CA,d0 // clear all entries, + move.l d0,MCF_MMU_MMUOR + nop +// 0000'0000 locked + moveq.l #0x00000000|std_mmutr,d0 + moveq.l #0x00000000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + moveq.l #mmuord_d,d2 // MMU update date + moveq.l #mmuord_i,d3 // MMU update instruction + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // MMU update date + move.l d3,MCF_MMU_MMUOR // MMU update instruction + +//--------------------------------------------------------------------------------------- +// 00d0'0000 locked ID=6 +// video ram: read write execute normal write true + move.l #0x00d00000|MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 + move.l #0x60d00000|wt_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // MMU update date + move.l #0x00d00000|std_mmutr,d0 + move.l d3,MCF_MMU_MMUOR // MMU update instruction + + move.l #0x2000,d0 + move.l d0,_video_tlb // setze page als video page + clr.l _video_sbt // zeit löschen +//------------------------------------------------------------------------------------- +// 00e0'0000 locked + move.l #0x00e00000|std_mmutr,d0 + move.l #0x00e00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen read only ?????? noch nicht + move.l d3,MCF_MMU_MMUOR // setzen +// 00f0'0000 locked + move.l #0x00f00000|std_mmutr,d0 + move.l #0xfff00000|nc_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // maped to ffffxxx, precise, + move.l d3,MCF_MMU_MMUOR // maped to ffffxxx, precise, +// 1fe0'0000 locked + move.l #0x1FE00000|std_mmutr,d0 + move.l #0x1FE00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen data + move.l d3,MCF_MMU_MMUOR // setzen instr +// 1ff0'0000 locked + move.l #0x1FF00000|std_mmutr,d0 + move.l #0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen data + move.l d3,MCF_MMU_MMUOR // setzen instr +// instr 0xFFF0'0000 nach 0x1FF0'0000 umleiten -->> short sprung +/* move.l #0xFFF00000|std_mmutr,d0 + move.l #0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d3,MCF_MMU_MMUOR // setzen instr +*/ + move.l #0xa10ca120,d0 + move.l d0,_rt_cacr // sichern + movec d0,cacr + nop + rts + +/********************************************************************/ + /* MMU table search /* +/********************************************************************/ +_mmutr_miss: + bsr cpusha + and.l #0xFFF00000,d0 + or.l #std_mmutr,d0 + move.l d0,MCF_MMU_MMUTR + and.l #0xFFF00000,d0 + or.l #cb_mmudr,d0 + move.l d0,MCF_MMU_MMUDR + moveq.l #mmuord_d,d0 // MMU update data + move.l d0,MCF_MMU_MMUOR // setzen + moveq.l #mmuord_i,d0 // MMU update instruction + move.l d0,MCF_MMU_MMUOR // setzen + move.l (sp)+,d0 + rte diff --git a/BaS_GNU/sources/movem.h b/BaS_GNU/sources/movem.h new file mode 100644 index 0000000..b79349d --- /dev/null +++ b/BaS_GNU/sources/movem.h @@ -0,0 +1,256 @@ +// movem +_ii_movem_lset: .macro +// movem rx,xxx.L + ii_lset 0x48f9 +// movem rx,-(ax) + +// movem (ax)+,rx + ii_lset 0x4cd8 + ii_lset 0x4cd9 + ii_lset 0x4cda + ii_lset 0x4cdb + ii_lset 0x4cdc + ii_lset 0x4cdd + ii_lset 0x4cde + ii_lset 0x4cdf +// movem xxx.L,rx + ii_lset 0x4cf9 +.endm +//***********************************************************************************/ +_ii_movem_func: .macro +//------------------------------------------------------------------- +// movem.l +//-------------------------------------------------------------------- +// movem.l (ax)+,reg +//-------------------------------------------------------------------- +//------------------------------------------------------------------------------- +ii_0x4cd8: // movem.l (a0)+,reglist + mvm_macro 0x4cd0,0x41e8,2 +ii_0x4cd9: // movem.l (a1)+,reglist + mvm_macro 0x4cd1,0x43e9,2 +ii_0x4cda: // movem.l (a2)+,reglist + mvm_macro 0x4cd2,0x45ea,2 +ii_0x4cdb: // movem.l (a3)+,reglist + mvm_macro 0x4cd3,0x47eb,2 +ii_0x4cdc: // movem.l (a4)+,reglist + mvm_macro 0x4cd4,0x49ec,2 +ii_0x4cdd: // movem.l (a5)+,reglist + mvm_macro 0x4cd5,0x4bed,2 +ii_0x4cde: // movem.l (a6)+,reglist + mvm_macro 0x4cd6,0x4dee,2 +ii_0x4cdf: // movem.l (a7)+,reglist + mvm_macro 0x4cd7,0x4fef,2 +//---------------------------------------------------------------------------- +ii_0x48f9: // movem.l reg,xxx.L + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro + ii_end +//--------------------------------------------------------------------------------------------- +ii_0x4cf9: // movem.l xxx.L,reg + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro + ii_end +.endm +//============================================================== +mvm_macro:.macro +halt + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x (ax),reg_list + move.w (a0)+,(a1)+ // register list + move.w #\2,(a1)+ // lea 0(ax),ax + lsl.l #\3,d1 // * anzahl byts pro wert + move.w d1,(a1)+ // offset von lea + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm + .long 0 +az_reg_table: + .byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70 + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0 + .byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0 +//--------------------------------------------------------------------------------- +movemrm_macro:.macro // in d0 register liste, in a1 zieladresse +halt + tst.b d0 // datenregister zu verschieben? + bne mrm_dx // ja-> + lsr.l #8,d0 // sonst zu addressregister + jmp mmrm_nd7 // -> +mrm_dx: + lsr.l #1,d0 + bcc mmrm_nd0 + move.l d0_off(a7),(a1)+ +mmrm_nd0: + lsr.l #1,d0 + bcc mmrm_nd1 + move.l d1_off(a7),(a1)+ +mmrm_nd1: + lsr.l #1,d0 + bcc mmrm_nd2 + move.l d2,(a1)+ +mmrm_nd2: + lsr.l #1,d0 + bcc mmrm_nd3 + move.l d3,(a1)+ +mmrm_nd3: + lsr.l #1,d0 + bcc mmrm_nd4 + move.l d4,(a1)+ +mmrm_nd4: + lsr.l #1,d0 + bcc mmrm_nd5 + move.l d5,(a1)+ +mmrm_nd5: + lsr.l #1,d0 + bcc mmrm_nd6 + move.l d6,(a1)+ +mmrm_nd6: + lsr.l #1,d0 + bcc mmrm_nd7 + move.l d7,(a1)+ +mmrm_nd7: + tst.b d0 // addressregister zu verschieben? + beq mmrm_na7 + lsr.l #1,d0 + bcc mmrm_na0 + move.l a0_off(a7),(a1)+ +mmrm_na0: + lsr.l #1,d0 + bcc mmrm_na1 + move.l a1_off(a7),(a1)+ +mmrm_na1: + lsr.l #1,d0 + bcc mmrm_na2 + move.l a2,(a1)+ +mmrm_na2: + lsr.l #1,d0 + bcc mmrm_na3 + move.l a3,(a1)+ +mmrm_na3: + lsr.l #1,d0 + bcc mmrm_na4 + move.l a4,(a1)+ +mmrm_na4: + lsr.l #1,d0 + bcc mmrm_na5 + move.l a5,(a1)+ +mmrm_na5: + lsr.l #1,d0 + bcc mmrm_na6 + move.l a6,(a1)+ +mmrm_na6: + lsr.l #1,d0 + bcc mmrm_na7 + move.l a0,d1 // sichern + move.l usp,a0 // ist ja usp + move.l a0,(a1)+ // nach a0 + move.l d1,a0 // pc zurück +mmrm_na7: + .endm +//--------------------------------------------------------------------------------------------- +movemmr_macro:.macro // in d0 register liste, in a1 source adr +halt + tst.b d0 // datenregister zu verschieben? + bne mmr_dx // ja-> + lsr.l #8,d0 // sonst zu addressregister + bra mmmr_nd7 // -> +mmr_dx: + lsr.l #1,d0 + bcc mmmr_nd0 + move.l (a1)+,d0_off(a7) +mmmr_nd0: + lsr.l #1,d0 + bcc mmmr_nd1 + move.l (a1)+,d1_off(a7) +mmmr_nd1: + lsr.l #1,d0 + bcc mmmr_nd2 + move.l (a1)+,d2 +mmmr_nd2: + lsr.l #1,d0 + bcc mmmr_nd3 + move.l (a1)+,d3 +mmmr_nd3: + lsr.l #1,d0 + bcc mmmr_nd4 + move.l (a1)+,d4 +mmmr_nd4: + lsr.l #1,d0 + bcc mmmr_nd5 + move.l (a1)+,d5 +mmmr_nd5: + lsr.l #1,d0 + bcc mmmr_nd6 + move.l (a1)+,d6 +mmmr_nd6: + lsr.l #1,d0 + bcc mmmr_nd7 + move.l (a1)+,d7 +mmmr_nd7: + tst.b d0 // addressregister zu verschieben? + beq mmmr_na7 // nein-> + lsr.l #1,d0 + bcc mmmr_na0 + move.l (a1)+,a0_off(a7) +mmmr_na0: + lsr.l #1,d0 + bcc mmmr_na1 + move.l (a1)+,a1_off(a7) +mmmr_na1: + lsr.l #1,d0 + bcc mmmr_na2 + move.l (a1)+,a2 +mmmr_na2: + lsr.l #1,d0 + bcc mmmr_na3 + move.l (a1)+,a3 +mmmr_na3: + lsr.l #1,d0 + bcc mmmr_na4 + move.l (a1)+,a4 +mmmr_na4: + lsr.l #1,d0 + bcc mmmr_na5 + move.l (a1)+,a5 +mmmr_na5: + lsr.l #1,d0 + bcc mmmr_na6 + move.l (a1)+,a6 +mmmr_na6: + lsr.l #1,d0 + bcc mmmr_na7 + move.l a0,d1 // sichern + move.l (a1)+,a0 // nach a0 + move.l a0,usp // war ja usp + move.l d1,a0 // pc zurück +mmmr_na7: + .endm diff --git a/BaS_GNU/sources/sd_card.s b/BaS_GNU/sources/sd_card.s new file mode 100644 index 0000000..c51147c --- /dev/null +++ b/BaS_GNU/sources/sd_card.s @@ -0,0 +1,406 @@ +/********************************************************************/ +// sd card +/********************************************************************/ +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 + +.text +sd_test: + lea MCF_PSC0_PSCTB_8BIT,a6 + move.l #'SD-C',(a6) + move.l #'ard ',(a6) + + move.l #__Bas_base,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) + move.l #0x1fffffff,d0 // normal dspi + move.l d0,MCF_PAD_PAR_DSPI + lea MCF_DSPI_DMCR,a0 + move.l #0x800d3c00,(a0) // 8 bit cs5 on + move.l #0x38558897,d0 + move.l d0,dspi_dtar0(a0) // 400kHz + move.l #0x082000ff,d4 // tx vorbesetzen + mov3q.l #-1,dspi_dsr(a0) + + bsr warte_1ms + move.l #0xc00d3c00,(a0) // 8 bit 4MHz clocken cs off + bsr warte_10ms + move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off + clr.b d4 + bsr sd_com + bsr sd_com + move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on + move.b #0xff,d4 + bsr sd_com + bsr sd_com + move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off + bsr warte_10ms + +// sd idle + move.l #100,d6 // 100 versuche + move.l #10,d3 // 10 versuche +sd_idle: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x40,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + move.b #0xff,d4 // receive byt + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + subq.l #1,d6 + beq sd_not + bra sd_idle +idle_end: +// cdm 8 +read_ic: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x48,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + move.b #0xaa,d4 + bsr sd_com + move.b #0x87,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #5,d5 + beq sd_v1 + cmp.b #1,d5 + bne read_ic + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com + cmp.b #0xaa,d5 + bne sd_testd3 + + move.l #'SDHC',(a6) + move.b #' ',(a6) +sd_v1: + +// cdm 58 +read_ocr: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x7a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + move.l #'Ver1',d6 + cmp.b #5,d5 + beq read_ocr + cmp.b #1,d5 + bne read_ocr + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com + +// acdm 41 + move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen +wait_of_aktiv: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x77,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x05,d5 + beq wait_of_aktiv + +wait_of_aktiv2: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x69,d4 + bsr sd_com + move.b #0x40,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq wait_of_aktiv2 + subq.l #1,d6 + bne wait_of_aktiv +sd_testd3: + subq.l #1,d3 + bne sd_idle + bra sd_error + +sd_init_ok: +// cdm 10 +read_cid: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x4a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + move.l a5,a4 // adresse setzen + bsr sd_rcv_info + +// name ausgeben + lea 1(a5),a4 + moveq #7,d7 +sd_nam_loop: + move.b (a4)+,(a6) + subq.l #1,d7 + bne sd_nam_loop + move.b #' ',(a6) + +// cdm 9 +read_csd: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x49,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + move.l a5,a4 // adresse setzen + bsr sd_rcv_info + + mvz.b (a5),d0 + lsr.l #6,d0 + + bne sd_csd2 // format v2 + move.l 6(a5),d1 + moveq #14,d0 // bit 73..62 c_size + lsr.l d0,d1 // bits extrahieren + and.l #0xfff,d1 // 12 bits + addq.l #1,d1 + mvz.w 9(a5),d0 + lsr.l #7,d0 // bits 49..47 + and.l #0x7,d0 // 3 bits + moveq.l #8,d2 // x256 (dif v1 v2) + sub.l d0,d2 + lsr.l d2,d1 + bra sd_print_size +sd_csd2: + mvz.w 8(a5),d1 + addq.l #1,d1 +sd_print_size: + swap d1 + lsl.l #1,d1 + bcc sd_16G + move.l #'32GB',(a6) + bra sd_ok +sd_16G: + lsl.l #1,d1 + bcc sd_8G + move.l #'16GB',(a6) + bra sd_ok +sd_8G: + lsl.l #1,d1 + bcc sd_4G + move.l #' 8GB',(a6) + bra sd_ok +sd_4G: + lsl.l #1,d1 + bcc sd_2G + move.l #' 4GB',(a6) + bra sd_ok +sd_2G: + lsl.l #1,d1 + bcc sd_1G + move.l #' 2GB',(a6) + bra sd_ok +sd_1G: + lsl.l #1,d1 + bcc sd_512M + move.l #' 1GB',(a6) + bra sd_ok +sd_512M: + lsl.l #1,d1 + bcc sd_256M + move.b #'5',(a6) + move.l #'12MB',(a6) + bra sd_ok +sd_256M: + lsl.l #1,d1 + bcc sd_128M + move.b #'2',(a6) + move.l #'56MB',(a6) + bra sd_ok +sd_128M: + lsl.l #1,d1 + bcc sd_64M + move.b #'1',(a6) + move.l #'28MB',(a6) + bra sd_ok +sd_64M: + lsl.l #1,d1 + bcc sd_32M + move.l #'64MB',(a6) + bra sd_ok +sd_32M: + lsl.l #1,d1 + bcc sd_16M + move.l #'32MB',(a6) + bra sd_ok +sd_16M: + lsl.l #1,d1 + bcc sd_8M + move.l #'16MB',(a6) + bra sd_ok +sd_8M: + move.l #'<9MB',(a6) +sd_ok: + move.l #' OK!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts +// subs ende ------------------------------- +sd_V1: + move.l #'non!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts +sd_error: + move.l #'Erro',(a6) + move.l #'r!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts +sd_not: + move.l #'non!',(a6) + move.l #0x0a0d,(a6) + halt + halt + rts + +// status holen ------------------------------- +sd_get_status: + move.b #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_get_status + rts +// byt senden und holen --------------------- +sd_com: + move.l d4,dspi_dtfr(a0) +wait_auf_complett: + btst.b #7,dspi_dsr(a0) + beq wait_auf_complett + move.l dspi_drfr(a0),d5 + mov3q.l #-1,dspi_dsr(a0) // clr status register + rts + +// daten holen ---------------------------- +sd_rcv_info: + moveq #18,d3 // 16 byts + 2 byts crc + move.b #0xff,d4 +sd_rcv_rb_w: + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rcv_rb_w // nein-> +sd_rcv_rd_rb: + bsr sd_com + move.b d5,(a4)+ + subq.l #1,d3 + bne sd_rcv_rd_rb + rts +/******************************************/ diff --git a/BaS_GNU/sources/sd_ide.c b/BaS_GNU/sources/sd_ide.c new file mode 100644 index 0000000..092f95e --- /dev/null +++ b/BaS_GNU/sources/sd_ide.c @@ -0,0 +1,543 @@ + + +#include "MCF5475.h" +#include "startcf.h" + +extern unsigned long far __SP_AFTER_RESET[]; +extern unsigned long far __Bas_base[]; + + /* imported routines */ +//extern int warten_20ms(); +//extern int warten_200us(); +//extern int warten_10us(); + +/********************************************************************/ +void asm sd_test(void) +{ + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} + + +/**************************************************/ +void asm ide_test(void) +{ + lea MCF_PAD_PAR_DSPI,a0 + move.w #0x1fff,(a0) + lea MCF_DSPI_DCTAR0,a0 + move.l #0x38a644e4,(a0) + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) + clr.l MCF_DSPI_DTCR + bsr warten_20ms + lea MCF_DSPI_DTFR,a0 + lea MCF_DSPI_DRFR,a1 + + moveq #10,d0 +sd_reset: + move.l #0x000100ff,(a0) + bsr warten_20ms + and.l (a1),d0 + subq.l #1,d0 + bne sd_reset + + moveq #10,d1 +sd_loop1: + bsr warten_20ms + moveq #-1,d0 +// cmd 0 set to idle + move.l #0x00200040,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200095,(a0) + bsr warten_20ms + and.l (a1),d0 + cmp.w #0x0001,d0 + beq sd_loop2 + subq.l #1,d1 + bne sd_loop1 + moveq #10,d1 + bra sd_test +sd_loop2: + moveq #-1,d0 +// cmd 41 + move.l #0x00200069,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200001,(a0) + bsr warten_20ms + and.l (a1),d0 + tst.w d0 + bne sd_loop2 + + nop + nop +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst.b #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} +/********************************************************************/ diff --git a/BaS_GNU/sources/sd_ide.s b/BaS_GNU/sources/sd_ide.s new file mode 100644 index 0000000..4d31184 --- /dev/null +++ b/BaS_GNU/sources/sd_ide.s @@ -0,0 +1,458 @@ + + +//.include "startcf.h" + +//.extern ___MBAR +//#define MCF_SLT0_SCNT ___MBAR+0x908 + +//.global ide_test + +.text +/* +sd_test: + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +/********************************************************************/ diff --git a/BaS_GNU/sources/startcf.S b/BaS_GNU/sources/startcf.S new file mode 100644 index 0000000..415f103 --- /dev/null +++ b/BaS_GNU/sources/startcf.S @@ -0,0 +1,82 @@ +/* + * CF_Startup.c - Default init/startup/termination routines for + * Embedded Metrowerks C++ + * + * Copyright � 1993-1998 Metrowerks, Inc. All Rights Reserved. + * Copyright � 2005 Freescale semiConductor Inc. All Rights Reserved. + * + * + * THEORY OF OPERATION + * + * This version of thestartup code is intended for linker relocated + * executables. The startup code will assign the stack pointer to + * __SP_INIT, assign the address of the data relative base address + * to a5, initialize the .bss/.sbss sections to zero, call any + * static C++ initializers and then call main. Upon returning from + * main it will call C++ destructors and call exit to terminate. + */ + +#ifdef __cplusplus +#pragma cplusplus off +#endif +#pragma PID off +#pragma PIC off + +#include + + + /* imported data */ + +extern unsigned long far _SP_INIT, _SDA_BASE; +extern unsigned long far _START_BSS, _END_BSS; +extern unsigned long far _START_SBSS, _END_SBSS; +extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END; +extern unsigned long far __Bas_base; + +extern unsigned long far __SUP_SP,__BOOT_FLASH; +extern unsigned long far rt_mbar; + + /* imported routines */ + +extern int BaS(int, char **); + + /* exported routines */ +extern void __initialize_hardware(void); +extern void init_slt(void); + + +void _startup(void) +{ + asm("\n\t" + "bra warmstart\n\t" + "jmp __BOOT_FLASH + 8 // ist zugleich reset vector\n\t" + "/* disable interrupts */\n\t" +"warmstart:\n\t" + "// disable interrupts\n\t" + "move.w #0x2700,sr\n\t" + "// Initialize MBAR\n\t" + "MOVE.L #__MBAR,D0\n\t" + "MOVEC D0,MBAR\n\t" + "MOVE.L D0,rt_mbar\n\t" +"// mmu off\n\t" + "move.l #__MMUBAR+1,d0\n\t" + movec d0,MMUBAR //mmubar setzen + clr.l d0 + move.l d0,MCF_MMU_MMUCR // mmu off + /* Initialize RAMBARs: locate SRAM and validate it */ \ + move.l #__RAMBAR0 + 0x7,d0 // supervisor only + movec d0,RAMBAR0 + move.l #__RAMBAR1 + 0x1,d0 // on for all + movec d0,RAMBAR1 + +// STACKPOINTER AUF ENDE SRAM1 + lea __SUP_SP,a7 + +// instruction cache on + move.l #0x000C8100,d0 + movec d0,cacr + nop +// initialize any hardware specific issues + bra __initialize_hardware +"); +} diff --git a/BaS_GNU/sources/startcf.h b/BaS_GNU/sources/startcf.h new file mode 100644 index 0000000..c538f16 --- /dev/null +++ b/BaS_GNU/sources/startcf.h @@ -0,0 +1,47 @@ +/****************************************************************************** + FILE : startcf.h + PURPOSE : startup code for ColdFire + LANGUAGE: C + + + Notes: + 1) Default entry point is _startup. + . disable interrupts + . the SP is set to __SP_AFTER_RESET + . SP must be initialized to valid memory + in case the memory it points to is not valid using MEMORY_INIT macro + 2) __initialize_hardware is called. Here you can initialize memory and some peripherics + at this point global variables are not initialized yet + 3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform + needed initialisations for the language (clear memory, data rom copy). + 4) void __initialize_system(void); is called + to allow additional hardware initialization (UART, GPIOs, etc...) + 5) Jump to main + +*/ +/********************************************************************************/ + +#define cf_stack + +//#define ii_on +#define halten +#define halten_dbcc +#define halten_and +#define halten_add +#define halten_sub +#define halten_or +#define halten_op +#define halten_opc +#define halten_movem +#define halten_lea +#define halten_shift +#define halten_move +#define halten_exg +#define halten_movep +#define halten_ewf + +#define DIP_SWITCH (*(vuint8 *)(&__MBAR[0xA2C])) +#define DIP_SWITCHa ___MBAR + 0xA2C + +#define sca_page_ID 6 + diff --git a/BaS_GNU/sources/supervisor.s b/BaS_GNU/sources/supervisor.s new file mode 100644 index 0000000..29cd97f --- /dev/null +++ b/BaS_GNU/sources/supervisor.s @@ -0,0 +1,585 @@ +/********************************************************/ +/* user/supervisor handler +/********************************************************/ + +.include "startcf.h" + +.extern _rt_cacr; +.extern _rt_mod; +.extern _rt_ssp; +.extern _rt_usp; +.extern ___MMUBAR + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + +.public _privileg_violation +.public cpusha + +.text +_privileg_violation: + move.w #0x2700,sr + lea -12(a7),a7 + movem.l d0/a0/a5,(a7) +#ifndef cf_stack + lea 0x52f0,a0 + move.l #0x20,(a0) // set auf 68030 +#endif + lea _rt_mod,a0 // zugriff setzen + tst.b (a0) // vom rt_supervisormodus? + bne pv_work // ja-> +// tatsächlich privileg violation + mov3q.l #-1,(a0) // sr_mod setzen + move.l usp,a5 // usp holen + move.l a5,8(a0) // sichern + move.l 4(a0),a5 // rt_ssp holen +#ifdef cf_stack + move.l 16(a7),-(a5) // pc verschieben + move.l 12(a7),-(a5) // sr verschieben + bset #5,2(a5) // auf super setzen +#else + move.w 12(a7),-(a5) // vector nr. + move.l 16(a7),-(a5) // pc verschieben + move.w 14(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif + move.l a5,usp + move.l 12(a0),a5 // rt_vbr + lea 0x18(a5),a5 // vector + move.l (a5),16(a7) // vector privileg violation + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// privileg violation +pv_work: + move.l 16(a7),a5 // fault pc + move.b (a5),d0 // fault code + cmp.b #0x4e,d0 // 1.byt 0x4e + beq pv_4e // ja-> + cmp.b #0x46,d0 // 1.byt 0x46 + beq pv_46 // ja-> + cmp.b #0x40,d0 // 1.byt 0x40 + beq pv_40 // ja-> + cmp.b #0xf4,d0 // 0xf4? + beq pv_f4 + cmp.b #0xf3,d0 // 0xf3? + beq pv_f3 +// hierher sollt man nicht kommen + nop + halt + nop +// code 0x4exx ******************************************** +pv_4e: + move.b 1(a5),d0 + cmp.b #0x73,d0 //rte? + beq pv_rte //ja-> + cmp.b #0x72,d0 //stop? + beq pv_stop //ja-> + cmp.b #0x7B,d0 //movec? + beq pv_movec //ja-> +// move usp + btst #3,d0 // to or from + bne pv_usp_to_ax // usp -> ax +// move ax->usp + cmp.b #0x60,d0 //movec? + beq pv_a0_usp //ja-> + cmp.b #0x61,d0 //movec? + beq pv_a1_usp //ja-> + cmp.b #0x62,d0 //movec? + beq pv_a2_usp //ja-> + cmp.b #0x63,d0 //movec? + beq pv_a3_usp //ja-> + cmp.b #0x64,d0 //movec? + beq pv_a4_usp //ja-> + cmp.b #0x65,d0 //movec? + beq pv_a5_usp //ja-> + cmp.b #0x66,d0 //movec? + beq pv_a6_usp //ja-> + halt + bra pv_a7_usp //ja-> +// move usp->ax +pv_usp_to_ax: + move.l 8(a0),a5 //rt_usp holen + cmp.b #0x68,d0 //movec? + beq pv_usp_a0 //ja-> + cmp.b #0x69,d0 //movec? + beq pv_usp_a1 //ja-> + cmp.b #0x6a,d0 //movec? + beq pv_usp_a2 //ja-> + cmp.b #0x6b,d0 //movec? + beq pv_usp_a3 //ja-> + cmp.b #0x6c,d0 //movec? + beq pv_usp_a4 //ja-> + cmp.b #0x6d,d0 //movec? + beq pv_usp_a5 //ja-> + cmp.b #0x6e,d0 //movec? + beq pv_usp_a6 //ja-> +// usp->a7 + move.l a5,4(a0) // rt usp -> rt ssp + move.l a5,usp // und setzen + bra pv_usp_ax +// a0->usp +pv_a0_usp: move.l 4(a7),a5 + bra pv_ax_usp +// a1->usp +pv_a1_usp: move.l a1,a5 + bra pv_ax_usp +// a2->usp +pv_a2_usp: move.l a2,a5 + bra pv_ax_usp +// a3->usp +pv_a3_usp: move.l a3,a5 + bra pv_ax_usp +// a4->usp +pv_a4_usp: move.l a4,a5 + bra pv_ax_usp +// a5->usp +pv_a5_usp: move.l 8(a7),a5 + bra pv_ax_usp +// a6->usp +pv_a6_usp: move.l a6,a5 + bra pv_ax_usp +// a7->usp +pv_a7_usp: move.l 4(a0),a5 // rt_ssp -> a5 +pv_ax_usp: + move.l a5,8(a0) // usp -> rt_usp + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// usp->a0 +pv_usp_a0: + move.l a5,4(a7) + bra pv_usp_ax +pv_usp_a1: + move.l a5,a1 + bra pv_usp_ax +pv_usp_a2: + move.l a5,a2 + bra pv_usp_ax +pv_usp_a3: + move.l a5,a3 + bra pv_usp_ax +pv_usp_a4: + move.l a5,a4 + bra pv_usp_ax +pv_usp_a5: + move.l a5,8(a7) + bra pv_usp_ax +pv_usp_a6: + move.l a5,a6 +pv_usp_ax: + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// rte +pv_rte: + move.l usp,a5 +#ifdef cf_stack + move.l (a5)+,12(a7) // sr verschieben + move.l (a5)+,16(a7) // pc verschieben +#else + move.w (a5)+,14(a7) // sr verschieben + move.l (a5)+,16(a7) // pc verschieben + move.w (a5)+,12(a7) // vector +#endif + bclr #5,14(a7) // war es von super? + bne pv_rte_sup // ja-> + clr.l (a0) // rt_mod auf user + move.l a5,4(a0) // rt_ssp sichern + move.l 8(a0),a5 // rt_usp holen +pv_rte_sup: + move.l a5,usp // usp setzen + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// stop +pv_stop: + move.b 2(a5),d0 // sr wert + and.l #0x0700,d0 // int mask + cmp.w #0x700,d0 + beq stop7 + cmp.w #0x600,d0 + beq stop6 + cmp.w #0x500,d0 + beq stop5 + cmp.w #0x400,d0 + beq stop4 + cmp.w #0x300,d0 + beq stop3 + cmp.w #0x200,d0 + beq stop2 + cmp.w #0x100,d0 + beq stop1 + stop #0x2000 + bra stop_weiter +stop1: + stop #0x2100 + bra stop_weiter +stop2: + stop #0x2200 + bra stop_weiter +stop3: + stop #0x2300 + bra stop_weiter +stop4: + stop #0x2400 + bra stop_weiter +stop5: + stop #0x2500 + bra stop_weiter +stop6: + stop #0x2600 + bra stop_weiter +stop7: + stop #0x2700 +stop_weiter: + addq.l #4,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// movec ??????? +pv_movec: + move.w 2(a5),d0 // 2.word holen + and.l #0xf000,d0 + btst #15,d0 // addressregister? + bne pv_movec_ax // ja-> + tst.w d0 // d0? + bne pvm_d1 // nein-> + move.l (a7),-(a7) // d0 holen und sichern + bra pvm_me +pvm_d1: + cmp.w #0x1000,d0 // d1? + bne pvm_d2 // nein-> + move.l d1,-(a7) // d1 holen und sichern + bra pvm_me // fertig machen +pvm_d2: + cmp.w #0x2000,d0 // d1? + bne pvm_d3 // nein-> + move.l d2,-(a7) // d2 holen und sichern + bra pvm_me // fertig machen +pvm_d3: + cmp.w #0x3000,d0 // d1? + bne pvm_d4 // nein-> + move.l d3,-(a7) // d3 holen und sichern + bra pvm_me // fertig machen +pvm_d4: + cmp.w #0x4000,d0 // d1? + bne pvm_d5 // nein-> + move.l d4,-(a7) // d4 holen und sichern + bra pvm_me // fertig machen +pvm_d5: + cmp.w #0x5000,d0 // d1? + bne pvm_d6 // nein-> + move.l d5,-(a7) // d5 holen und sichern + bra pvm_me // fertig machen +pvm_d6: + cmp.w #0x6000,d0 // d1? + bne pvm_d7 // nein-> + move.l d6,-(a7) // d6 holen und sichern + bra pvm_me // fertig machen +pvm_d7: + move.l d7,-(a7) // d7 holen und sichern + bra pvm_me // fertig machen +pv_movec_ax: + cmp.w #0x8000,d0 // a0? + bne pvm_a1 // nein-> + move.l 4(a7),-(a7) // a0 holen und sichern + bra pvm_me // fertig machen +pvm_a1: + cmp.w #0x9000,d0 // a0? + bne pvm_a2 // nein-> + move.l a1,-(a7) // a1 holen und sichern + bra pvm_me // fertig machen +pvm_a2: + cmp.w #0xa000,d0 // a0? + bne pvm_a3 // nein-> + move.l a2,-(a7) // a2 holen und sichern + bra pvm_me // fertig machen +pvm_a3: + cmp.w #0xb000,d0 // a0? + bne pvm_a4 // nein-> + move.l a3,-(a7) // a3 holen und sichern + bra pvm_me // fertig machen +pvm_a4: + cmp.w #0xc000,d0 // a0? + bne pvm_a5 // nein-> + move.l a4,-(a7) // a4 holen und sichern + bra pvm_me // fertig machen +pvm_a5: + cmp.w #0xd000,d0 // a0? + bne pvm_a6 // nein-> + move.l 8(a7),-(a7) // a5 holen und sichern + bra pvm_me // fertig machen +pvm_a6: + cmp.w #0xe000,d0 // a0? + bne pvm_a7 // nein-> + move.l a6,-(a7) // a6 holen und sichern + bra pvm_me // fertig machen +pvm_a7: + move.l 4(a7),-(a7) // a7 holen und sichern +pvm_me: + move.w 2(a5),d0 // 2.word holen + andi.l #0xf,d0 // nur letzte 4 bits + move.l (a7)+,8(a0,d0*4) // start bei +8, *4 weil long + jsr cpusha // gesammten cache flushen + rte +// code 0x46xx ***************************************** +pv_46: + move.b 1(a5),d0 + cmp.b #0xfc,d0 //#d16->sr + beq im_sr //ja-> +//move dx->sr (sr und rt_mod ist supervisor sonst wäre es privileg violation + cmp.b #0xc0,d0 //d0->sr? + bne d1_sr //nein-> + move.w 2(a7),d0 //hier ist d0 gesichert + bra d0_sr +d1_sr: + cmp.b #0xc1,d0 //d1->sr? + bne d2_sr //nein-> + move.w d1,d0 + bra d0_sr +d2_sr: + cmp.b #0xc2,d0 //d2->sr? + bne d3_sr + move.w d2,d0 + bra d0_sr +d3_sr: + cmp.b #0xc3,d0 //d3->sr? + bne d4_sr + move.w d3,d0 + bra d0_sr +d4_sr: + cmp.b #0xc4,d0 //d4->sr? + bne d5_sr + move.w d4,d0 + bra d0_sr +d5_sr: + cmp.b #0xc5,d0 //d5->sr? + bne d6_sr + move.w d5,d0 + bra d0_sr +d6_sr: + cmp.b #0xc6,d0 //d6->sr? + bne d7_sr + move.w d6,d0 + bra d0_sr +d7_sr: + move.w d7,d0 // sonst d7->sr +d0_sr: + addq.l #2,16(a7) // next + bra pv_set_sr_end // fertig machen +// move #xxxx,sr +im_sr: + addq.l #4,16(a7) // next + move.w 2(a5),d0 // data +pv_set_sr_end: + bclr #13,d0 // war super? + bne pv_sre2 // ja -> + clr.l (a0) + move.l usp,a5 // usp + move.l a5,4(a0) // rt_ssp speichern + move.l 8(a0),a5 // rt_usp holen + move.l a5,usp // setzen +pv_sre2: + move.w d0,14(a7) // sr setzen + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// code 0x40xx ***************************************** +pv_40: + move.b 1(a5),d0 // 2.byt + cmp.b #0xe7,d0 + beq pv_strldsr +// move sr->dx + move.l 12(a7),a5 // sr holen + tst.b (a0) // super? + beq pv_40_user // nein? + lea 0x2000(a5),a5 // super zuaddieren +pv_40_user: + cmp.b #0xc0,d0 + bne nsr_d1 + move.w a5,2(a7) + bra sr_dx_end +nsr_d1: + cmp.b #0xc1,d0 + bne nsr_d2 + move.w a5,d1 + bra sr_dx_end +nsr_d2: + cmp.b #0xc2,d0 + bne nsr_d3 + move.w a5,d2 + bra sr_dx_end +nsr_d3: + cmp.b #0xc3,d0 + bne nsr_d4 + move.w a5,d3 + bra sr_dx_end +nsr_d4: + cmp.b #0xc4,d0 + bne nsr_d5 + move.w a5,d4 + bra sr_dx_end +nsr_d5: + cmp.b #0xc5,d0 + bne nsr_d6 + move.w a5,d5 + bra sr_dx_end +nsr_d6: + cmp.b #0xc6,d0 + bne nsr_d7 + move.w a5,d6 + bra sr_dx_end +nsr_d7: + move.w a5,d7 + halt +sr_dx_end: + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// strldsr +pv_strldsr: + nop + halt + nop +// code 0xf4xx *********************************** +pv_f4: + addq.l #2,16(a7) // next instr + move.b 1(a5),d0 // 2.byt + bsr pv_ax_a0 // richtiges register + move.b 1(a5),d0 // 2.byt + cmp.b #0x30,d0 // >0xf430 + blo pv_intouch +// cpushl + cpushl bc,(a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +pv_intouch: + intouch (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +// subroutine register ax->a0 +pv_ax_a0: + and.l #0x7,d0 // nur register nummer + subq.l #1,d0 + bmi pv_a0_a0 + subq.l #1,d0 + bmi pv_a1_a0 + subq.l #1,d0 + bmi pv_a2_a0 + subq.l #1,d0 + bmi pv_a3_a0 + subq.l #1,d0 + bmi pv_a4_a0 + subq.l #1,d0 + bmi pv_a5_a0 + subq.l #1,d0 + bmi pv_a6_a0 + move.l a7,a0 + rts +pv_a0_a0: + move.l 8(a7),a0 + rts +pv_a1_a0: + move.l a1,a0 + rts +pv_a2_a0: + move.l a2,a0 + rts +pv_a3_a0: + move.l a3,a0 + rts +pv_a4_a0: + move.l a4,a0 + rts +pv_a5_a0: + move.l 12(a7),a0 + rts +pv_a6_a0: + move.l a6,a0 + rts +// code 0xf4xx *********************************** +pv_f3: + addq.l #2,16(a7) // next instr + move.b 1(a5),d0 // 2. byt + cmp.b #0x40,d0 + bgt pv_frestore +//fsave (ax) oder d16(ax) + jsr pv_ax_a0 // richtiges register holen + move.b 1(a5),d0 + cmp.b #0x20,d0 +// +d16 + blt pv_f3_ax + addq.l #2,16(a7) // next instr + clr.l d0 + move.w 2(a0),d0 // d16 + add.l d0,a0 +pv_f3_ax: + fsave (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +pv_frestore: + cmp.b #0x7a,d0 + beq pv_f_d16pc +// frestore (ax) oder d16(ax) + jsr pv_ax_a0 // richtiges register holen + move.b 1(a5),d0 + cmp.b #0x60,d0 + blt pv_frestore_ax +pv_fend: + addq.l #2,16(a7) // next instr + clr.l d0 + move.w 2(a0),d0 // d16 + add.l d0,a0 +pv_frestore_ax: + frestore (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +// frestore d16(pc) +pv_f_d16pc: + move.l 16(a7),a0 // pc holen + bra pv_fend +//***************************************************** +cpusha: + lea -16(a7),a7 + movem.l d0-d2/a0,(a7) // register sichern + move sr,d2 + nop + move #0x2700,sr // no interrupts + + clr.l d0 + clr.l d1 + move.l d0,a0 +cfa_setloop: + cpushl bc,(a0) // flush + lea 0x10(a0),a0 // index+1 + addq.l #1,d1 // index+1 + cmpi.w #512,d1 // alle sets? + bne cfa_setloop // nein-> + clr.l d1 + addq.l #1,d0 + move.l d0,a0 + cmpi.w #4,d0 // all ways? + bne cfa_setloop // nein-> + nop + move.l _rt_cacr,d0 // holen + movec d0,cacr // setzen + move.w d2,sr // alte interrupt maske + movem.l (a7),d0-d2/a0 // register zurück + lea 16(a7),a7 + + rts +//*******************************************************33 + From ec72e69a6cb19638a2afa956ef4e553d4c247be7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 12:14:25 +0000 Subject: [PATCH 030/276] converted to GNU asm --- BaS_GNU/sources/last.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/BaS_GNU/sources/last.c b/BaS_GNU/sources/last.c index 0cb3a3e..0ceffec 100644 --- a/BaS_GNU/sources/last.c +++ b/BaS_GNU/sources/last.c @@ -1,11 +1,14 @@ -// letztes file der liste -// wichtig als endpunkt des kopierens - +/* + * last file of the list. In the original sources, this marks the end of the + * copy loop that copies the BaS to its final place. + * + * FIXME: + * + * no need to do it that way - this file will probably vanish and be replaced by + * a matching entry in the linker script. + */ void copy_end(void) { - asm - { -copy_end: - nop - } -} \ No newline at end of file + asm(".globl copy_end\n\t"); + asm("copy_end: nop\n\t"); +} From 1536376c371fc4b1f430e2d53279598622c590a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 15:45:50 +0000 Subject: [PATCH 031/276] changed types to use --- BaS_GNU/.cproject | 142 +++++ BaS_GNU/.project | 82 +++ .../org.eclipse.cdt.codan.core.prefs | 66 +++ BaS_GNU/Makefile | 2 +- BaS_GNU/cfg/DDRAM.cfg | 57 ++ BaS_GNU/cfg/DDRAM.mem | 47 ++ BaS_GNU/cfg/flash.cfg | 11 + BaS_GNU/cfg/mem.cfg | 48 ++ BaS_GNU/cfg/mem.mem | 38 ++ BaS_GNU/firebeeV1.mcp | Bin 0 -> 110530 bytes BaS_GNU/flash_config.xml | 47 ++ BaS_GNU/hardware_diagnostic.xml | 40 ++ BaS_GNU/include/MCF5475.h | 74 +-- BaS_GNU/include/MCF5475_CLOCK.h | 2 +- BaS_GNU/include/MCF5475_CTM.h | 20 +- BaS_GNU/include/MCF5475_DMA.h | 126 ++-- BaS_GNU/include/MCF5475_DSPI.h | 50 +- BaS_GNU/include/MCF5475_EPORT.h | 12 +- BaS_GNU/include/MCF5475_FBCS.h | 42 +- BaS_GNU/include/MCF5475_FEC.h | 540 +++++++++--------- BaS_GNU/include/MCF5475_GPIO.h | 104 ++-- BaS_GNU/include/MCF5475_GPT.h | 40 +- BaS_GNU/include/MCF5475_I2C.h | 12 +- BaS_GNU/include/MCF5475_INTC.h | 162 +++--- BaS_GNU/include/MCF5475_MMU.h | 12 +- BaS_GNU/include/MCF5475_PAD.h | 24 +- BaS_GNU/include/MCF5475_PCI.h | 94 +-- BaS_GNU/include/MCF5475_PCIARB.h | 4 +- BaS_GNU/include/MCF5475_PSC.h | 438 +++++++------- BaS_GNU/include/MCF5475_SDRAMC.h | 20 +- BaS_GNU/include/MCF5475_SEC.h | 96 ++-- BaS_GNU/include/MCF5475_SIU.h | 8 +- BaS_GNU/include/MCF5475_SLT.h | 24 +- BaS_GNU/include/MCF5475_SRAM.h | 10 +- BaS_GNU/include/MCF5475_USB.h | 462 +++++++-------- BaS_GNU/include/MCF5475_XLB.h | 22 +- BaS_GNU/lcf/DDRAM.lcf | 88 +++ BaS_GNU/lcf/FLASH.lcf | 88 +++ BaS_GNU/sources/BaS.c | 2 +- BaS_GNU/sources/sd_card.c | 77 ++- BaS_GNU/sources/sd_ide.c | 10 +- BaS_GNU/sources/{startcf.S => startcf.c} | 29 +- BaS_GNU/sources/startcf.h | 2 +- BaS_GNU/sources/sysinit.c | 6 +- 44 files changed, 1990 insertions(+), 1290 deletions(-) create mode 100644 BaS_GNU/.cproject create mode 100644 BaS_GNU/.project create mode 100644 BaS_GNU/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 BaS_GNU/cfg/DDRAM.cfg create mode 100644 BaS_GNU/cfg/DDRAM.mem create mode 100644 BaS_GNU/cfg/flash.cfg create mode 100644 BaS_GNU/cfg/mem.cfg create mode 100644 BaS_GNU/cfg/mem.mem create mode 100644 BaS_GNU/firebeeV1.mcp create mode 100644 BaS_GNU/flash_config.xml create mode 100644 BaS_GNU/hardware_diagnostic.xml create mode 100644 BaS_GNU/lcf/DDRAM.lcf create mode 100644 BaS_GNU/lcf/FLASH.lcf rename BaS_GNU/sources/{startcf.S => startcf.c} (78%) diff --git a/BaS_GNU/.cproject b/BaS_GNU/.cproject new file mode 100644 index 0000000..91dd41f --- /dev/null +++ b/BaS_GNU/.cproject @@ -0,0 +1,142 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + make + + all + true + true + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/BaS_GNU/.project b/BaS_GNU/.project new file mode 100644 index 0000000..e715825 --- /dev/null +++ b/BaS_GNU/.project @@ -0,0 +1,82 @@ + + + BaS_GNU + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/BaS_GNU} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/BaS_GNU/.settings/org.eclipse.cdt.codan.core.prefs b/BaS_GNU/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..bf3ef64 --- /dev/null +++ b/BaS_GNU/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,66 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={no_break_comment\=>"no break",last_case_param\=>true,empty_case_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={} +org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error +org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error +org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +useParentScope=false diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 5593a74..fa070ee 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -23,13 +23,13 @@ OBJDIR=objs EXEC=bas.hex CSRCS= \ + $(SRCDIR)/startcf.c \ $(SRCDIR)/sysinit.c \ $(SRCDIR)/BaS.c \ $(SRCDIR)/sd_card.c \ $(SRCDIR)/last.c ASRCS= \ - $(SRCDIR)/startcf.S \ $(SRCDIR)/mmu.S \ $(SRCDIR)/exceptions.S \ $(SRCDIR)/supervisor.S \ diff --git a/BaS_GNU/cfg/DDRAM.cfg b/BaS_GNU/cfg/DDRAM.cfg new file mode 100644 index 0000000..7545850 --- /dev/null +++ b/BaS_GNU/cfg/DDRAM.cfg @@ -0,0 +1,57 @@ +; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture +; $RCSfile: M5475EVB.cfg,v $ +; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $ +; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file. + +ResetHalt + +;Set VBR - debugger must know this in order +; to do exception capture +writecontrolreg 0x0801 0x00000000 + +; If MBAR changes all following writes must change +; and if a memory configuration file is used, +; the reserved areas in the register block must +; change also. +;Turn on MBAR at 0xFF00_0000 +writecontrolreg 0x0C0F 0xFF000000 + +;Turn on RAMBAR0 at address FF10_0000 +writecontrolreg 0x0C04 0xFF100035 + +;Turn on RAMBAR1 at address FF10_1000 +writecontrolreg 0x0C05 0xFF101035 + +;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +writemem.l 0xFF000500 0xE0000000; +writemem.l 0xFF000508 0x00101980; 16-bit port +writemem.l 0xFF000504 0x007F0001; + +;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration +writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF) +writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +;writemem.l 0xFF000108 0x73611730; SDCFG1 +writemem.l 0xFF000108 0x53611730; SDCFG1 +;writemem.l 0xFF00010C 0x46770000; SDCFG2 +writemem.l 0xFF00010C 0x24730000; SDCFG2 + +;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR) +;writemem.l 0xFF000100 0x048D0000; SDMR (write to LMR) +writemem.l 0xFF000100 0x04890000; SDMR (write to LMR) +;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (first refresh) +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh) +;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (second refresh) +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh) +;writemem.l 0xFF000100 0x008D0000; SDMR (write to LMR) +writemem.l 0xFF000100 0x00890000; SDMR (write to LMR) +;writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh) +writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh) + +delay 1000 diff --git a/BaS_GNU/cfg/DDRAM.mem b/BaS_GNU/cfg/DDRAM.mem new file mode 100644 index 0000000..1bc400b --- /dev/null +++ b/BaS_GNU/cfg/DDRAM.mem @@ -0,0 +1,47 @@ +// Memory Configuration File +// +// Description: +// A memory configuration file contains commands that define the legally accessible +// areas of memory for your specific board. Useful for example when the debugger +// tries to display the content of a "char *" variable, that has not yet been initialized. +// In this case the debugger may try to read from a bogus address, which could cause a +// bus error. +// +// Board: +// LogicPD COLDARI1 +// +// Reference: +// MCF5475RM.pdf + + +// All reserved ranges read back 0xBABA... +reservedchar 0xBA + +address MBAR_BASE 0xFF000000 +address MMUBAR_BASE 0xFF040000 + +usederivative "MCF5475" + +// Memory Map: +// ---------------------------------------------------------------------- +range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM +reserved 0x20000000 0x5FFFFFFF + +range 0x60000000 0x7FFFFFFF 4 ReadWrite + +range 0x80000000 0xCFFFFFFF 4 ReadWrite + +range 0xD0000000 0xFBFFFFFF 4 ReadWrite + +reserved 0xFC000000 $MBAR_BASE-1 + + $MBAR_BASE $MBAR_BASE+0x3FFFF // Memory Mapped Registers +range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM + +range $MMUBAR_BASE $MMUBAR_BASE+0xFFFF +reserved $MMUBAR_BASE+1x0000 0xFF0FFFFF // Added to fill gap in MMR + +range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0) +range 0xFF101000 0xFFFFFFFF 4 ReadWrite // 4K SRAM1 (RAMBAR1) + + diff --git a/BaS_GNU/cfg/flash.cfg b/BaS_GNU/cfg/flash.cfg new file mode 100644 index 0000000..cfa2772 --- /dev/null +++ b/BaS_GNU/cfg/flash.cfg @@ -0,0 +1,11 @@ +; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture +; $RCSfile: M5475EVB.cfg,v $ +; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $ +; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file. + + +;Init CS0 (BootFLASH @ FE00_0000 - FE7F_FFFF 8Mbytes) +writemem.l 0xFF000500 0xFE000000; +writemem.l 0xFF000508 0x00101980; 16-bit port +writemem.l 0xFF000504 0x007F0001; + diff --git a/BaS_GNU/cfg/mem.cfg b/BaS_GNU/cfg/mem.cfg new file mode 100644 index 0000000..20830c0 --- /dev/null +++ b/BaS_GNU/cfg/mem.cfg @@ -0,0 +1,48 @@ +; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture +; $RCSfile: M5475EVB.cfg,v $ +; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $ +; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file. + +ResetHalt + +;Set VBR - debugger must know this in order +; to do exception capture +writecontrolreg 0x0801 0x00000000 + +; If MBAR changes all following writes must change +; and if a memory configuration file is used, +; the reserved areas in the register block must +; change also. +;Turn on MBAR at 0xFF00_0000 +writecontrolreg 0x0C0F 0xFF000000 + +;Turn on RAMBAR0 at address FF10_0000 +writecontrolreg 0x0C04 0xFF100035 + +;Turn on RAMBAR1 at address FF10_1000 +writecontrolreg 0x0C05 0xFF101035 + +;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +writemem.l 0xFF000500 0xE0000000; +writemem.l 0xFF000508 0x00001180; 16-bit port +writemem.l 0xFF000504 0x007F0001; + +;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration +writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +writemem.l 0xFF000108 0x53722938; SDCFG1 +writemem.l 0xFF00010C 0x24330000; SDCFG2 + +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR) +writemem.l 0xFF000100 0x05890000; SDRM (write to LMR) +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh) +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (second refresh) +writemem.l 0xFF000100 0x01890000; SDMR (write to LMR) +writemem.l 0xFF000104 0x710F0F00; SDCR (lock SDMR and enable refresh) + +delay 1000 diff --git a/BaS_GNU/cfg/mem.mem b/BaS_GNU/cfg/mem.mem new file mode 100644 index 0000000..46bda65 --- /dev/null +++ b/BaS_GNU/cfg/mem.mem @@ -0,0 +1,38 @@ +// Memory Configuration File +// +// Description: +// A memory configuration file contains commands that define the legally accessible +// areas of memory for your specific board. Useful for example when the debugger +// tries to display the content of a "char *" variable, that has not yet been initialized. +// In this case the debugger may try to read from a bogus address, which could cause a +// bus error. +// +// Board: +// LogicPD COLDARI1 +// +// Reference: +// MCF5475RM.pdf + + +// All reserved ranges read back 0xBABA... +reservedchar 0xBA + +address MBAR_BASE 0xFF000000 +address MMUBAR_BASE 0xFF040000 + +usederivative "MCF5475" + +// Memory Map: +// ---------------------------------------------------------------------- +range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM +reserved 0x20000000 $MBAR_BASE-1 + + $MBAR_BASE $MBAR_BASE+0x3FFFF 4 ReadWrite // Memory Mapped Registers +range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM +reserved $MBAR_BASE+0x17FFD $MBAR_BASE+0x1FFBF + + $MMUBAR_BASE $MMUBAR_BASE+0x001B +reserved $MMUBAR_BASE+0x001C 0xFF0FFFFF + +range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0) +range 0xFF101000 0xFF101FFF 4 ReadWrite // 4K SRAM1 (RAMBAR1) diff --git a/BaS_GNU/firebeeV1.mcp b/BaS_GNU/firebeeV1.mcp new file mode 100644 index 0000000000000000000000000000000000000000..af6610311b9139379d75980a8eb8c2741bdacbf3 GIT binary patch literal 110530 zcmeHwd6*m3mG5oS0%L5_VGCe2kqwx|wlKyf#@N{1YPH>_7t!6um^8?0sk&RXHniAn zvzf*0VGDsk*b}xu0wFsI1Og-^e`NXIOx|QB!#6MF%Of+Bd0FO5-n=2n`<;7Fl~n4| zVpFB3^We93bX|j2JHZKfOp+)+)`EPXO`z*Rw}Ea2-3hu2bQ9V zY0w>@Pk`Vg{IutY$ zGzWAz$OSqc0(}H@E$uWgk-Z-UT|t#WqiNqM1^m8E!IT=Hf@9H`A^eHZXv~PLUOs2mn>gZM zK$nvR&}!OuN@OfD4jGX2u}*0;GCC0%nhZpSBcqVf=@>F18ITM{$C1H_PX;A9>IC9b z2T><_csmbU>cIIRI-WX}_G2LG0X6Ip=dsI_!dq2Aqwo>P2#6vK)m1xjXd&g$DHmxidKg^*ULd zLV$YL3<*G)ptBVgZH1mzl+lX()}wxM zaleC?mnKABRz4LTK-k&L>yg143uYIfO!+jBqB19B~QA3+e>e$Kog+FpwmGi5IHJ2EIB8c1`Z|Gf;vEJKxcs95OU6ibI3W;z%~oYfUX5y z1&V`c*tiCCIS9@q=g%v#-36i%Aq~obQlL@LZqRnn6`*lY5)=i&LFF8HJ+{|@wt>z9 z!SUre4jkV)|M?j3*`O7mQ$Pzq^FcR)MnE42od`M^gdmagD}qDL(_64bV90rQC$>j` zT0xX3K;isy-n<3dO`sbrI?zj#H%>ZHSaIFGiY;s}zav=s> z@LiW5gqU%`&s`YPTo~V6h$$E1({(8be(%}>3V{&Mt_a8gVH|K_Ja8pIh-uelAjG~4 z@bQW*?f{<4_(@|uN^@I1zs0MBQ9 zHSmdyp8!6I@ehGdX8c>=1&lw04mySLGGLkoC|w9lvjU|Zz|^ml9s{PCfYSGX5mhq% z4tO!+W6;rF#;bwPV4MJ6!uWn*Is>5e67W(5#oNGVF`fxmUdDJK@N&j|z%)Zr+6GKB zCZz{~Y1X9lJ>YW`6n_9-$=D5NquG|yT40P4G9`gmGrkWPku1||z-t))0eCIrW8kPA zjF$j+GTs2}V>|)e#dr^}pYfx>-HcxXUdQ-<0s2aM5IrmetqmPF|m;7b)0&jHif2&KOV z-Xf6@zXuL6o`XSPl<{f6Va7ec5ylh12ID=zV~igI9%uY2@C4&u07n`B8F(w>xfo=& zFm>1Q;`hOg{upG5$ZmG!9alg~1B5iA<*gXBhVa(^)B{C~!_e zu?KiN4IpbmAD;Qr1d?n*YfUjcwI`Gwu{{wh8 z>Gw}6{W59bDUk!W%<9mT`Wc(cPO^ja!zM1j=0KSFsZ-8%Q z{2uUaj1R|P{t3pX0pHGe4e%X|F9yDo@nyhwF}@l2ZpP07f0FU{f$w4bbKp-g{tw`L z86SFtxe*pXlW&uewgW%T{58OzWjqZ0ImY9_PcYsE{3PSMfS+Rg6!6oGzXkjZ;~xQkp7F1MpJn`K z;O7`0dX&0DO1mckf06ksfuCo*5%>khG2kyTz8?5R#!mu&nelglzry(MfWON4H^5(G z+ChHk8#^XjJiz#KGe`uiBAM{@| z>>up!=nW2b^ojmt!Vn$du#w4l0-@|gMs$X<;fcXqB4OZnm{7uq**R&WH=5X%&&x$) z5s!Z|n+|1!FPF(C!=d!Jkrmyzed_58rBczv zct#8*bLp_*8BQBUMkoo?KAV-9wpv>|-Mt+{>jet%8nH3ax5?u>!?$pu$A9*U^F>D{ z?&$;Y_h>5%U81` zP+?%Cw?`>z;i?RY9|=Yy27ncU@aR0w6yQ)MF5;nZI+=k_O5n|iXe?%ohhos1$)ka;jQ$I4d7m>kcuxC$xrh^=wvkOd|Lyq3%% zH(?PTJA1{pSadYFWGPvK`x>^VUWD|HP?SclQRN5WP&$%F(n#E$)1SSkUqZ|Di`ef= zz%7Cg^p59L1G>TTfLx$t{)Qj+DDnKf(smAHGHvH)Ceu8BuuiVbjN&sVlW#xSGP#|F zCvYayDx1&KO#Yw|Pi75u>S9&7BbQAs#>`JAbf#cOA{5(+vlg7w;6zf6br~zO_%zWx z$no67%$#zTWM)h~Uv)oX@q)+``i|lNa#eq%SK^%y6<{HHz7NIF-tuw3^4D z9KUrQWE}!-PXgzo>0ByrIWPxlAhe{cz6kXAtde~Z9DYPZrBRE`ps<;}|%N2%g)a}=`2o}-8@5FI6~`fyY_3fV%`QKB$jodukN*HN-K zk{yK{!`e}DN{l;7O%3?UVnxyKc!2Xz;3!%+E;tGl4HD&K>?4Mwq<#1(C6XUYN=c}J z#WC0NEr(IY@c_pm$5FDx_~R_=G#EKb7L81fGPaS%HcUB+JB(S5a<*d40nAad+-T-_ zK+(`vc=cx=(rh`lq0E+Jb*njq*>a1AE?cI3$g*YGhALZ*rH_XwTc&MjvgH&GN%jn< zp~xmtJOtS?9fuy9#FQb&mOFK*DV<$3#MlI#hZdVi;gDj>C>lzf^6W#1O~O8O6ldj! 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v9qVcruQLBn9WB + + + + true + 5474 + PEMICRO_USB + true + C:\FireBee\codewarrior\firebeeV1\cfg\mem.cfg + 0x00000000 + 0x00006000 + true + false + + + + 0xE0000000 + M29W640DB + 4Mx16x1 + 0xE0000000 + 0xE07FFFFF + + + + true + C:\FireBee\codewarrior\firebeeV1\bin\FLASH.elf.S19 + Auto Detect + false + 0xFF800000 + 0xFFFFFFFF + false + 0xC0200000 + + + + false + + false + + + + FileOnTarg + 0xFF800000 + 0x007FFFFF + + + diff --git a/BaS_GNU/hardware_diagnostic.xml b/BaS_GNU/hardware_diagnostic.xml new file mode 100644 index 0000000..b45676f --- /dev/null +++ b/BaS_GNU/hardware_diagnostic.xml @@ -0,0 +1,40 @@ + + + + + true + 5474 + PEMICRO_USB + true + {CodeWarrior}\ColdFire_Support\Initialization_Files\MCF5475.cfg + + + + read + long_word + 0x60001000 + FFFFFFFF + + + + read + long_word + 0x00100000 + 0x67 + 1000 + + + + true + true + true + 0x00DE1000 + 0x00DE11FF + long_word + 1 + false + 0x00000100 + 0x0000FFFF + + + diff --git a/BaS_GNU/include/MCF5475.h b/BaS_GNU/include/MCF5475.h index be18fec..e64b900 100644 --- a/BaS_GNU/include/MCF5475.h +++ b/BaS_GNU/include/MCF5475.h @@ -16,69 +16,26 @@ #ifndef __MCF5475_H__ #define __MCF5475_H__ - -/********************************************************************/ -/* - * The basic data types - */ - -typedef unsigned char uint8; /* 8 bits */ -typedef unsigned short int uint16; /* 16 bits */ -typedef unsigned long int uint32; /* 32 bits */ - -typedef signed char int8; /* 8 bits */ -typedef signed short int int16; /* 16 bits */ -typedef signed long int int32; /* 32 bits */ - -typedef volatile uint8 vuint8; /* 8 bits */ -typedef volatile uint16 vuint16; /* 16 bits */ -typedef volatile uint32 vuint32; /* 32 bits */ - -#ifdef __cplusplus -extern "C" { -#endif - -#pragma define_section system ".system" far_absolute RW - -/* get rid of __declspec */ -#if __GNUC__ -#undef __declspec -/* the following should work if we had an ELF capable toolchain. Unfortunately, it doesn't - * for the current m68k-atari-mint aoutx toolchain since it does not support the - * __attribute__ ((section("x"))) syntax. - */ -/* #define __declspec(a) __attribute__ ((section ("a"))) */ -#define __declspec(a) /* */ - +#include /*** * MCF5475 Derivative Memory map definitions from linker command files: * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE * linker symbols must be defined in the linker command file. */ -#ifdef __GNUC__ -/* get rid of the __declspec() keyword */ -#undef __declspec -#define __declspec(a) /* */ +extern uint8_t __MBAR[]; +extern uint8_t __MMUBAR[]; +extern uint8_t __RAMBAR0[]; +extern uint8_t __RAMBAR0_SIZE[]; +extern uint8_t __RAMBAR1[]; +extern uint8_t __RAMBAR1_SIZE[]; -/* the same for "far" */ -#undef far -#define far /* */ -#endif - -extern __declspec(system) uint8 __MBAR[]; -extern __declspec(system) uint8 __MMUBAR[]; -extern __declspec(system) uint8 __RAMBAR0[]; -extern __declspec(system) uint8 __RAMBAR0_SIZE[]; -extern __declspec(system) uint8 __RAMBAR1[]; -extern __declspec(system) uint8 __RAMBAR1_SIZE[]; - -#define MBAR_ADDRESS (uint32)__MBAR -#define MMUBAR_ADDRESS (uint32)__MMUBAR -#define RAMBAR0_ADDRESS (uint32)__RAMBAR0 -#define RAMBAR0_SIZE (uint32)__RAMBAR0_SIZE -#define RAMBAR1_ADDRESS (uint32)__RAMBAR1 -#define RAMBAR1_SIZE (uint32)__RAMBAR1_SIZE +#define MBAR_ADDRESS (uint32_t)__MBAR +#define MMUBAR_ADDRESS (uint32_t)__MMUBAR +#define RAMBAR0_ADDRESS (uint32_t)__RAMBAR0 +#define RAMBAR0_SIZE (uint32_t)__RAMBAR0_SIZE +#define RAMBAR1_ADDRESS (uint32_t)__RAMBAR1 +#define RAMBAR1_SIZE (uint32_t)__RAMBAR1_SIZE #include "MCF5475_SIU.h" @@ -105,9 +62,4 @@ extern __declspec(system) uint8 __RAMBAR1_SIZE[]; #include "MCF5475_SRAM.h" #include "MCF5475_SEC.h" -#ifdef __cplusplus -} -#endif - - #endif /* __MCF5475_H__ */ diff --git a/BaS_GNU/include/MCF5475_CLOCK.h b/BaS_GNU/include/MCF5475_CLOCK.h index 96e173f..d56c057 100644 --- a/BaS_GNU/include/MCF5475_CLOCK.h +++ b/BaS_GNU/include/MCF5475_CLOCK.h @@ -24,7 +24,7 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_CLOCK_SPCR (*(vuint32*)(&__MBAR[0x300])) +#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&__MBAR[0x300])) /* Bit definitions and macros for MCF_CLOCK_SPCR */ diff --git a/BaS_GNU/include/MCF5475_CTM.h b/BaS_GNU/include/MCF5475_CTM.h index 1b516fd..b2d8776 100644 --- a/BaS_GNU/include/MCF5475_CTM.h +++ b/BaS_GNU/include/MCF5475_CTM.h @@ -24,16 +24,16 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_CTM_CTCR0 (*(vuint32*)(&__MBAR[0x7F00])) -#define MCF_CTM_CTCR1 (*(vuint32*)(&__MBAR[0x7F04])) -#define MCF_CTM_CTCR2 (*(vuint32*)(&__MBAR[0x7F08])) -#define MCF_CTM_CTCR3 (*(vuint32*)(&__MBAR[0x7F0C])) -#define MCF_CTM_CTCR4 (*(vuint32*)(&__MBAR[0x7F10])) -#define MCF_CTM_CTCR5 (*(vuint32*)(&__MBAR[0x7F14])) -#define MCF_CTM_CTCR6 (*(vuint32*)(&__MBAR[0x7F18])) -#define MCF_CTM_CTCR7 (*(vuint32*)(&__MBAR[0x7F1C])) -#define MCF_CTM_CTCRF(x) (*(vuint32*)(&__MBAR[0x7F00 + ((x)*0x4)])) -#define MCF_CTM_CTCRV(x) (*(vuint32*)(&__MBAR[0x7F10 + ((x-4)*0x4)])) +#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&__MBAR[0x7F00])) +#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&__MBAR[0x7F04])) +#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&__MBAR[0x7F08])) +#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&__MBAR[0x7F0C])) +#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&__MBAR[0x7F10])) +#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&__MBAR[0x7F14])) +#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&__MBAR[0x7F18])) +#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&__MBAR[0x7F1C])) +#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&__MBAR[0x7F00 + ((x)*0x4)])) +#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&__MBAR[0x7F10 + ((x-4)*0x4)])) /* Bit definitions and macros for MCF_CTM_CTCRF */ diff --git a/BaS_GNU/include/MCF5475_DMA.h b/BaS_GNU/include/MCF5475_DMA.h index a9667c1..9d84060 100644 --- a/BaS_GNU/include/MCF5475_DMA.h +++ b/BaS_GNU/include/MCF5475_DMA.h @@ -24,69 +24,69 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_DMA_TASKBAR (*(vuint32*)(&__MBAR[0x8000])) -#define MCF_DMA_CP (*(vuint32*)(&__MBAR[0x8004])) -#define MCF_DMA_EP (*(vuint32*)(&__MBAR[0x8008])) -#define MCF_DMA_VP (*(vuint32*)(&__MBAR[0x800C])) -#define MCF_DMA_PTD (*(vuint32*)(&__MBAR[0x8010])) -#define MCF_DMA_DIPR (*(vuint32*)(&__MBAR[0x8014])) -#define MCF_DMA_DIMR (*(vuint32*)(&__MBAR[0x8018])) -#define MCF_DMA_TCR0 (*(vuint16*)(&__MBAR[0x801C])) -#define MCF_DMA_TCR1 (*(vuint16*)(&__MBAR[0x801E])) -#define MCF_DMA_TCR2 (*(vuint16*)(&__MBAR[0x8020])) -#define MCF_DMA_TCR3 (*(vuint16*)(&__MBAR[0x8022])) -#define MCF_DMA_TCR4 (*(vuint16*)(&__MBAR[0x8024])) -#define MCF_DMA_TCR5 (*(vuint16*)(&__MBAR[0x8026])) -#define MCF_DMA_TCR6 (*(vuint16*)(&__MBAR[0x8028])) -#define MCF_DMA_TCR7 (*(vuint16*)(&__MBAR[0x802A])) -#define MCF_DMA_TCR8 (*(vuint16*)(&__MBAR[0x802C])) -#define MCF_DMA_TCR9 (*(vuint16*)(&__MBAR[0x802E])) -#define MCF_DMA_TCR10 (*(vuint16*)(&__MBAR[0x8030])) -#define MCF_DMA_TCR11 (*(vuint16*)(&__MBAR[0x8032])) -#define MCF_DMA_TCR12 (*(vuint16*)(&__MBAR[0x8034])) -#define MCF_DMA_TCR13 (*(vuint16*)(&__MBAR[0x8036])) -#define MCF_DMA_TCR14 (*(vuint16*)(&__MBAR[0x8038])) -#define MCF_DMA_TCR15 (*(vuint16*)(&__MBAR[0x803A])) -#define MCF_DMA_PRIOR0 (*(vuint8 *)(&__MBAR[0x803C])) -#define MCF_DMA_PRIOR1 (*(vuint8 *)(&__MBAR[0x803D])) -#define MCF_DMA_PRIOR2 (*(vuint8 *)(&__MBAR[0x803E])) -#define MCF_DMA_PRIOR3 (*(vuint8 *)(&__MBAR[0x803F])) -#define MCF_DMA_PRIOR4 (*(vuint8 *)(&__MBAR[0x8040])) -#define MCF_DMA_PRIOR5 (*(vuint8 *)(&__MBAR[0x8041])) -#define MCF_DMA_PRIOR6 (*(vuint8 *)(&__MBAR[0x8042])) -#define MCF_DMA_PRIOR7 (*(vuint8 *)(&__MBAR[0x8043])) -#define MCF_DMA_PRIOR8 (*(vuint8 *)(&__MBAR[0x8044])) -#define MCF_DMA_PRIOR9 (*(vuint8 *)(&__MBAR[0x8045])) -#define MCF_DMA_PRIOR10 (*(vuint8 *)(&__MBAR[0x8046])) -#define MCF_DMA_PRIOR11 (*(vuint8 *)(&__MBAR[0x8047])) -#define MCF_DMA_PRIOR12 (*(vuint8 *)(&__MBAR[0x8048])) -#define MCF_DMA_PRIOR13 (*(vuint8 *)(&__MBAR[0x8049])) -#define MCF_DMA_PRIOR14 (*(vuint8 *)(&__MBAR[0x804A])) -#define MCF_DMA_PRIOR15 (*(vuint8 *)(&__MBAR[0x804B])) -#define MCF_DMA_PRIOR16 (*(vuint8 *)(&__MBAR[0x804C])) -#define MCF_DMA_PRIOR17 (*(vuint8 *)(&__MBAR[0x804D])) -#define MCF_DMA_PRIOR18 (*(vuint8 *)(&__MBAR[0x804E])) -#define MCF_DMA_PRIOR19 (*(vuint8 *)(&__MBAR[0x804F])) -#define MCF_DMA_PRIOR20 (*(vuint8 *)(&__MBAR[0x8050])) -#define MCF_DMA_PRIOR21 (*(vuint8 *)(&__MBAR[0x8051])) -#define MCF_DMA_PRIOR22 (*(vuint8 *)(&__MBAR[0x8052])) -#define MCF_DMA_PRIOR23 (*(vuint8 *)(&__MBAR[0x8053])) -#define MCF_DMA_PRIOR24 (*(vuint8 *)(&__MBAR[0x8054])) -#define MCF_DMA_PRIOR25 (*(vuint8 *)(&__MBAR[0x8055])) -#define MCF_DMA_PRIOR26 (*(vuint8 *)(&__MBAR[0x8056])) -#define MCF_DMA_PRIOR27 (*(vuint8 *)(&__MBAR[0x8057])) -#define MCF_DMA_PRIOR28 (*(vuint8 *)(&__MBAR[0x8058])) -#define MCF_DMA_PRIOR29 (*(vuint8 *)(&__MBAR[0x8059])) -#define MCF_DMA_PRIOR30 (*(vuint8 *)(&__MBAR[0x805A])) -#define MCF_DMA_PRIOR31 (*(vuint8 *)(&__MBAR[0x805B])) -#define MCF_DMA_IMCR (*(vuint32*)(&__MBAR[0x805C])) -#define MCF_DMA_TSKSZ0 (*(vuint32*)(&__MBAR[0x8060])) -#define MCF_DMA_TSKSZ1 (*(vuint32*)(&__MBAR[0x8064])) -#define MCF_DMA_DBGCOMP0 (*(vuint32*)(&__MBAR[0x8070])) -#define MCF_DMA_DBGCOMP2 (*(vuint32*)(&__MBAR[0x8074])) -#define MCF_DMA_DBGCTL (*(vuint32*)(&__MBAR[0x8078])) -#define MCF_DMA_TCR(x) (*(vuint16*)(&__MBAR[0x801C + ((x)*0x2)])) -#define MCF_DMA_PRIOR(x) (*(vuint8 *)(&__MBAR[0x803C + ((x)*0x1)])) +#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&__MBAR[0x8000])) +#define MCF_DMA_CP (*(volatile uint32_t*)(&__MBAR[0x8004])) +#define MCF_DMA_EP (*(volatile uint32_t*)(&__MBAR[0x8008])) +#define MCF_DMA_VP (*(volatile uint32_t*)(&__MBAR[0x800C])) +#define MCF_DMA_PTD (*(volatile uint32_t*)(&__MBAR[0x8010])) +#define MCF_DMA_DIPR (*(volatile uint32_t*)(&__MBAR[0x8014])) +#define MCF_DMA_DIMR (*(volatile uint32_t*)(&__MBAR[0x8018])) +#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&__MBAR[0x801C])) +#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&__MBAR[0x801E])) +#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&__MBAR[0x8020])) +#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&__MBAR[0x8022])) +#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&__MBAR[0x8024])) +#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&__MBAR[0x8026])) +#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&__MBAR[0x8028])) +#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&__MBAR[0x802A])) +#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&__MBAR[0x802C])) +#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&__MBAR[0x802E])) +#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&__MBAR[0x8030])) +#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&__MBAR[0x8032])) +#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&__MBAR[0x8034])) +#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&__MBAR[0x8036])) +#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&__MBAR[0x8038])) +#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&__MBAR[0x803A])) +#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&__MBAR[0x803C])) +#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&__MBAR[0x803D])) +#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&__MBAR[0x803E])) +#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&__MBAR[0x803F])) +#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&__MBAR[0x8040])) +#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&__MBAR[0x8041])) +#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&__MBAR[0x8042])) +#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&__MBAR[0x8043])) +#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&__MBAR[0x8044])) +#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&__MBAR[0x8045])) +#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&__MBAR[0x8046])) +#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&__MBAR[0x8047])) +#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&__MBAR[0x8048])) +#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&__MBAR[0x8049])) +#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&__MBAR[0x804A])) +#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&__MBAR[0x804B])) +#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&__MBAR[0x804C])) +#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&__MBAR[0x804D])) +#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&__MBAR[0x804E])) +#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&__MBAR[0x804F])) +#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&__MBAR[0x8050])) +#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&__MBAR[0x8051])) +#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&__MBAR[0x8052])) +#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&__MBAR[0x8053])) +#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&__MBAR[0x8054])) +#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&__MBAR[0x8055])) +#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&__MBAR[0x8056])) +#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&__MBAR[0x8057])) +#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&__MBAR[0x8058])) +#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&__MBAR[0x8059])) +#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&__MBAR[0x805A])) +#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&__MBAR[0x805B])) +#define MCF_DMA_IMCR (*(volatile uint32_t*)(&__MBAR[0x805C])) +#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&__MBAR[0x8060])) +#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&__MBAR[0x8064])) +#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&__MBAR[0x8070])) +#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&__MBAR[0x8074])) +#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&__MBAR[0x8078])) +#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&__MBAR[0x801C + ((x)*0x2)])) +#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&__MBAR[0x803C + ((x)*0x1)])) /* Bit definitions and macros for MCF_DMA_TASKBAR */ diff --git a/BaS_GNU/include/MCF5475_DSPI.h b/BaS_GNU/include/MCF5475_DSPI.h index ec4369d..d969e8f 100644 --- a/BaS_GNU/include/MCF5475_DSPI.h +++ b/BaS_GNU/include/MCF5475_DSPI.h @@ -24,31 +24,31 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_DSPI_DMCR (*(vuint32*)(&__MBAR[0x8A00])) -#define MCF_DSPI_DTCR (*(vuint32*)(&__MBAR[0x8A08])) -#define MCF_DSPI_DCTAR0 (*(vuint32*)(&__MBAR[0x8A0C])) -#define MCF_DSPI_DCTAR1 (*(vuint32*)(&__MBAR[0x8A10])) -#define MCF_DSPI_DCTAR2 (*(vuint32*)(&__MBAR[0x8A14])) -#define MCF_DSPI_DCTAR3 (*(vuint32*)(&__MBAR[0x8A18])) -#define MCF_DSPI_DCTAR4 (*(vuint32*)(&__MBAR[0x8A1C])) -#define MCF_DSPI_DCTAR5 (*(vuint32*)(&__MBAR[0x8A20])) -#define MCF_DSPI_DCTAR6 (*(vuint32*)(&__MBAR[0x8A24])) -#define MCF_DSPI_DCTAR7 (*(vuint32*)(&__MBAR[0x8A28])) -#define MCF_DSPI_DSR (*(vuint32*)(&__MBAR[0x8A2C])) -#define MCF_DSPI_DIRSR (*(vuint32*)(&__MBAR[0x8A30])) -#define MCF_DSPI_DTFR (*(vuint32*)(&__MBAR[0x8A34])) -#define MCF_DSPI_DRFR (*(vuint32*)(&__MBAR[0x8A38])) -#define MCF_DSPI_DTFDR0 (*(vuint32*)(&__MBAR[0x8A3C])) -#define MCF_DSPI_DTFDR1 (*(vuint32*)(&__MBAR[0x8A40])) -#define MCF_DSPI_DTFDR2 (*(vuint32*)(&__MBAR[0x8A44])) -#define MCF_DSPI_DTFDR3 (*(vuint32*)(&__MBAR[0x8A48])) -#define MCF_DSPI_DRFDR0 (*(vuint32*)(&__MBAR[0x8A7C])) -#define MCF_DSPI_DRFDR1 (*(vuint32*)(&__MBAR[0x8A80])) -#define MCF_DSPI_DRFDR2 (*(vuint32*)(&__MBAR[0x8A84])) -#define MCF_DSPI_DRFDR3 (*(vuint32*)(&__MBAR[0x8A88])) -#define MCF_DSPI_DCTAR(x) (*(vuint32*)(&__MBAR[0x8A0C + ((x)*0x4)])) -#define MCF_DSPI_DTFDR(x) (*(vuint32*)(&__MBAR[0x8A3C + ((x)*0x4)])) -#define MCF_DSPI_DRFDR(x) (*(vuint32*)(&__MBAR[0x8A7C + ((x)*0x4)])) +#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&__MBAR[0x8A00])) +#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&__MBAR[0x8A08])) +#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&__MBAR[0x8A0C])) +#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&__MBAR[0x8A10])) +#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&__MBAR[0x8A14])) +#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&__MBAR[0x8A18])) +#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&__MBAR[0x8A1C])) +#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&__MBAR[0x8A20])) +#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&__MBAR[0x8A24])) +#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&__MBAR[0x8A28])) +#define MCF_DSPI_DSR (*(volatile uint32_t*)(&__MBAR[0x8A2C])) +#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&__MBAR[0x8A30])) +#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&__MBAR[0x8A34])) +#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&__MBAR[0x8A38])) +#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&__MBAR[0x8A3C])) +#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&__MBAR[0x8A40])) +#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&__MBAR[0x8A44])) +#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&__MBAR[0x8A48])) +#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&__MBAR[0x8A7C])) +#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&__MBAR[0x8A80])) +#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&__MBAR[0x8A84])) +#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&__MBAR[0x8A88])) +#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&__MBAR[0x8A0C + ((x)*0x4)])) +#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8A3C + ((x)*0x4)])) +#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8A7C + ((x)*0x4)])) /* Bit definitions and macros for MCF_DSPI_DMCR */ diff --git a/BaS_GNU/include/MCF5475_EPORT.h b/BaS_GNU/include/MCF5475_EPORT.h index 6616406..37d9bf8 100644 --- a/BaS_GNU/include/MCF5475_EPORT.h +++ b/BaS_GNU/include/MCF5475_EPORT.h @@ -24,12 +24,12 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_EPORT_EPPAR (*(vuint16*)(&__MBAR[0xF00])) -#define MCF_EPORT_EPDDR (*(vuint8 *)(&__MBAR[0xF04])) -#define MCF_EPORT_EPIER (*(vuint8 *)(&__MBAR[0xF05])) -#define MCF_EPORT_EPDR (*(vuint8 *)(&__MBAR[0xF08])) -#define MCF_EPORT_EPPDR (*(vuint8 *)(&__MBAR[0xF09])) -#define MCF_EPORT_EPFR (*(vuint8 *)(&__MBAR[0xF0C])) +#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&__MBAR[0xF00])) +#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&__MBAR[0xF04])) +#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&__MBAR[0xF05])) +#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&__MBAR[0xF08])) +#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&__MBAR[0xF09])) +#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&__MBAR[0xF0C])) diff --git a/BaS_GNU/include/MCF5475_FBCS.h b/BaS_GNU/include/MCF5475_FBCS.h index 26bb585..938a5f0 100644 --- a/BaS_GNU/include/MCF5475_FBCS.h +++ b/BaS_GNU/include/MCF5475_FBCS.h @@ -24,33 +24,33 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_FBCS0_CSAR (*(vuint32*)(&__MBAR[0x500])) -#define MCF_FBCS0_CSMR (*(vuint32*)(&__MBAR[0x504])) -#define MCF_FBCS0_CSCR (*(vuint32*)(&__MBAR[0x508])) +#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&__MBAR[0x500])) +#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&__MBAR[0x504])) +#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&__MBAR[0x508])) -#define MCF_FBCS1_CSAR (*(vuint32*)(&__MBAR[0x50C])) -#define MCF_FBCS1_CSMR (*(vuint32*)(&__MBAR[0x510])) -#define MCF_FBCS1_CSCR (*(vuint32*)(&__MBAR[0x514])) +#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&__MBAR[0x50C])) +#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&__MBAR[0x510])) +#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&__MBAR[0x514])) -#define MCF_FBCS2_CSAR (*(vuint32*)(&__MBAR[0x518])) -#define MCF_FBCS2_CSMR (*(vuint32*)(&__MBAR[0x51C])) -#define MCF_FBCS2_CSCR (*(vuint32*)(&__MBAR[0x520])) +#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&__MBAR[0x518])) +#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&__MBAR[0x51C])) +#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&__MBAR[0x520])) -#define MCF_FBCS3_CSAR (*(vuint32*)(&__MBAR[0x524])) -#define MCF_FBCS3_CSMR (*(vuint32*)(&__MBAR[0x528])) -#define MCF_FBCS3_CSCR (*(vuint32*)(&__MBAR[0x52C])) +#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&__MBAR[0x524])) +#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&__MBAR[0x528])) +#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&__MBAR[0x52C])) -#define MCF_FBCS4_CSAR (*(vuint32*)(&__MBAR[0x530])) -#define MCF_FBCS4_CSMR (*(vuint32*)(&__MBAR[0x534])) -#define MCF_FBCS4_CSCR (*(vuint32*)(&__MBAR[0x538])) +#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&__MBAR[0x530])) +#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&__MBAR[0x534])) +#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&__MBAR[0x538])) -#define MCF_FBCS5_CSAR (*(vuint32*)(&__MBAR[0x53C])) -#define MCF_FBCS5_CSMR (*(vuint32*)(&__MBAR[0x540])) -#define MCF_FBCS5_CSCR (*(vuint32*)(&__MBAR[0x544])) +#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&__MBAR[0x53C])) +#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&__MBAR[0x540])) +#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&__MBAR[0x544])) -#define MCF_FBCS_CSAR(x) (*(vuint32*)(&__MBAR[0x500 + ((x)*0xC)])) -#define MCF_FBCS_CSMR(x) (*(vuint32*)(&__MBAR[0x504 + ((x)*0xC)])) -#define MCF_FBCS_CSCR(x) (*(vuint32*)(&__MBAR[0x508 + ((x)*0xC)])) +#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&__MBAR[0x500 + ((x)*0xC)])) +#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&__MBAR[0x504 + ((x)*0xC)])) +#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&__MBAR[0x508 + ((x)*0xC)])) /* Bit definitions and macros for MCF_FBCS_CSAR */ diff --git a/BaS_GNU/include/MCF5475_FEC.h b/BaS_GNU/include/MCF5475_FEC.h index 01a0ae7..dc998ff 100644 --- a/BaS_GNU/include/MCF5475_FEC.h +++ b/BaS_GNU/include/MCF5475_FEC.h @@ -24,278 +24,278 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_FEC0_EIR (*(vuint32*)(&__MBAR[0x9004])) -#define MCF_FEC0_EIMR (*(vuint32*)(&__MBAR[0x9008])) -#define MCF_FEC0_ECR (*(vuint32*)(&__MBAR[0x9024])) -#define MCF_FEC0_MMFR (*(vuint32*)(&__MBAR[0x9040])) -#define MCF_FEC0_MSCR (*(vuint32*)(&__MBAR[0x9044])) -#define MCF_FEC0_MIBC (*(vuint32*)(&__MBAR[0x9064])) -#define MCF_FEC0_RCR (*(vuint32*)(&__MBAR[0x9084])) -#define MCF_FEC0_RHR (*(vuint32*)(&__MBAR[0x9088])) -#define MCF_FEC0_TCR (*(vuint32*)(&__MBAR[0x90C4])) -#define MCF_FEC0_PALR (*(vuint32*)(&__MBAR[0x90E4])) -#define MCF_FEC0_PAHR (*(vuint32*)(&__MBAR[0x90E8])) -#define MCF_FEC0_OPD (*(vuint32*)(&__MBAR[0x90EC])) -#define MCF_FEC0_IAUR (*(vuint32*)(&__MBAR[0x9118])) -#define MCF_FEC0_IALR (*(vuint32*)(&__MBAR[0x911C])) -#define MCF_FEC0_GAUR (*(vuint32*)(&__MBAR[0x9120])) -#define MCF_FEC0_GALR (*(vuint32*)(&__MBAR[0x9124])) -#define MCF_FEC0_FECTFWR (*(vuint32*)(&__MBAR[0x9144])) -#define MCF_FEC0_FECRFDR (*(vuint32*)(&__MBAR[0x9184])) -#define MCF_FEC0_FECRFSR (*(vuint32*)(&__MBAR[0x9188])) -#define MCF_FEC0_FECRFCR (*(vuint32*)(&__MBAR[0x918C])) -#define MCF_FEC0_FECRLRFP (*(vuint32*)(&__MBAR[0x9190])) -#define MCF_FEC0_FECRLWFP (*(vuint32*)(&__MBAR[0x9194])) -#define MCF_FEC0_FECRFAR (*(vuint32*)(&__MBAR[0x9198])) -#define MCF_FEC0_FECRFRP (*(vuint32*)(&__MBAR[0x919C])) -#define MCF_FEC0_FECRFWP (*(vuint32*)(&__MBAR[0x91A0])) -#define MCF_FEC0_FECTFDR (*(vuint32*)(&__MBAR[0x91A4])) -#define MCF_FEC0_FECTFSR (*(vuint32*)(&__MBAR[0x91A8])) -#define MCF_FEC0_FECTFCR (*(vuint32*)(&__MBAR[0x91AC])) -#define MCF_FEC0_FECTLRFP (*(vuint32*)(&__MBAR[0x91B0])) -#define MCF_FEC0_FECTLWFP (*(vuint32*)(&__MBAR[0x91B4])) -#define MCF_FEC0_FECTFAR (*(vuint32*)(&__MBAR[0x91B8])) -#define MCF_FEC0_FECTFRP (*(vuint32*)(&__MBAR[0x91BC])) -#define MCF_FEC0_FECTFWP (*(vuint32*)(&__MBAR[0x91C0])) -#define MCF_FEC0_FECFRST (*(vuint32*)(&__MBAR[0x91C4])) -#define MCF_FEC0_FECCTCWR (*(vuint32*)(&__MBAR[0x91C8])) -#define MCF_FEC0_RMON_T_DROP (*(vuint32*)(&__MBAR[0x9200])) -#define MCF_FEC0_RMON_T_PACKETS (*(vuint32*)(&__MBAR[0x9204])) -#define MCF_FEC0_RMON_T_BC_PKT (*(vuint32*)(&__MBAR[0x9208])) -#define MCF_FEC0_RMON_T_MC_PKT (*(vuint32*)(&__MBAR[0x920C])) -#define MCF_FEC0_RMON_T_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9210])) -#define MCF_FEC0_RMON_T_UNDERSIZE (*(vuint32*)(&__MBAR[0x9214])) -#define MCF_FEC0_RMON_T_OVERSIZE (*(vuint32*)(&__MBAR[0x9218])) -#define MCF_FEC0_RMON_T_FRAG (*(vuint32*)(&__MBAR[0x921C])) -#define MCF_FEC0_RMON_T_JAB (*(vuint32*)(&__MBAR[0x9220])) -#define MCF_FEC0_RMON_T_COL (*(vuint32*)(&__MBAR[0x9224])) -#define MCF_FEC0_RMON_T_P64 (*(vuint32*)(&__MBAR[0x9228])) -#define MCF_FEC0_RMON_T_P65TO127 (*(vuint32*)(&__MBAR[0x922C])) -#define MCF_FEC0_RMON_T_P128TO255 (*(vuint32*)(&__MBAR[0x9230])) -#define MCF_FEC0_RMON_T_P256TO511 (*(vuint32*)(&__MBAR[0x9234])) -#define MCF_FEC0_RMON_T_P512TO1023 (*(vuint32*)(&__MBAR[0x9238])) -#define MCF_FEC0_RMON_T_P1024TO2047 (*(vuint32*)(&__MBAR[0x923C])) -#define MCF_FEC0_RMON_T_P_GTE2048 (*(vuint32*)(&__MBAR[0x9240])) -#define MCF_FEC0_RMON_T_OCTETS (*(vuint32*)(&__MBAR[0x9244])) -#define MCF_FEC0_IEEE_T_DROP (*(vuint32*)(&__MBAR[0x9248])) -#define MCF_FEC0_IEEE_T_FRAME_OK (*(vuint32*)(&__MBAR[0x924C])) -#define MCF_FEC0_IEEE_T_1COL (*(vuint32*)(&__MBAR[0x9250])) -#define MCF_FEC0_IEEE_T_MCOL (*(vuint32*)(&__MBAR[0x9254])) -#define MCF_FEC0_IEEE_T_DEF (*(vuint32*)(&__MBAR[0x9258])) -#define MCF_FEC0_IEEE_T_LCOL (*(vuint32*)(&__MBAR[0x925C])) -#define MCF_FEC0_IEEE_T_EXCOL (*(vuint32*)(&__MBAR[0x9260])) -#define MCF_FEC0_IEEE_T_MACERR (*(vuint32*)(&__MBAR[0x9264])) -#define MCF_FEC0_IEEE_T_CSERR (*(vuint32*)(&__MBAR[0x9268])) -#define MCF_FEC0_IEEE_T_SQE (*(vuint32*)(&__MBAR[0x926C])) -#define MCF_FEC0_IEEE_T_FDXFC (*(vuint32*)(&__MBAR[0x9270])) -#define MCF_FEC0_IEEE_T_OCTETS_OK (*(vuint32*)(&__MBAR[0x9274])) -#define MCF_FEC0_RMON_R_DROP (*(vuint32*)(&__MBAR[0x9280])) -#define MCF_FEC0_RMON_R_PACKETS (*(vuint32*)(&__MBAR[0x9284])) -#define MCF_FEC0_RMON_R_BC_PKT (*(vuint32*)(&__MBAR[0x9288])) -#define MCF_FEC0_RMON_R_MC_PKT (*(vuint32*)(&__MBAR[0x928C])) -#define MCF_FEC0_RMON_R_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9290])) -#define MCF_FEC0_RMON_R_UNDERSIZE (*(vuint32*)(&__MBAR[0x9294])) -#define MCF_FEC0_RMON_R_OVERSIZE (*(vuint32*)(&__MBAR[0x9298])) -#define MCF_FEC0_RMON_R_FRAG (*(vuint32*)(&__MBAR[0x929C])) -#define MCF_FEC0_RMON_R_JAB (*(vuint32*)(&__MBAR[0x92A0])) -#define MCF_FEC0_RMON_R_RESVD_0 (*(vuint32*)(&__MBAR[0x92A4])) -#define MCF_FEC0_RMON_R_P64 (*(vuint32*)(&__MBAR[0x92A8])) -#define MCF_FEC0_RMON_R_P65TO127 (*(vuint32*)(&__MBAR[0x92AC])) -#define MCF_FEC0_RMON_R_P128TO255 (*(vuint32*)(&__MBAR[0x92B0])) -#define MCF_FEC0_RMON_R_P256TO511 (*(vuint32*)(&__MBAR[0x92B4])) -#define MCF_FEC0_RMON_R_P512TO1023 (*(vuint32*)(&__MBAR[0x92B8])) -#define MCF_FEC0_RMON_R_P1024TO2047 (*(vuint32*)(&__MBAR[0x92BC])) -#define MCF_FEC0_RMON_R_P_GTE2048 (*(vuint32*)(&__MBAR[0x92C0])) -#define MCF_FEC0_RMON_R_OCTETS (*(vuint32*)(&__MBAR[0x92C4])) -#define MCF_FEC0_IEEE_R_DROP (*(vuint32*)(&__MBAR[0x92C8])) -#define MCF_FEC0_IEEE_R_FRAME_OK (*(vuint32*)(&__MBAR[0x92CC])) -#define MCF_FEC0_IEEE_R_CRC (*(vuint32*)(&__MBAR[0x92D0])) -#define MCF_FEC0_IEEE_R_ALIGN (*(vuint32*)(&__MBAR[0x92D4])) -#define MCF_FEC0_IEEE_R_MACERR (*(vuint32*)(&__MBAR[0x92D8])) -#define MCF_FEC0_IEEE_R_FDXFC (*(vuint32*)(&__MBAR[0x92DC])) -#define MCF_FEC0_IEEE_R_OCTETS_OK (*(vuint32*)(&__MBAR[0x92E0])) +#define MCF_FEC0_EIR (*(volatile uint32_t*)(&__MBAR[0x9004])) +#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&__MBAR[0x9008])) +#define MCF_FEC0_ECR (*(volatile uint32_t*)(&__MBAR[0x9024])) +#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&__MBAR[0x9040])) +#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&__MBAR[0x9044])) +#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&__MBAR[0x9064])) +#define MCF_FEC0_RCR (*(volatile uint32_t*)(&__MBAR[0x9084])) +#define MCF_FEC0_RHR (*(volatile uint32_t*)(&__MBAR[0x9088])) +#define MCF_FEC0_TCR (*(volatile uint32_t*)(&__MBAR[0x90C4])) +#define MCF_FEC0_PALR (*(volatile uint32_t*)(&__MBAR[0x90E4])) +#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&__MBAR[0x90E8])) +#define MCF_FEC0_OPD (*(volatile uint32_t*)(&__MBAR[0x90EC])) +#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&__MBAR[0x9118])) +#define MCF_FEC0_IALR (*(volatile uint32_t*)(&__MBAR[0x911C])) +#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&__MBAR[0x9120])) +#define MCF_FEC0_GALR (*(volatile uint32_t*)(&__MBAR[0x9124])) +#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&__MBAR[0x9144])) +#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&__MBAR[0x9184])) +#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&__MBAR[0x9188])) +#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&__MBAR[0x918C])) +#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&__MBAR[0x9190])) +#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&__MBAR[0x9194])) +#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&__MBAR[0x9198])) +#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&__MBAR[0x919C])) +#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&__MBAR[0x91A0])) +#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&__MBAR[0x91A4])) +#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&__MBAR[0x91A8])) +#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&__MBAR[0x91AC])) +#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&__MBAR[0x91B0])) +#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&__MBAR[0x91B4])) +#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&__MBAR[0x91B8])) +#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&__MBAR[0x91BC])) +#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&__MBAR[0x91C0])) +#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&__MBAR[0x91C4])) +#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&__MBAR[0x91C8])) +#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9200])) +#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9204])) +#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9208])) +#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x920C])) +#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9210])) +#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9214])) +#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9218])) +#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&__MBAR[0x921C])) +#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&__MBAR[0x9220])) +#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&__MBAR[0x9224])) +#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&__MBAR[0x9228])) +#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x922C])) +#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x9230])) +#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x9234])) +#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x9238])) +#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x923C])) +#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x9240])) +#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&__MBAR[0x9244])) +#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9248])) +#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x924C])) +#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&__MBAR[0x9250])) +#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&__MBAR[0x9254])) +#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&__MBAR[0x9258])) +#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&__MBAR[0x925C])) +#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&__MBAR[0x9260])) +#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&__MBAR[0x9264])) +#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&__MBAR[0x9268])) +#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&__MBAR[0x926C])) +#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&__MBAR[0x9270])) +#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x9274])) +#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&__MBAR[0x9280])) +#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9284])) +#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9288])) +#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x928C])) +#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9290])) +#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9294])) +#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9298])) +#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&__MBAR[0x929C])) +#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&__MBAR[0x92A0])) +#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&__MBAR[0x92A4])) +#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&__MBAR[0x92A8])) +#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x92AC])) +#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x92B0])) +#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x92B4])) +#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x92B8])) +#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x92BC])) +#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x92C0])) +#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&__MBAR[0x92C4])) +#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&__MBAR[0x92C8])) +#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x92CC])) +#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&__MBAR[0x92D0])) +#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&__MBAR[0x92D4])) +#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&__MBAR[0x92D8])) +#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&__MBAR[0x92DC])) +#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x92E0])) -#define MCF_FEC1_EIR (*(vuint32*)(&__MBAR[0x9804])) -#define MCF_FEC1_EIMR (*(vuint32*)(&__MBAR[0x9808])) -#define MCF_FEC1_ECR (*(vuint32*)(&__MBAR[0x9824])) -#define MCF_FEC1_MMFR (*(vuint32*)(&__MBAR[0x9840])) -#define MCF_FEC1_MSCR (*(vuint32*)(&__MBAR[0x9844])) -#define MCF_FEC1_MIBC (*(vuint32*)(&__MBAR[0x9864])) -#define MCF_FEC1_RCR (*(vuint32*)(&__MBAR[0x9884])) -#define MCF_FEC1_RHR (*(vuint32*)(&__MBAR[0x9888])) -#define MCF_FEC1_TCR (*(vuint32*)(&__MBAR[0x98C4])) -#define MCF_FEC1_PALR (*(vuint32*)(&__MBAR[0x98E4])) -#define MCF_FEC1_PAHR (*(vuint32*)(&__MBAR[0x98E8])) -#define MCF_FEC1_OPD (*(vuint32*)(&__MBAR[0x98EC])) -#define MCF_FEC1_IAUR (*(vuint32*)(&__MBAR[0x9918])) -#define MCF_FEC1_IALR (*(vuint32*)(&__MBAR[0x991C])) -#define MCF_FEC1_GAUR (*(vuint32*)(&__MBAR[0x9920])) -#define MCF_FEC1_GALR (*(vuint32*)(&__MBAR[0x9924])) -#define MCF_FEC1_FECTFWR (*(vuint32*)(&__MBAR[0x9944])) -#define MCF_FEC1_FECRFDR (*(vuint32*)(&__MBAR[0x9984])) -#define MCF_FEC1_FECRFSR (*(vuint32*)(&__MBAR[0x9988])) -#define MCF_FEC1_FECRFCR (*(vuint32*)(&__MBAR[0x998C])) -#define MCF_FEC1_FECRLRFP (*(vuint32*)(&__MBAR[0x9990])) -#define MCF_FEC1_FECRLWFP (*(vuint32*)(&__MBAR[0x9994])) -#define MCF_FEC1_FECRFAR (*(vuint32*)(&__MBAR[0x9998])) -#define MCF_FEC1_FECRFRP (*(vuint32*)(&__MBAR[0x999C])) -#define MCF_FEC1_FECRFWP (*(vuint32*)(&__MBAR[0x99A0])) -#define MCF_FEC1_FECTFDR (*(vuint32*)(&__MBAR[0x99A4])) -#define MCF_FEC1_FECTFSR (*(vuint32*)(&__MBAR[0x99A8])) -#define MCF_FEC1_FECTFCR (*(vuint32*)(&__MBAR[0x99AC])) -#define MCF_FEC1_FECTLRFP (*(vuint32*)(&__MBAR[0x99B0])) -#define MCF_FEC1_FECTLWFP (*(vuint32*)(&__MBAR[0x99B4])) -#define MCF_FEC1_FECTFAR (*(vuint32*)(&__MBAR[0x99B8])) -#define MCF_FEC1_FECTFRP (*(vuint32*)(&__MBAR[0x99BC])) -#define MCF_FEC1_FECTFWP (*(vuint32*)(&__MBAR[0x99C0])) -#define MCF_FEC1_FECFRST (*(vuint32*)(&__MBAR[0x99C4])) -#define MCF_FEC1_FECCTCWR (*(vuint32*)(&__MBAR[0x99C8])) -#define MCF_FEC1_RMON_T_DROP (*(vuint32*)(&__MBAR[0x9A00])) -#define MCF_FEC1_RMON_T_PACKETS (*(vuint32*)(&__MBAR[0x9A04])) -#define MCF_FEC1_RMON_T_BC_PKT (*(vuint32*)(&__MBAR[0x9A08])) -#define MCF_FEC1_RMON_T_MC_PKT (*(vuint32*)(&__MBAR[0x9A0C])) -#define MCF_FEC1_RMON_T_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9A10])) -#define MCF_FEC1_RMON_T_UNDERSIZE (*(vuint32*)(&__MBAR[0x9A14])) -#define MCF_FEC1_RMON_T_OVERSIZE (*(vuint32*)(&__MBAR[0x9A18])) -#define MCF_FEC1_RMON_T_FRAG (*(vuint32*)(&__MBAR[0x9A1C])) -#define MCF_FEC1_RMON_T_JAB (*(vuint32*)(&__MBAR[0x9A20])) -#define MCF_FEC1_RMON_T_COL (*(vuint32*)(&__MBAR[0x9A24])) -#define MCF_FEC1_RMON_T_P64 (*(vuint32*)(&__MBAR[0x9A28])) -#define MCF_FEC1_RMON_T_P65TO127 (*(vuint32*)(&__MBAR[0x9A2C])) -#define MCF_FEC1_RMON_T_P128TO255 (*(vuint32*)(&__MBAR[0x9A30])) -#define MCF_FEC1_RMON_T_P256TO511 (*(vuint32*)(&__MBAR[0x9A34])) -#define MCF_FEC1_RMON_T_P512TO1023 (*(vuint32*)(&__MBAR[0x9A38])) -#define MCF_FEC1_RMON_T_P1024TO2047 (*(vuint32*)(&__MBAR[0x9A3C])) -#define MCF_FEC1_RMON_T_P_GTE2048 (*(vuint32*)(&__MBAR[0x9A40])) -#define MCF_FEC1_RMON_T_OCTETS (*(vuint32*)(&__MBAR[0x9A44])) -#define MCF_FEC1_IEEE_T_DROP (*(vuint32*)(&__MBAR[0x9A48])) -#define MCF_FEC1_IEEE_T_FRAME_OK (*(vuint32*)(&__MBAR[0x9A4C])) -#define MCF_FEC1_IEEE_T_1COL (*(vuint32*)(&__MBAR[0x9A50])) -#define MCF_FEC1_IEEE_T_MCOL (*(vuint32*)(&__MBAR[0x9A54])) -#define MCF_FEC1_IEEE_T_DEF (*(vuint32*)(&__MBAR[0x9A58])) -#define MCF_FEC1_IEEE_T_LCOL (*(vuint32*)(&__MBAR[0x9A5C])) -#define MCF_FEC1_IEEE_T_EXCOL (*(vuint32*)(&__MBAR[0x9A60])) -#define MCF_FEC1_IEEE_T_MACERR (*(vuint32*)(&__MBAR[0x9A64])) -#define MCF_FEC1_IEEE_T_CSERR (*(vuint32*)(&__MBAR[0x9A68])) -#define MCF_FEC1_IEEE_T_SQE (*(vuint32*)(&__MBAR[0x9A6C])) -#define MCF_FEC1_IEEE_T_FDXFC (*(vuint32*)(&__MBAR[0x9A70])) -#define MCF_FEC1_IEEE_T_OCTETS_OK (*(vuint32*)(&__MBAR[0x9A74])) -#define MCF_FEC1_RMON_R_DROP (*(vuint32*)(&__MBAR[0x9A80])) -#define MCF_FEC1_RMON_R_PACKETS (*(vuint32*)(&__MBAR[0x9A84])) -#define MCF_FEC1_RMON_R_BC_PKT (*(vuint32*)(&__MBAR[0x9A88])) -#define MCF_FEC1_RMON_R_MC_PKT (*(vuint32*)(&__MBAR[0x9A8C])) -#define MCF_FEC1_RMON_R_CRC_ALIGN (*(vuint32*)(&__MBAR[0x9A90])) -#define MCF_FEC1_RMON_R_UNDERSIZE (*(vuint32*)(&__MBAR[0x9A94])) -#define MCF_FEC1_RMON_R_OVERSIZE (*(vuint32*)(&__MBAR[0x9A98])) -#define MCF_FEC1_RMON_R_FRAG (*(vuint32*)(&__MBAR[0x9A9C])) -#define MCF_FEC1_RMON_R_JAB (*(vuint32*)(&__MBAR[0x9AA0])) -#define MCF_FEC1_RMON_R_RESVD_0 (*(vuint32*)(&__MBAR[0x9AA4])) -#define MCF_FEC1_RMON_R_P64 (*(vuint32*)(&__MBAR[0x9AA8])) -#define MCF_FEC1_RMON_R_P65TO127 (*(vuint32*)(&__MBAR[0x9AAC])) -#define MCF_FEC1_RMON_R_P128TO255 (*(vuint32*)(&__MBAR[0x9AB0])) -#define MCF_FEC1_RMON_R_P256TO511 (*(vuint32*)(&__MBAR[0x9AB4])) -#define MCF_FEC1_RMON_R_P512TO1023 (*(vuint32*)(&__MBAR[0x9AB8])) -#define MCF_FEC1_RMON_R_P1024TO2047 (*(vuint32*)(&__MBAR[0x9ABC])) -#define MCF_FEC1_RMON_R_P_GTE2048 (*(vuint32*)(&__MBAR[0x9AC0])) -#define MCF_FEC1_RMON_R_OCTETS (*(vuint32*)(&__MBAR[0x9AC4])) -#define MCF_FEC1_IEEE_R_DROP (*(vuint32*)(&__MBAR[0x9AC8])) -#define MCF_FEC1_IEEE_R_FRAME_OK (*(vuint32*)(&__MBAR[0x9ACC])) -#define MCF_FEC1_IEEE_R_CRC (*(vuint32*)(&__MBAR[0x9AD0])) -#define MCF_FEC1_IEEE_R_ALIGN (*(vuint32*)(&__MBAR[0x9AD4])) -#define MCF_FEC1_IEEE_R_MACERR (*(vuint32*)(&__MBAR[0x9AD8])) -#define MCF_FEC1_IEEE_R_FDXFC (*(vuint32*)(&__MBAR[0x9ADC])) -#define MCF_FEC1_IEEE_R_OCTETS_OK (*(vuint32*)(&__MBAR[0x9AE0])) +#define MCF_FEC1_EIR (*(volatile uint32_t*)(&__MBAR[0x9804])) +#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&__MBAR[0x9808])) +#define MCF_FEC1_ECR (*(volatile uint32_t*)(&__MBAR[0x9824])) +#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&__MBAR[0x9840])) +#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&__MBAR[0x9844])) +#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&__MBAR[0x9864])) +#define MCF_FEC1_RCR (*(volatile uint32_t*)(&__MBAR[0x9884])) +#define MCF_FEC1_RHR (*(volatile uint32_t*)(&__MBAR[0x9888])) +#define MCF_FEC1_TCR (*(volatile uint32_t*)(&__MBAR[0x98C4])) +#define MCF_FEC1_PALR (*(volatile uint32_t*)(&__MBAR[0x98E4])) +#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&__MBAR[0x98E8])) +#define MCF_FEC1_OPD (*(volatile uint32_t*)(&__MBAR[0x98EC])) +#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&__MBAR[0x9918])) +#define MCF_FEC1_IALR (*(volatile uint32_t*)(&__MBAR[0x991C])) +#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&__MBAR[0x9920])) +#define MCF_FEC1_GALR (*(volatile uint32_t*)(&__MBAR[0x9924])) +#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&__MBAR[0x9944])) +#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&__MBAR[0x9984])) +#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&__MBAR[0x9988])) +#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&__MBAR[0x998C])) +#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&__MBAR[0x9990])) +#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&__MBAR[0x9994])) +#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&__MBAR[0x9998])) +#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&__MBAR[0x999C])) +#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&__MBAR[0x99A0])) +#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&__MBAR[0x99A4])) +#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&__MBAR[0x99A8])) +#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&__MBAR[0x99AC])) +#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&__MBAR[0x99B0])) +#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&__MBAR[0x99B4])) +#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&__MBAR[0x99B8])) +#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&__MBAR[0x99BC])) +#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&__MBAR[0x99C0])) +#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&__MBAR[0x99C4])) +#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&__MBAR[0x99C8])) +#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9A00])) +#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9A04])) +#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A08])) +#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A0C])) +#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9A10])) +#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A14])) +#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A18])) +#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&__MBAR[0x9A1C])) +#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&__MBAR[0x9A20])) +#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&__MBAR[0x9A24])) +#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&__MBAR[0x9A28])) +#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x9A2C])) +#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x9A30])) +#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x9A34])) +#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x9A38])) +#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x9A3C])) +#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x9A40])) +#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&__MBAR[0x9A44])) +#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9A48])) +#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x9A4C])) +#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&__MBAR[0x9A50])) +#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&__MBAR[0x9A54])) +#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&__MBAR[0x9A58])) +#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&__MBAR[0x9A5C])) +#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&__MBAR[0x9A60])) +#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&__MBAR[0x9A64])) +#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&__MBAR[0x9A68])) +#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&__MBAR[0x9A6C])) +#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&__MBAR[0x9A70])) +#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x9A74])) +#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&__MBAR[0x9A80])) +#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9A84])) +#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A88])) +#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A8C])) +#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9A90])) +#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A94])) +#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A98])) +#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&__MBAR[0x9A9C])) +#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&__MBAR[0x9AA0])) +#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&__MBAR[0x9AA4])) +#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&__MBAR[0x9AA8])) +#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x9AAC])) +#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x9AB0])) +#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x9AB4])) +#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x9AB8])) +#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x9ABC])) +#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x9AC0])) +#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&__MBAR[0x9AC4])) +#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&__MBAR[0x9AC8])) +#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x9ACC])) +#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&__MBAR[0x9AD0])) +#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9AD4])) +#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&__MBAR[0x9AD8])) +#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&__MBAR[0x9ADC])) +#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x9AE0])) -#define MCF_FEC_EIR(x) (*(vuint32*)(&__MBAR[0x9004 + ((x)*0x800)])) -#define MCF_FEC_EIMR(x) (*(vuint32*)(&__MBAR[0x9008 + ((x)*0x800)])) -#define MCF_FEC_ECR(x) (*(vuint32*)(&__MBAR[0x9024 + ((x)*0x800)])) -#define MCF_FEC_MMFR(x) (*(vuint32*)(&__MBAR[0x9040 + ((x)*0x800)])) -#define MCF_FEC_MSCR(x) (*(vuint32*)(&__MBAR[0x9044 + ((x)*0x800)])) -#define MCF_FEC_MIBC(x) (*(vuint32*)(&__MBAR[0x9064 + ((x)*0x800)])) -#define MCF_FEC_RCR(x) (*(vuint32*)(&__MBAR[0x9084 + ((x)*0x800)])) -#define MCF_FEC_RHR(x) (*(vuint32*)(&__MBAR[0x9088 + ((x)*0x800)])) -#define MCF_FEC_TCR(x) (*(vuint32*)(&__MBAR[0x90C4 + ((x)*0x800)])) -#define MCF_FEC_PALR(x) (*(vuint32*)(&__MBAR[0x90E4 + ((x)*0x800)])) -#define MCF_FEC_PAHR(x) (*(vuint32*)(&__MBAR[0x90E8 + ((x)*0x800)])) -#define MCF_FEC_OPD(x) (*(vuint32*)(&__MBAR[0x90EC + ((x)*0x800)])) -#define MCF_FEC_IAUR(x) (*(vuint32*)(&__MBAR[0x9118 + ((x)*0x800)])) -#define MCF_FEC_IALR(x) (*(vuint32*)(&__MBAR[0x911C + ((x)*0x800)])) -#define MCF_FEC_GAUR(x) (*(vuint32*)(&__MBAR[0x9120 + ((x)*0x800)])) -#define MCF_FEC_GALR(x) (*(vuint32*)(&__MBAR[0x9124 + ((x)*0x800)])) -#define MCF_FEC_FECTFWR(x) (*(vuint32*)(&__MBAR[0x9144 + ((x)*0x800)])) -#define MCF_FEC_FECRFDR(x) (*(vuint32*)(&__MBAR[0x9184 + ((x)*0x800)])) -#define MCF_FEC_FECRFSR(x) (*(vuint32*)(&__MBAR[0x9188 + ((x)*0x800)])) -#define MCF_FEC_FECRFCR(x) (*(vuint32*)(&__MBAR[0x918C + ((x)*0x800)])) -#define MCF_FEC_FECRLRFP(x) (*(vuint32*)(&__MBAR[0x9190 + ((x)*0x800)])) -#define MCF_FEC_FECRLWFP(x) (*(vuint32*)(&__MBAR[0x9194 + ((x)*0x800)])) -#define MCF_FEC_FECRFAR(x) (*(vuint32*)(&__MBAR[0x9198 + ((x)*0x800)])) -#define MCF_FEC_FECRFRP(x) (*(vuint32*)(&__MBAR[0x919C + ((x)*0x800)])) -#define MCF_FEC_FECRFWP(x) (*(vuint32*)(&__MBAR[0x91A0 + ((x)*0x800)])) -#define MCF_FEC_FECTFDR(x) (*(vuint32*)(&__MBAR[0x91A4 + ((x)*0x800)])) -#define MCF_FEC_FECTFSR(x) (*(vuint32*)(&__MBAR[0x91A8 + ((x)*0x800)])) -#define MCF_FEC_FECTFCR(x) (*(vuint32*)(&__MBAR[0x91AC + ((x)*0x800)])) -#define MCF_FEC_FECTLRFP(x) (*(vuint32*)(&__MBAR[0x91B0 + ((x)*0x800)])) -#define MCF_FEC_FECTLWFP(x) (*(vuint32*)(&__MBAR[0x91B4 + ((x)*0x800)])) -#define MCF_FEC_FECTFAR(x) (*(vuint32*)(&__MBAR[0x91B8 + ((x)*0x800)])) -#define MCF_FEC_FECTFRP(x) (*(vuint32*)(&__MBAR[0x91BC + ((x)*0x800)])) -#define MCF_FEC_FECTFWP(x) (*(vuint32*)(&__MBAR[0x91C0 + ((x)*0x800)])) -#define MCF_FEC_FECFRST(x) (*(vuint32*)(&__MBAR[0x91C4 + ((x)*0x800)])) -#define MCF_FEC_FECCTCWR(x) (*(vuint32*)(&__MBAR[0x91C8 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_DROP(x) (*(vuint32*)(&__MBAR[0x9200 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_PACKETS(x) (*(vuint32*)(&__MBAR[0x9204 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_BC_PKT(x) (*(vuint32*)(&__MBAR[0x9208 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_MC_PKT(x) (*(vuint32*)(&__MBAR[0x920C + ((x)*0x800)])) -#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(vuint32*)(&__MBAR[0x9210 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(vuint32*)(&__MBAR[0x9214 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_OVERSIZE(x) (*(vuint32*)(&__MBAR[0x9218 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_FRAG(x) (*(vuint32*)(&__MBAR[0x921C + ((x)*0x800)])) -#define MCF_FEC_RMON_T_JAB(x) (*(vuint32*)(&__MBAR[0x9220 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_COL(x) (*(vuint32*)(&__MBAR[0x9224 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P64(x) (*(vuint32*)(&__MBAR[0x9228 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P65TO127(x) (*(vuint32*)(&__MBAR[0x922C + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P128TO255(x) (*(vuint32*)(&__MBAR[0x9230 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P256TO511(x) (*(vuint32*)(&__MBAR[0x9234 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P512TO1023(x) (*(vuint32*)(&__MBAR[0x9238 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P1024TO2047(x) (*(vuint32*)(&__MBAR[0x923C + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P_GTE2048(x) (*(vuint32*)(&__MBAR[0x9240 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_OCTETS(x) (*(vuint32*)(&__MBAR[0x9244 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_DROP(x) (*(vuint32*)(&__MBAR[0x9248 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(vuint32*)(&__MBAR[0x924C + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_1COL(x) (*(vuint32*)(&__MBAR[0x9250 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_MCOL(x) (*(vuint32*)(&__MBAR[0x9254 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_DEF(x) (*(vuint32*)(&__MBAR[0x9258 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_LCOL(x) (*(vuint32*)(&__MBAR[0x925C + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_EXCOL(x) (*(vuint32*)(&__MBAR[0x9260 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_MACERR(x) (*(vuint32*)(&__MBAR[0x9264 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_CSERR(x) (*(vuint32*)(&__MBAR[0x9268 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_SQE(x) (*(vuint32*)(&__MBAR[0x926C + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_FDXFC(x) (*(vuint32*)(&__MBAR[0x9270 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(vuint32*)(&__MBAR[0x9274 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_DROP(x) (*(vuint32*)(&__MBAR[0x9280 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_PACKETS(x) (*(vuint32*)(&__MBAR[0x9284 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_BC_PKT(x) (*(vuint32*)(&__MBAR[0x9288 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_MC_PKT(x) (*(vuint32*)(&__MBAR[0x928C + ((x)*0x800)])) -#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(vuint32*)(&__MBAR[0x9290 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(vuint32*)(&__MBAR[0x9294 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_OVERSIZE(x) (*(vuint32*)(&__MBAR[0x9298 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_FRAG(x) (*(vuint32*)(&__MBAR[0x929C + ((x)*0x800)])) -#define MCF_FEC_RMON_R_JAB(x) (*(vuint32*)(&__MBAR[0x92A0 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_RESVD_0(x) (*(vuint32*)(&__MBAR[0x92A4 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P64(x) (*(vuint32*)(&__MBAR[0x92A8 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P65TO127(x) (*(vuint32*)(&__MBAR[0x92AC + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P128TO255(x) (*(vuint32*)(&__MBAR[0x92B0 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P256TO511(x) (*(vuint32*)(&__MBAR[0x92B4 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P512TO1023(x) (*(vuint32*)(&__MBAR[0x92B8 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P1024TO2047(x) (*(vuint32*)(&__MBAR[0x92BC + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P_GTE2048(x) (*(vuint32*)(&__MBAR[0x92C0 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_OCTETS(x) (*(vuint32*)(&__MBAR[0x92C4 + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_DROP(x) (*(vuint32*)(&__MBAR[0x92C8 + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(vuint32*)(&__MBAR[0x92CC + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_CRC(x) (*(vuint32*)(&__MBAR[0x92D0 + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_ALIGN(x) (*(vuint32*)(&__MBAR[0x92D4 + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_MACERR(x) (*(vuint32*)(&__MBAR[0x92D8 + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_FDXFC(x) (*(vuint32*)(&__MBAR[0x92DC + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(vuint32*)(&__MBAR[0x92E0 + ((x)*0x800)])) +#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&__MBAR[0x9004 + ((x)*0x800)])) +#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&__MBAR[0x9008 + ((x)*0x800)])) +#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&__MBAR[0x9024 + ((x)*0x800)])) +#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&__MBAR[0x9040 + ((x)*0x800)])) +#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&__MBAR[0x9044 + ((x)*0x800)])) +#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&__MBAR[0x9064 + ((x)*0x800)])) +#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&__MBAR[0x9084 + ((x)*0x800)])) +#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&__MBAR[0x9088 + ((x)*0x800)])) +#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&__MBAR[0x90C4 + ((x)*0x800)])) +#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&__MBAR[0x90E4 + ((x)*0x800)])) +#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&__MBAR[0x90E8 + ((x)*0x800)])) +#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&__MBAR[0x90EC + ((x)*0x800)])) +#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&__MBAR[0x9118 + ((x)*0x800)])) +#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&__MBAR[0x911C + ((x)*0x800)])) +#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&__MBAR[0x9120 + ((x)*0x800)])) +#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&__MBAR[0x9124 + ((x)*0x800)])) +#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&__MBAR[0x9144 + ((x)*0x800)])) +#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&__MBAR[0x9184 + ((x)*0x800)])) +#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&__MBAR[0x9188 + ((x)*0x800)])) +#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&__MBAR[0x918C + ((x)*0x800)])) +#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&__MBAR[0x9190 + ((x)*0x800)])) +#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&__MBAR[0x9194 + ((x)*0x800)])) +#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&__MBAR[0x9198 + ((x)*0x800)])) +#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&__MBAR[0x919C + ((x)*0x800)])) +#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&__MBAR[0x91A0 + ((x)*0x800)])) +#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&__MBAR[0x91A4 + ((x)*0x800)])) +#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&__MBAR[0x91A8 + ((x)*0x800)])) +#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&__MBAR[0x91AC + ((x)*0x800)])) +#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&__MBAR[0x91B0 + ((x)*0x800)])) +#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&__MBAR[0x91B4 + ((x)*0x800)])) +#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&__MBAR[0x91B8 + ((x)*0x800)])) +#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&__MBAR[0x91BC + ((x)*0x800)])) +#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&__MBAR[0x91C0 + ((x)*0x800)])) +#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&__MBAR[0x91C4 + ((x)*0x800)])) +#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&__MBAR[0x91C8 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x9200 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&__MBAR[0x9204 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x9208 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x920C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&__MBAR[0x9210 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9214 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9218 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&__MBAR[0x921C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&__MBAR[0x9220 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&__MBAR[0x9224 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&__MBAR[0x9228 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&__MBAR[0x922C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&__MBAR[0x9230 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&__MBAR[0x9234 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&__MBAR[0x9238 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&__MBAR[0x923C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&__MBAR[0x9240 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&__MBAR[0x9244 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x9248 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&__MBAR[0x924C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&__MBAR[0x9250 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&__MBAR[0x9254 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&__MBAR[0x9258 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&__MBAR[0x925C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&__MBAR[0x9260 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&__MBAR[0x9264 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&__MBAR[0x9268 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&__MBAR[0x926C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&__MBAR[0x9270 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&__MBAR[0x9274 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x9280 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&__MBAR[0x9284 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x9288 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x928C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&__MBAR[0x9290 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9294 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9298 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&__MBAR[0x929C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&__MBAR[0x92A0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&__MBAR[0x92A4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&__MBAR[0x92A8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&__MBAR[0x92AC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&__MBAR[0x92B0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&__MBAR[0x92B4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&__MBAR[0x92B8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&__MBAR[0x92BC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&__MBAR[0x92C0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&__MBAR[0x92C4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x92C8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&__MBAR[0x92CC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&__MBAR[0x92D0 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&__MBAR[0x92D4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&__MBAR[0x92D8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&__MBAR[0x92DC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&__MBAR[0x92E0 + ((x)*0x800)])) /* Bit definitions and macros for MCF_FEC_EIR */ diff --git a/BaS_GNU/include/MCF5475_GPIO.h b/BaS_GNU/include/MCF5475_GPIO.h index 7ef3dce..fba9b56 100644 --- a/BaS_GNU/include/MCF5475_GPIO.h +++ b/BaS_GNU/include/MCF5475_GPIO.h @@ -24,70 +24,70 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_GPIO_PODR_FBCTL (*(vuint8 *)(&__MBAR[0xA00])) -#define MCF_GPIO_PDDR_FBCTL (*(vuint8 *)(&__MBAR[0xA10])) -#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8 *)(&__MBAR[0xA20])) -#define MCF_GPIO_PCLRR_FBCTL (*(vuint8 *)(&__MBAR[0xA30])) +#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA00])) +#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA10])) +#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA20])) +#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA30])) -#define MCF_GPIO_PODR_FBCS (*(vuint8 *)(&__MBAR[0xA01])) -#define MCF_GPIO_PDDR_FBCS (*(vuint8 *)(&__MBAR[0xA11])) -#define MCF_GPIO_PPDSDR_FBCS (*(vuint8 *)(&__MBAR[0xA21])) -#define MCF_GPIO_PCLRR_FBCS (*(vuint8 *)(&__MBAR[0xA31])) +#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA01])) +#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA11])) +#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA21])) +#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA31])) -#define MCF_GPIO_PODR_DMA (*(vuint8 *)(&__MBAR[0xA02])) -#define MCF_GPIO_PDDR_DMA (*(vuint8 *)(&__MBAR[0xA12])) -#define MCF_GPIO_PPDSDR_DMA (*(vuint8 *)(&__MBAR[0xA22])) -#define MCF_GPIO_PCLRR_DMA (*(vuint8 *)(&__MBAR[0xA32])) +#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&__MBAR[0xA02])) +#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&__MBAR[0xA12])) +#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&__MBAR[0xA22])) +#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&__MBAR[0xA32])) -#define MCF_GPIO_PODR_FEC0H (*(vuint8 *)(&__MBAR[0xA04])) -#define MCF_GPIO_PDDR_FEC0H (*(vuint8 *)(&__MBAR[0xA14])) -#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8 *)(&__MBAR[0xA24])) -#define MCF_GPIO_PCLRR_FEC0H (*(vuint8 *)(&__MBAR[0xA34])) +#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA04])) +#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA14])) +#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA24])) +#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA34])) -#define MCF_GPIO_PODR_FEC0L (*(vuint8 *)(&__MBAR[0xA05])) -#define MCF_GPIO_PDDR_FEC0L (*(vuint8 *)(&__MBAR[0xA15])) -#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8 *)(&__MBAR[0xA25])) -#define MCF_GPIO_PCLRR_FEC0L (*(vuint8 *)(&__MBAR[0xA35])) +#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA05])) +#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA15])) +#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA25])) +#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA35])) -#define MCF_GPIO_PODR_FEC1H (*(vuint8 *)(&__MBAR[0xA06])) -#define MCF_GPIO_PDDR_FEC1H (*(vuint8 *)(&__MBAR[0xA16])) -#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8 *)(&__MBAR[0xA26])) -#define MCF_GPIO_PCLRR_FEC1H (*(vuint8 *)(&__MBAR[0xA36])) +#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA06])) +#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA16])) +#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA26])) +#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA36])) -#define MCF_GPIO_PODR_FEC1L (*(vuint8 *)(&__MBAR[0xA07])) -#define MCF_GPIO_PDDR_FEC1L (*(vuint8 *)(&__MBAR[0xA17])) -#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8 *)(&__MBAR[0xA27])) -#define MCF_GPIO_PCLRR_FEC1L (*(vuint8 *)(&__MBAR[0xA37])) +#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA07])) +#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA17])) +#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA27])) +#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA37])) -#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(&__MBAR[0xA08])) -#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(&__MBAR[0xA18])) -#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(&__MBAR[0xA28])) -#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(&__MBAR[0xA38])) +#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA08])) +#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA18])) +#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA28])) +#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA38])) -#define MCF_GPIO_PODR_PCIBG (*(vuint8 *)(&__MBAR[0xA09])) -#define MCF_GPIO_PDDR_PCIBG (*(vuint8 *)(&__MBAR[0xA19])) -#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8 *)(&__MBAR[0xA29])) -#define MCF_GPIO_PCLRR_PCIBG (*(vuint8 *)(&__MBAR[0xA39])) +#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA09])) +#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA19])) +#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA29])) +#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA39])) -#define MCF_GPIO_PODR_PCIBR (*(vuint8 *)(&__MBAR[0xA0A])) -#define MCF_GPIO_PDDR_PCIBR (*(vuint8 *)(&__MBAR[0xA1A])) -#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8 *)(&__MBAR[0xA2A])) -#define MCF_GPIO_PCLRR_PCIBR (*(vuint8 *)(&__MBAR[0xA3A])) +#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA0A])) +#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA1A])) +#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA2A])) +#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA3A])) -#define MCF_GPIO2_PODR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA0C])) -#define MCF_GPIO2_PDDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA1C])) -#define MCF_GPIO2_PPDSDR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA2C])) -#define MCF_GPIO2_PCLRR_PSC3PSC (*(vuint8 *)(&__MBAR[0xA3C])) +#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA0C])) +#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA1C])) +#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA2C])) +#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA3C])) -#define MCF_GPIO0_PODR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA0D])) -#define MCF_GPIO0_PDDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA1D])) -#define MCF_GPIO0_PPDSDR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA2D])) -#define MCF_GPIO0_PCLRR_PSC1PSC (*(vuint8 *)(&__MBAR[0xA3D])) +#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA0D])) +#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA1D])) +#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA2D])) +#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA3D])) -#define MCF_GPIO_PODR_DSPI (*(vuint8 *)(&__MBAR[0xA0E])) -#define MCF_GPIO_PDDR_DSPI (*(vuint8 *)(&__MBAR[0xA1E])) -#define MCF_GPIO_PPDSDR_DSPI (*(vuint8 *)(&__MBAR[0xA2E])) -#define MCF_GPIO_PCLRR_DSPI (*(vuint8 *)(&__MBAR[0xA3E])) +#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA0E])) +#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA1E])) +#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA2E])) +#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA3E])) diff --git a/BaS_GNU/include/MCF5475_GPT.h b/BaS_GNU/include/MCF5475_GPT.h index ab99d05..caf2d5b 100644 --- a/BaS_GNU/include/MCF5475_GPT.h +++ b/BaS_GNU/include/MCF5475_GPT.h @@ -24,30 +24,30 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_GPT0_GMS (*(vuint32*)(&__MBAR[0x800])) -#define MCF_GPT0_GCIR (*(vuint32*)(&__MBAR[0x804])) -#define MCF_GPT0_GPWM (*(vuint32*)(&__MBAR[0x808])) -#define MCF_GPT0_GSR (*(vuint32*)(&__MBAR[0x80C])) +#define MCF_GPT0_GMS (*(volatile uint32_t*)(&__MBAR[0x800])) +#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&__MBAR[0x804])) +#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&__MBAR[0x808])) +#define MCF_GPT0_GSR (*(volatile uint32_t*)(&__MBAR[0x80C])) -#define MCF_GPT1_GMS (*(vuint32*)(&__MBAR[0x810])) -#define MCF_GPT1_GCIR (*(vuint32*)(&__MBAR[0x814])) -#define MCF_GPT1_GPWM (*(vuint32*)(&__MBAR[0x818])) -#define MCF_GPT1_GSR (*(vuint32*)(&__MBAR[0x81C])) +#define MCF_GPT1_GMS (*(volatile uint32_t*)(&__MBAR[0x810])) +#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&__MBAR[0x814])) +#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&__MBAR[0x818])) +#define MCF_GPT1_GSR (*(volatile uint32_t*)(&__MBAR[0x81C])) -#define MCF_GPT2_GMS (*(vuint32*)(&__MBAR[0x820])) -#define MCF_GPT2_GCIR (*(vuint32*)(&__MBAR[0x824])) -#define MCF_GPT2_GPWM (*(vuint32*)(&__MBAR[0x828])) -#define MCF_GPT2_GSR (*(vuint32*)(&__MBAR[0x82C])) +#define MCF_GPT2_GMS (*(volatile uint32_t*)(&__MBAR[0x820])) +#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&__MBAR[0x824])) +#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&__MBAR[0x828])) +#define MCF_GPT2_GSR (*(volatile uint32_t*)(&__MBAR[0x82C])) -#define MCF_GPT3_GMS (*(vuint32*)(&__MBAR[0x830])) -#define MCF_GPT3_GCIR (*(vuint32*)(&__MBAR[0x834])) -#define MCF_GPT3_GPWM (*(vuint32*)(&__MBAR[0x838])) -#define MCF_GPT3_GSR (*(vuint32*)(&__MBAR[0x83C])) +#define MCF_GPT3_GMS (*(volatile uint32_t*)(&__MBAR[0x830])) +#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&__MBAR[0x834])) +#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&__MBAR[0x838])) +#define MCF_GPT3_GSR (*(volatile uint32_t*)(&__MBAR[0x83C])) -#define MCF_GPT_GMS(x) (*(vuint32*)(&__MBAR[0x800 + ((x)*0x10)])) -#define MCF_GPT_GCIR(x) (*(vuint32*)(&__MBAR[0x804 + ((x)*0x10)])) -#define MCF_GPT_GPWM(x) (*(vuint32*)(&__MBAR[0x808 + ((x)*0x10)])) -#define MCF_GPT_GSR(x) (*(vuint32*)(&__MBAR[0x80C + ((x)*0x10)])) +#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&__MBAR[0x800 + ((x)*0x10)])) +#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&__MBAR[0x804 + ((x)*0x10)])) +#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&__MBAR[0x808 + ((x)*0x10)])) +#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&__MBAR[0x80C + ((x)*0x10)])) /* Bit definitions and macros for MCF_GPT_GMS */ diff --git a/BaS_GNU/include/MCF5475_I2C.h b/BaS_GNU/include/MCF5475_I2C.h index dbbd626..70a77e9 100644 --- a/BaS_GNU/include/MCF5475_I2C.h +++ b/BaS_GNU/include/MCF5475_I2C.h @@ -24,12 +24,12 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_I2C_I2ADR (*(vuint8 *)(&__MBAR[0x8F00])) -#define MCF_I2C_I2FDR (*(vuint8 *)(&__MBAR[0x8F04])) -#define MCF_I2C_I2CR (*(vuint8 *)(&__MBAR[0x8F08])) -#define MCF_I2C_I2SR (*(vuint8 *)(&__MBAR[0x8F0C])) -#define MCF_I2C_I2DR (*(vuint8 *)(&__MBAR[0x8F10])) -#define MCF_I2C_I2ICR (*(vuint8 *)(&__MBAR[0x8F20])) +#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&__MBAR[0x8F00])) +#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&__MBAR[0x8F04])) +#define MCF_I2C_I2CR (*(volatile uint8_t *)(&__MBAR[0x8F08])) +#define MCF_I2C_I2SR (*(volatile uint8_t *)(&__MBAR[0x8F0C])) +#define MCF_I2C_I2DR (*(volatile uint8_t *)(&__MBAR[0x8F10])) +#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&__MBAR[0x8F20])) diff --git a/BaS_GNU/include/MCF5475_INTC.h b/BaS_GNU/include/MCF5475_INTC.h index 4dfc6d2..c9bd59e 100644 --- a/BaS_GNU/include/MCF5475_INTC.h +++ b/BaS_GNU/include/MCF5475_INTC.h @@ -24,87 +24,87 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_INTC_IPRH (*(vuint32*)(&__MBAR[0x700])) -#define MCF_INTC_IPRL (*(vuint32*)(&__MBAR[0x704])) -#define MCF_INTC_IMRH (*(vuint32*)(&__MBAR[0x708])) -#define MCF_INTC_IMRL (*(vuint32*)(&__MBAR[0x70C])) -#define MCF_INTC_INTFRCH (*(vuint32*)(&__MBAR[0x710])) -#define MCF_INTC_INTFRCL (*(vuint32*)(&__MBAR[0x714])) -#define MCF_INTC_IRLR (*(vuint8 *)(&__MBAR[0x718])) -#define MCF_INTC_IACKLPR (*(vuint8 *)(&__MBAR[0x719])) -#define MCF_INTC_ICR01 (*(vuint8 *)(&__MBAR[0x741])) -#define MCF_INTC_ICR02 (*(vuint8 *)(&__MBAR[0x742])) -#define MCF_INTC_ICR03 (*(vuint8 *)(&__MBAR[0x743])) -#define MCF_INTC_ICR04 (*(vuint8 *)(&__MBAR[0x744])) -#define MCF_INTC_ICR05 (*(vuint8 *)(&__MBAR[0x745])) -#define MCF_INTC_ICR06 (*(vuint8 *)(&__MBAR[0x746])) -#define MCF_INTC_ICR07 (*(vuint8 *)(&__MBAR[0x747])) -#define MCF_INTC_ICR08 (*(vuint8 *)(&__MBAR[0x748])) -#define MCF_INTC_ICR09 (*(vuint8 *)(&__MBAR[0x749])) -#define MCF_INTC_ICR10 (*(vuint8 *)(&__MBAR[0x74A])) -#define MCF_INTC_ICR11 (*(vuint8 *)(&__MBAR[0x74B])) -#define MCF_INTC_ICR12 (*(vuint8 *)(&__MBAR[0x74C])) -#define MCF_INTC_ICR13 (*(vuint8 *)(&__MBAR[0x74D])) -#define MCF_INTC_ICR14 (*(vuint8 *)(&__MBAR[0x74E])) -#define MCF_INTC_ICR15 (*(vuint8 *)(&__MBAR[0x74F])) -#define MCF_INTC_ICR16 (*(vuint8 *)(&__MBAR[0x750])) -#define MCF_INTC_ICR17 (*(vuint8 *)(&__MBAR[0x751])) -#define MCF_INTC_ICR18 (*(vuint8 *)(&__MBAR[0x752])) -#define MCF_INTC_ICR19 (*(vuint8 *)(&__MBAR[0x753])) -#define MCF_INTC_ICR20 (*(vuint8 *)(&__MBAR[0x754])) -#define MCF_INTC_ICR21 (*(vuint8 *)(&__MBAR[0x755])) -#define MCF_INTC_ICR22 (*(vuint8 *)(&__MBAR[0x756])) -#define MCF_INTC_ICR23 (*(vuint8 *)(&__MBAR[0x757])) -#define MCF_INTC_ICR24 (*(vuint8 *)(&__MBAR[0x758])) -#define MCF_INTC_ICR25 (*(vuint8 *)(&__MBAR[0x759])) -#define MCF_INTC_ICR26 (*(vuint8 *)(&__MBAR[0x75A])) -#define MCF_INTC_ICR27 (*(vuint8 *)(&__MBAR[0x75B])) -#define MCF_INTC_ICR28 (*(vuint8 *)(&__MBAR[0x75C])) -#define MCF_INTC_ICR29 (*(vuint8 *)(&__MBAR[0x75D])) -#define MCF_INTC_ICR30 (*(vuint8 *)(&__MBAR[0x75E])) -#define MCF_INTC_ICR31 (*(vuint8 *)(&__MBAR[0x75F])) -#define MCF_INTC_ICR32 (*(vuint8 *)(&__MBAR[0x760])) -#define MCF_INTC_ICR33 (*(vuint8 *)(&__MBAR[0x761])) -#define MCF_INTC_ICR34 (*(vuint8 *)(&__MBAR[0x762])) -#define MCF_INTC_ICR35 (*(vuint8 *)(&__MBAR[0x763])) -#define MCF_INTC_ICR36 (*(vuint8 *)(&__MBAR[0x764])) -#define MCF_INTC_ICR37 (*(vuint8 *)(&__MBAR[0x765])) -#define MCF_INTC_ICR38 (*(vuint8 *)(&__MBAR[0x766])) -#define MCF_INTC_ICR39 (*(vuint8 *)(&__MBAR[0x767])) -#define MCF_INTC_ICR40 (*(vuint8 *)(&__MBAR[0x768])) -#define MCF_INTC_ICR41 (*(vuint8 *)(&__MBAR[0x769])) -#define MCF_INTC_ICR42 (*(vuint8 *)(&__MBAR[0x76A])) -#define MCF_INTC_ICR43 (*(vuint8 *)(&__MBAR[0x76B])) -#define MCF_INTC_ICR44 (*(vuint8 *)(&__MBAR[0x76C])) -#define MCF_INTC_ICR45 (*(vuint8 *)(&__MBAR[0x76D])) -#define MCF_INTC_ICR46 (*(vuint8 *)(&__MBAR[0x76E])) -#define MCF_INTC_ICR47 (*(vuint8 *)(&__MBAR[0x76F])) -#define MCF_INTC_ICR48 (*(vuint8 *)(&__MBAR[0x770])) -#define MCF_INTC_ICR49 (*(vuint8 *)(&__MBAR[0x771])) -#define MCF_INTC_ICR50 (*(vuint8 *)(&__MBAR[0x772])) -#define MCF_INTC_ICR51 (*(vuint8 *)(&__MBAR[0x773])) -#define MCF_INTC_ICR52 (*(vuint8 *)(&__MBAR[0x774])) -#define MCF_INTC_ICR53 (*(vuint8 *)(&__MBAR[0x775])) -#define MCF_INTC_ICR54 (*(vuint8 *)(&__MBAR[0x776])) -#define MCF_INTC_ICR55 (*(vuint8 *)(&__MBAR[0x777])) -#define MCF_INTC_ICR56 (*(vuint8 *)(&__MBAR[0x778])) -#define MCF_INTC_ICR57 (*(vuint8 *)(&__MBAR[0x779])) -#define MCF_INTC_ICR58 (*(vuint8 *)(&__MBAR[0x77A])) -#define MCF_INTC_ICR59 (*(vuint8 *)(&__MBAR[0x77B])) -#define MCF_INTC_ICR60 (*(vuint8 *)(&__MBAR[0x77C])) -#define MCF_INTC_ICR61 (*(vuint8 *)(&__MBAR[0x77D])) -#define MCF_INTC_ICR62 (*(vuint8 *)(&__MBAR[0x77E])) -#define MCF_INTC_ICR63 (*(vuint8 *)(&__MBAR[0x77F])) -#define MCF_INTC_SWIACK (*(vuint8 *)(&__MBAR[0x7E0])) -#define MCF_INTC_L1IACK (*(vuint8 *)(&__MBAR[0x7E4])) -#define MCF_INTC_L2IACK (*(vuint8 *)(&__MBAR[0x7E8])) -#define MCF_INTC_L3IACK (*(vuint8 *)(&__MBAR[0x7EC])) -#define MCF_INTC_L4IACK (*(vuint8 *)(&__MBAR[0x7F0])) -#define MCF_INTC_L5IACK (*(vuint8 *)(&__MBAR[0x7F4])) -#define MCF_INTC_L6IACK (*(vuint8 *)(&__MBAR[0x7F8])) -#define MCF_INTC_L7IACK (*(vuint8 *)(&__MBAR[0x7FC])) -#define MCF_INTC_ICR(x) (*(vuint8 *)(&__MBAR[0x741 + ((x-1)*0x1)])) -#define MCF_INTC_LIACK(x) (*(vuint8 *)(&__MBAR[0x7E4 + ((x-1)*0x4)])) +#define MCF_INTC_IPRH (*(volatile uint32_t*)(&__MBAR[0x700])) +#define MCF_INTC_IPRL (*(volatile uint32_t*)(&__MBAR[0x704])) +#define MCF_INTC_IMRH (*(volatile uint32_t*)(&__MBAR[0x708])) +#define MCF_INTC_IMRL (*(volatile uint32_t*)(&__MBAR[0x70C])) +#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&__MBAR[0x710])) +#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&__MBAR[0x714])) +#define MCF_INTC_IRLR (*(volatile uint8_t *)(&__MBAR[0x718])) +#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&__MBAR[0x719])) +#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&__MBAR[0x741])) +#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&__MBAR[0x742])) +#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&__MBAR[0x743])) +#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&__MBAR[0x744])) +#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&__MBAR[0x745])) +#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&__MBAR[0x746])) +#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&__MBAR[0x747])) +#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&__MBAR[0x748])) +#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&__MBAR[0x749])) +#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&__MBAR[0x74A])) +#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&__MBAR[0x74B])) +#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&__MBAR[0x74C])) +#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&__MBAR[0x74D])) +#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&__MBAR[0x74E])) +#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&__MBAR[0x74F])) +#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&__MBAR[0x750])) +#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&__MBAR[0x751])) +#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&__MBAR[0x752])) +#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&__MBAR[0x753])) +#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&__MBAR[0x754])) +#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&__MBAR[0x755])) +#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&__MBAR[0x756])) +#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&__MBAR[0x757])) +#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&__MBAR[0x758])) +#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&__MBAR[0x759])) +#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&__MBAR[0x75A])) +#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&__MBAR[0x75B])) +#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&__MBAR[0x75C])) +#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&__MBAR[0x75D])) +#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&__MBAR[0x75E])) +#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&__MBAR[0x75F])) +#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&__MBAR[0x760])) +#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&__MBAR[0x761])) +#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&__MBAR[0x762])) +#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&__MBAR[0x763])) +#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&__MBAR[0x764])) +#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&__MBAR[0x765])) +#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&__MBAR[0x766])) +#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&__MBAR[0x767])) +#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&__MBAR[0x768])) +#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&__MBAR[0x769])) +#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&__MBAR[0x76A])) +#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&__MBAR[0x76B])) +#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&__MBAR[0x76C])) +#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&__MBAR[0x76D])) +#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&__MBAR[0x76E])) +#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&__MBAR[0x76F])) +#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&__MBAR[0x770])) +#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&__MBAR[0x771])) +#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&__MBAR[0x772])) +#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&__MBAR[0x773])) +#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&__MBAR[0x774])) +#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&__MBAR[0x775])) +#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&__MBAR[0x776])) +#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&__MBAR[0x777])) +#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&__MBAR[0x778])) +#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&__MBAR[0x779])) +#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&__MBAR[0x77A])) +#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&__MBAR[0x77B])) +#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&__MBAR[0x77C])) +#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&__MBAR[0x77D])) +#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&__MBAR[0x77E])) +#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&__MBAR[0x77F])) +#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&__MBAR[0x7E0])) +#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&__MBAR[0x7E4])) +#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&__MBAR[0x7E8])) +#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&__MBAR[0x7EC])) +#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&__MBAR[0x7F0])) +#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&__MBAR[0x7F4])) +#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&__MBAR[0x7F8])) +#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&__MBAR[0x7FC])) +#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&__MBAR[0x741 + ((x-1)*0x1)])) +#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&__MBAR[0x7E4 + ((x-1)*0x4)])) diff --git a/BaS_GNU/include/MCF5475_MMU.h b/BaS_GNU/include/MCF5475_MMU.h index 84d57b9..a93397a 100644 --- a/BaS_GNU/include/MCF5475_MMU.h +++ b/BaS_GNU/include/MCF5475_MMU.h @@ -24,12 +24,12 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_MMU_MMUCR (*(vuint32*)(&__MMUBAR[0])) -#define MCF_MMU_MMUOR (*(vuint32*)(&__MMUBAR[0x4])) -#define MCF_MMU_MMUSR (*(vuint32*)(&__MMUBAR[0x8])) -#define MCF_MMU_MMUAR (*(vuint32*)(&__MMUBAR[0x10])) -#define MCF_MMU_MMUTR (*(vuint32*)(&__MMUBAR[0x14])) -#define MCF_MMU_MMUDR (*(vuint32*)(&__MMUBAR[0x18])) +#define MCF_MMU_MMUCR (*(volatile uint32_t*)(&__MMUBAR[0])) +#define MCF_MMU_MMUOR (*(volatile uint32_t*)(&__MMUBAR[0x4])) +#define MCF_MMU_MMUSR (*(volatile uint32_t*)(&__MMUBAR[0x8])) +#define MCF_MMU_MMUAR (*(volatile uint32_t*)(&__MMUBAR[0x10])) +#define MCF_MMU_MMUTR (*(volatile uint32_t*)(&__MMUBAR[0x14])) +#define MCF_MMU_MMUDR (*(volatile uint32_t*)(&__MMUBAR[0x18])) /* Bit definitions and macros for MCF_MMU_MMUCR */ diff --git a/BaS_GNU/include/MCF5475_PAD.h b/BaS_GNU/include/MCF5475_PAD.h index 9c0fcf7..e2db4be 100644 --- a/BaS_GNU/include/MCF5475_PAD.h +++ b/BaS_GNU/include/MCF5475_PAD.h @@ -24,18 +24,18 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_PAD_PAR_FBCTL (*(vuint16*)(&__MBAR[0xA40])) -#define MCF_PAD_PAR_FBCS (*(vuint8 *)(&__MBAR[0xA42])) -#define MCF_PAD_PAR_DMA (*(vuint8 *)(&__MBAR[0xA43])) -#define MCF_PAD_PAR_FECI2CIRQ (*(vuint16*)(&__MBAR[0xA44])) -#define MCF_PAD_PAR_PCIBG (*(vuint16*)(&__MBAR[0xA48])) -#define MCF_PAD_PAR_PCIBR (*(vuint16*)(&__MBAR[0xA4A])) -#define MCF_PAD_PAR_PSC3 (*(vuint8 *)(&__MBAR[0xA4C])) -#define MCF_PAD_PAR_PSC2 (*(vuint8 *)(&__MBAR[0xA4D])) -#define MCF_PAD_PAR_PSC1 (*(vuint8 *)(&__MBAR[0xA4E])) -#define MCF_PAD_PAR_PSC0 (*(vuint8 *)(&__MBAR[0xA4F])) -#define MCF_PAD_PAR_DSPI (*(vuint16*)(&__MBAR[0xA50])) -#define MCF_PAD_PAR_TIMER (*(vuint8 *)(&__MBAR[0xA52])) +#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&__MBAR[0xA40])) +#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA42])) +#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&__MBAR[0xA43])) +#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&__MBAR[0xA44])) +#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&__MBAR[0xA48])) +#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&__MBAR[0xA4A])) +#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&__MBAR[0xA4C])) +#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&__MBAR[0xA4D])) +#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&__MBAR[0xA4E])) +#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&__MBAR[0xA4F])) +#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&__MBAR[0xA50])) +#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&__MBAR[0xA52])) /* Bit definitions and macros for MCF_PAD_PAR_FBCTL */ diff --git a/BaS_GNU/include/MCF5475_PCI.h b/BaS_GNU/include/MCF5475_PCI.h index 47e9e98..b89c24d 100644 --- a/BaS_GNU/include/MCF5475_PCI.h +++ b/BaS_GNU/include/MCF5475_PCI.h @@ -24,53 +24,53 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_PCI_PCIIDR (*(vuint32*)(&__MBAR[0xB00])) -#define MCF_PCI_PCISCR (*(vuint32*)(&__MBAR[0xB04])) -#define MCF_PCI_PCICCRIR (*(vuint32*)(&__MBAR[0xB08])) -#define MCF_PCI_PCICR1 (*(vuint32*)(&__MBAR[0xB0C])) -#define MCF_PCI_PCIBAR0 (*(vuint32*)(&__MBAR[0xB10])) -#define MCF_PCI_PCIBAR1 (*(vuint32*)(&__MBAR[0xB14])) -#define MCF_PCI_PCICCPR (*(vuint32*)(&__MBAR[0xB28])) -#define MCF_PCI_PCISID (*(vuint32*)(&__MBAR[0xB2C])) -#define MCF_PCI_PCICR2 (*(vuint32*)(&__MBAR[0xB3C])) -#define MCF_PCI_PCIGSCR (*(vuint32*)(&__MBAR[0xB60])) -#define MCF_PCI_PCITBATR0 (*(vuint32*)(&__MBAR[0xB64])) -#define MCF_PCI_PCITBATR1 (*(vuint32*)(&__MBAR[0xB68])) -#define MCF_PCI_PCITCR (*(vuint32*)(&__MBAR[0xB6C])) -#define MCF_PCI_PCIIW0BTAR (*(vuint32*)(&__MBAR[0xB70])) -#define MCF_PCI_PCIIW1BTAR (*(vuint32*)(&__MBAR[0xB74])) -#define MCF_PCI_PCIIW2BTAR (*(vuint32*)(&__MBAR[0xB78])) -#define MCF_PCI_PCIIWCR (*(vuint32*)(&__MBAR[0xB80])) -#define MCF_PCI_PCIICR (*(vuint32*)(&__MBAR[0xB84])) -#define MCF_PCI_PCIISR (*(vuint32*)(&__MBAR[0xB88])) -#define MCF_PCI_PCICAR (*(vuint32*)(&__MBAR[0xBF8])) -#define MCF_PCI_PCITPSR (*(vuint32*)(&__MBAR[0x8400])) -#define MCF_PCI_PCITSAR (*(vuint32*)(&__MBAR[0x8404])) -#define MCF_PCI_PCITTCR (*(vuint32*)(&__MBAR[0x8408])) -#define MCF_PCI_PCITER (*(vuint32*)(&__MBAR[0x840C])) -#define MCF_PCI_PCITNAR (*(vuint32*)(&__MBAR[0x8410])) -#define MCF_PCI_PCITLWR (*(vuint32*)(&__MBAR[0x8414])) -#define MCF_PCI_PCITDCR (*(vuint32*)(&__MBAR[0x8418])) -#define MCF_PCI_PCITSR (*(vuint32*)(&__MBAR[0x841C])) -#define MCF_PCI_PCITFDR (*(vuint32*)(&__MBAR[0x8440])) -#define MCF_PCI_PCITFSR (*(vuint32*)(&__MBAR[0x8444])) -#define MCF_PCI_PCITFCR (*(vuint32*)(&__MBAR[0x8448])) -#define MCF_PCI_PCITFAR (*(vuint32*)(&__MBAR[0x844C])) -#define MCF_PCI_PCITFRPR (*(vuint32*)(&__MBAR[0x8450])) -#define MCF_PCI_PCITFWPR (*(vuint32*)(&__MBAR[0x8454])) -#define MCF_PCI_PCIRPSR (*(vuint32*)(&__MBAR[0x8480])) -#define MCF_PCI_PCIRSAR (*(vuint32*)(&__MBAR[0x8484])) -#define MCF_PCI_PCIRTCR (*(vuint32*)(&__MBAR[0x8488])) -#define MCF_PCI_PCIRER (*(vuint32*)(&__MBAR[0x848C])) -#define MCF_PCI_PCIRNAR (*(vuint32*)(&__MBAR[0x8490])) -#define MCF_PCI_PCIRDCR (*(vuint32*)(&__MBAR[0x8498])) -#define MCF_PCI_PCIRSR (*(vuint32*)(&__MBAR[0x849C])) -#define MCF_PCI_PCIRFDR (*(vuint32*)(&__MBAR[0x84C0])) -#define MCF_PCI_PCIRFSR (*(vuint32*)(&__MBAR[0x84C4])) -#define MCF_PCI_PCIRFCR (*(vuint32*)(&__MBAR[0x84C8])) -#define MCF_PCI_PCIRFAR (*(vuint32*)(&__MBAR[0x84CC])) -#define MCF_PCI_PCIRFRPR (*(vuint32*)(&__MBAR[0x84D0])) -#define MCF_PCI_PCIRFWPR (*(vuint32*)(&__MBAR[0x84D4])) +#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&__MBAR[0xB00])) +#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&__MBAR[0xB04])) +#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&__MBAR[0xB08])) +#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&__MBAR[0xB0C])) +#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&__MBAR[0xB10])) +#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&__MBAR[0xB14])) +#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&__MBAR[0xB28])) +#define MCF_PCI_PCISID (*(volatile uint32_t*)(&__MBAR[0xB2C])) +#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&__MBAR[0xB3C])) +#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&__MBAR[0xB60])) +#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&__MBAR[0xB64])) +#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&__MBAR[0xB68])) +#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&__MBAR[0xB6C])) +#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&__MBAR[0xB70])) +#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&__MBAR[0xB74])) +#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&__MBAR[0xB78])) +#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&__MBAR[0xB80])) +#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&__MBAR[0xB84])) +#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&__MBAR[0xB88])) +#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&__MBAR[0xBF8])) +#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&__MBAR[0x8400])) +#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&__MBAR[0x8404])) +#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&__MBAR[0x8408])) +#define MCF_PCI_PCITER (*(volatile uint32_t*)(&__MBAR[0x840C])) +#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&__MBAR[0x8410])) +#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&__MBAR[0x8414])) +#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&__MBAR[0x8418])) +#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&__MBAR[0x841C])) +#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&__MBAR[0x8440])) +#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&__MBAR[0x8444])) +#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&__MBAR[0x8448])) +#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&__MBAR[0x844C])) +#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&__MBAR[0x8450])) +#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&__MBAR[0x8454])) +#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&__MBAR[0x8480])) +#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&__MBAR[0x8484])) +#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&__MBAR[0x8488])) +#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&__MBAR[0x848C])) +#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&__MBAR[0x8490])) +#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&__MBAR[0x8498])) +#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&__MBAR[0x849C])) +#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&__MBAR[0x84C0])) +#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&__MBAR[0x84C4])) +#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&__MBAR[0x84C8])) +#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&__MBAR[0x84CC])) +#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&__MBAR[0x84D0])) +#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&__MBAR[0x84D4])) /* Bit definitions and macros for MCF_PCI_PCIIDR */ diff --git a/BaS_GNU/include/MCF5475_PCIARB.h b/BaS_GNU/include/MCF5475_PCIARB.h index 3e793a1..5fa1b18 100644 --- a/BaS_GNU/include/MCF5475_PCIARB.h +++ b/BaS_GNU/include/MCF5475_PCIARB.h @@ -24,8 +24,8 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_PCIARB_PACR (*(vuint32*)(&__MBAR[0xC00])) -#define MCF_PCIARB_PASR (*(vuint32*)(&__MBAR[0xC04])) +#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&__MBAR[0xC00])) +#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&__MBAR[0xC04])) /* Bit definitions and macros for MCF_PCIARB_PACR */ diff --git a/BaS_GNU/include/MCF5475_PSC.h b/BaS_GNU/include/MCF5475_PSC.h index 2165c57..8f51214 100644 --- a/BaS_GNU/include/MCF5475_PSC.h +++ b/BaS_GNU/include/MCF5475_PSC.h @@ -24,229 +24,229 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_PSC0_PSCMR2 (*(vuint8 *)(&__MBAR[0x8600])) -#define MCF_PSC0_PSCMR1 (*(vuint8 *)(&__MBAR[0x8600])) -#define MCF_PSC0_PSCCSR (*(vuint8 *)(&__MBAR[0x8604])) -#define MCF_PSC0_PSCSR (*(vuint16*)(&__MBAR[0x8604])) -#define MCF_PSC0_PSCCR (*(vuint8 *)(&__MBAR[0x8608])) -#define MCF_PSC0_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCIPCR (*(vuint8 *)(&__MBAR[0x8610])) -#define MCF_PSC0_PSCACR (*(vuint8 *)(&__MBAR[0x8610])) -#define MCF_PSC0_PSCIMR (*(vuint16*)(&__MBAR[0x8614])) -#define MCF_PSC0_PSCISR (*(vuint16*)(&__MBAR[0x8614])) -#define MCF_PSC0_PSCCTUR (*(vuint8 *)(&__MBAR[0x8618])) -#define MCF_PSC0_PSCCTLR (*(vuint8 *)(&__MBAR[0x861C])) -#define MCF_PSC0_PSCIP (*(vuint8 *)(&__MBAR[0x8634])) -#define MCF_PSC0_PSCOPSET (*(vuint8 *)(&__MBAR[0x8638])) -#define MCF_PSC0_PSCOPRESET (*(vuint8 *)(&__MBAR[0x863C])) -#define MCF_PSC0_PSCSICR (*(vuint8 *)(&__MBAR[0x8640])) -#define MCF_PSC0_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8644])) -#define MCF_PSC0_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8648])) -#define MCF_PSC0_PSCIRSDR (*(vuint8 *)(&__MBAR[0x864C])) -#define MCF_PSC0_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8650])) -#define MCF_PSC0_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8654])) -#define MCF_PSC0_PSCRFCNT (*(vuint16*)(&__MBAR[0x8658])) -#define MCF_PSC0_PSCTFCNT (*(vuint16*)(&__MBAR[0x865C])) -#define MCF_PSC0_PSCRFDR (*(vuint32*)(&__MBAR[0x8660])) -#define MCF_PSC0_PSCRFSR (*(vuint16*)(&__MBAR[0x8664])) -#define MCF_PSC0_PSCRFCR (*(vuint32*)(&__MBAR[0x8668])) -#define MCF_PSC0_PSCRFAR (*(vuint16*)(&__MBAR[0x866E])) -#define MCF_PSC0_PSCRFRP (*(vuint16*)(&__MBAR[0x8672])) -#define MCF_PSC0_PSCRFWP (*(vuint16*)(&__MBAR[0x8676])) -#define MCF_PSC0_PSCRLRFP (*(vuint16*)(&__MBAR[0x867A])) -#define MCF_PSC0_PSCRLWFP (*(vuint16*)(&__MBAR[0x867E])) -#define MCF_PSC0_PSCTFDR (*(vuint32*)(&__MBAR[0x8680])) -#define MCF_PSC0_PSCTFSR (*(vuint16*)(&__MBAR[0x8684])) -#define MCF_PSC0_PSCTFCR (*(vuint32*)(&__MBAR[0x8688])) -#define MCF_PSC0_PSCTFAR (*(vuint16*)(&__MBAR[0x868E])) -#define MCF_PSC0_PSCTFRP (*(vuint16*)(&__MBAR[0x8692])) -#define MCF_PSC0_PSCTFWP (*(vuint16*)(&__MBAR[0x8696])) -#define MCF_PSC0_PSCTLRFP (*(vuint16*)(&__MBAR[0x869A])) -#define MCF_PSC0_PSCTLWFP (*(vuint16*)(&__MBAR[0x869E])) +#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8600])) +#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8600])) +#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8604])) +#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8604])) +#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8608])) +#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x860C])) +#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8610])) +#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8610])) +#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8614])) +#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8614])) +#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8618])) +#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x861C])) +#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8634])) +#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8638])) +#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x863C])) +#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8640])) +#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8644])) +#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8648])) +#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x864C])) +#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8650])) +#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8654])) +#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8658])) +#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x865C])) +#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8660])) +#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8664])) +#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8668])) +#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x866E])) +#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8672])) +#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8676])) +#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x867A])) +#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x867E])) +#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8680])) +#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8684])) +#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8688])) +#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x868E])) +#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8692])) +#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8696])) +#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x869A])) +#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x869E])) -#define MCF_PSC1_PSCMR2 (*(vuint8 *)(&__MBAR[0x8700])) -#define MCF_PSC1_PSCMR1 (*(vuint8 *)(&__MBAR[0x8700])) -#define MCF_PSC1_PSCCSR (*(vuint8 *)(&__MBAR[0x8704])) -#define MCF_PSC1_PSCSR (*(vuint16*)(&__MBAR[0x8704])) -#define MCF_PSC1_PSCCR (*(vuint8 *)(&__MBAR[0x8708])) -#define MCF_PSC1_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCIPCR (*(vuint8 *)(&__MBAR[0x8710])) -#define MCF_PSC1_PSCACR (*(vuint8 *)(&__MBAR[0x8710])) -#define MCF_PSC1_PSCIMR (*(vuint16*)(&__MBAR[0x8714])) -#define MCF_PSC1_PSCISR (*(vuint16*)(&__MBAR[0x8714])) -#define MCF_PSC1_PSCCTUR (*(vuint8 *)(&__MBAR[0x8718])) -#define MCF_PSC1_PSCCTLR (*(vuint8 *)(&__MBAR[0x871C])) -#define MCF_PSC1_PSCIP (*(vuint8 *)(&__MBAR[0x8734])) -#define MCF_PSC1_PSCOPSET (*(vuint8 *)(&__MBAR[0x8738])) -#define MCF_PSC1_PSCOPRESET (*(vuint8 *)(&__MBAR[0x873C])) -#define MCF_PSC1_PSCSICR (*(vuint8 *)(&__MBAR[0x8740])) -#define MCF_PSC1_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8744])) -#define MCF_PSC1_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8748])) -#define MCF_PSC1_PSCIRSDR (*(vuint8 *)(&__MBAR[0x874C])) -#define MCF_PSC1_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8750])) -#define MCF_PSC1_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8754])) -#define MCF_PSC1_PSCRFCNT (*(vuint16*)(&__MBAR[0x8758])) -#define MCF_PSC1_PSCTFCNT (*(vuint16*)(&__MBAR[0x875C])) -#define MCF_PSC1_PSCRFDR (*(vuint32*)(&__MBAR[0x8760])) -#define MCF_PSC1_PSCRFSR (*(vuint16*)(&__MBAR[0x8764])) -#define MCF_PSC1_PSCRFCR (*(vuint32*)(&__MBAR[0x8768])) -#define MCF_PSC1_PSCRFAR (*(vuint16*)(&__MBAR[0x876E])) -#define MCF_PSC1_PSCRFRP (*(vuint16*)(&__MBAR[0x8772])) -#define MCF_PSC1_PSCRFWP (*(vuint16*)(&__MBAR[0x8776])) -#define MCF_PSC1_PSCRLRFP (*(vuint16*)(&__MBAR[0x877A])) -#define MCF_PSC1_PSCRLWFP (*(vuint16*)(&__MBAR[0x877E])) -#define MCF_PSC1_PSCTFDR (*(vuint32*)(&__MBAR[0x8780])) -#define MCF_PSC1_PSCTFSR (*(vuint16*)(&__MBAR[0x8784])) -#define MCF_PSC1_PSCTFCR (*(vuint32*)(&__MBAR[0x8788])) -#define MCF_PSC1_PSCTFAR (*(vuint16*)(&__MBAR[0x878E])) -#define MCF_PSC1_PSCTFRP (*(vuint16*)(&__MBAR[0x8792])) -#define MCF_PSC1_PSCTFWP (*(vuint16*)(&__MBAR[0x8796])) -#define MCF_PSC1_PSCTLRFP (*(vuint16*)(&__MBAR[0x879A])) -#define MCF_PSC1_PSCTLWFP (*(vuint16*)(&__MBAR[0x879E])) +#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8700])) +#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8700])) +#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8704])) +#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8704])) +#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8708])) +#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x870C])) +#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8710])) +#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8710])) +#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8714])) +#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8714])) +#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8718])) +#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x871C])) +#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8734])) +#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8738])) +#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x873C])) +#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8740])) +#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8744])) +#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8748])) +#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x874C])) +#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8750])) +#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8754])) +#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8758])) +#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x875C])) +#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8760])) +#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8764])) +#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8768])) +#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x876E])) +#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8772])) +#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8776])) +#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x877A])) +#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x877E])) +#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8780])) +#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8784])) +#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8788])) +#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x878E])) +#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8792])) +#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8796])) +#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x879A])) +#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x879E])) -#define MCF_PSC2_PSCMR2 (*(vuint8 *)(&__MBAR[0x8800])) -#define MCF_PSC2_PSCMR1 (*(vuint8 *)(&__MBAR[0x8800])) -#define MCF_PSC2_PSCCSR (*(vuint8 *)(&__MBAR[0x8804])) -#define MCF_PSC2_PSCSR (*(vuint16*)(&__MBAR[0x8804])) -#define MCF_PSC2_PSCCR (*(vuint8 *)(&__MBAR[0x8808])) -#define MCF_PSC2_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCIPCR (*(vuint8 *)(&__MBAR[0x8810])) -#define MCF_PSC2_PSCACR (*(vuint8 *)(&__MBAR[0x8810])) -#define MCF_PSC2_PSCIMR (*(vuint16*)(&__MBAR[0x8814])) -#define MCF_PSC2_PSCISR (*(vuint16*)(&__MBAR[0x8814])) -#define MCF_PSC2_PSCCTUR (*(vuint8 *)(&__MBAR[0x8818])) -#define MCF_PSC2_PSCCTLR (*(vuint8 *)(&__MBAR[0x881C])) -#define MCF_PSC2_PSCIP (*(vuint8 *)(&__MBAR[0x8834])) -#define MCF_PSC2_PSCOPSET (*(vuint8 *)(&__MBAR[0x8838])) -#define MCF_PSC2_PSCOPRESET (*(vuint8 *)(&__MBAR[0x883C])) -#define MCF_PSC2_PSCSICR (*(vuint8 *)(&__MBAR[0x8840])) -#define MCF_PSC2_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8844])) -#define MCF_PSC2_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8848])) -#define MCF_PSC2_PSCIRSDR (*(vuint8 *)(&__MBAR[0x884C])) -#define MCF_PSC2_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8850])) -#define MCF_PSC2_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8854])) -#define MCF_PSC2_PSCRFCNT (*(vuint16*)(&__MBAR[0x8858])) -#define MCF_PSC2_PSCTFCNT (*(vuint16*)(&__MBAR[0x885C])) -#define MCF_PSC2_PSCRFDR (*(vuint32*)(&__MBAR[0x8860])) -#define MCF_PSC2_PSCRFSR (*(vuint16*)(&__MBAR[0x8864])) -#define MCF_PSC2_PSCRFCR (*(vuint32*)(&__MBAR[0x8868])) -#define MCF_PSC2_PSCRFAR (*(vuint16*)(&__MBAR[0x886E])) -#define MCF_PSC2_PSCRFRP (*(vuint16*)(&__MBAR[0x8872])) -#define MCF_PSC2_PSCRFWP (*(vuint16*)(&__MBAR[0x8876])) -#define MCF_PSC2_PSCRLRFP (*(vuint16*)(&__MBAR[0x887A])) -#define MCF_PSC2_PSCRLWFP (*(vuint16*)(&__MBAR[0x887E])) -#define MCF_PSC2_PSCTFDR (*(vuint32*)(&__MBAR[0x8880])) -#define MCF_PSC2_PSCTFSR (*(vuint16*)(&__MBAR[0x8884])) -#define MCF_PSC2_PSCTFCR (*(vuint32*)(&__MBAR[0x8888])) -#define MCF_PSC2_PSCTFAR (*(vuint16*)(&__MBAR[0x888E])) -#define MCF_PSC2_PSCTFRP (*(vuint16*)(&__MBAR[0x8892])) -#define MCF_PSC2_PSCTFWP (*(vuint16*)(&__MBAR[0x8896])) -#define MCF_PSC2_PSCTLRFP (*(vuint16*)(&__MBAR[0x889A])) -#define MCF_PSC2_PSCTLWFP (*(vuint16*)(&__MBAR[0x889E])) +#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8800])) +#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8800])) +#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8804])) +#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8804])) +#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8808])) +#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x880C])) +#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8810])) +#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8810])) +#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8814])) +#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8814])) +#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8818])) +#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x881C])) +#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8834])) +#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8838])) +#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x883C])) +#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8840])) +#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8844])) +#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8848])) +#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x884C])) +#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8850])) +#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8854])) +#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8858])) +#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x885C])) +#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8860])) +#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8864])) +#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8868])) +#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x886E])) +#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8872])) +#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8876])) +#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x887A])) +#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x887E])) +#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8880])) +#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8884])) +#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8888])) +#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x888E])) +#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8892])) +#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8896])) +#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x889A])) +#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x889E])) -#define MCF_PSC3_PSCMR2 (*(vuint8 *)(&__MBAR[0x8900])) -#define MCF_PSC3_PSCMR1 (*(vuint8 *)(&__MBAR[0x8900])) -#define MCF_PSC3_PSCCSR (*(vuint8 *)(&__MBAR[0x8904])) -#define MCF_PSC3_PSCSR (*(vuint16*)(&__MBAR[0x8904])) -#define MCF_PSC3_PSCCR (*(vuint8 *)(&__MBAR[0x8908])) -#define MCF_PSC3_PSCRB_8BIT (*(vuint32*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCTB_8BIT (*(vuint32*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCRB_16BIT (*(vuint32*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCTB_16BIT (*(vuint32*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCRB_AC97 (*(vuint32*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCTB_AC97 (*(vuint32*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCIPCR (*(vuint8 *)(&__MBAR[0x8910])) -#define MCF_PSC3_PSCACR (*(vuint8 *)(&__MBAR[0x8910])) -#define MCF_PSC3_PSCIMR (*(vuint16*)(&__MBAR[0x8914])) -#define MCF_PSC3_PSCISR (*(vuint16*)(&__MBAR[0x8914])) -#define MCF_PSC3_PSCCTUR (*(vuint8 *)(&__MBAR[0x8918])) -#define MCF_PSC3_PSCCTLR (*(vuint8 *)(&__MBAR[0x891C])) -#define MCF_PSC3_PSCIP (*(vuint8 *)(&__MBAR[0x8934])) -#define MCF_PSC3_PSCOPSET (*(vuint8 *)(&__MBAR[0x8938])) -#define MCF_PSC3_PSCOPRESET (*(vuint8 *)(&__MBAR[0x893C])) -#define MCF_PSC3_PSCSICR (*(vuint8 *)(&__MBAR[0x8940])) -#define MCF_PSC3_PSCIRCR1 (*(vuint8 *)(&__MBAR[0x8944])) -#define MCF_PSC3_PSCIRCR2 (*(vuint8 *)(&__MBAR[0x8948])) -#define MCF_PSC3_PSCIRSDR (*(vuint8 *)(&__MBAR[0x894C])) -#define MCF_PSC3_PSCIRMDR (*(vuint8 *)(&__MBAR[0x8950])) -#define MCF_PSC3_PSCIRFDR (*(vuint8 *)(&__MBAR[0x8954])) -#define MCF_PSC3_PSCRFCNT (*(vuint16*)(&__MBAR[0x8958])) -#define MCF_PSC3_PSCTFCNT (*(vuint16*)(&__MBAR[0x895C])) -#define MCF_PSC3_PSCRFDR (*(vuint32*)(&__MBAR[0x8960])) -#define MCF_PSC3_PSCRFSR (*(vuint16*)(&__MBAR[0x8964])) -#define MCF_PSC3_PSCRFCR (*(vuint32*)(&__MBAR[0x8968])) -#define MCF_PSC3_PSCRFAR (*(vuint16*)(&__MBAR[0x896E])) -#define MCF_PSC3_PSCRFRP (*(vuint16*)(&__MBAR[0x8972])) -#define MCF_PSC3_PSCRFWP (*(vuint16*)(&__MBAR[0x8976])) -#define MCF_PSC3_PSCRLRFP (*(vuint16*)(&__MBAR[0x897A])) -#define MCF_PSC3_PSCRLWFP (*(vuint16*)(&__MBAR[0x897E])) -#define MCF_PSC3_PSCTFDR (*(vuint32*)(&__MBAR[0x8980])) -#define MCF_PSC3_PSCTFSR (*(vuint16*)(&__MBAR[0x8984])) -#define MCF_PSC3_PSCTFCR (*(vuint32*)(&__MBAR[0x8988])) -#define MCF_PSC3_PSCTFAR (*(vuint16*)(&__MBAR[0x898E])) -#define MCF_PSC3_PSCTFRP (*(vuint16*)(&__MBAR[0x8992])) -#define MCF_PSC3_PSCTFWP (*(vuint16*)(&__MBAR[0x8996])) -#define MCF_PSC3_PSCTLRFP (*(vuint16*)(&__MBAR[0x899A])) -#define MCF_PSC3_PSCTLWFP (*(vuint16*)(&__MBAR[0x899E])) +#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8900])) +#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8900])) +#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8904])) +#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8904])) +#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8908])) +#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x890C])) +#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8910])) +#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8910])) +#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8914])) +#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8914])) +#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8918])) +#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x891C])) +#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8934])) +#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8938])) +#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x893C])) +#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8940])) +#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8944])) +#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8948])) +#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x894C])) +#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8950])) +#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8954])) +#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8958])) +#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x895C])) +#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8960])) +#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8964])) +#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8968])) +#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x896E])) +#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8972])) +#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8976])) +#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x897A])) +#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x897E])) +#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8980])) +#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8984])) +#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8988])) +#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x898E])) +#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8992])) +#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8996])) +#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x899A])) +#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x899E])) -#define MCF_PSC_PSCMR(x) (*(vuint8 *)(&__MBAR[0x8600 + ((x)*0x100)])) -#define MCF_PSC_PSCCSR(x) (*(vuint8 *)(&__MBAR[0x8604 + ((x)*0x100)])) -#define MCF_PSC_PSCSR(x) (*(vuint16*)(&__MBAR[0x8604 + ((x)*0x100)])) -#define MCF_PSC_PSCCR(x) (*(vuint8 *)(&__MBAR[0x8608 + ((x)*0x100)])) -#define MCF_PSC_PSCRB_8BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCTB_8BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCRB_16BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCTB_16BIT(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCRB_AC97(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCTB_AC97(x) (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCIPCR(x) (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)])) -#define MCF_PSC_PSCACR(x) (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)])) -#define MCF_PSC_PSCIMR(x) (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)])) -#define MCF_PSC_PSCISR(x) (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)])) -#define MCF_PSC_PSCCTUR(x) (*(vuint8 *)(&__MBAR[0x8618 + ((x)*0x100)])) -#define MCF_PSC_PSCCTLR(x) (*(vuint8 *)(&__MBAR[0x861C + ((x)*0x100)])) -#define MCF_PSC_PSCIP(x) (*(vuint8 *)(&__MBAR[0x8634 + ((x)*0x100)])) -#define MCF_PSC_PSCOPSET(x) (*(vuint8 *)(&__MBAR[0x8638 + ((x)*0x100)])) -#define MCF_PSC_PSCOPRESET(x) (*(vuint8 *)(&__MBAR[0x863C + ((x)*0x100)])) -#define MCF_PSC_PSCSICR(x) (*(vuint8 *)(&__MBAR[0x8640 + ((x)*0x100)])) -#define MCF_PSC_PSCIRCR1(x) (*(vuint8 *)(&__MBAR[0x8644 + ((x)*0x100)])) -#define MCF_PSC_PSCIRCR2(x) (*(vuint8 *)(&__MBAR[0x8648 + ((x)*0x100)])) -#define MCF_PSC_PSCIRSDR(x) (*(vuint8 *)(&__MBAR[0x864C + ((x)*0x100)])) -#define MCF_PSC_PSCIRMDR(x) (*(vuint8 *)(&__MBAR[0x8650 + ((x)*0x100)])) -#define MCF_PSC_PSCIRFDR(x) (*(vuint8 *)(&__MBAR[0x8654 + ((x)*0x100)])) -#define MCF_PSC_PSCRFCNT(x) (*(vuint16*)(&__MBAR[0x8658 + ((x)*0x100)])) -#define MCF_PSC_PSCTFCNT(x) (*(vuint16*)(&__MBAR[0x865C + ((x)*0x100)])) -#define MCF_PSC_PSCRFDR(x) (*(vuint32*)(&__MBAR[0x8660 + ((x)*0x100)])) -#define MCF_PSC_PSCRFSR(x) (*(vuint16*)(&__MBAR[0x8664 + ((x)*0x100)])) -#define MCF_PSC_PSCRFCR(x) (*(vuint32*)(&__MBAR[0x8668 + ((x)*0x100)])) -#define MCF_PSC_PSCRFAR(x) (*(vuint16*)(&__MBAR[0x866E + ((x)*0x100)])) -#define MCF_PSC_PSCRFRP(x) (*(vuint16*)(&__MBAR[0x8672 + ((x)*0x100)])) -#define MCF_PSC_PSCRFWP(x) (*(vuint16*)(&__MBAR[0x8676 + ((x)*0x100)])) -#define MCF_PSC_PSCRLRFP(x) (*(vuint16*)(&__MBAR[0x867A + ((x)*0x100)])) -#define MCF_PSC_PSCRLWFP(x) (*(vuint16*)(&__MBAR[0x867E + ((x)*0x100)])) -#define MCF_PSC_PSCTFDR(x) (*(vuint32*)(&__MBAR[0x8680 + ((x)*0x100)])) -#define MCF_PSC_PSCTFSR(x) (*(vuint16*)(&__MBAR[0x8684 + ((x)*0x100)])) -#define MCF_PSC_PSCTFCR(x) (*(vuint32*)(&__MBAR[0x8688 + ((x)*0x100)])) -#define MCF_PSC_PSCTFAR(x) (*(vuint16*)(&__MBAR[0x868E + ((x)*0x100)])) -#define MCF_PSC_PSCTFRP(x) (*(vuint16*)(&__MBAR[0x8692 + ((x)*0x100)])) -#define MCF_PSC_PSCTFWP(x) (*(vuint16*)(&__MBAR[0x8696 + ((x)*0x100)])) -#define MCF_PSC_PSCTLRFP(x) (*(vuint16*)(&__MBAR[0x869A + ((x)*0x100)])) -#define MCF_PSC_PSCTLWFP(x) (*(vuint16*)(&__MBAR[0x869E + ((x)*0x100)])) +#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&__MBAR[0x8600 + ((x)*0x100)])) +#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&__MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&__MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&__MBAR[0x8608 + ((x)*0x100)])) +#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&__MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&__MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&__MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&__MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&__MBAR[0x8618 + ((x)*0x100)])) +#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&__MBAR[0x861C + ((x)*0x100)])) +#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&__MBAR[0x8634 + ((x)*0x100)])) +#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&__MBAR[0x8638 + ((x)*0x100)])) +#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&__MBAR[0x863C + ((x)*0x100)])) +#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&__MBAR[0x8640 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&__MBAR[0x8644 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&__MBAR[0x8648 + ((x)*0x100)])) +#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&__MBAR[0x864C + ((x)*0x100)])) +#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&__MBAR[0x8650 + ((x)*0x100)])) +#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&__MBAR[0x8654 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&__MBAR[0x8658 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&__MBAR[0x865C + ((x)*0x100)])) +#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8660 + ((x)*0x100)])) +#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&__MBAR[0x8664 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&__MBAR[0x8668 + ((x)*0x100)])) +#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&__MBAR[0x866E + ((x)*0x100)])) +#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&__MBAR[0x8672 + ((x)*0x100)])) +#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&__MBAR[0x8676 + ((x)*0x100)])) +#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&__MBAR[0x867A + ((x)*0x100)])) +#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&__MBAR[0x867E + ((x)*0x100)])) +#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8680 + ((x)*0x100)])) +#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&__MBAR[0x8684 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&__MBAR[0x8688 + ((x)*0x100)])) +#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&__MBAR[0x868E + ((x)*0x100)])) +#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&__MBAR[0x8692 + ((x)*0x100)])) +#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&__MBAR[0x8696 + ((x)*0x100)])) +#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&__MBAR[0x869A + ((x)*0x100)])) +#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&__MBAR[0x869E + ((x)*0x100)])) /* Bit definitions and macros for MCF_PSC_PSCMR */ #define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0) diff --git a/BaS_GNU/include/MCF5475_SDRAMC.h b/BaS_GNU/include/MCF5475_SDRAMC.h index 843ac12..d3d5f46 100644 --- a/BaS_GNU/include/MCF5475_SDRAMC.h +++ b/BaS_GNU/include/MCF5475_SDRAMC.h @@ -24,16 +24,16 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_SDRAMC_SDRAMDS (*(vuint32*)(&__MBAR[0x4])) -#define MCF_SDRAMC_CS0CFG (*(vuint32*)(&__MBAR[0x20])) -#define MCF_SDRAMC_CS1CFG (*(vuint32*)(&__MBAR[0x24])) -#define MCF_SDRAMC_CS2CFG (*(vuint32*)(&__MBAR[0x28])) -#define MCF_SDRAMC_CS3CFG (*(vuint32*)(&__MBAR[0x2C])) -#define MCF_SDRAMC_SDMR (*(vuint32*)(&__MBAR[0x100])) -#define MCF_SDRAMC_SDCR (*(vuint32*)(&__MBAR[0x104])) -#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(&__MBAR[0x108])) -#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(&__MBAR[0x10C])) -#define MCF_SDRAMC_CSCFG(x) (*(vuint32*)(&__MBAR[0x20 + ((x)*0x4)])) +#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&__MBAR[0x4])) +#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&__MBAR[0x20])) +#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&__MBAR[0x24])) +#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&__MBAR[0x28])) +#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&__MBAR[0x2C])) +#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&__MBAR[0x100])) +#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&__MBAR[0x104])) +#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&__MBAR[0x108])) +#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&__MBAR[0x10C])) +#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&__MBAR[0x20 + ((x)*0x4)])) /* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ diff --git a/BaS_GNU/include/MCF5475_SEC.h b/BaS_GNU/include/MCF5475_SEC.h index ce02c30..64e9b97 100644 --- a/BaS_GNU/include/MCF5475_SEC.h +++ b/BaS_GNU/include/MCF5475_SEC.h @@ -24,54 +24,54 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_SEC_EUACRH (*(vuint32*)(&__MBAR[0x21000])) -#define MCF_SEC_EUACRL (*(vuint32*)(&__MBAR[0x21004])) -#define MCF_SEC_SIMRH (*(vuint32*)(&__MBAR[0x21008])) -#define MCF_SEC_SIMRL (*(vuint32*)(&__MBAR[0x2100C])) -#define MCF_SEC_SISRH (*(vuint32*)(&__MBAR[0x21010])) -#define MCF_SEC_SISRL (*(vuint32*)(&__MBAR[0x21014])) -#define MCF_SEC_SICRH (*(vuint32*)(&__MBAR[0x21018])) -#define MCF_SEC_SICRL (*(vuint32*)(&__MBAR[0x2101C])) -#define MCF_SEC_SIDR (*(vuint32*)(&__MBAR[0x21020])) -#define MCF_SEC_EUASRH (*(vuint32*)(&__MBAR[0x21028])) -#define MCF_SEC_EUASRL (*(vuint32*)(&__MBAR[0x2102C])) -#define MCF_SEC_SMCR (*(vuint32*)(&__MBAR[0x21030])) -#define MCF_SEC_MEAR (*(vuint32*)(&__MBAR[0x21038])) -#define MCF_SEC_CCCR0 (*(vuint32*)(&__MBAR[0x2200C])) -#define MCF_SEC_CCPSRH0 (*(vuint32*)(&__MBAR[0x22010])) -#define MCF_SEC_CCPSRL0 (*(vuint32*)(&__MBAR[0x22014])) -#define MCF_SEC_CDPR0 (*(vuint32*)(&__MBAR[0x22044])) -#define MCF_SEC_FR0 (*(vuint32*)(&__MBAR[0x2204C])) -#define MCF_SEC_CCCR1 (*(vuint32*)(&__MBAR[0x2300C])) -#define MCF_SEC_CCPSRH1 (*(vuint32*)(&__MBAR[0x23010])) -#define MCF_SEC_CCPSRL1 (*(vuint32*)(&__MBAR[0x23014])) -#define MCF_SEC_CDPR1 (*(vuint32*)(&__MBAR[0x23044])) -#define MCF_SEC_FR1 (*(vuint32*)(&__MBAR[0x2304C])) -#define MCF_SEC_AFRCR (*(vuint32*)(&__MBAR[0x28018])) -#define MCF_SEC_AFSR (*(vuint32*)(&__MBAR[0x28028])) -#define MCF_SEC_AFISR (*(vuint32*)(&__MBAR[0x28030])) -#define MCF_SEC_AFIMR (*(vuint32*)(&__MBAR[0x28038])) -#define MCF_SEC_DRCR (*(vuint32*)(&__MBAR[0x2A018])) -#define MCF_SEC_DSR (*(vuint32*)(&__MBAR[0x2A028])) -#define MCF_SEC_DISR (*(vuint32*)(&__MBAR[0x2A030])) -#define MCF_SEC_DIMR (*(vuint32*)(&__MBAR[0x2A038])) -#define MCF_SEC_MDRCR (*(vuint32*)(&__MBAR[0x2C018])) -#define MCF_SEC_MDSR (*(vuint32*)(&__MBAR[0x2C028])) -#define MCF_SEC_MDISR (*(vuint32*)(&__MBAR[0x2C030])) -#define MCF_SEC_MDIMR (*(vuint32*)(&__MBAR[0x2C038])) -#define MCF_SEC_RNGRCR (*(vuint32*)(&__MBAR[0x2E018])) -#define MCF_SEC_RNGSR (*(vuint32*)(&__MBAR[0x2E028])) -#define MCF_SEC_RNGISR (*(vuint32*)(&__MBAR[0x2E030])) -#define MCF_SEC_RNGIMR (*(vuint32*)(&__MBAR[0x2E038])) -#define MCF_SEC_AESRCR (*(vuint32*)(&__MBAR[0x32018])) -#define MCF_SEC_AESSR (*(vuint32*)(&__MBAR[0x32028])) -#define MCF_SEC_AESISR (*(vuint32*)(&__MBAR[0x32030])) -#define MCF_SEC_AESIMR (*(vuint32*)(&__MBAR[0x32038])) -#define MCF_SEC_CCCRn(x) (*(vuint32*)(&__MBAR[0x2200C + ((x)*0x1000)])) -#define MCF_SEC_CCPSRHn(x) (*(vuint32*)(&__MBAR[0x22010 + ((x)*0x1000)])) -#define MCF_SEC_CCPSRLn(x) (*(vuint32*)(&__MBAR[0x22014 + ((x)*0x1000)])) -#define MCF_SEC_CDPRn(x) (*(vuint32*)(&__MBAR[0x22044 + ((x)*0x1000)])) -#define MCF_SEC_FRn(x) (*(vuint32*)(&__MBAR[0x2204C + ((x)*0x1000)])) +#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&__MBAR[0x21000])) +#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&__MBAR[0x21004])) +#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&__MBAR[0x21008])) +#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&__MBAR[0x2100C])) +#define MCF_SEC_SISRH (*(volatile uint32_t*)(&__MBAR[0x21010])) +#define MCF_SEC_SISRL (*(volatile uint32_t*)(&__MBAR[0x21014])) +#define MCF_SEC_SICRH (*(volatile uint32_t*)(&__MBAR[0x21018])) +#define MCF_SEC_SICRL (*(volatile uint32_t*)(&__MBAR[0x2101C])) +#define MCF_SEC_SIDR (*(volatile uint32_t*)(&__MBAR[0x21020])) +#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&__MBAR[0x21028])) +#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&__MBAR[0x2102C])) +#define MCF_SEC_SMCR (*(volatile uint32_t*)(&__MBAR[0x21030])) +#define MCF_SEC_MEAR (*(volatile uint32_t*)(&__MBAR[0x21038])) +#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&__MBAR[0x2200C])) +#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&__MBAR[0x22010])) +#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&__MBAR[0x22014])) +#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&__MBAR[0x22044])) +#define MCF_SEC_FR0 (*(volatile uint32_t*)(&__MBAR[0x2204C])) +#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&__MBAR[0x2300C])) +#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&__MBAR[0x23010])) +#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&__MBAR[0x23014])) +#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&__MBAR[0x23044])) +#define MCF_SEC_FR1 (*(volatile uint32_t*)(&__MBAR[0x2304C])) +#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&__MBAR[0x28018])) +#define MCF_SEC_AFSR (*(volatile uint32_t*)(&__MBAR[0x28028])) +#define MCF_SEC_AFISR (*(volatile uint32_t*)(&__MBAR[0x28030])) +#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&__MBAR[0x28038])) +#define MCF_SEC_DRCR (*(volatile uint32_t*)(&__MBAR[0x2A018])) +#define MCF_SEC_DSR (*(volatile uint32_t*)(&__MBAR[0x2A028])) +#define MCF_SEC_DISR (*(volatile uint32_t*)(&__MBAR[0x2A030])) +#define MCF_SEC_DIMR (*(volatile uint32_t*)(&__MBAR[0x2A038])) +#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&__MBAR[0x2C018])) +#define MCF_SEC_MDSR (*(volatile uint32_t*)(&__MBAR[0x2C028])) +#define MCF_SEC_MDISR (*(volatile uint32_t*)(&__MBAR[0x2C030])) +#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&__MBAR[0x2C038])) +#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&__MBAR[0x2E018])) +#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&__MBAR[0x2E028])) +#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&__MBAR[0x2E030])) +#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&__MBAR[0x2E038])) +#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&__MBAR[0x32018])) +#define MCF_SEC_AESSR (*(volatile uint32_t*)(&__MBAR[0x32028])) +#define MCF_SEC_AESISR (*(volatile uint32_t*)(&__MBAR[0x32030])) +#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&__MBAR[0x32038])) +#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&__MBAR[0x2200C + ((x)*0x1000)])) +#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&__MBAR[0x22010 + ((x)*0x1000)])) +#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&__MBAR[0x22014 + ((x)*0x1000)])) +#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&__MBAR[0x22044 + ((x)*0x1000)])) +#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&__MBAR[0x2204C + ((x)*0x1000)])) /* Bit definitions and macros for MCF_SEC_EUACRH */ diff --git a/BaS_GNU/include/MCF5475_SIU.h b/BaS_GNU/include/MCF5475_SIU.h index 498aa91..f8d900f 100644 --- a/BaS_GNU/include/MCF5475_SIU.h +++ b/BaS_GNU/include/MCF5475_SIU.h @@ -24,10 +24,10 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_SIU_SBCR (*(vuint32*)(&__MBAR[0x10])) -#define MCF_SIU_SECSACR (*(vuint32*)(&__MBAR[0x38])) -#define MCF_SIU_RSR (*(vuint32*)(&__MBAR[0x44])) -#define MCF_SIU_JTAGID (*(vuint32*)(&__MBAR[0x50])) +#define MCF_SIU_SBCR (*(volatile uint32_t*)(&__MBAR[0x10])) +#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&__MBAR[0x38])) +#define MCF_SIU_RSR (*(volatile uint32_t*)(&__MBAR[0x44])) +#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&__MBAR[0x50])) /* Bit definitions and macros for MCF_SIU_SBCR */ diff --git a/BaS_GNU/include/MCF5475_SLT.h b/BaS_GNU/include/MCF5475_SLT.h index 44a74c6..7a3c52e 100644 --- a/BaS_GNU/include/MCF5475_SLT.h +++ b/BaS_GNU/include/MCF5475_SLT.h @@ -24,20 +24,20 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_SLT0_STCNT (*(vuint32*)(&__MBAR[0x900])) -#define MCF_SLT0_SCR (*(vuint32*)(&__MBAR[0x904])) -#define MCF_SLT0_SCNT (*(vuint32*)(&__MBAR[0x908])) -#define MCF_SLT0_SSR (*(vuint32*)(&__MBAR[0x90C])) +#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&__MBAR[0x900])) +#define MCF_SLT0_SCR (*(volatile uint32_t*)(&__MBAR[0x904])) +#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&__MBAR[0x908])) +#define MCF_SLT0_SSR (*(volatile uint32_t*)(&__MBAR[0x90C])) -#define MCF_SLT1_STCNT (*(vuint32*)(&__MBAR[0x910])) -#define MCF_SLT1_SCR (*(vuint32*)(&__MBAR[0x914])) -#define MCF_SLT1_SCNT (*(vuint32*)(&__MBAR[0x918])) -#define MCF_SLT1_SSR (*(vuint32*)(&__MBAR[0x91C])) +#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&__MBAR[0x910])) +#define MCF_SLT1_SCR (*(volatile uint32_t*)(&__MBAR[0x914])) +#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&__MBAR[0x918])) +#define MCF_SLT1_SSR (*(volatile uint32_t*)(&__MBAR[0x91C])) -#define MCF_SLT_STCNT(x) (*(vuint32*)(&__MBAR[0x900 + ((x)*0x10)])) -#define MCF_SLT_SCR(x) (*(vuint32*)(&__MBAR[0x904 + ((x)*0x10)])) -#define MCF_SLT_SCNT(x) (*(vuint32*)(&__MBAR[0x908 + ((x)*0x10)])) -#define MCF_SLT_SSR(x) (*(vuint32*)(&__MBAR[0x90C + ((x)*0x10)])) +#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&__MBAR[0x900 + ((x)*0x10)])) +#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&__MBAR[0x904 + ((x)*0x10)])) +#define MCF_SLT_SCNT(x) (*(volatile uint32_t*)(&__MBAR[0x908 + ((x)*0x10)])) +#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&__MBAR[0x90C + ((x)*0x10)])) /* Bit definitions and macros for MCF_SLT_STCNT */ diff --git a/BaS_GNU/include/MCF5475_SRAM.h b/BaS_GNU/include/MCF5475_SRAM.h index 7e645fe..d111f13 100644 --- a/BaS_GNU/include/MCF5475_SRAM.h +++ b/BaS_GNU/include/MCF5475_SRAM.h @@ -24,11 +24,11 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_SRAM_SSCR (*(vuint32*)(&__MBAR[0x1FFC0])) -#define MCF_SRAM_TCCR (*(vuint32*)(&__MBAR[0x1FFC4])) -#define MCF_SRAM_TCCRDR (*(vuint32*)(&__MBAR[0x1FFC8])) -#define MCF_SRAM_TCCRDW (*(vuint32*)(&__MBAR[0x1FFCC])) -#define MCF_SRAM_TCCRSEC (*(vuint32*)(&__MBAR[0x1FFD0])) +#define MCF_SRAM_SSCR (*(volatile uint32_t*)(&__MBAR[0x1FFC0])) +#define MCF_SRAM_TCCR (*(volatile uint32_t*)(&__MBAR[0x1FFC4])) +#define MCF_SRAM_TCCRDR (*(volatile uint32_t*)(&__MBAR[0x1FFC8])) +#define MCF_SRAM_TCCRDW (*(volatile uint32_t*)(&__MBAR[0x1FFCC])) +#define MCF_SRAM_TCCRSEC (*(volatile uint32_t*)(&__MBAR[0x1FFD0])) /* Bit definitions and macros for MCF_SRAM_SSCR */ diff --git a/BaS_GNU/include/MCF5475_USB.h b/BaS_GNU/include/MCF5475_USB.h index da9e6db..c60273c 100644 --- a/BaS_GNU/include/MCF5475_USB.h +++ b/BaS_GNU/include/MCF5475_USB.h @@ -24,237 +24,237 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_USB_USBAISR (*(vuint8 *)(&__MBAR[0xB000])) -#define MCF_USB_USBAIMR (*(vuint8 *)(&__MBAR[0xB001])) -#define MCF_USB_EPINFO (*(vuint8 *)(&__MBAR[0xB003])) -#define MCF_USB_CFGR (*(vuint8 *)(&__MBAR[0xB004])) -#define MCF_USB_CFGAR (*(vuint8 *)(&__MBAR[0xB005])) -#define MCF_USB_SPEEDR (*(vuint8 *)(&__MBAR[0xB006])) -#define MCF_USB_FRMNUMR (*(vuint16*)(&__MBAR[0xB00E])) -#define MCF_USB_EPTNR (*(vuint16*)(&__MBAR[0xB010])) -#define MCF_USB_IFUR (*(vuint16*)(&__MBAR[0xB014])) -#define MCF_USB_IFR0 (*(vuint16*)(&__MBAR[0xB040])) -#define MCF_USB_IFR1 (*(vuint16*)(&__MBAR[0xB042])) -#define MCF_USB_IFR2 (*(vuint16*)(&__MBAR[0xB044])) -#define MCF_USB_IFR3 (*(vuint16*)(&__MBAR[0xB046])) -#define MCF_USB_IFR4 (*(vuint16*)(&__MBAR[0xB048])) -#define MCF_USB_IFR5 (*(vuint16*)(&__MBAR[0xB04A])) -#define MCF_USB_IFR6 (*(vuint16*)(&__MBAR[0xB04C])) -#define MCF_USB_IFR7 (*(vuint16*)(&__MBAR[0xB04E])) -#define MCF_USB_IFR8 (*(vuint16*)(&__MBAR[0xB050])) -#define MCF_USB_IFR9 (*(vuint16*)(&__MBAR[0xB052])) -#define MCF_USB_IFR10 (*(vuint16*)(&__MBAR[0xB054])) -#define MCF_USB_IFR11 (*(vuint16*)(&__MBAR[0xB056])) -#define MCF_USB_IFR12 (*(vuint16*)(&__MBAR[0xB058])) -#define MCF_USB_IFR13 (*(vuint16*)(&__MBAR[0xB05A])) -#define MCF_USB_IFR14 (*(vuint16*)(&__MBAR[0xB05C])) -#define MCF_USB_IFR15 (*(vuint16*)(&__MBAR[0xB05E])) -#define MCF_USB_IFR16 (*(vuint16*)(&__MBAR[0xB060])) -#define MCF_USB_IFR17 (*(vuint16*)(&__MBAR[0xB062])) -#define MCF_USB_IFR18 (*(vuint16*)(&__MBAR[0xB064])) -#define MCF_USB_IFR19 (*(vuint16*)(&__MBAR[0xB066])) -#define MCF_USB_IFR20 (*(vuint16*)(&__MBAR[0xB068])) -#define MCF_USB_IFR21 (*(vuint16*)(&__MBAR[0xB06A])) -#define MCF_USB_IFR22 (*(vuint16*)(&__MBAR[0xB06C])) -#define MCF_USB_IFR23 (*(vuint16*)(&__MBAR[0xB06E])) -#define MCF_USB_IFR24 (*(vuint16*)(&__MBAR[0xB070])) -#define MCF_USB_IFR25 (*(vuint16*)(&__MBAR[0xB072])) -#define MCF_USB_IFR26 (*(vuint16*)(&__MBAR[0xB074])) -#define MCF_USB_IFR27 (*(vuint16*)(&__MBAR[0xB076])) -#define MCF_USB_IFR28 (*(vuint16*)(&__MBAR[0xB078])) -#define MCF_USB_IFR29 (*(vuint16*)(&__MBAR[0xB07A])) -#define MCF_USB_IFR30 (*(vuint16*)(&__MBAR[0xB07C])) -#define MCF_USB_IFR31 (*(vuint16*)(&__MBAR[0xB07E])) -#define MCF_USB_PPCNT (*(vuint16*)(&__MBAR[0xB080])) -#define MCF_USB_DPCNT (*(vuint16*)(&__MBAR[0xB082])) -#define MCF_USB_CRCECNT (*(vuint16*)(&__MBAR[0xB084])) -#define MCF_USB_BSECNT (*(vuint16*)(&__MBAR[0xB086])) -#define MCF_USB_PIDECNT (*(vuint16*)(&__MBAR[0xB088])) -#define MCF_USB_FRMECNT (*(vuint16*)(&__MBAR[0xB08A])) -#define MCF_USB_TXPCNT (*(vuint16*)(&__MBAR[0xB08C])) -#define MCF_USB_CNTOVR (*(vuint8 *)(&__MBAR[0xB08E])) -#define MCF_USB_EP0ACR (*(vuint8 *)(&__MBAR[0xB101])) -#define MCF_USB_EP0MPSR (*(vuint16*)(&__MBAR[0xB102])) -#define MCF_USB_EP0IFR (*(vuint8 *)(&__MBAR[0xB104])) -#define MCF_USB_EP0SR (*(vuint8 *)(&__MBAR[0xB105])) -#define MCF_USB_BMRTR (*(vuint8 *)(&__MBAR[0xB106])) -#define MCF_USB_BRTR (*(vuint8 *)(&__MBAR[0xB107])) -#define MCF_USB_WVALUER (*(vuint16*)(&__MBAR[0xB108])) -#define MCF_USB_WINDEXR (*(vuint16*)(&__MBAR[0xB10A])) -#define MCF_USB_WLENGTHR (*(vuint16*)(&__MBAR[0xB10C])) -#define MCF_USB_EP1OUTACR (*(vuint8 *)(&__MBAR[0xB131])) -#define MCF_USB_EP1OUTMPSR (*(vuint16*)(&__MBAR[0xB132])) -#define MCF_USB_EP1OUTIFR (*(vuint8 *)(&__MBAR[0xB134])) -#define MCF_USB_EP1OUTSR (*(vuint8 *)(&__MBAR[0xB135])) -#define MCF_USB_EP1OUTSFR (*(vuint16*)(&__MBAR[0xB13E])) -#define MCF_USB_EP1INACR (*(vuint8 *)(&__MBAR[0xB149])) -#define MCF_USB_EP1INMPSR (*(vuint16*)(&__MBAR[0xB14A])) -#define MCF_USB_EP1INIFR (*(vuint8 *)(&__MBAR[0xB14C])) -#define MCF_USB_EP1INSR (*(vuint8 *)(&__MBAR[0xB14D])) -#define MCF_USB_EP1INSFR (*(vuint16*)(&__MBAR[0xB156])) -#define MCF_USB_EP2OUTACR (*(vuint8 *)(&__MBAR[0xB161])) -#define MCF_USB_EP2OUTMPSR (*(vuint16*)(&__MBAR[0xB162])) -#define MCF_USB_EP2OUTIFR (*(vuint8 *)(&__MBAR[0xB164])) -#define MCF_USB_EP2OUTSR (*(vuint8 *)(&__MBAR[0xB165])) -#define MCF_USB_EP2OUTSFR (*(vuint16*)(&__MBAR[0xB16E])) -#define MCF_USB_EP2INACR (*(vuint8 *)(&__MBAR[0xB179])) -#define MCF_USB_EP2INMPSR (*(vuint16*)(&__MBAR[0xB17A])) -#define MCF_USB_EP2INIFR (*(vuint8 *)(&__MBAR[0xB17C])) -#define MCF_USB_EP2INSR (*(vuint8 *)(&__MBAR[0xB17D])) -#define MCF_USB_EP2INSFR (*(vuint16*)(&__MBAR[0xB186])) -#define MCF_USB_EP3OUTACR (*(vuint8 *)(&__MBAR[0xB191])) -#define MCF_USB_EP3OUTMPSR (*(vuint16*)(&__MBAR[0xB192])) -#define MCF_USB_EP3OUTIFR (*(vuint8 *)(&__MBAR[0xB194])) -#define MCF_USB_EP3OUTSR (*(vuint8 *)(&__MBAR[0xB195])) -#define MCF_USB_EP3OUTSFR (*(vuint16*)(&__MBAR[0xB19E])) -#define MCF_USB_EP3INACR (*(vuint8 *)(&__MBAR[0xB1A9])) -#define MCF_USB_EP3INMPSR (*(vuint16*)(&__MBAR[0xB1AA])) -#define MCF_USB_EP3INIFR (*(vuint8 *)(&__MBAR[0xB1AC])) -#define MCF_USB_EP3INSR (*(vuint8 *)(&__MBAR[0xB1AD])) -#define MCF_USB_EP3INSFR (*(vuint16*)(&__MBAR[0xB1B6])) -#define MCF_USB_EP4OUTACR (*(vuint8 *)(&__MBAR[0xB1C1])) -#define MCF_USB_EP4OUTMPSR (*(vuint16*)(&__MBAR[0xB1C2])) -#define MCF_USB_EP4OUTIFR (*(vuint8 *)(&__MBAR[0xB1C4])) -#define MCF_USB_EP4OUTSR (*(vuint8 *)(&__MBAR[0xB1C5])) -#define MCF_USB_EP4OUTSFR (*(vuint16*)(&__MBAR[0xB1CE])) -#define MCF_USB_EP4INACR (*(vuint8 *)(&__MBAR[0xB1D9])) -#define MCF_USB_EP4INMPSR (*(vuint16*)(&__MBAR[0xB1DA])) -#define MCF_USB_EP4INIFR (*(vuint8 *)(&__MBAR[0xB1DC])) -#define MCF_USB_EP4INSR (*(vuint8 *)(&__MBAR[0xB1DD])) -#define MCF_USB_EP4INSFR (*(vuint16*)(&__MBAR[0xB1E6])) -#define MCF_USB_EP5OUTACR (*(vuint8 *)(&__MBAR[0xB1F1])) -#define MCF_USB_EP5OUTMPSR (*(vuint16*)(&__MBAR[0xB1F2])) -#define MCF_USB_EP5OUTIFR (*(vuint8 *)(&__MBAR[0xB1F4])) -#define MCF_USB_EP5OUTSR (*(vuint8 *)(&__MBAR[0xB1F5])) -#define MCF_USB_EP5OUTSFR (*(vuint16*)(&__MBAR[0xB1FE])) -#define MCF_USB_EP5INACR (*(vuint8 *)(&__MBAR[0xB209])) -#define MCF_USB_EP5INMPSR (*(vuint16*)(&__MBAR[0xB20A])) -#define MCF_USB_EP5INIFR (*(vuint8 *)(&__MBAR[0xB20C])) -#define MCF_USB_EP5INSR (*(vuint8 *)(&__MBAR[0xB20D])) -#define MCF_USB_EP5INSFR (*(vuint16*)(&__MBAR[0xB216])) -#define MCF_USB_EP6OUTACR (*(vuint8 *)(&__MBAR[0xB221])) -#define MCF_USB_EP6OUTMPSR (*(vuint16*)(&__MBAR[0xB222])) -#define MCF_USB_EP6OUTIFR (*(vuint8 *)(&__MBAR[0xB224])) -#define MCF_USB_EP6OUTSR (*(vuint8 *)(&__MBAR[0xB225])) -#define MCF_USB_EP6OUTSFR (*(vuint16*)(&__MBAR[0xB22E])) -#define MCF_USB_EP6INACR (*(vuint8 *)(&__MBAR[0xB239])) -#define MCF_USB_EP6INMPSR (*(vuint16*)(&__MBAR[0xB23A])) -#define MCF_USB_EP6INIFR (*(vuint8 *)(&__MBAR[0xB23C])) -#define MCF_USB_EP6INSR (*(vuint8 *)(&__MBAR[0xB23D])) -#define MCF_USB_EP6INSFR (*(vuint16*)(&__MBAR[0xB246])) -#define MCF_USB_USBSR (*(vuint32*)(&__MBAR[0xB400])) -#define MCF_USB_USBCR (*(vuint32*)(&__MBAR[0xB404])) -#define MCF_USB_DRAMCR (*(vuint32*)(&__MBAR[0xB408])) -#define MCF_USB_DRAMDR (*(vuint32*)(&__MBAR[0xB40C])) -#define MCF_USB_USBISR (*(vuint32*)(&__MBAR[0xB410])) -#define MCF_USB_USBIMR (*(vuint32*)(&__MBAR[0xB414])) -#define MCF_USB_EP0STAT (*(vuint32*)(&__MBAR[0xB440])) -#define MCF_USB_EP0ISR (*(vuint32*)(&__MBAR[0xB444])) -#define MCF_USB_EP0IMR (*(vuint32*)(&__MBAR[0xB448])) -#define MCF_USB_EP0FRCFGR (*(vuint32*)(&__MBAR[0xB44C])) -#define MCF_USB_EP0FDR (*(vuint32*)(&__MBAR[0xB450])) -#define MCF_USB_EP0FSR (*(vuint32*)(&__MBAR[0xB454])) -#define MCF_USB_EP0FCR (*(vuint32*)(&__MBAR[0xB458])) -#define MCF_USB_EP0FAR (*(vuint32*)(&__MBAR[0xB45C])) -#define MCF_USB_EP0FRP (*(vuint32*)(&__MBAR[0xB460])) -#define MCF_USB_EP0FWP (*(vuint32*)(&__MBAR[0xB464])) -#define MCF_USB_EP0LRFP (*(vuint32*)(&__MBAR[0xB468])) -#define MCF_USB_EP0LWFP (*(vuint32*)(&__MBAR[0xB46C])) -#define MCF_USB_EP1STAT (*(vuint32*)(&__MBAR[0xB470])) -#define MCF_USB_EP1ISR (*(vuint32*)(&__MBAR[0xB474])) -#define MCF_USB_EP1IMR (*(vuint32*)(&__MBAR[0xB478])) -#define MCF_USB_EP1FRCFGR (*(vuint32*)(&__MBAR[0xB47C])) -#define MCF_USB_EP1FDR (*(vuint32*)(&__MBAR[0xB480])) -#define MCF_USB_EP1FSR (*(vuint32*)(&__MBAR[0xB484])) -#define MCF_USB_EP1FCR (*(vuint32*)(&__MBAR[0xB488])) -#define MCF_USB_EP1FAR (*(vuint32*)(&__MBAR[0xB48C])) -#define MCF_USB_EP1FRP (*(vuint32*)(&__MBAR[0xB490])) -#define MCF_USB_EP1FWP (*(vuint32*)(&__MBAR[0xB494])) -#define MCF_USB_EP1LRFP (*(vuint32*)(&__MBAR[0xB498])) -#define MCF_USB_EP1LWFP (*(vuint32*)(&__MBAR[0xB49C])) -#define MCF_USB_EP2STAT (*(vuint32*)(&__MBAR[0xB4A0])) -#define MCF_USB_EP2ISR (*(vuint32*)(&__MBAR[0xB4A4])) -#define MCF_USB_EP2IMR (*(vuint32*)(&__MBAR[0xB4A8])) -#define MCF_USB_EP2FRCFGR (*(vuint32*)(&__MBAR[0xB4AC])) -#define MCF_USB_EP2FDR (*(vuint32*)(&__MBAR[0xB4B0])) -#define MCF_USB_EP2FSR (*(vuint32*)(&__MBAR[0xB4B4])) -#define MCF_USB_EP2FCR (*(vuint32*)(&__MBAR[0xB4B8])) -#define MCF_USB_EP2FAR (*(vuint32*)(&__MBAR[0xB4BC])) -#define MCF_USB_EP2FRP (*(vuint32*)(&__MBAR[0xB4C0])) -#define MCF_USB_EP2FWP (*(vuint32*)(&__MBAR[0xB4C4])) -#define MCF_USB_EP2LRFP (*(vuint32*)(&__MBAR[0xB4C8])) -#define MCF_USB_EP2LWFP (*(vuint32*)(&__MBAR[0xB4CC])) -#define MCF_USB_EP3STAT (*(vuint32*)(&__MBAR[0xB4D0])) -#define MCF_USB_EP3ISR (*(vuint32*)(&__MBAR[0xB4D4])) -#define MCF_USB_EP3IMR (*(vuint32*)(&__MBAR[0xB4D8])) -#define MCF_USB_EP3FRCFGR (*(vuint32*)(&__MBAR[0xB4DC])) -#define MCF_USB_EP3FDR (*(vuint32*)(&__MBAR[0xB4E0])) -#define MCF_USB_EP3FSR (*(vuint32*)(&__MBAR[0xB4E4])) -#define MCF_USB_EP3FCR (*(vuint32*)(&__MBAR[0xB4E8])) -#define MCF_USB_EP3FAR (*(vuint32*)(&__MBAR[0xB4EC])) -#define MCF_USB_EP3FRP (*(vuint32*)(&__MBAR[0xB4F0])) -#define MCF_USB_EP3FWP (*(vuint32*)(&__MBAR[0xB4F4])) -#define MCF_USB_EP3LRFP (*(vuint32*)(&__MBAR[0xB4F8])) -#define MCF_USB_EP3LWFP (*(vuint32*)(&__MBAR[0xB4FC])) -#define MCF_USB_EP4STAT (*(vuint32*)(&__MBAR[0xB500])) -#define MCF_USB_EP4ISR (*(vuint32*)(&__MBAR[0xB504])) -#define MCF_USB_EP4IMR (*(vuint32*)(&__MBAR[0xB508])) -#define MCF_USB_EP4FRCFGR (*(vuint32*)(&__MBAR[0xB50C])) -#define MCF_USB_EP4FDR (*(vuint32*)(&__MBAR[0xB510])) -#define MCF_USB_EP4FSR (*(vuint32*)(&__MBAR[0xB514])) -#define MCF_USB_EP4FCR (*(vuint32*)(&__MBAR[0xB518])) -#define MCF_USB_EP4FAR (*(vuint32*)(&__MBAR[0xB51C])) -#define MCF_USB_EP4FRP (*(vuint32*)(&__MBAR[0xB520])) -#define MCF_USB_EP4FWP (*(vuint32*)(&__MBAR[0xB524])) -#define MCF_USB_EP4LRFP (*(vuint32*)(&__MBAR[0xB528])) -#define MCF_USB_EP4LWFP (*(vuint32*)(&__MBAR[0xB52C])) -#define MCF_USB_EP5STAT (*(vuint32*)(&__MBAR[0xB530])) -#define MCF_USB_EP5ISR (*(vuint32*)(&__MBAR[0xB534])) -#define MCF_USB_EP5IMR (*(vuint32*)(&__MBAR[0xB538])) -#define MCF_USB_EP5FRCFGR (*(vuint32*)(&__MBAR[0xB53C])) -#define MCF_USB_EP5FDR (*(vuint32*)(&__MBAR[0xB540])) -#define MCF_USB_EP5FSR (*(vuint32*)(&__MBAR[0xB544])) -#define MCF_USB_EP5FCR (*(vuint32*)(&__MBAR[0xB548])) -#define MCF_USB_EP5FAR (*(vuint32*)(&__MBAR[0xB54C])) -#define MCF_USB_EP5FRP (*(vuint32*)(&__MBAR[0xB550])) -#define MCF_USB_EP5FWP (*(vuint32*)(&__MBAR[0xB554])) -#define MCF_USB_EP5LRFP (*(vuint32*)(&__MBAR[0xB558])) -#define MCF_USB_EP5LWFP (*(vuint32*)(&__MBAR[0xB55C])) -#define MCF_USB_EP6STAT (*(vuint32*)(&__MBAR[0xB560])) -#define MCF_USB_EP6ISR (*(vuint32*)(&__MBAR[0xB564])) -#define MCF_USB_EP6IMR (*(vuint32*)(&__MBAR[0xB568])) -#define MCF_USB_EP6FRCFGR (*(vuint32*)(&__MBAR[0xB56C])) -#define MCF_USB_EP6FDR (*(vuint32*)(&__MBAR[0xB570])) -#define MCF_USB_EP6FSR (*(vuint32*)(&__MBAR[0xB574])) -#define MCF_USB_EP6FCR (*(vuint32*)(&__MBAR[0xB578])) -#define MCF_USB_EP6FAR (*(vuint32*)(&__MBAR[0xB57C])) -#define MCF_USB_EP6FRP (*(vuint32*)(&__MBAR[0xB580])) -#define MCF_USB_EP6FWP (*(vuint32*)(&__MBAR[0xB584])) -#define MCF_USB_EP6LRFP (*(vuint32*)(&__MBAR[0xB588])) -#define MCF_USB_EP6LWFP (*(vuint32*)(&__MBAR[0xB58C])) -#define MCF_USB_IFR(x) (*(vuint16*)(&__MBAR[0xB040 + ((x)*0x2)])) -#define MCF_USB_EPOUTACR(x) (*(vuint8 *)(&__MBAR[0xB131 + ((x-1)*0x30)])) -#define MCF_USB_EPOUTMPSR(x) (*(vuint16*)(&__MBAR[0xB132 + ((x-1)*0x30)])) -#define MCF_USB_EPOUTIFR(x) (*(vuint8 *)(&__MBAR[0xB134 + ((x-1)*0x30)])) -#define MCF_USB_EPOUTSR(x) (*(vuint8 *)(&__MBAR[0xB135 + ((x-1)*0x30)])) -#define MCF_USB_EPOUTSFR(x) (*(vuint16*)(&__MBAR[0xB13E + ((x-1)*0x30)])) -#define MCF_USB_EPINACR(x) (*(vuint8 *)(&__MBAR[0xB149 + ((x-1)*0x30)])) -#define MCF_USB_EPINMPSR(x) (*(vuint16*)(&__MBAR[0xB14A + ((x-1)*0x30)])) -#define MCF_USB_EPINIFR(x) (*(vuint8 *)(&__MBAR[0xB14C + ((x-1)*0x30)])) -#define MCF_USB_EPINSR(x) (*(vuint8 *)(&__MBAR[0xB14D + ((x-1)*0x30)])) -#define MCF_USB_EPINSFR(x) (*(vuint16*)(&__MBAR[0xB156 + ((x-1)*0x30)])) -#define MCF_USB_EPSTAT(x) (*(vuint32*)(&__MBAR[0xB440 + ((x)*0x30)])) -#define MCF_USB_EPISR(x) (*(vuint32*)(&__MBAR[0xB444 + ((x)*0x30)])) -#define MCF_USB_EPIMR(x) (*(vuint32*)(&__MBAR[0xB448 + ((x)*0x30)])) -#define MCF_USB_EPFRCFGR(x) (*(vuint32*)(&__MBAR[0xB44C + ((x)*0x30)])) -#define MCF_USB_EPFDR(x) (*(vuint32*)(&__MBAR[0xB450 + ((x)*0x30)])) -#define MCF_USB_EPFSR(x) (*(vuint32*)(&__MBAR[0xB454 + ((x)*0x30)])) -#define MCF_USB_EPFCR(x) (*(vuint32*)(&__MBAR[0xB458 + ((x)*0x30)])) -#define MCF_USB_EPFAR(x) (*(vuint32*)(&__MBAR[0xB45C + ((x)*0x30)])) -#define MCF_USB_EPFRP(x) (*(vuint32*)(&__MBAR[0xB460 + ((x)*0x30)])) -#define MCF_USB_EPFWP(x) (*(vuint32*)(&__MBAR[0xB464 + ((x)*0x30)])) -#define MCF_USB_EPLRFP(x) (*(vuint32*)(&__MBAR[0xB468 + ((x)*0x30)])) -#define MCF_USB_EPLWFP(x) (*(vuint32*)(&__MBAR[0xB46C + ((x)*0x30)])) +#define MCF_USB_USBAISR (*(volatile uint8_t *)(&__MBAR[0xB000])) +#define MCF_USB_USBAIMR (*(volatile uint8_t *)(&__MBAR[0xB001])) +#define MCF_USB_EPINFO (*(volatile uint8_t *)(&__MBAR[0xB003])) +#define MCF_USB_CFGR (*(volatile uint8_t *)(&__MBAR[0xB004])) +#define MCF_USB_CFGAR (*(volatile uint8_t *)(&__MBAR[0xB005])) +#define MCF_USB_SPEEDR (*(volatile uint8_t *)(&__MBAR[0xB006])) +#define MCF_USB_FRMNUMR (*(volatile uint16_t*)(&__MBAR[0xB00E])) +#define MCF_USB_EPTNR (*(volatile uint16_t*)(&__MBAR[0xB010])) +#define MCF_USB_IFUR (*(volatile uint16_t*)(&__MBAR[0xB014])) +#define MCF_USB_IFR0 (*(volatile uint16_t*)(&__MBAR[0xB040])) +#define MCF_USB_IFR1 (*(volatile uint16_t*)(&__MBAR[0xB042])) +#define MCF_USB_IFR2 (*(volatile uint16_t*)(&__MBAR[0xB044])) +#define MCF_USB_IFR3 (*(volatile uint16_t*)(&__MBAR[0xB046])) +#define MCF_USB_IFR4 (*(volatile uint16_t*)(&__MBAR[0xB048])) +#define MCF_USB_IFR5 (*(volatile uint16_t*)(&__MBAR[0xB04A])) +#define MCF_USB_IFR6 (*(volatile uint16_t*)(&__MBAR[0xB04C])) +#define MCF_USB_IFR7 (*(volatile uint16_t*)(&__MBAR[0xB04E])) +#define MCF_USB_IFR8 (*(volatile uint16_t*)(&__MBAR[0xB050])) +#define MCF_USB_IFR9 (*(volatile uint16_t*)(&__MBAR[0xB052])) +#define MCF_USB_IFR10 (*(volatile uint16_t*)(&__MBAR[0xB054])) +#define MCF_USB_IFR11 (*(volatile uint16_t*)(&__MBAR[0xB056])) +#define MCF_USB_IFR12 (*(volatile uint16_t*)(&__MBAR[0xB058])) +#define MCF_USB_IFR13 (*(volatile uint16_t*)(&__MBAR[0xB05A])) +#define MCF_USB_IFR14 (*(volatile uint16_t*)(&__MBAR[0xB05C])) +#define MCF_USB_IFR15 (*(volatile uint16_t*)(&__MBAR[0xB05E])) +#define MCF_USB_IFR16 (*(volatile uint16_t*)(&__MBAR[0xB060])) +#define MCF_USB_IFR17 (*(volatile uint16_t*)(&__MBAR[0xB062])) +#define MCF_USB_IFR18 (*(volatile uint16_t*)(&__MBAR[0xB064])) +#define MCF_USB_IFR19 (*(volatile uint16_t*)(&__MBAR[0xB066])) +#define MCF_USB_IFR20 (*(volatile uint16_t*)(&__MBAR[0xB068])) +#define MCF_USB_IFR21 (*(volatile uint16_t*)(&__MBAR[0xB06A])) +#define MCF_USB_IFR22 (*(volatile uint16_t*)(&__MBAR[0xB06C])) +#define MCF_USB_IFR23 (*(volatile uint16_t*)(&__MBAR[0xB06E])) +#define MCF_USB_IFR24 (*(volatile uint16_t*)(&__MBAR[0xB070])) +#define MCF_USB_IFR25 (*(volatile uint16_t*)(&__MBAR[0xB072])) +#define MCF_USB_IFR26 (*(volatile uint16_t*)(&__MBAR[0xB074])) +#define MCF_USB_IFR27 (*(volatile uint16_t*)(&__MBAR[0xB076])) +#define MCF_USB_IFR28 (*(volatile uint16_t*)(&__MBAR[0xB078])) +#define MCF_USB_IFR29 (*(volatile uint16_t*)(&__MBAR[0xB07A])) +#define MCF_USB_IFR30 (*(volatile uint16_t*)(&__MBAR[0xB07C])) +#define MCF_USB_IFR31 (*(volatile uint16_t*)(&__MBAR[0xB07E])) +#define MCF_USB_PPCNT (*(volatile uint16_t*)(&__MBAR[0xB080])) +#define MCF_USB_DPCNT (*(volatile uint16_t*)(&__MBAR[0xB082])) +#define MCF_USB_CRCECNT (*(volatile uint16_t*)(&__MBAR[0xB084])) +#define MCF_USB_BSECNT (*(volatile uint16_t*)(&__MBAR[0xB086])) +#define MCF_USB_PIDECNT (*(volatile uint16_t*)(&__MBAR[0xB088])) +#define MCF_USB_FRMECNT (*(volatile uint16_t*)(&__MBAR[0xB08A])) +#define MCF_USB_TXPCNT (*(volatile uint16_t*)(&__MBAR[0xB08C])) +#define MCF_USB_CNTOVR (*(volatile uint8_t *)(&__MBAR[0xB08E])) +#define MCF_USB_EP0ACR (*(volatile uint8_t *)(&__MBAR[0xB101])) +#define MCF_USB_EP0MPSR (*(volatile uint16_t*)(&__MBAR[0xB102])) +#define MCF_USB_EP0IFR (*(volatile uint8_t *)(&__MBAR[0xB104])) +#define MCF_USB_EP0SR (*(volatile uint8_t *)(&__MBAR[0xB105])) +#define MCF_USB_BMRTR (*(volatile uint8_t *)(&__MBAR[0xB106])) +#define MCF_USB_BRTR (*(volatile uint8_t *)(&__MBAR[0xB107])) +#define MCF_USB_WVALUER (*(volatile uint16_t*)(&__MBAR[0xB108])) +#define MCF_USB_WINDEXR (*(volatile uint16_t*)(&__MBAR[0xB10A])) +#define MCF_USB_WLENGTHR (*(volatile uint16_t*)(&__MBAR[0xB10C])) +#define MCF_USB_EP1OUTACR (*(volatile uint8_t *)(&__MBAR[0xB131])) +#define MCF_USB_EP1OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB132])) +#define MCF_USB_EP1OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB134])) +#define MCF_USB_EP1OUTSR (*(volatile uint8_t *)(&__MBAR[0xB135])) +#define MCF_USB_EP1OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB13E])) +#define MCF_USB_EP1INACR (*(volatile uint8_t *)(&__MBAR[0xB149])) +#define MCF_USB_EP1INMPSR (*(volatile uint16_t*)(&__MBAR[0xB14A])) +#define MCF_USB_EP1INIFR (*(volatile uint8_t *)(&__MBAR[0xB14C])) +#define MCF_USB_EP1INSR (*(volatile uint8_t *)(&__MBAR[0xB14D])) +#define MCF_USB_EP1INSFR (*(volatile uint16_t*)(&__MBAR[0xB156])) +#define MCF_USB_EP2OUTACR (*(volatile uint8_t *)(&__MBAR[0xB161])) +#define MCF_USB_EP2OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB162])) +#define MCF_USB_EP2OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB164])) +#define MCF_USB_EP2OUTSR (*(volatile uint8_t *)(&__MBAR[0xB165])) +#define MCF_USB_EP2OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB16E])) +#define MCF_USB_EP2INACR (*(volatile uint8_t *)(&__MBAR[0xB179])) +#define MCF_USB_EP2INMPSR (*(volatile uint16_t*)(&__MBAR[0xB17A])) +#define MCF_USB_EP2INIFR (*(volatile uint8_t *)(&__MBAR[0xB17C])) +#define MCF_USB_EP2INSR (*(volatile uint8_t *)(&__MBAR[0xB17D])) +#define MCF_USB_EP2INSFR (*(volatile uint16_t*)(&__MBAR[0xB186])) +#define MCF_USB_EP3OUTACR (*(volatile uint8_t *)(&__MBAR[0xB191])) +#define MCF_USB_EP3OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB192])) +#define MCF_USB_EP3OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB194])) +#define MCF_USB_EP3OUTSR (*(volatile uint8_t *)(&__MBAR[0xB195])) +#define MCF_USB_EP3OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB19E])) +#define MCF_USB_EP3INACR (*(volatile uint8_t *)(&__MBAR[0xB1A9])) +#define MCF_USB_EP3INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1AA])) +#define MCF_USB_EP3INIFR (*(volatile uint8_t *)(&__MBAR[0xB1AC])) +#define MCF_USB_EP3INSR (*(volatile uint8_t *)(&__MBAR[0xB1AD])) +#define MCF_USB_EP3INSFR (*(volatile uint16_t*)(&__MBAR[0xB1B6])) +#define MCF_USB_EP4OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1C1])) +#define MCF_USB_EP4OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1C2])) +#define MCF_USB_EP4OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1C4])) +#define MCF_USB_EP4OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1C5])) +#define MCF_USB_EP4OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1CE])) +#define MCF_USB_EP4INACR (*(volatile uint8_t *)(&__MBAR[0xB1D9])) +#define MCF_USB_EP4INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1DA])) +#define MCF_USB_EP4INIFR (*(volatile uint8_t *)(&__MBAR[0xB1DC])) +#define MCF_USB_EP4INSR (*(volatile uint8_t *)(&__MBAR[0xB1DD])) +#define MCF_USB_EP4INSFR (*(volatile uint16_t*)(&__MBAR[0xB1E6])) +#define MCF_USB_EP5OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1F1])) +#define MCF_USB_EP5OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1F2])) +#define MCF_USB_EP5OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1F4])) +#define MCF_USB_EP5OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1F5])) +#define MCF_USB_EP5OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1FE])) +#define MCF_USB_EP5INACR (*(volatile uint8_t *)(&__MBAR[0xB209])) +#define MCF_USB_EP5INMPSR (*(volatile uint16_t*)(&__MBAR[0xB20A])) +#define MCF_USB_EP5INIFR (*(volatile uint8_t *)(&__MBAR[0xB20C])) +#define MCF_USB_EP5INSR (*(volatile uint8_t *)(&__MBAR[0xB20D])) +#define MCF_USB_EP5INSFR (*(volatile uint16_t*)(&__MBAR[0xB216])) +#define MCF_USB_EP6OUTACR (*(volatile uint8_t *)(&__MBAR[0xB221])) +#define MCF_USB_EP6OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB222])) +#define MCF_USB_EP6OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB224])) +#define MCF_USB_EP6OUTSR (*(volatile uint8_t *)(&__MBAR[0xB225])) +#define MCF_USB_EP6OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB22E])) +#define MCF_USB_EP6INACR (*(volatile uint8_t *)(&__MBAR[0xB239])) +#define MCF_USB_EP6INMPSR (*(volatile uint16_t*)(&__MBAR[0xB23A])) +#define MCF_USB_EP6INIFR (*(volatile uint8_t *)(&__MBAR[0xB23C])) +#define MCF_USB_EP6INSR (*(volatile uint8_t *)(&__MBAR[0xB23D])) +#define MCF_USB_EP6INSFR (*(volatile uint16_t*)(&__MBAR[0xB246])) +#define MCF_USB_USBSR (*(volatile uint32_t*)(&__MBAR[0xB400])) +#define MCF_USB_USBCR (*(volatile uint32_t*)(&__MBAR[0xB404])) +#define MCF_USB_DRAMCR (*(volatile uint32_t*)(&__MBAR[0xB408])) +#define MCF_USB_DRAMDR (*(volatile uint32_t*)(&__MBAR[0xB40C])) +#define MCF_USB_USBISR (*(volatile uint32_t*)(&__MBAR[0xB410])) +#define MCF_USB_USBIMR (*(volatile uint32_t*)(&__MBAR[0xB414])) +#define MCF_USB_EP0STAT (*(volatile uint32_t*)(&__MBAR[0xB440])) +#define MCF_USB_EP0ISR (*(volatile uint32_t*)(&__MBAR[0xB444])) +#define MCF_USB_EP0IMR (*(volatile uint32_t*)(&__MBAR[0xB448])) +#define MCF_USB_EP0FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB44C])) +#define MCF_USB_EP0FDR (*(volatile uint32_t*)(&__MBAR[0xB450])) +#define MCF_USB_EP0FSR (*(volatile uint32_t*)(&__MBAR[0xB454])) +#define MCF_USB_EP0FCR (*(volatile uint32_t*)(&__MBAR[0xB458])) +#define MCF_USB_EP0FAR (*(volatile uint32_t*)(&__MBAR[0xB45C])) +#define MCF_USB_EP0FRP (*(volatile uint32_t*)(&__MBAR[0xB460])) +#define MCF_USB_EP0FWP (*(volatile uint32_t*)(&__MBAR[0xB464])) +#define MCF_USB_EP0LRFP (*(volatile uint32_t*)(&__MBAR[0xB468])) +#define MCF_USB_EP0LWFP (*(volatile uint32_t*)(&__MBAR[0xB46C])) +#define MCF_USB_EP1STAT (*(volatile uint32_t*)(&__MBAR[0xB470])) +#define MCF_USB_EP1ISR (*(volatile uint32_t*)(&__MBAR[0xB474])) +#define MCF_USB_EP1IMR (*(volatile uint32_t*)(&__MBAR[0xB478])) +#define MCF_USB_EP1FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB47C])) +#define MCF_USB_EP1FDR (*(volatile uint32_t*)(&__MBAR[0xB480])) +#define MCF_USB_EP1FSR (*(volatile uint32_t*)(&__MBAR[0xB484])) +#define MCF_USB_EP1FCR (*(volatile uint32_t*)(&__MBAR[0xB488])) +#define MCF_USB_EP1FAR (*(volatile uint32_t*)(&__MBAR[0xB48C])) +#define MCF_USB_EP1FRP (*(volatile uint32_t*)(&__MBAR[0xB490])) +#define MCF_USB_EP1FWP (*(volatile uint32_t*)(&__MBAR[0xB494])) +#define MCF_USB_EP1LRFP (*(volatile uint32_t*)(&__MBAR[0xB498])) +#define MCF_USB_EP1LWFP (*(volatile uint32_t*)(&__MBAR[0xB49C])) +#define MCF_USB_EP2STAT (*(volatile uint32_t*)(&__MBAR[0xB4A0])) +#define MCF_USB_EP2ISR (*(volatile uint32_t*)(&__MBAR[0xB4A4])) +#define MCF_USB_EP2IMR (*(volatile uint32_t*)(&__MBAR[0xB4A8])) +#define MCF_USB_EP2FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4AC])) +#define MCF_USB_EP2FDR (*(volatile uint32_t*)(&__MBAR[0xB4B0])) +#define MCF_USB_EP2FSR (*(volatile uint32_t*)(&__MBAR[0xB4B4])) +#define MCF_USB_EP2FCR (*(volatile uint32_t*)(&__MBAR[0xB4B8])) +#define MCF_USB_EP2FAR (*(volatile uint32_t*)(&__MBAR[0xB4BC])) +#define MCF_USB_EP2FRP (*(volatile uint32_t*)(&__MBAR[0xB4C0])) +#define MCF_USB_EP2FWP (*(volatile uint32_t*)(&__MBAR[0xB4C4])) +#define MCF_USB_EP2LRFP (*(volatile uint32_t*)(&__MBAR[0xB4C8])) +#define MCF_USB_EP2LWFP (*(volatile uint32_t*)(&__MBAR[0xB4CC])) +#define MCF_USB_EP3STAT (*(volatile uint32_t*)(&__MBAR[0xB4D0])) +#define MCF_USB_EP3ISR (*(volatile uint32_t*)(&__MBAR[0xB4D4])) +#define MCF_USB_EP3IMR (*(volatile uint32_t*)(&__MBAR[0xB4D8])) +#define MCF_USB_EP3FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4DC])) +#define MCF_USB_EP3FDR (*(volatile uint32_t*)(&__MBAR[0xB4E0])) +#define MCF_USB_EP3FSR (*(volatile uint32_t*)(&__MBAR[0xB4E4])) +#define MCF_USB_EP3FCR (*(volatile uint32_t*)(&__MBAR[0xB4E8])) +#define MCF_USB_EP3FAR (*(volatile uint32_t*)(&__MBAR[0xB4EC])) +#define MCF_USB_EP3FRP (*(volatile uint32_t*)(&__MBAR[0xB4F0])) +#define MCF_USB_EP3FWP (*(volatile uint32_t*)(&__MBAR[0xB4F4])) +#define MCF_USB_EP3LRFP (*(volatile uint32_t*)(&__MBAR[0xB4F8])) +#define MCF_USB_EP3LWFP (*(volatile uint32_t*)(&__MBAR[0xB4FC])) +#define MCF_USB_EP4STAT (*(volatile uint32_t*)(&__MBAR[0xB500])) +#define MCF_USB_EP4ISR (*(volatile uint32_t*)(&__MBAR[0xB504])) +#define MCF_USB_EP4IMR (*(volatile uint32_t*)(&__MBAR[0xB508])) +#define MCF_USB_EP4FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB50C])) +#define MCF_USB_EP4FDR (*(volatile uint32_t*)(&__MBAR[0xB510])) +#define MCF_USB_EP4FSR (*(volatile uint32_t*)(&__MBAR[0xB514])) +#define MCF_USB_EP4FCR (*(volatile uint32_t*)(&__MBAR[0xB518])) +#define MCF_USB_EP4FAR (*(volatile uint32_t*)(&__MBAR[0xB51C])) +#define MCF_USB_EP4FRP (*(volatile uint32_t*)(&__MBAR[0xB520])) +#define MCF_USB_EP4FWP (*(volatile uint32_t*)(&__MBAR[0xB524])) +#define MCF_USB_EP4LRFP (*(volatile uint32_t*)(&__MBAR[0xB528])) +#define MCF_USB_EP4LWFP (*(volatile uint32_t*)(&__MBAR[0xB52C])) +#define MCF_USB_EP5STAT (*(volatile uint32_t*)(&__MBAR[0xB530])) +#define MCF_USB_EP5ISR (*(volatile uint32_t*)(&__MBAR[0xB534])) +#define MCF_USB_EP5IMR (*(volatile uint32_t*)(&__MBAR[0xB538])) +#define MCF_USB_EP5FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB53C])) +#define MCF_USB_EP5FDR (*(volatile uint32_t*)(&__MBAR[0xB540])) +#define MCF_USB_EP5FSR (*(volatile uint32_t*)(&__MBAR[0xB544])) +#define MCF_USB_EP5FCR (*(volatile uint32_t*)(&__MBAR[0xB548])) +#define MCF_USB_EP5FAR (*(volatile uint32_t*)(&__MBAR[0xB54C])) +#define MCF_USB_EP5FRP (*(volatile uint32_t*)(&__MBAR[0xB550])) +#define MCF_USB_EP5FWP (*(volatile uint32_t*)(&__MBAR[0xB554])) +#define MCF_USB_EP5LRFP (*(volatile uint32_t*)(&__MBAR[0xB558])) +#define MCF_USB_EP5LWFP (*(volatile uint32_t*)(&__MBAR[0xB55C])) +#define MCF_USB_EP6STAT (*(volatile uint32_t*)(&__MBAR[0xB560])) +#define MCF_USB_EP6ISR (*(volatile uint32_t*)(&__MBAR[0xB564])) +#define MCF_USB_EP6IMR (*(volatile uint32_t*)(&__MBAR[0xB568])) +#define MCF_USB_EP6FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB56C])) +#define MCF_USB_EP6FDR (*(volatile uint32_t*)(&__MBAR[0xB570])) +#define MCF_USB_EP6FSR (*(volatile uint32_t*)(&__MBAR[0xB574])) +#define MCF_USB_EP6FCR (*(volatile uint32_t*)(&__MBAR[0xB578])) +#define MCF_USB_EP6FAR (*(volatile uint32_t*)(&__MBAR[0xB57C])) +#define MCF_USB_EP6FRP (*(volatile uint32_t*)(&__MBAR[0xB580])) +#define MCF_USB_EP6FWP (*(volatile uint32_t*)(&__MBAR[0xB584])) +#define MCF_USB_EP6LRFP (*(volatile uint32_t*)(&__MBAR[0xB588])) +#define MCF_USB_EP6LWFP (*(volatile uint32_t*)(&__MBAR[0xB58C])) +#define MCF_USB_IFR(x) (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)])) +#define MCF_USB_EPOUTACR(x) (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSR(x) (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)])) +#define MCF_USB_EPINACR(x) (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)])) +#define MCF_USB_EPINMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)])) +#define MCF_USB_EPINIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)])) +#define MCF_USB_EPINSR(x) (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)])) +#define MCF_USB_EPINSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)])) +#define MCF_USB_EPSTAT(x) (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)])) +#define MCF_USB_EPISR(x) (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)])) +#define MCF_USB_EPIMR(x) (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)])) +#define MCF_USB_EPFRCFGR(x) (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)])) +#define MCF_USB_EPFDR(x) (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)])) +#define MCF_USB_EPFSR(x) (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)])) +#define MCF_USB_EPFCR(x) (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)])) +#define MCF_USB_EPFAR(x) (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)])) +#define MCF_USB_EPFRP(x) (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)])) +#define MCF_USB_EPFWP(x) (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)])) +#define MCF_USB_EPLRFP(x) (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)])) +#define MCF_USB_EPLWFP(x) (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)])) /* Bit definitions and macros for MCF_USB_USBAISR */ diff --git a/BaS_GNU/include/MCF5475_XLB.h b/BaS_GNU/include/MCF5475_XLB.h index f13a20c..d995dd2 100644 --- a/BaS_GNU/include/MCF5475_XLB.h +++ b/BaS_GNU/include/MCF5475_XLB.h @@ -24,17 +24,17 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_XLB_XARB_CFG (*(vuint32*)(&__MBAR[0x240])) -#define MCF_XLB_XARB_VER (*(vuint32*)(&__MBAR[0x244])) -#define MCF_XLB_XARB_SR (*(vuint32*)(&__MBAR[0x248])) -#define MCF_XLB_XARB_IMR (*(vuint32*)(&__MBAR[0x24C])) -#define MCF_XLB_XARB_ADRCAP (*(vuint32*)(&__MBAR[0x250])) -#define MCF_XLB_XARB_SIGCAP (*(vuint32*)(&__MBAR[0x254])) -#define MCF_XLB_XARB_ADRTO (*(vuint32*)(&__MBAR[0x258])) -#define MCF_XLB_XARB_DATTO (*(vuint32*)(&__MBAR[0x25C])) -#define MCF_XLB_XARB_BUSTO (*(vuint32*)(&__MBAR[0x260])) -#define MCF_XLB_XARB_PRIEN (*(vuint32*)(&__MBAR[0x264])) -#define MCF_XLB_XARB_PRI (*(vuint32*)(&__MBAR[0x268])) +#define MCF_XLB_XARB_CFG (*(volatile uint32_t*)(&__MBAR[0x240])) +#define MCF_XLB_XARB_VER (*(volatile uint32_t*)(&__MBAR[0x244])) +#define MCF_XLB_XARB_SR (*(volatile uint32_t*)(&__MBAR[0x248])) +#define MCF_XLB_XARB_IMR (*(volatile uint32_t*)(&__MBAR[0x24C])) +#define MCF_XLB_XARB_ADRCAP (*(volatile uint32_t*)(&__MBAR[0x250])) +#define MCF_XLB_XARB_SIGCAP (*(volatile uint32_t*)(&__MBAR[0x254])) +#define MCF_XLB_XARB_ADRTO (*(volatile uint32_t*)(&__MBAR[0x258])) +#define MCF_XLB_XARB_DATTO (*(volatile uint32_t*)(&__MBAR[0x25C])) +#define MCF_XLB_XARB_BUSTO (*(volatile uint32_t*)(&__MBAR[0x260])) +#define MCF_XLB_XARB_PRIEN (*(volatile uint32_t*)(&__MBAR[0x264])) +#define MCF_XLB_XARB_PRI (*(volatile uint32_t*)(&__MBAR[0x268])) /* Bit definitions and macros for MCF_XLB_XARB_CFG */ diff --git a/BaS_GNU/lcf/DDRAM.lcf b/BaS_GNU/lcf/DDRAM.lcf new file mode 100644 index 0000000..795732d --- /dev/null +++ b/BaS_GNU/lcf/DDRAM.lcf @@ -0,0 +1,88 @@ +# Sample Linker Command File for CodeWarrior for ColdFire + +KEEP_SECTION {.vectortable} + +# Memory ranges + +MEMORY { + code (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0 +} + +SECTIONS { + +#BaS Basis adresse + ___Bas_base = 0x1FE00000; + +# Board Memory map definitions from linker command files: +# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE +# linker symbols must be defined in the linker command file. + +#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) + ___BOOT_FLASH = 0xE0000000; + ___BOOT_FLASH_SIZE = 0x00800000; +#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes + ___SDRAM = 0x00000000; + ___SDRAM_SIZE = 0x20000000; + +#VIDEO RAM BASIS + ___VRAM = 0x60000000; + +# MCF5475 Derivative Memory map definitions from linker command files: +# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE +# linker symbols must be defined in the linker command file. + +# Memory mapped registers + ___MBAR = 0xFF000000; + ___MMUBAR = 0xFF040000; +# 4KB on-chip Core SRAM0: -> exception table and exception stack + ___RAMBAR0 = 0xFF100000; + ___RAMBAR0_SIZE = 0x00001000; + + ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4; + +# 4KB on-chip Core SRAM1: -> modified code + ___RAMBAR1 = 0xFF101000; + ___RAMBAR1_SIZE = 0x00001000; + +# Systemveriablem:****************************************** +# RAMBAR0 0 bis 0x7FF -> exception vectoren +_rt_mod = ___RAMBAR0 + 0x800; +_rt_ssp = ___RAMBAR0 + 0x804; +_rt_usp = ___RAMBAR0 + 0x808; +_rt_vbr = ___RAMBAR0 + 0x80C; # (8)01 +_rt_cacr = ___RAMBAR0 + 0x810; # 002 +_rt_asid = ___RAMBAR0 + 0x814; # 003 +_rt_acr0 = ___RAMBAR0 + 0x818; # 004 +_rt_acr1 = ___RAMBAR0 + 0x81c; # 005 +_rt_acr2 = ___RAMBAR0 + 0x820; # 006 +_rt_acr3 = ___RAMBAR0 + 0x824; # 007 +_rt_mmubar = ___RAMBAR0 + 0x828; # 008 +_rt_sr = ___RAMBAR0 + 0x82c; +_d0_save = ___RAMBAR0 + 0x830; +_a7_save = ___RAMBAR0 + 0x834; +_video_tlb = ___RAMBAR0 + 0x838; +_video_sbt = ___RAMBAR0 + 0x83C; +_rt_mbar = ___RAMBAR0 + 0x844; # (c)0f +#*********************************************************** + +# 32KB on-chip System SRAM + ___SYS_SRAM = 0xFF010000; + ___SYS_SRAM_SIZE = 0x00008000; + + + .text : + { + startcf.c(.text) + sysinit.c(.text) + BaS.c(.text) + sd_card.c(.text) + mmu.s(.text) + exceptions.s(.text) + supervisor.s(.text) + ewf.s(.text) + illegal_instruction.s(.text) + last.c(.text) + . = ALIGN (0x4); + } > code + +} \ No newline at end of file diff --git a/BaS_GNU/lcf/FLASH.lcf b/BaS_GNU/lcf/FLASH.lcf new file mode 100644 index 0000000..0315e2f --- /dev/null +++ b/BaS_GNU/lcf/FLASH.lcf @@ -0,0 +1,88 @@ +# Sample Linker Command File for CodeWarrior for ColdFire + +KEEP_SECTION {.vectortable} + +# Memory ranges + +MEMORY { + code (RX) : ORIGIN = 0xE0000000, LENGTH = 0x00200000 +} + +SECTIONS { + +#BaS Basis adresse + ___Bas_base = 0x1FE00000; + +# Board Memory map definitions from linker command files: +# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE +# linker symbols must be defined in the linker command file. + +#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) + ___BOOT_FLASH = 0xE0000000; + ___BOOT_FLASH_SIZE = 0x00800000; +#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes + ___SDRAM = 0x00000000; + ___SDRAM_SIZE = 0x20000000; + +#VIDEO RAM BASIS + ___VRAM = 0x60000000; + +# MCF5475 Derivative Memory map definitions from linker command files: +# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE +# linker symbols must be defined in the linker command file. + +# Memory mapped registers + ___MBAR = 0xFF000000; + ___MMUBAR = 0xFF040000; +# 4KB on-chip Core SRAM0: -> exception table and exception stack + ___RAMBAR0 = 0xFF100000; + ___RAMBAR0_SIZE = 0x00001000; + + ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4; + +# 4KB on-chip Core SRAM1: -> modified code + ___RAMBAR1 = 0xFF101000; + ___RAMBAR1_SIZE = 0x00001000; + +# Systemveriablem:****************************************** +# RAMBAR0 0 bis 0x7FF -> exception vectoren +_rt_mod = ___RAMBAR0 + 0x800; +_rt_ssp = ___RAMBAR0 + 0x804; +_rt_usp = ___RAMBAR0 + 0x808; +_rt_vbr = ___RAMBAR0 + 0x80C; # (8)01 +_rt_cacr = ___RAMBAR0 + 0x810; # 002 +_rt_asid = ___RAMBAR0 + 0x814; # 003 +_rt_acr0 = ___RAMBAR0 + 0x818; # 004 +_rt_acr1 = ___RAMBAR0 + 0x81c; # 005 +_rt_acr2 = ___RAMBAR0 + 0x820; # 006 +_rt_acr3 = ___RAMBAR0 + 0x824; # 007 +_rt_mmubar = ___RAMBAR0 + 0x828; # 008 +_rt_sr = ___RAMBAR0 + 0x82c; +_d0_save = ___RAMBAR0 + 0x830; +_a7_save = ___RAMBAR0 + 0x834; +_video_tlb = ___RAMBAR0 + 0x838; +_video_sbt = ___RAMBAR0 + 0x83C; +_rt_mbar = ___RAMBAR0 + 0x844; # (c)0f +#*********************************************************** + +# 32KB on-chip System SRAM + ___SYS_SRAM = 0xFF010000; + ___SYS_SRAM_SIZE = 0x00008000; + + .code : {} > code + + .text : + { + startcf.c(.text) + sysinit.c(.text) + BaS.c(.text) + sd_card.c(.text) + mmu.s(.text) + exceptions.s(.text) + supervisor.s(.text) + ewf.s(.text) + illegal_instruction.s(.text) + last.c(.text) + } >> code + +} \ No newline at end of file diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 7e9a2cf..d60feb0 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -203,7 +203,7 @@ void BaS(void) /* TT-RAM */ - * (uint32_t *) 0x5a4 = __Bas_base; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a4 = (uint32_t *) __Bas_base; /* ramtop TOS system variable */ * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ /* init ACIA */ diff --git a/BaS_GNU/sources/sd_card.c b/BaS_GNU/sources/sd_card.c index 2fd7bb0..b3c9453 100644 --- a/BaS_GNU/sources/sd_card.c +++ b/BaS_GNU/sources/sd_card.c @@ -3,64 +3,59 @@ */ #include +#include -#define dspi_dtar0 0x0c -#define dspi_dsr 0x2c -#define dspi_dtfr 0x34 -#define dspi_drfr 0x38 -#define time1us 1320 +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 +#define time1us 1320 extern void wait_10ms(void); -void sd_com(void) // byt senden und holen --------------------- +uint8_t sd_com(uint32_t cmd) { + uint8_t res; - asm - { + MCF_DSPI_DTFR = cmd; + while (! MCF_DSPI_DSR & (1 << 7)); - move.l d4,dspi_dtfr(a0) -wait_auf_complett: - btst.b #7,dspi_dsr(a0) - beq wait_auf_complett - move.l dspi_drfr(a0),d5 - mov3q.l #-1,dspi_dsr(a0) // clr status register - } + res = MCF_DSPI_DRFR; + MCF_DSPI_DSR = -1L; + + return res; } -void sd_get_status(void) // status holen ------------------------------- +/* + * fetch status from SD controller + */ +uint8_t sd_get_status(void) { - asm - { -sd_get_status: - move.b #0xff,d4 - bsr sd_com - cmp.b #0xff,d5 - beq sd_get_status - } + uint8_t res; + + while ((res = sd_com(0xff)) == 0xff); + + return res; } -void sd_rcv_info(void) // daten holen ---------------------------- +void sd_rcv_info(uint8_t *buf, uint32_t size) { - asm - { - moveq #18,d3 // 16 byts + 2 byts crc - move.b #0xff,d4 -sd_rcv_rb_w: - bsr sd_get_status - cmp.b #0xfe,d5 // daten bereit? - bne sd_rcv_rb_w // nein-> -sd_rcv_rd_rb: - bsr sd_com - move.b d5,(a2)+ - subq.l #1,d3 - bne sd_rcv_rd_rb - } + uint32_t rcvd = 0; + + while (sd_get_status() != 0xfe); /* loop until data available */ + + do { + *buf++ = sd_com(0x18); + rcvd++; + } while (rcvd <= size); } + void sd_card_idle(void) { +#ifdef _NOT_USED_ asm { // sd idle @@ -85,8 +80,11 @@ void sd_card_idle(void) move.b #0x95,d4 bsr sd_com } +#endif } +#ifdef _NOT_USED_ + int sd_card_init(void) { @@ -591,3 +589,4 @@ sd_csw_ok: } return status; } +#endif /* _NOT_USED */ diff --git a/BaS_GNU/sources/sd_ide.c b/BaS_GNU/sources/sd_ide.c index 092f95e..7068a26 100644 --- a/BaS_GNU/sources/sd_ide.c +++ b/BaS_GNU/sources/sd_ide.c @@ -3,10 +3,10 @@ #include "MCF5475.h" #include "startcf.h" -extern unsigned long far __SP_AFTER_RESET[]; -extern unsigned long far __Bas_base[]; +extern unsigned long __SP_AFTER_RESET[]; +extern unsigned long __Bas_base[]; - /* imported routines */ +/* imported routines */ //extern int warten_20ms(); //extern int warten_200us(); //extern int warten_10us(); @@ -112,7 +112,7 @@ wait_of_aktiv: sd_init_ok: -// blockgrösse 512byt +// blockgr�sse 512byt sd_bg: bsr sd_16clk moveq #0x50,d4 @@ -451,7 +451,7 @@ ide_test_loop3: bsr drq_wait bsr ds_tx bsr wait_int -// fertig und zurück +// fertig und zur�ck nop rts // wait auf int diff --git a/BaS_GNU/sources/startcf.S b/BaS_GNU/sources/startcf.c similarity index 78% rename from BaS_GNU/sources/startcf.S rename to BaS_GNU/sources/startcf.c index 415f103..9376197 100644 --- a/BaS_GNU/sources/startcf.S +++ b/BaS_GNU/sources/startcf.c @@ -16,37 +16,31 @@ * main it will call C++ destructors and call exit to terminate. */ -#ifdef __cplusplus -#pragma cplusplus off -#endif -#pragma PID off -#pragma PIC off - #include +/* imported data */ - /* imported data */ +extern uint32_t _SP_INIT, _SDA_BASE; +extern uint32_t _START_BSS, _END_BSS; +extern uint32_t _START_SBSS, _END_SBSS; +extern uint32_t __DATA_RAM, __DATA_ROM, __DATA_END; +extern uint32_t __Bas_base; -extern unsigned long far _SP_INIT, _SDA_BASE; -extern unsigned long far _START_BSS, _END_BSS; -extern unsigned long far _START_SBSS, _END_SBSS; -extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END; -extern unsigned long far __Bas_base; +extern uint32_t __SUP_SP,__BOOT_FLASH; +extern uint32_t rt_mbar; -extern unsigned long far __SUP_SP,__BOOT_FLASH; -extern unsigned long far rt_mbar; - - /* imported routines */ +/* imported routines */ extern int BaS(int, char **); - /* exported routines */ +/* exported routines */ extern void __initialize_hardware(void); extern void init_slt(void); void _startup(void) { +#ifdef _NOT_USED_ asm("\n\t" "bra warmstart\n\t" "jmp __BOOT_FLASH + 8 // ist zugleich reset vector\n\t" @@ -79,4 +73,5 @@ void _startup(void) // initialize any hardware specific issues bra __initialize_hardware "); +#endif /* _NOT_USED_ */ } diff --git a/BaS_GNU/sources/startcf.h b/BaS_GNU/sources/startcf.h index c538f16..0fe3808 100644 --- a/BaS_GNU/sources/startcf.h +++ b/BaS_GNU/sources/startcf.h @@ -40,7 +40,7 @@ #define halten_movep #define halten_ewf -#define DIP_SWITCH (*(vuint8 *)(&__MBAR[0xA2C])) +#define DIP_SWITCH (*(volatile uint8_t *)(&__MBAR[0xA2C])) #define DIP_SWITCHa ___MBAR + 0xA2C #define sca_page_ID 6 diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index e1e70a7..10ae0e2 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -237,7 +237,7 @@ void init_fpga(void) /* * excerpt from an Altera configuration manual: * The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The - * configuration cycle consists of 3 stagesÑreset, configuration, and initialization. + * configuration cycle consists of 3 stages�reset, configuration, and initialization. * While nCONFIG is low, the device is in reset. When the device comes out of reset, * nCONFIG must be at a logic high level in order for the device to release the open-drain * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA @@ -527,8 +527,8 @@ void test_upd720101(void) * TFP410 (vdi) einschalten /* */ void vdi_on(void) { - uint8 RBYT; - uint8 DBYT; + uint8_t RBYT; + uint8_t DBYT; int versuche; int startzeit; From d84a7694f65cd1b98bceb7bf0fe579f69c95aff3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 15:58:32 +0000 Subject: [PATCH 032/276] removed emulator (?) files --- BaS_GNU/sources/ii_add.h | 581 ---------------- BaS_GNU/sources/ii_and.h | 441 ------------- BaS_GNU/sources/ii_dbcc.h | 117 ---- BaS_GNU/sources/ii_ewf.h | 181 ----- BaS_GNU/sources/ii_exg.h | 120 ---- BaS_GNU/sources/ii_func.h | 945 --------------------------- BaS_GNU/sources/ii_jmp.h | 59 -- BaS_GNU/sources/ii_lea.h | 105 --- BaS_GNU/sources/ii_macro.h | 144 ---- BaS_GNU/sources/ii_move.h | 1271 ------------------------------------ BaS_GNU/sources/ii_movem.h | 374 ----------- BaS_GNU/sources/ii_movep.h | 179 ----- BaS_GNU/sources/ii_op.h | 661 ------------------- BaS_GNU/sources/ii_opc.h | 263 -------- BaS_GNU/sources/ii_or.h | 442 ------------- BaS_GNU/sources/ii_pea.h | 74 --- BaS_GNU/sources/ii_shd.h | 247 ------- BaS_GNU/sources/ii_shift.h | 687 ------------------- BaS_GNU/sources/ii_sub.h | 584 ----------------- 19 files changed, 7475 deletions(-) delete mode 100644 BaS_GNU/sources/ii_add.h delete mode 100644 BaS_GNU/sources/ii_and.h delete mode 100644 BaS_GNU/sources/ii_dbcc.h delete mode 100644 BaS_GNU/sources/ii_ewf.h delete mode 100644 BaS_GNU/sources/ii_exg.h delete mode 100644 BaS_GNU/sources/ii_func.h delete mode 100644 BaS_GNU/sources/ii_jmp.h delete mode 100644 BaS_GNU/sources/ii_lea.h delete mode 100644 BaS_GNU/sources/ii_macro.h delete mode 100644 BaS_GNU/sources/ii_move.h delete mode 100644 BaS_GNU/sources/ii_movem.h delete mode 100644 BaS_GNU/sources/ii_movep.h delete mode 100644 BaS_GNU/sources/ii_op.h delete mode 100644 BaS_GNU/sources/ii_opc.h delete mode 100644 BaS_GNU/sources/ii_or.h delete mode 100644 BaS_GNU/sources/ii_pea.h delete mode 100644 BaS_GNU/sources/ii_shd.h delete mode 100644 BaS_GNU/sources/ii_shift.h delete mode 100644 BaS_GNU/sources/ii_sub.h diff --git a/BaS_GNU/sources/ii_add.h b/BaS_GNU/sources/ii_add.h deleted file mode 100644 index bc23f63..0000000 --- a/BaS_GNU/sources/ii_add.h +++ /dev/null @@ -1,581 +0,0 @@ -//-------------------------------------------------------------------- -// add -//-------------------------------------------------------------------- -/*****************************************************************************************/ -//-------------------------------------------------------------------- -// byt -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// add.b #im,dx -//-------------------------------------------------------------------- -addbir_macro:.macro - move.w (a0)+,d0 - extb.l d0 - mvs.b \2,d1 - add.l d0,d1 - set_cc0 - move.b d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add ea,dx -//-------------------------------------------------------------------- -adddd:.macro -#ifdef halten_add - halt -#endif - mvs.\3 \1,d0 - mvs.\3 \2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add ea,dx (first ea->a1 z.B. für a0,a1,USP) -//-------------------------------------------------------------------- -addddd:.macro -#ifdef halten_add - halt -#endif - move.l \1,a1 - mvs.\3 a1,d0 - mvs.\3 \2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add (ea),dx (first ea->a1 z.B. für a0,a1,USP) -//-------------------------------------------------------------------- -adddda:.macro -#ifdef halten_add - halt -#endif - move.l \1,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add (ay)+,dx (first ea->a1 z.B. für a0,a1,USP) -//-------------------------------------------------------------------- -addddai:.macro -#ifdef halten_add - halt -#endif - move.l \1,a1 - mvs.\3 (a1)+,d0 - move.l a1,\1 - mvs.\3 \2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add -(ay),dx (first ea->a1 z.B. für a0,a1,USP) -//-------------------------------------------------------------------- -addddad:.macro -#ifdef halten_add - halt -#endif - move.l \1,a1 - mvs.\3 -(a1),d0 - move.l a1,\1 - mvs.\3 \2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add d16(ay),dx -//-------------------------------------------------------------------- -addd16ad:.macro -#ifdef halten_add - halt -#endif - move.l \1,a1 - mvs.w (a0)+,d0 - add.l d0,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add d8(ay,dy),dx -//-------------------------------------------------------------------- -addd8ad:.macro -#ifdef halten_add - halt -#endif - move.l \1,a1 - jsr ewf -.ifc \3,l - move.l (a1),d0 - move.l \2,d1 -.else - mvs.\3 (a1),d0 - mvs.\3 \2,d1 -.endif - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add xxx.w,dx -//-------------------------------------------------------------------- -addxwd:.macro -#ifdef halten_add - halt -#endif - move.w (a0)+,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add xxx.l,dx -//-------------------------------------------------------------------- -addxld:.macro -#ifdef halten_add - halt -#endif - move.l (a0)+,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add d16(pc),dx -//-------------------------------------------------------------------- -addd16pcd:.macro -#ifdef halten_add - halt -#endif - move.l a0,a1 - mvs.w (a0)+,d0 - add.l d0,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add d8(pc,dy),dx -//-------------------------------------------------------------------- -addd8pcd:.macro -#ifdef halten_add - halt -#endif - move.l a0,a1 - jsr ewf -.ifc \3,l - move.l (a1),d0 - move.l \2,d1 -.else - mvs.\3 (a1),d0 - mvs.\3 \2,d1 -.endif - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// add dy,ea -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// // add dx,(ay) (first ea->a1 z.B. für a0,a1,USP) -//-------------------------------------------------------------------- -addeda:.macro -#ifdef halten_add - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 (a1),d1 - add.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // add dx,(ay)+ (first ea->a1 z.B. für a0,a1,USP) -//-------------------------------------------------------------------- -addedai:.macro -#ifdef halten_add - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 (a1),d1 - add.l d0,d1 - set_cc0 - move.\3 d1,(a1)+ - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add dx,(ay)+ -//-------------------------------------------------------------------- -addedaid:.macro -#ifdef halten_add - halt -#endif - mvs.\3 \1,d0 - mvs.\3 \2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2+ - ii_end - .endm; -//-------------------------------------------------------------------- -// // add dx,-(ay) -//-------------------------------------------------------------------- -addedad:.macro -#ifdef halten_add - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 -(a1),d1 - move.l a1,\2 - add.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // add dx,-(ay) -//-------------------------------------------------------------------- -addedadd:.macro -#ifdef halten_add - halt -#endif - mvs.\3 \1,d0 - mvs.\3 -\2,d1 - add.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // add dx,d16(ay) -//-------------------------------------------------------------------- -adde16ad:.macro -#ifdef halten_add - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - mvs.\3 (a1),d1 - add.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // add.w d8(ay,dy),dx -//-------------------------------------------------------------------- -adde8ad:.macro -#ifdef halten_add - halt -#endif - move.l \2,a1 - jsr ewf -.ifc \3,l - move.l (a1),d1 - move.l \1,d0 -.else - mvs.\3 (a1),d1 - mvs.\3 \1,d0 -.endif - add.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // add dx,xxx.w -//-------------------------------------------------------------------- -addxwe:.macro -#ifdef halten_add - halt -#endif - mvs.\3 \1,d0 - move.w (a0)+,a1 - mvs.\3 (a1),d1 - add.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // add dx,xxx.l -//-------------------------------------------------------------------- -addxle:.macro -#ifdef halten_add - halt -#endif - mvs.\3 \1,d0 - move.l (a0)+,a1 - mvs.\3 (a1),d1 - add.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -/******************************************************/ -// adress register -/******************************************************/ -//-------------------------------------------------------------------- -// // adda.w ea,ax (ea = dx;ax;(ax);(ax)+,-(ax) -//-------------------------------------------------------------------- -addaw:.macro -#ifdef halten_add - halt -#endif - move.l a0,pc_off(a7) // pc auf next - movem.l (a7),d0/d1/a0/a1 // register zurpück - mvs.w \1,d0 - adda.l d0,\2 - move.l d0_off(a7),d0 - lea ii_ss(a7),a7 // stack erhöhen - rte - .endm; -//-------------------------------------------------------------------- -// add.w ea,usp -//-------------------------------------------------------------------- -addawa7:.macro -#ifdef halten_add - halt -#endif - mvs.w \1,d0 - move.l usp,a1 - add.l d0,a1 - move.l a1,usp - ii_end - .endm; -//-------------------------------------------------------------------- -// // adda.w ea,usp (ea = dx;ax;(ax);(ax)+,-(ax) -//-------------------------------------------------------------------- -addawu:.macro -#ifdef halten_add - halt -#endif - move.l a0,pc_off(a7) // pc auf next - movem.l (a7),d0/d1/a0/a1 // register zurpück - move.l a7,_a7_save - move.l usp,a7 - move.l \1,d0 - adda.l d0,\2 - move.l a7,usp - move.l _a7_save,a7 - move.l d0_off(a7),d0 - lea ii_ss(a7),a7 // stack erhöhen - rte - .endm; -//-------------------------------------------------------------------- -// // adda.w ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax) -//-------------------------------------------------------------------- -addawua7:.macro - addawu \1,\2 - .endm; -//-------------------------------------------------------------------- -// // adda.w d16(ay),ax -//-------------------------------------------------------------------- -addawd16a:.macro -#ifdef halten_add - halt -#endif - move.l \1,a1 - mvs.w (a0)+,d0 - adda.l d0,a1 - mvs.w (a1),d0 - move.l \2,a1 - add.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // adda.w d8(ay,dy),ax -//-------------------------------------------------------------------- -addawd8a:.macro -#ifdef halten_add - halt -#endif - move.l \1,a1 - jsr ewf - mvs.w (a1),d0 - move.l \2,a1 - add.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // adda.w xxx.w,ax -//-------------------------------------------------------------------- -addawxwax:.macro -#ifdef halten_add - halt -#endif - move.w \1,a1 - mvs.w (a1),d0 - move.l \2,a1 - adda.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // adda.w xxx.l,ax -//-------------------------------------------------------------------- -addawxlax:.macro -#ifdef halten_add - halt -#endif - move.l \1,a1 - mvs.w (a1),d0 - move.l \2,a1 - adda.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // adda.w d16(pc),ax -//-------------------------------------------------------------------- -addawd16pcax:.macro -#ifdef halten_add - halt -#endif - move.w \1,a1 - adda.l a0,a1 - mvs.w (a1),d0 - move.l \2,a1 - adda.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // adda.w d8(pc,dy),ax -//-------------------------------------------------------------------- -addawd8pcax:.macro -#ifdef halten_add - halt -#endif - move.l a0,a1 - jsr ewf - mvs.w (a1),d0 - move.l \2,a1 - adda.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // adda.w #im,ax -//-------------------------------------------------------------------- -addawim:.macro -#ifdef halten_add - halt -#endif - mvs.w \1,d0 - move.l \2,a1 - adda.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // adda.l d8(ay,dy),ax -//-------------------------------------------------------------------- -addald8a:.macro -#ifdef halten_add - halt -#endif - move.l \1,a1 - jsr ewf - move.l (a1),d0 - move.l \2,a1 - adda.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // adda.l d8(pc,dy),ax -//-------------------------------------------------------------------- -addakd8pcax:.macro -#ifdef halten_add - halt -#endif - move.l a0,a1 - jsr ewf - move.l (a1),d0 - move.l \2,a1 - adda.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//***************************************************************************************** -// addx -//***************************************************************************************** -//-------------------------------------------------------------------- -// // addx dy,dx -//-------------------------------------------------------------------- -adddx:.macro -#ifdef halten_add - halt -#endif - move.b sr_off+1(a7),d0 //ccr holen - move d0,ccr //setzen - mvs.\3 \2,d0 - mvs.\3 \1,d1 - addx.l d0,d1 - set_cc0 - move.\3 d1,\1 - ii_end - .endm; -//-------------------------------------------------------------------- -// // addx -(ay),-(ax) -//-------------------------------------------------------------------- -adddax:.macro -#ifdef halten_add - halt -#endif - move.b sr_off+1(a7),d0 //ccr holen - move d0,ccr //setzen - move.l \1,a1 -.ifc \3,l - move.l -(a1),d0 -.else - mvs.\3 -(a1),d0 -.endif - move.l \2,a1 -.ifc \3,l - move.l -(a1),d0 -.else - mvs.\3 -(a1),d1 -.endif - addx.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_and.h b/BaS_GNU/sources/ii_and.h deleted file mode 100644 index f74afde..0000000 --- a/BaS_GNU/sources/ii_and.h +++ /dev/null @@ -1,441 +0,0 @@ -//-------------------------------------------------------------------- -// and -//-------------------------------------------------------------------- -/*****************************************************************************************/ -//-------------------------------------------------------------------- -// byt -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// and.b #im,dx -//-------------------------------------------------------------------- -andbir_macro:.macro - move.w (a0)+,d0 - extb.l d0 - mvs.b \2,d1 - and.l d0,d1 - set_cc0 - move.b d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and ea,dx -//-------------------------------------------------------------------- -anddd:.macro -#ifdef halten_and - halt -#endif - mvs.\3 \1,d0 - mvs.\3 \2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and ea(l)->dy(w),dx z.B. für USP -//-------------------------------------------------------------------- -andddd:.macro -#ifdef halten_and - halt -#endif - move.l \1,a1 - mvs.\3 a1,d0 - mvs.\3 \2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and (ea)->dy,dx -//-------------------------------------------------------------------- -anddda:.macro -#ifdef halten_and - halt -#endif - move.l \1,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and ea->ay,(ay)+,dx -//-------------------------------------------------------------------- -andddai:.macro -#ifdef halten_and - halt -#endif - move.l \1,a1 - mvs.\3 (a1)+,d0 - move.l a1,\1 - mvs.\3 \2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and ea->ay,-(ay),dx -//-------------------------------------------------------------------- -andddad:.macro -#ifdef halten_and - halt -#endif - move.l \1,a1 - mvs.\3 -(a1),d0 - move.l a1,\1 - mvs.\3 \2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and d16(ay),dx -//-------------------------------------------------------------------- -andd16ad:.macro -#ifdef halten_and - halt -#endif - move.l \1,a1 - mvs.w (a0)+,d0 - add.l d0,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and d8(ay,dy),dx -//-------------------------------------------------------------------- -andd8ad:.macro -#ifdef halten_and - halt -#endif - move.l \1,a1 - jsr ewf -.ifc \3,l - move.l (a1),d0 - move.l \2,d1 -.else - mvs.\3 (a1),d0 - mvs.\3 \2,d1 -.endif - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and xxx.w,dx -//-------------------------------------------------------------------- -andxwd:.macro -#ifdef halten_and - halt -#endif - move.w (a0)+,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and xxx.l,dx -//-------------------------------------------------------------------- -andxld:.macro -#ifdef halten_and - halt -#endif - move.l (a0)+,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and d16(pc),dx -//-------------------------------------------------------------------- -andd16pcd:.macro -#ifdef halten_and - halt -#endif - move.l a0,a1 - mvs.w (a0)+,d0 - add.l d0,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and d8(pc,dy),dx -//-------------------------------------------------------------------- -andd8pcd:.macro -#ifdef halten_and - halt -#endif - move.l a0,a1 - jsr ewf -.ifc \3,l - move.l (a1),d0 - move.l \2,d1 -.else - mvs.\3 (a1),d0 - mvs.\3 \2,d1 -.endif - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// and dx,ea -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// // and dx,(ea)->dy -//-------------------------------------------------------------------- -andeda:.macro -#ifdef halten_and - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 (a1),d1 - and.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // and dx,ea->ay,(ay)+ -//-------------------------------------------------------------------- -andedai:.macro -#ifdef halten_and - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 (a1),d1 - and.l d0,d1 - set_cc0 - move.\3 d1,(a1)+ - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and dx,ea->ay,(ay)+ -//-------------------------------------------------------------------- -andedaid:.macro -#ifdef halten_and - halt -#endif - mvs.\3 \1,d0 - mvs.\3 \2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2+ - ii_end - .endm; -//-------------------------------------------------------------------- -// // and dx,ea->ay,-(ay) -//-------------------------------------------------------------------- -andedad:.macro -#ifdef halten_and - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 -(a1),d1 - move.l a1,\2 - and.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // and dx,ea->ay,-(ay) -//-------------------------------------------------------------------- -andedadd:.macro -#ifdef halten_and - halt -#endif - mvs.\3 \1,d0 - mvs.\3 -\2,d1 - and.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // and dx,d16(ay) -//-------------------------------------------------------------------- -ande16ad:.macro -#ifdef halten_and - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - mvs.\3 (a1),d1 - and.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // and.w dx,d8(ay,dy) -//-------------------------------------------------------------------- -ande8ad:.macro -#ifdef halten_and - halt -#endif - move.l \2,a1 - jsr ewf -.ifc \3,l - move.l (a1),d1 - move.l \1,d0 -.else - mvs.\3 (a1),d1 - mvs.\3 \1,d0 -.endif - and.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // and dx,xxx.w -//-------------------------------------------------------------------- -andxwe:.macro -#ifdef halten_and - halt -#endif - mvs.\3 \1,d0 - move.w (a0)+,a1 - mvs.\3 (a1),d1 - and.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // and dx,xxx.l -//-------------------------------------------------------------------- -andxle:.macro -#ifdef halten_and - halt -#endif - mvs.\3 \1,d0 - move.l (a0)+,a1 - mvs.\3 (a1),d1 - and.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // anda.w ea,ax -//-------------------------------------------------------------------- -andaw:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// and.w ea,usp -//-------------------------------------------------------------------- -andawa7:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // anda.w usp?,ax -//-------------------------------------------------------------------- -andawu:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // anda.w usp?,usp -//-------------------------------------------------------------------- -andawua7:.macro - andawu \1,\2 - .endm; -//-------------------------------------------------------------------- -// // anda.w d16(ay),ax -//-------------------------------------------------------------------- -andawd16a:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // anda.w d8(ay,dy),ax -//-------------------------------------------------------------------- -andawd8a:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // anda.w xxx.w,ax -//-------------------------------------------------------------------- -andawxwax:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // anda.w xxx.l,ax -//-------------------------------------------------------------------- -andawxlax:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // anda.w d16(pc),ax -//-------------------------------------------------------------------- -andawd16pcax:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // anda.w d8(pc,dy),ax -//-------------------------------------------------------------------- -andawd8pcax:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // anda.w #im,ax -//-------------------------------------------------------------------- -andawim:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // anda.l d8(ay,dy),ax -//-------------------------------------------------------------------- -andald8a:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // anda.l d8(pc,dy),ax -//-------------------------------------------------------------------- -andald8pcax:.macro - jmp ii_error - .endm; -//***************************************************************************************** -// spezial addx subx etc. -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// // addx dy,dx -//-------------------------------------------------------------------- -anddx:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // addx -(ay),-(ax) -//-------------------------------------------------------------------- -anddax:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_dbcc.h b/BaS_GNU/sources/ii_dbcc.h deleted file mode 100644 index 652cdbe..0000000 --- a/BaS_GNU/sources/ii_dbcc.h +++ /dev/null @@ -1,117 +0,0 @@ -//-------------------------------------------------------------------- -// dbcc,trapcc -//-------------------------------------------------------------------- -.text -ii_lset_dbcc:.macro -// dbra - ii_lset_opeau 51,c - ii_lset_opeau 52,c - ii_lset_opeau 53,c - ii_lset_opeau 54,c - ii_lset_opeau 55,c - ii_lset_opeau 56,c - ii_lset_opeau 57,c - ii_lset_opeau 58,c - ii_lset_opeau 59,c - ii_lset_opeau 5a,c - ii_lset_opeau 5b,c - ii_lset_opeau 5c,c - ii_lset_opeau 5d,c - ii_lset_opeau 5e,c - ii_lset_opeau 5f,c -.endm - -ii_dbcc_func:.macro -ii_0x51c8: - dbra_macro d0_off+2(a7) -ii_0x51c9: - dbra_macro d1_off+2(a7) -ii_0x51ca: - dbra_macro d2 -ii_0x51cb: - dbra_macro d3 -ii_0x51cc: - dbra_macro d4 -ii_0x51cd: - dbra_macro d5 -ii_0x51ce: - dbra_macro d6 -ii_0x51cf: - dbra_macro d7 -//--------------------------------------------------------------------------------------------- -// dbcc dx -//--------------------------------------------------------------------------------------------- - ii_dbcc 2,hi - ii_dbcc 3,ls - ii_dbcc 4,cc - ii_dbcc 5,cs - ii_dbcc 6,ne - ii_dbcc 7,eq - ii_dbcc 8,vc - ii_dbcc 9,vs - ii_dbcc a,pl - ii_dbcc b,mi - ii_dbcc c,ge - ii_dbcc d,lt - ii_dbcc e,gt - ii_dbcc f,le -.endm -//--------------------------------------------------------------------------------------------- -// dbra dx -//--------------------------------------------------------------------------------------------- -dbra_macro:.macro -#ifdef halten_dbcc - halt -#endif - mvz.w \1,d1 // dx holen - subq.l #1,d1 // dx-1 - bcc dbra\@ // bra if plus? - addq.l #2,a0 // offset überspringen - move.w d1,\1 // dx sichern - ii_end -dbra\@: - move.w (a0),a1 // offset (wird auf long erweitert) - add.l a1,a0 // dazuadieren - move.w d1,\1 // dx sichern - ii_end -.endm -//--------------------------------------------------------------------------------------------- -// dbcc dx -//--------------------------------------------------------------------------------------------- -dbcc_macro:.macro -#ifdef halten_dbcc - halt -#endif - b\2 dbncc\@ - mvz.w \1,d1 // dx holen - subq.l #1,d1 // dx-1 - bcc dbcc\@ // bra if plus? -dbncc\@: - addq.l #2,a0 // offset überspringen - move.w d1,\1 // dx sichern - ii_end -dbcc\@: - move.w (a0),a1 // offset (wird auf long erweitert) - add.l a1,a0 // dazuadieren - move.w d1,\1 // dx sichern - ii_end -.endm -//db -ii_dbcc:.macro -ii_0x5\1c8: - dbcc_macro d0_off+2(a7),\2 -ii_0x5\1c9: - dbcc_macro d1_off+2(a7),\2 -ii_0x5\1ca: - dbcc_macro d2,\2 -ii_0x5\1cb: - dbcc_macro d3,\2 -ii_0x5\1cc: - dbcc_macro d4,\2 -ii_0x5\1cd: - dbcc_macro d5,\2 -ii_0x5\1ce: - dbcc_macro d6,\2 -ii_0x5\1cf: - dbcc_macro d7,\2 -.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_ewf.h b/BaS_GNU/sources/ii_ewf.h deleted file mode 100644 index 34d2483..0000000 --- a/BaS_GNU/sources/ii_ewf.h +++ /dev/null @@ -1,181 +0,0 @@ -//-------------------------------------------------------------------- -// extension word format missing -//-------------------------------------------------------------------- -.text -ii_ewf_lset:.macro -// pea - ii_lset_opeag 48,7 - ii_lset 0x487b -// jmp - ii_lset_opeag 4e,f - ii_lset 0x4efb -// jsr - ii_lset_opeag 4e,b - ii_lset 0x4ebb -// tas - ii_lset_opeag 4a,f - ii_lset 0x4ebb -// tst.b - ii_lset_opeag 4a,3 - ii_lset 0x4ebb -// tst.w - ii_lset_opeag 4a,7 - ii_lset 0x4ebb -// tst.l - ii_lset_opeag 4a,b - ii_lset 0x4ebb -// clr.b - ii_lset_opeag 42,3 - ii_lset 0x423b -// clr.w - ii_lset_opeag 42,7 - ii_lset 0x423b -// clr.l - ii_lset_opeag 42,b - ii_lset 0x423b -.endm -//--------------------------------------------------------------------------------------------- -ii_ewf_func:.macro - ewf_func_macro pea,487 - ewf_func_macro jmp,4ef - ewf_func_macro jsr,4eb - ewf_func_macro tas,4af - ewf_func_macro tstb,4a3 - ewf_func_macro tstw,4a7 - ewf_func_macro tstl,4ab - ewf_func_macro clrb,423 - ewf_func_macro clrw,427 - ewf_func_macro clrl,42b -.endm -//--------------------------------------------------------------------------------------------- -pea_macro:.macro - jsr ewf - move.l (a1),d0 - move.l usp,a1 - move.l d0,-(a1) - move.l a1,usp - ii_end -.endm - -jmp_macro:.macro - jsr ewf - move.l a1,a0 - ii_end -.endm - -jsr_macro:.macro - jsr ewf - move.l a1,d0 - move.l usp,a1 - move.l a0,-(a1) - move.l a1,usp - move.l d0,a0 - ii_end -.endm - -tas_macro:.macro - jsr ewf - tas (a1) - set_cc0 - ii_end -.endm - -tstb_macro:.macro - jsr ewf - tst.b (a1) - set_cc0 - ii_end -.endm - -tstw_macro:.macro - jsr ewf - tst.w (a1) - set_cc0 - ii_end -.endm - -tstl_macro:.macro - jsr ewf - tst.l (a1) - set_cc0 - ii_end -.endm - -clrb_macro:.macro - jsr ewf - clr.b (a1) - set_cc0 - ii_end -.endm - -clrw_macro:.macro - jsr ewf - clr.w (a1) - set_cc0 - ii_end -.endm - -clrl_macro:.macro - jsr ewf - clr.l (a1) - set_cc0 - ii_end -.endm -//-------------------------------------------------------------------- -ewf_func_macro:.macro //1=art 2=code -ii_0x\20: -#ifdef halten_ewf - halt -#endif - move.l a0_off(a7),a1 - \1_macro -ii_0x\21: -#ifdef halten_ewf - halt -#endif - move.l a1_off(a7),a1 - \1_macro -ii_0x\22: -#ifdef halten_ewf - halt -#endif - move.l a2,a1 - \1_macro -ii_0x\23: -#ifdef halten_ewf - halt -#endif - move.l a3,a1 - \1_macro -ii_0x\24: -#ifdef halten_ewf - halt -#endif - move.l a4,a1 - \1_macro -ii_0x\25: -#ifdef halten_ewf - halt -#endif - move.l a5,a1 - \1_macro -ii_0x\26: -#ifdef halten_ewf - halt -#endif - move.l a6,a1 - \1_macro -ii_0x\27: -#ifdef halten_ewf - halt -#endif - move.l usp,a1 - \1_macro -ii_0x\2b: -#ifdef halten_ewf - halt -#endif - move.l a0,a1 - \1_macro -.endm - diff --git a/BaS_GNU/sources/ii_exg.h b/BaS_GNU/sources/ii_exg.h deleted file mode 100644 index a0544af..0000000 --- a/BaS_GNU/sources/ii_exg.h +++ /dev/null @@ -1,120 +0,0 @@ -//-------------------------------------------------------------------- -// exg -//-------------------------------------------------------------------- -.text -ii_exg_lset:.macro -/* ii_lset_dxu c,40 //dx,d0 - ii_lset_dxu c,41 //dx,d1 - ii_lset_dxu c,42 //dx,d2 - ii_lset_dxu c,43 //dx,d3 - ii_lset_dxu c,44 //dx,d4 - ii_lset_dxu c,45 //dx,d5 - ii_lset_dxu c,46 //dx,d6 - ii_lset_dxu c,47 //dx,d7 - ii_lset_dxu c,48 //ax,a0 - ii_lset_dxu c,49 //ax,a1 - ii_lset_dxu c,4a //ax,a2 - ii_lset_dxu c,4b //ax,a3 - ii_lset_dxu c,4c //ax,a4 - ii_lset_dxu c,4d //ax,a5 - ii_lset_dxu c,4e //ax,a6 - ii_lset_dxu c,4f //ax,a7 */ -->setting by "and" - ii_lset_dxu c,88 //dx,a0 - ii_lset_dxu c,89 //dx,a1 - ii_lset_dxu c,8a //dx,a2 - ii_lset_dxu c,8b //dx,a3 - ii_lset_dxu c,8c //dx,a4 - ii_lset_dxu c,8d //dx,a5 - ii_lset_dxu c,8e //dx,a6 - ii_lset_dxu c,8f //dx,a7 -.endm -//--------------------------------------------------------------------------------------------- -ii_exg_func:.macro -// exg dx,dy - ii_exg_dx_dx 14,d0_off(a7) - ii_exg_dx_dx 34,d1_off(a7) - ii_exg_dx_dx 54,d2 - ii_exg_dx_dx 74,d3 - ii_exg_dx_dx 94,d4 - ii_exg_dx_dx b4,d5 - ii_exg_dx_dx d4,d6 - ii_exg_dx_dx f4,d7 -// exg ax,ay - ii_exg_to_ax 14,a0_off(a7) - ii_exg_to_ax 34,a1_off(a7) - ii_exg_to_ax 54,a2 - ii_exg_to_ax 74,a3 - ii_exg_to_ax 94,a4 - ii_exg_to_ax b4,a5 - ii_exg_to_ax d4,a6 - ii_exg_to_ax f4,usp -// exg dx,ay - ii_exg_to_ax 18,d0_off(a7) - ii_exg_to_ax 38,d1_off(a7) - ii_exg_to_ax 58,d2 - ii_exg_to_ax 78,d3 - ii_exg_to_ax 98,d4 - ii_exg_to_ax b8,d5 - ii_exg_to_ax d8,d6 - ii_exg_to_ax f8,d7 -.endm -//--------------------------------------------------------------------------------------------- -exg_macro:.macro -#ifdef halten_exg - halt -#endif - move.l \1,a1 -.ifc \2,usp - move.l a1,d0 - move.l \2,a1 - move.l a1,\1 - move.l d0,a1 -.else - .ifc \1,usp - move.l a1,d0 - move.l \2,a1 - move.l a1,\1 - move.l d0,a1 - .else - move.l \2,\1 - .endif -.endif - move.l a1,\2 - ii_end -.endm -ii_exg_dx_dx:.macro -ii_0xc\10: - exg_macro \2,d0_off(a7) -ii_0xc\11: - exg_macro \2,d1_off(a7) -ii_0xc\12: - exg_macro \2,d2 -ii_0xc\13: - exg_macro \2,d3 -ii_0xc\14: - exg_macro \2,d4 -ii_0xc\15: - exg_macro \2,d5 -ii_0xc\16: - exg_macro \2,d6 -ii_0xc\17: - exg_macro \2,d7 -.endm -ii_exg_to_ax:.macro -ii_0xc\18: - exg_macro \2,a0_off(a7) -ii_0xc\19: - exg_macro \2,a1_off(a7) -ii_0xc\1a: - exg_macro \2,a2 -ii_0xc\1b: - exg_macro \2,a3 -ii_0xc\1c: - exg_macro \2,a4 -ii_0xc\1d: - exg_macro \2,a5 -ii_0xc\1e: - exg_macro \2,a6 -ii_0xc\1f: - exg_macro \2,usp -.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_func.h b/BaS_GNU/sources/ii_func.h deleted file mode 100644 index f545f47..0000000 --- a/BaS_GNU/sources/ii_func.h +++ /dev/null @@ -1,945 +0,0 @@ -//-------------------------------------------------------------------- -// functionen macros -//-------------------------------------------------------------------- -ii_lset_func:.macro -/******************************************************/ -// byt -/******************************************************/ -// func.b dy,dx - ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c - ii_lset_dx \1,01 - ii_lset_dx \1,02 - ii_lset_dx \1,03 - ii_lset_dx \1,04 - ii_lset_dx \1,05 - ii_lset_dx \1,06 - ii_lset_dx \1,07 -// func.b ax,dx - ii_lset_dxu \1,08 - ii_lset_dxu \1,09 - ii_lset_dxu \1,0a - ii_lset_dxu \1,0b - ii_lset_dxu \1,0c - ii_lset_dxu \1,0d - ii_lset_dxu \1,0e - ii_lset_dxu \1,0f -// func.b (ax),dx - ii_lset_dx \1,10 - ii_lset_dx \1,11 - ii_lset_dx \1,12 - ii_lset_dx \1,13 - ii_lset_dx \1,14 - ii_lset_dx \1,15 - ii_lset_dx \1,16 - ii_lset_dx \1,17 -// func.b (ax)+,dx - ii_lset_dx \1,18 - ii_lset_dx \1,19 - ii_lset_dx \1,1a - ii_lset_dx \1,1b - ii_lset_dx \1,1c - ii_lset_dx \1,1d - ii_lset_dx \1,1e - ii_lset_dx \1,1f -// func.b -(ax),dx - ii_lset_dx \1,20 - ii_lset_dx \1,21 - ii_lset_dx \1,22 - ii_lset_dx \1,23 - ii_lset_dx \1,24 - ii_lset_dx \1,25 - ii_lset_dx \1,26 - ii_lset_dx \1,27 -// func.b d16(ax),dx - ii_lset_dx \1,28 - ii_lset_dx \1,29 - ii_lset_dx \1,2a - ii_lset_dx \1,2b - ii_lset_dx \1,2c - ii_lset_dx \1,2d - ii_lset_dx \1,2e - ii_lset_dx \1,2f -// func.b dd8(ax,dy),dx - ii_lset_dx \1,30 - ii_lset_dx \1,31 - ii_lset_dx \1,32 - ii_lset_dx \1,33 - ii_lset_dx \1,34 - ii_lset_dx \1,35 - ii_lset_dx \1,36 - ii_lset_dx \1,37 -// func.b xxx.w,dx - ii_lset_dx \1,38 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -// func.b xxx.l,dx - ii_lset_dx \1,39 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -// func.b d16(pc),dx - ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -// func.b d8(pc,dy),dx - ii_lset_dxg \1,3b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -// func.b #im,dx - ii_lset_dxg \1,3c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -/******************************************************/ -// word -/******************************************************/ -// func.w dy,dx - ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c - ii_lset_dx \1,41 - ii_lset_dx \1,42 - ii_lset_dx \1,43 - ii_lset_dx \1,44 - ii_lset_dx \1,45 - ii_lset_dx \1,46 - ii_lset_dx \1,47 -// func.w ax,dx - ii_lset_dx \1,48 - ii_lset_dx \1,49 - ii_lset_dx \1,4a - ii_lset_dx \1,4b - ii_lset_dx \1,4c - ii_lset_dx \1,4d - ii_lset_dx \1,4e - ii_lset_dx \1,4f -// func.w (ax),dx - ii_lset_dx \1,50 - ii_lset_dx \1,51 - ii_lset_dx \1,52 - ii_lset_dx \1,53 - ii_lset_dx \1,54 - ii_lset_dx \1,55 - ii_lset_dx \1,56 - ii_lset_dx \1,57 -// func.w (ax)+,dx - ii_lset_dx \1,58 - ii_lset_dx \1,59 - ii_lset_dx \1,5a - ii_lset_dx \1,5b - ii_lset_dx \1,5c - ii_lset_dx \1,5d - ii_lset_dx \1,5e - ii_lset_dx \1,5f -// func.w -(ax),dx - ii_lset_dx \1,60 - ii_lset_dx \1,61 - ii_lset_dx \1,62 - ii_lset_dx \1,63 - ii_lset_dx \1,64 - ii_lset_dx \1,65 - ii_lset_dx \1,66 - ii_lset_dx \1,67 -// func.w d16(ax),dx - ii_lset_dx \1,68 - ii_lset_dx \1,69 - ii_lset_dx \1,6a - ii_lset_dx \1,6b - ii_lset_dx \1,6c - ii_lset_dx \1,6d - ii_lset_dx \1,6e - ii_lset_dx \1,6f -// func.w d8(ax,dy),dx - ii_lset_dx \1,70 - ii_lset_dx \1,71 - ii_lset_dx \1,72 - ii_lset_dx \1,73 - ii_lset_dx \1,74 - ii_lset_dx \1,75 - ii_lset_dx \1,76 - ii_lset_dx \1,77 -// func.w xxx.w,dx - ii_lset_dx \1,78 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -// func.w xxx.l,dx - ii_lset_dx \1,79 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -// func.w d16(pc),dx - ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -// func.w d8(pc,dy),dx - ii_lset_dxg \1,7b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -// func.w #im,dx - ii_lset_dxg \1,7c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -/******************************************************/ -// long -/******************************************************/ -// func.l ax,dx -> -(ay),-(ax) - ii_lset_dxu \1,c8 - ii_lset_dxu \1,c9 - ii_lset_dxu \1,ca - ii_lset_dxu \1,cb - ii_lset_dxu \1,cc - ii_lset_dxu \1,cd - ii_lset_dxu \1,ce - ii_lset_dxu \1,cf -// func.w d8(ax,dy),dx - ii_lset_dx \1,b0 - ii_lset_dx \1,b1 - ii_lset_dx \1,b2 - ii_lset_dx \1,b3 - ii_lset_dx \1,b4 - ii_lset_dx \1,b5 - ii_lset_dx \1,b6 - ii_lset_dx \1,b7 -// func.l d8(pc,dy),dx - ii_lset_dxg \1,bb // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c -/******************************************************/ -// adress register -/******************************************************/ -//func.w dy,ax - ii_lset_dxg \1,c0 - ii_lset_dxg \1,c1 - ii_lset_dxg \1,c2 - ii_lset_dxg \1,c3 - ii_lset_dxg \1,c4 - ii_lset_dxg \1,c5 - ii_lset_dxg \1,c6 - ii_lset_dxg \1,c7 -//func.w ay,ax - ii_lset_dxg \1,c8 - ii_lset_dxg \1,c9 - ii_lset_dxg \1,ca - ii_lset_dxg \1,cb - ii_lset_dxg \1,cc - ii_lset_dxg \1,cd - ii_lset_dxg \1,ce - ii_lset_dxg \1,cf -//func.w (ay),ax - ii_lset_dxg \1,d0 - ii_lset_dxg \1,d1 - ii_lset_dxg \1,d2 - ii_lset_dxg \1,d3 - ii_lset_dxg \1,d4 - ii_lset_dxg \1,d5 - ii_lset_dxg \1,d6 - ii_lset_dxg \1,d7 -//func.w (ay)+,ax - ii_lset_dxg \1,d8 - ii_lset_dxg \1,d9 - ii_lset_dxg \1,da - ii_lset_dxg \1,db - ii_lset_dxg \1,dc - ii_lset_dxg \1,dd - ii_lset_dxg \1,de - ii_lset_dxg \1,df -//func.w -(ay),ax - ii_lset_dxg \1,e0 - ii_lset_dxg \1,e1 - ii_lset_dxg \1,e2 - ii_lset_dxg \1,e3 - ii_lset_dxg \1,e4 - ii_lset_dxg \1,e5 - ii_lset_dxg \1,e6 - ii_lset_dxg \1,e7 -//func.w d16(ay),ax - ii_lset_dxg \1,e8 - ii_lset_dxg \1,e9 - ii_lset_dxg \1,ea - ii_lset_dxg \1,eb - ii_lset_dxg \1,ec - ii_lset_dxg \1,ed - ii_lset_dxg \1,ee - ii_lset_dxg \1,ef -//func.w d8(ay,dy),ax - ii_lset_dxg \1,f0 - ii_lset_dxg \1,f1 - ii_lset_dxg \1,f2 - ii_lset_dxg \1,f3 - ii_lset_dxg \1,f4 - ii_lset_dxg \1,f5 - ii_lset_dxg \1,f6 - ii_lset_dxg \1,f7 -// func.w xxx.w,ax - ii_lset_dxg \1,f8 -// func.w xxx.l,ax - ii_lset_dxg \1,f9 -// func.w d16(pc),ax - ii_lset_dxg \1,fa -// func.w d8(pc,dy),ax - ii_lset_dxg \1,fb -// func.w #im,ax - ii_lset_dxg \1,fc -//-------------------------------------------------------------------- -// ende - .endm; -/*****************************************************************************************/ -ii_func:.macro -//-------------------------------------------------------------------- -// byt -//-------------------------------------------------------------------- -///-------------------------------------------------------------------- -// func.b ds,dx -//-------------------------------------------------------------------- - funcbeadx \1,00,\2dd,d0_off+3(a7) - funcbeadx \1,01,\2dd,d1_off+3(a7) - funcbeadx \1,02,\2dd,d2 - funcbeadx \1,03,\2dd,d3 - funcbeadx \1,04,\2dd,d4 - funcbeadx \1,05,\2dd,d5 - funcbeadx \1,06,\2dd,d6 - funcbeadx \1,07,\2dd,d7 -//-------------------------------------------------------------------- -// func.b (ax),dx -//-------------------------------------------------------------------- - funcbeadx \1,10,\2dda,a0_off(a7) - funcbeadx \1,11,\2dda,a1_off(a7) - funcbeadx \1,12,\2dd,(a2) - funcbeadx \1,13,\2dd,(a3) - funcbeadx \1,14,\2dd,(a4) - funcbeadx \1,15,\2dd,(a5) - funcbeadx \1,16,\2dd,(a6) - funcbeadx \1,17,\2dda,usp -//-------------------------------------------------------------------- -// func.b (ax)+,dx -//-------------------------------------------------------------------- - funcbeadx \1,18,\2ddai,a0_off(a7) - funcbeadx \1,19,\2ddai,a1_off(a7) - funcbeadx \1,1a,\2dd,(a2)+ - funcbeadx \1,1b,\2dd,(a3)+ - funcbeadx \1,1c,\2dd,(a4)+ - funcbeadx \1,1d,\2dd,(a5)+ - funcbeadx \1,1e,\2dd,(a6)+ - funcbeadx \1,1f,\2ddai,usp -//-------------------------------------------------------------------- -// func.b -(ax),dx -//-------------------------------------------------------------------- - funcbeadx \1,20,\2ddad,a0_off(a7) - funcbeadx \1,21,\2ddad,a1_off(a7) - funcbeadx \1,22,\2dd,-(a2) - funcbeadx \1,23,\2dd,-(a3) - funcbeadx \1,24,\2dd,-(a4) - funcbeadx \1,25,\2dd,-(a5) - funcbeadx \1,26,\2dd,-(a6) - funcbeadx \1,27,\2ddad,usp -//-------------------------------------------------------------------- -// func.b d16(ax),dx -//-------------------------------------------------------------------- - funcbeadx \1,28,\2d16ad,a0_off(a7) - funcbeadx \1,29,\2d16ad,a1_off(a7) - funcbeadx \1,2a,\2d16ad,a2 - funcbeadx \1,2b,\2d16ad,a3 - funcbeadx \1,2c,\2d16ad,a4 - funcbeadx \1,2d,\2d16ad,a5 - funcbeadx \1,2e,\2d16ad,a6 - funcbeadx \1,2f,\2d16ad,usp -//-------------------------------------------------------------------- -// func.b d8(ax,dy),dx -//-------------------------------------------------------------------- - funcbeadx \1,30,\2d8ad,a0_off(a7) - funcbeadx \1,31,\2d8ad,a1_off(a7) - funcbeadx \1,32,\2d8ad,a2 - funcbeadx \1,33,\2d8ad,a3 - funcbeadx \1,34,\2d8ad,a4 - funcbeadx \1,35,\2d8ad,a5 - funcbeadx \1,36,\2d8ad,a6 - funcbeadx \1,37,\2d8ad,usp -//-------------------------------------------------------------------- -// func.b xxx.w,dx -//-------------------------------------------------------------------- - funcbeadx \1,38,\2xwd,(a0)+ -//-------------------------------------------------------------------- -// func.b xxx.w,dx -//-------------------------------------------------------------------- - funcbeadx \1,39,\2xld,(a0)+ -//-------------------------------------------------------------------- -// func.b d16(pc),dx -//-------------------------------------------------------------------- - funcbeadx \1,3a,\2d16pcd,(a0)+ -//-------------------------------------------------------------------- -// func.b d8(pc,dy),dx -//-------------------------------------------------------------------- - funcbeadx \1,3b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) -//-------------------------------------------------------------------- -// func.b #im,dx -//-------------------------------------------------------------------- - funcbeadx \1,3c,\2bir_macro,(a0)+ -//-------------------------------------------------------------------- -// func.b dy,ea -//-------------------------------------------------------------------- -///-------------------------------------------------------------------- -// func.b dx,dd -> addx subx etc. src und dest vertauscht! -//-------------------------------------------------------------------- - funcbdxea \1,00,\2dx,d0_off+3(a7) - funcbdxea \1,01,\2dx,d1_off+3(a7) - funcbdxea \1,02,\2dx,d2 - funcbdxea \1,03,\2dx,d3 - funcbdxea \1,04,\2dx,d4 - funcbdxea \1,05,\2dx,d5 - funcbdxea \1,06,\2dx,d6 - funcbdxea \1,07,\2dx,d7 -//-------------------------------------------------------------------- -// func.b -(ax),-(ay) addx subx etc. src und dest vertauscht! -//-------------------------------------------------------------------- - funcaxay \1,08,\2dax,a0_off(a7),b - funcaxay \1,09,\2dax,a1_off(a7).b - funcaxay \1,0a,\2dax,a2,b - funcaxay \1,0b,\2dax,a3,b - funcaxay \1,0c,\2dax,a4,b - funcaxay \1,0d,\2dax,a5,b - funcaxay \1,0e,\2dax,a6,b - funcaxay \1,0f,\2dax,usp,b -//-------------------------------------------------------------------- -// func.b dy,(ax) -//-------------------------------------------------------------------- - funcbdxea \1,10,\2eda,a0_off(a7) - funcbdxea \1,11,\2eda,a1_off(a7) - funcbdxea \1,12,\2dd,(a2) - funcbdxea \1,13,\2dd,(a3) - funcbdxea \1,14,\2dd,(a4) - funcbdxea \1,15,\2dd,(a5) - funcbdxea \1,16,\2dd,(a6) - funcbdxea \1,17,\2eda,usp -//-------------------------------------------------------------------- -// func.b dy,(ax)+ -//-------------------------------------------------------------------- - funcbdxea \1,18,\2edai,a0_off(a7) - funcbdxea \1,19,\2edai,a1_off(a7) - funcbdxea \1,1a,\2edaid,(a2) - funcbdxea \1,1b,\2edaid,(a3) - funcbdxea \1,1c,\2edaid,(a4) - funcbdxea \1,1d,\2edaid,(a5) - funcbdxea \1,1e,\2edaid,(a6) - funcbdxea \1,1f,\2edai,usp -//-------------------------------------------------------------------- -// func.b dy,-(ax) -//-------------------------------------------------------------------- - funcbdxea \1,20,\2edad,a0_off(a7) - funcbdxea \1,21,\2edad,a1_off(a7) - funcbdxea \1,22,\2edadd,(a2) - funcbdxea \1,23,\2edadd,(a3) - funcbdxea \1,24,\2edadd,(a4) - funcbdxea \1,25,\2edadd,(a5) - funcbdxea \1,26,\2edadd,(a6) - funcbdxea \1,27,\2edad,usp -//-------------------------------------------------------------------- -// func.b dy,d16(ax) -//-------------------------------------------------------------------- - funcbdxea \1,28,\2e16ad,a0_off(a7) - funcbdxea \1,29,\2e16ad,a1_off(a7) - funcbdxea \1,2a,\2e16ad,a2 - funcbdxea \1,2b,\2e16ad,a3 - funcbdxea \1,2c,\2e16ad,a4 - funcbdxea \1,2d,\2e16ad,a5 - funcbdxea \1,2e,\2e16ad,a6 - funcbdxea \1,2f,\2e16ad,usp -//-------------------------------------------------------------------- -// func.b dy,d8(ax,dy) -//-------------------------------------------------------------------- - funcbdxea \1,30,\2e8ad,a0_off(a7) - funcbdxea \1,31,\2e8ad,a1_off(a7) - funcbdxea \1,32,\2e8ad,a2 - funcbdxea \1,33,\2e8ad,a3 - funcbdxea \1,34,\2e8ad,a4 - funcbdxea \1,35,\2e8ad,a5 - funcbdxea \1,36,\2e8ad,a6 - funcbdxea \1,37,\2e8ad,usp -//-------------------------------------------------------------------- -// func.w dy,xxx.w -//-------------------------------------------------------------------- - funcwdxea \1,38,\2xwe,(a0)+ -//-------------------------------------------------------------------- -// func.w dy,xxx.w -//-------------------------------------------------------------------- - funcwdxea \1,39,\2xld,(a0)+ -/*****************************************************************************************/ -// word -/*****************************************************************************************/ -// func.w ds,dx -//-------------------------------------------------------------------- - funcweadx \1,40,\2dd,d0_off+2(a7) - funcweadx \1,41,\2dd,d1_off+2(a7) - funcweadx \1,42,\2dd,d2 - funcweadx \1,43,\2dd,d3 - funcweadx \1,44,\2dd,d4 - funcweadx \1,45,\2dd,d5 - funcweadx \1,46,\2dd,d6 - funcweadx \1,47,\2dd,d7 -//-------------------------------------------------------------------- -// func.w ax,dx -//-------------------------------------------------------------------- - funcweadx \1,48,\2dd,a0_off+2(a7) - funcweadx \1,49,\2dd,a1_off+2(a7) - funcweadx \1,4a,\2dd,a2 - funcweadx \1,4b,\2dd,a3 - funcweadx \1,4c,\2dd,a4 - funcweadx \1,4d,\2dd,a5 - funcweadx \1,4e,\2dd,a6 - funcweadx \1,4f,\2ddd,usp -//-------------------------------------------------------------------- -// func.w (ax),dx -//-------------------------------------------------------------------- - funcweadx \1,50,\2dda,a0_off(a7) - funcweadx \1,51,\2dda,a1_off(a7) - funcweadx \1,52,\2dd,(a2) - funcweadx \1,53,\2dd,(a3) - funcweadx \1,54,\2dd,(a4) - funcweadx \1,55,\2dd,(a5) - funcweadx \1,56,\2dd,(a6) - funcweadx \1,57,\2dda,usp -//-------------------------------------------------------------------- -// func.w (ax)+,dx -//-------------------------------------------------------------------- - funcweadx \1,58,\2ddai,a0_off(a7) - funcweadx \1,59,\2ddai,a1_off(a7) - funcweadx \1,5a,\2dd,(a2)+ - funcweadx \1,5b,\2dd,(a3)+ - funcweadx \1,5c,\2dd,(a4)+ - funcweadx \1,5d,\2dd,(a5)+ - funcweadx \1,5e,\2dd,(a6)+ - funcweadx \1,5f,\2ddai,usp -//-------------------------------------------------------------------- -// func.w -(ax),dx -//-------------------------------------------------------------------- - funcweadx \1,60,\2ddad,a0_off(a7) - funcweadx \1,61,\2ddad,a1_off(a7) - funcweadx \1,62,\2dd,-(a2) - funcweadx \1,63,\2dd,-(a3) - funcweadx \1,64,\2dd,-(a4) - funcweadx \1,65,\2dd,-(a5) - funcweadx \1,66,\2dd,-(a6) - funcweadx \1,67,\2ddad,usp -//-------------------------------------------------------------------- -// func.w d16(ax),dx -//-------------------------------------------------------------------- - funcweadx \1,68,\2d16ad,a0_off(a7) - funcweadx \1,69,\2d16ad,a1_off(a7) - funcweadx \1,6a,\2d16ad,a2 - funcweadx \1,6b,\2d16ad,a3 - funcweadx \1,6c,\2d16ad,a4 - funcweadx \1,6d,\2d16ad,a5 - funcweadx \1,6e,\2d16ad,a6 - funcweadx \1,6f,\2d16ad,usp -//-------------------------------------------------------------------- -// func.w d8(ax,dy),dx -//-------------------------------------------------------------------- - funcweadx \1,70,\2d8ad,a0_off(a7) - funcweadx \1,71,\2d8ad,a1_off(a7) - funcweadx \1,72,\2d8ad,a2 - funcweadx \1,73,\2d8ad,a3 - funcweadx \1,74,\2d8ad,a4 - funcweadx \1,75,\2d8ad,a5 - funcweadx \1,76,\2d8ad,a6 - funcweadx \1,77,\2d8ad,usp -//-------------------------------------------------------------------- -// func.w xxx.w,dx -//-------------------------------------------------------------------- - funcweadx \1,78,\2xwd,(a0)+ -//-------------------------------------------------------------------- -// func.w xxx.w,dx -//-------------------------------------------------------------------- - funcweadx \1,79,\2xld,(a0)+ -//-------------------------------------------------------------------- -// func.w d16(pc),dx -//-------------------------------------------------------------------- - funcweadx \1,7a,\2d16pcd,(a0)+ -//-------------------------------------------------------------------- -// func.w d8(pc,dy),dx -//-------------------------------------------------------------------- - funcweadx \1,7b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) -//-------------------------------------------------------------------- -// func.w #im,dx -//-------------------------------------------------------------------- - funcweadx \1,7c,\2dd,(a0)+ -//-------------------------------------------------------------------- -// func.w dy,ea -//-------------------------------------------------------------------- -///-------------------------------------------------------------------- -// func.w dx,dd -> addx subx etc. -//-------------------------------------------------------------------- -.ifnc \2,and //platz für exg - funcwdxea \1,40,\2dx,d0_off+2(a7) - funcwdxea \1,41,\2dx,d1_off+2(a7) - funcwdxea \1,42,\2dx,d2 - funcwdxea \1,43,\2dx,d3 - funcwdxea \1,44,\2dx,d4 - funcwdxea \1,45,\2dx,d5 - funcwdxea \1,46,\2dx,d6 - funcwdxea \1,47,\2dx,d7 -//-------------------------------------------------------------------- -// func.w -(ax),-(ay) -> addx,subx -//-------------------------------------------------------------------- - funcaxay \1,48,\2dax,a0_off(a7),w - funcaxay \1,49,\2dax,a1_off(a7).w - funcaxay \1,4a,\2dax,a2,w - funcaxay \1,4b,\2dax,a3,w - funcaxay \1,4c,\2dax,a4,w - funcaxay \1,4d,\2dax,a5,w - funcaxay \1,4e,\2dax,a6,w - funcaxay \1,4f,\2dax,usp,w -.endif -//-------------------------------------------------------------------- -// func.w dy,(ax) -//-------------------------------------------------------------------- - funcwdxea \1,50,\2eda,a0_off(a7) - funcwdxea \1,51,\2eda,a1_off(a7) - funcwdxea \1,52,\2dd,(a2) - funcwdxea \1,53,\2dd,(a3) - funcwdxea \1,54,\2dd,(a4) - funcwdxea \1,55,\2dd,(a5) - funcwdxea \1,56,\2dd,(a6) - funcwdxea \1,57,\2eda,usp -//-------------------------------------------------------------------- -// func.w dy,(ax)+ -//-------------------------------------------------------------------- - funcwdxea \1,58,\2edai,a0_off(a7) - funcwdxea \1,59,\2edai,a1_off(a7) - funcwdxea \1,5a,\2edaid,(a2) - funcwdxea \1,5b,\2edaid,(a3) - funcwdxea \1,5c,\2edaid,(a4) - funcwdxea \1,5d,\2edaid,(a5) - funcwdxea \1,5e,\2edaid,(a6) - funcwdxea \1,5f,\2edai,usp -//-------------------------------------------------------------------- -// func.w dy,-(ax) -//-------------------------------------------------------------------- - funcwdxea \1,60,\2edad,a0_off(a7) - funcwdxea \1,61,\2edad,a1_off(a7) - funcwdxea \1,62,\2edadd,(a2) - funcwdxea \1,63,\2edadd,(a3) - funcwdxea \1,64,\2edadd,(a4) - funcwdxea \1,65,\2edadd,(a5) - funcwdxea \1,66,\2edadd,(a6) - funcwdxea \1,67,\2edad,usp -//-------------------------------------------------------------------- -// func.w dy,d16(ax) -//-------------------------------------------------------------------- - funcwdxea \1,68,\2e16ad,a0_off(a7) - funcwdxea \1,69,\2e16ad,a1_off(a7) - funcwdxea \1,6a,\2e16ad,a2 - funcwdxea \1,6b,\2e16ad,a3 - funcwdxea \1,6c,\2e16ad,a4 - funcwdxea \1,6d,\2e16ad,a5 - funcwdxea \1,6e,\2e16ad,a6 - funcwdxea \1,6f,\2e16ad,usp -//-------------------------------------------------------------------- -// func.w dy,d8(ax,dy) -//-------------------------------------------------------------------- - funcwdxea \1,70,\2e8ad,a0_off(a7) - funcwdxea \1,71,\2e8ad,a1_off(a7) - funcwdxea \1,72,\2e8ad,a2 - funcwdxea \1,73,\2e8ad,a3 - funcwdxea \1,74,\2e8ad,a4 - funcwdxea \1,75,\2e8ad,a5 - funcwdxea \1,76,\2e8ad,a6 - funcwdxea \1,77,\2e8ad,usp -//-------------------------------------------------------------------- -// func.w dy,xxx.w -//-------------------------------------------------------------------- - funcwdxea \1,78,\2xwe,(a0)+ -//-------------------------------------------------------------------- -// func.w dy,xxx.w -//-------------------------------------------------------------------- - funcwdxea \1,79,\2xld,(a0)+ -/*****************************************************************************************/ -// long -/*****************************************************************************************/ -//-------------------------------------------------------------------- -// func.l -(ax),-(ay) -//-------------------------------------------------------------------- - funcaxay \1,c8,\2dax,a0_off(a7),l - funcaxay \1,c9,\2dax,a1_off(a7).l - funcaxay \1,ca,\2dax,a2,l - funcaxay \1,cb,\2dax,a3,l - funcaxay \1,cc,\2dax,a4,l - funcaxay \1,cd,\2dax,a5,l - funcaxay \1,ce,\2dax,a6,l - funcaxay \1,cf,\2dax,usp,l -//-------------------------------------------------------------------- -// func.l d8(ax,dy),dx -//-------------------------------------------------------------------- - funcleadx \1,b0,\2d8ad,a0_off(a7) - funcleadx \1,b1,\2d8ad,a1_off(a7) - funcleadx \1,b2,\2d8ad,a2 - funcleadx \1,b3,\2d8ad,a3 - funcleadx \1,b4,\2d8ad,a4 - funcleadx \1,b5,\2d8ad,a5 - funcleadx \1,b6,\2d8ad,a6 - funcleadx \1,b7,\2d8ad,usp -//-------------------------------------------------------------------- -// func.l d8(pc,dy),dx -//-------------------------------------------------------------------- - funcleadx \1,bb,\2d8pcd,(a0)+ (a0 wird nicht verwendet) -//-------------------------------------------------------------------- -// func.l dy,d8(ax,dy) -//-------------------------------------------------------------------- - funcldxea \1,b0,\2e8ad,a0_off(a7) - funcldxea \1,b1,\2e8ad,a1_off(a7) - funcldxea \1,b2,\2e8ad,a2 - funcldxea \1,b3,\2e8ad,a3 - funcldxea \1,b4,\2e8ad,a4 - funcldxea \1,b5,\2e8ad,a5 - funcldxea \1,b6,\2e8ad,a6 - funcldxea \1,b7,\2e8ad,usp -/******************************************************/ -// adress register -/******************************************************/ -//-------------------------------------------------------------------- -// func.w ea,ax -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// func.w dx,ax -//-------------------------------------------------------------------- - funcweaax \1,c0,\2aw,d0 - funcweaax \1,c1,\2aw,d1 - funcweaax \1,c2,\2aw,d2 - funcweaax \1,c3,\2aw,d3 - funcweaax \1,c4,\2aw,d4 - funcweaax \1,c5,\2aw,d5 - funcweaax \1,c6,\2aw,d6 - funcweaax \1,c7,\2aw,d7 -//-------------------------------------------------------------------- -// func.w ay,ax -//-------------------------------------------------------------------- - funcweaax \1,c8,\2aw,a0 - funcweaax \1,c9,\2aw,a1 - funcweaax \1,ca,\2aw,a2 - funcweaax \1,cb,\2aw,a3 - funcweaax \1,cc,\2aw,a4 - funcweaax \1,cd,\2aw,a5 - funcweaax \1,ce,\2aw,a6 - funcweaax \1,cf,\2awu,a7 -//-------------------------------------------------------------------- -// func.w (ay),ax -//-------------------------------------------------------------------- - funcweaax \1,d0,\2aw,(a0) - funcweaax \1,d1,\2aw,(a1) - funcweaax \1,d2,\2aw,(a2) - funcweaax \1,d3,\2aw,(a3) - funcweaax \1,d4,\2aw,(a4) - funcweaax \1,d5,\2aw,(a5) - funcweaax \1,d6,\2aw,(a6) - funcweaax \1,d7,\2awu,(a7) -//-------------------------------------------------------------------- -// func.w (ay)+,ax -//-------------------------------------------------------------------- - funcweaax \1,d8,\2aw,(a0)+ - funcweaax \1,d9,\2aw,(a1)+ - funcweaax \1,da,\2aw,(a2)+ - funcweaax \1,db,\2aw,(a3)+ - funcweaax \1,dc,\2aw,(a4)+ - funcweaax \1,dd,\2aw,(a5)+ - funcweaax \1,de,\2aw,(a6)+ - funcweaax \1,df,\2awu,(a7)+ -//-------------------------------------------------------------------- -// func.w -(ay),ax -//-------------------------------------------------------------------- - funcweaax \1,e0,\2aw,-(a0) - funcweaax \1,e1,\2aw,-(a1) - funcweaax \1,e2,\2aw,-(a2) - funcweaax \1,e3,\2aw,-(a3) - funcweaax \1,e4,\2aw,-(a4) - funcweaax \1,e5,\2aw,-(a5) - funcweaax \1,e6,\2aw,-(a6) - funcweaax \1,e7,\2awu,-(a7) -//-------------------------------------------------------------------- -// func.w d16(ay),ax -//-------------------------------------------------------------------- - funcweaaxn \1,e8,\2awd16a,a0_off(a7) - funcweaaxn \1,e9,\2awd16a,a1_off(a7) - funcweaaxn \1,ea,\2awd16a,a2 - funcweaaxn \1,eb,\2awd16a,a3 - funcweaaxn \1,ec,\2awd16a,a4 - funcweaaxn \1,ed,\2awd16a,a5 - funcweaaxn \1,ee,\2awd16a,a6 - funcweaaxn \1,ef,\2awd16a,usp -//-------------------------------------------------------------------- -// func.w d8(ay,dy),ax -//-------------------------------------------------------------------- - funcweaaxn \1,f0,\2awd8a,a0_off(a7) - funcweaaxn \1,f1,\2awd8a,a1_off(a7) - funcweaaxn \1,f2,\2awd8a,a2 - funcweaaxn \1,f3,\2awd8a,a3 - funcweaaxn \1,f4,\2awd8a,a4 - funcweaaxn \1,f5,\2awd8a,a5 - funcweaaxn \1,f6,\2awd8a,a6 - funcweaaxn \1,f7,\2awd8a,usp -//-------------------------------------------------------------------- -// func.w xxx.w,ax -//-------------------------------------------------------------------- - funcweaaxn \1,f8,\2awxwax,(a0)+ -//-------------------------------------------------------------------- -// func.w xxxlw,ax -//-------------------------------------------------------------------- - funcweaaxn \1,f9,\2awxlax,(a0)+ -//-------------------------------------------------------------------- -// func.w d16(pc),ax -//-------------------------------------------------------------------- - funcweaaxn \1,fa,\2awd16pcax,(a0)+ -//-------------------------------------------------------------------- -// func.w d8(pc,dy),ax -//-------------------------------------------------------------------- - funcweaaxn \1,fb,\2awd8pcax,(a0)+ //(a0 wird nicht verwendet) -//-------------------------------------------------------------------- -// func.w #im,ax -//-------------------------------------------------------------------- - funcweaaxn \1,fc,\2awim,(a0)+ -//-------------------------------------------------------------------- -// ende - .endm; -//-------------------------------------------------------------------- -// byt -funcbeadx:.macro // function byt: im,dx -ii_0x\10\2: - \3 \4,d0_off+3(a7),b -ii_0x\12\2: - \3 \4,d1_off+3(a7),b -ii_0x\14\2: - \3 \4,d2,b -ii_0x\16\2: - \3 \4,d3,b -ii_0x\18\2: - \3 \4,d4,b -ii_0x\1a\2: - \3 \4,d5,b -ii_0x\1c\2: - \3 \4,d6,b -ii_0x\1e\2: - \3 \4,d7,b - .endm; -funcbdxea:.macro // ea(\4) function(\3) dx -> ea -ii_0x\11\2: - \3 d0_off+3(a7),\4,b -ii_0x\13\2: - \3 d1_off+3(a7),\4,b -ii_0x\15\2: - \3 d2,\4,b -ii_0x\17\2: - \3 d3,\4,b -ii_0x\19\2: - \3 d4,\4,b -ii_0x\1b\2: - \3 d5,\4,b -ii_0x\1d\2: - \3 d6,\4,b -ii_0x\1f\2: - \3 d7,\4,b - .endm; -//-------------------------------------------------------------------- -// word -funcweadx:.macro // dx function(\3) ea(\4) -> dx -ii_0x\10\2: - \3 \4,d0_off+2(a7),w -ii_0x\12\2: - \3 \4,d1_off+2(a7),w -ii_0x\14\2: - \3 \4,d2,w -ii_0x\16\2: - \3 \4,d3,w -ii_0x\18\2: - \3 \4,d4,w -ii_0x\1a\2: - \3 \4,d5,w -ii_0x\1c\2: - \3 \4,d6,w -ii_0x\1e\2: - \3 \4,d7,w - .endm; -funcwdxea:.macro // ea(\4) function(\3) dx -> ea -ii_0x\11\2: - \3 d0_off+2(a7),\4,w -ii_0x\13\2: - \3 d1_off+2(a7),\4,w -ii_0x\15\2: - \3 d2,\4,w -ii_0x\17\2: - \3 d3,\4,w -ii_0x\19\2: - \3 d4,\4,w -ii_0x\1b\2: - \3 d5,\4,w -ii_0x\1d\2: - \3 d6,\4,w -ii_0x\1f\2: - \3 d7,\4,w - .endm; -//-------------------------------------------------------------------- -// long -funcleadx:.macro // dx function(\3) ea(\4) -> dx -ii_0x\10\2: - \3 \4,d0_off(a7),w -ii_0x\12\2: - \3 \4,d1_off(a7),w -ii_0x\14\2: - \3 \4,d2,w -ii_0x\16\2: - \3 \4,d3,w -ii_0x\18\2: - \3 \4,d4,w -ii_0x\1a\2: - \3 \4,d5,w -ii_0x\1c\2: - \3 \4,d6,w -ii_0x\1e\2: - \3 \4,d7,w - .endm; -funcldxea:.macro // ea(\4) function(\3) dx -> ea -ii_0x\11\2: - \3 d0_off(a7),\4,w -ii_0x\13\2: - \3 d1_off(a7),\4,w -ii_0x\15\2: - \3 d2,\4,w -ii_0x\17\2: - \3 d3,\4,w -ii_0x\19\2: - \3 d4,\4,w -ii_0x\1b\2: - \3 d5,\4,w -ii_0x\1d\2: - \3 d6,\4,w -ii_0x\1f\2: - \3 d7,\4,w - .endm; -//-------------------------------------------------------------- -// address -funcweaax:.macro // ax function(\3) ea(\4)(ext long!) -> ax -ii_0x\10\2: - \3 \4,a0 -ii_0x\12\2: - \3 \4,a1 -ii_0x\14\2: - \3 \4,a2 -ii_0x\16\2: - \3 \4,a3 -ii_0x\18\2: - \3 \4,a4 -ii_0x\1a\2: - \3 \4,a5 -ii_0x\1c\2: - \3 \4,a6 -ii_0x\1e\2: - \3a7 \4,a7 // "a7" beachten wegen usp - .endm; -funcweaaxn:.macro // ax function(\3) ea(\4)(ext long!) -> ax -ii_0x\10\2: - \3 \4,a0_off(a7) -ii_0x\12\2: - \3 \4,a1_off(a7) -ii_0x\14\2: - \3 \4,a2 -ii_0x\16\2: - \3 \4,a3 -ii_0x\18\2: - \3 \4,a4 -ii_0x\1a\2: - \3 \4,a5 -ii_0x\1c\2: - \3 \4,a6 -ii_0x\1e\2: - \3 \4,usp - .endm; -//-------------------------------------------------------------- -// byt, word, long -//-------------------------------------------------------------- -funcaxay:.macro // ea(\4) function(\3) dx -> ea,\5 = size -ii_0x\11\2: - \3 a0_off(a7),\4,\5 -ii_0x\13\2: - \3 a1_off(a7),\4,\5 -ii_0x\15\2: - \3 a2,\4,\5 -ii_0x\17\2: - \3 a3,\4,\5 -ii_0x\19\2: - \3 a4,\4,\5 -ii_0x\1b\2: - \3 a5,\4,\5 -ii_0x\1d\2: - \3 a6,\4,\5 -ii_0x\1f\2: - \3 usp,\4,\5 - .endm; diff --git a/BaS_GNU/sources/ii_jmp.h b/BaS_GNU/sources/ii_jmp.h deleted file mode 100644 index 1896118..0000000 --- a/BaS_GNU/sources/ii_jmp.h +++ /dev/null @@ -1,59 +0,0 @@ -//-------------------------------------------------------------------- -// extension word format missing -//-------------------------------------------------------------------- -ii_\1_func:.macro -ii_0x\20: -#ifdef halten_\1 - halt -#endif - move.l a0_off(a7),a1 - \1_macro -ii_0x\21: -#ifdef halten_\1 - halt -#endif - move.l a1_off(a7),a1 - \1_macro -ii_0x\22: -#ifdef halten_\1 - halt -#endif - move.l a2,a1 - \1_macro -ii_0x\23: -#ifdef halten_\1 - halt -#endif - move.l a3,a1 - \1_macro -ii_0x\24: -#ifdef halten_\1 - halt -#endif - move.l a4,a1 - \1_macro -ii_0x\25: -#ifdef halten_\1 - halt -#endif - move.l a5,a1 - \1_macro -ii_0x\26: -#ifdef halten_\1 - halt -#endif - move.l a6,a1 - \1_macro -ii_0x\27: -#ifdef halten_\1 - halt -#endif - move.l usp,a1 - \1_macro -ii_0x\2b: -#ifdef halten_\1 - halt -#endif - move.l a0,a1 - \1_macro -.endm diff --git a/BaS_GNU/sources/ii_lea.h b/BaS_GNU/sources/ii_lea.h deleted file mode 100644 index 7a422a7..0000000 --- a/BaS_GNU/sources/ii_lea.h +++ /dev/null @@ -1,105 +0,0 @@ -//------------------------------------------------------------------- -// lea -//------------------------------------------------------------------- -.text -ii_lea_lset:.macro - ii_lset_dxu 4,f0 // lea d8(a0,dy.w),a0-a7 - ii_lset_dxu 4,f1 // lea d8(a1,dy.w),a0-a7 - ii_lset_dxu 4,f2 // lea d8(a2,dy.w),a0-a7 - ii_lset_dxu 4,f3 // lea d8(a3,dy.w),a0-a7 - ii_lset_dxu 4,f4 // lea d8(a4,dy.w),a0-a7 - ii_lset_dxu 4,f5 // lea d8(a5,dy.w),a0-a7 - ii_lset_dxu 4,f6 // lea d8(a6,dy.w),a0-a7 - ii_lset_dxu 4,f7 // lea d8(a7,dy.w),a0-a7 - ii_lset_dxu 4,fb // lea d8(pc,dy.w),a0-a7 -.endm - -//--------------------------------------------------------------------------------------------- -// function -//--------------------------------------------------------------------------------------------- -ii_lea_sub:.macro -ii_0x4\1\2: -#ifdef halten_lea - halt -#endif - move.l \4,a1 - jsr ewf - move.l a1,\3 - ii_end -.endm -ii_lea_func:.macro -//lea d8(ax,dy.w),a0-a7 - ii_lea_sub 1,f0,a0_off(a7),a0_off(a7) - ii_lea_sub 1,f1,a0_off(a7),a1_off(a7) - ii_lea_sub 1,f2,a0_off(a7),a2 - ii_lea_sub 1,f3,a0_off(a7),a3 - ii_lea_sub 1,f4,a0_off(a7),a4 - ii_lea_sub 1,f5,a0_off(a7),a5 - ii_lea_sub 1,f6,a0_off(a7),a6 - ii_lea_sub 1,f7,a0_off(a7),usp - ii_lea_sub 3,f0,a1_off(a7),a0_off(a7) - ii_lea_sub 3,f1,a1_off(a7),a1_off(a7) - ii_lea_sub 3,f2,a1_off(a7),a2 - ii_lea_sub 3,f3,a1_off(a7),a3 - ii_lea_sub 3,f4,a1_off(a7),a4 - ii_lea_sub 3,f5,a1_off(a7),a5 - ii_lea_sub 3,f6,a1_off(a7),a6 - ii_lea_sub 3,f7,a1_off(a7),usp - ii_lea_sub 5,f0,a2,a0_off(a7) - ii_lea_sub 5,f1,a2,a1_off(a7) - ii_lea_sub 5,f2,a2,a2 - ii_lea_sub 5,f3,a2,a3 - ii_lea_sub 5,f4,a2,a4 - ii_lea_sub 5,f5,a2,a5 - ii_lea_sub 5,f6,a2,a6 - ii_lea_sub 5,f7,a2,usp - ii_lea_sub 7,f0,a3,a0_off(a7) - ii_lea_sub 7,f1,a3,a1_off(a7) - ii_lea_sub 7,f2,a3,a2 - ii_lea_sub 7,f3,a3,a3 - ii_lea_sub 7,f4,a3,a4 - ii_lea_sub 7,f5,a3,a5 - ii_lea_sub 7,f6,a3,a6 - ii_lea_sub 7,f7,a3,usp - ii_lea_sub 9,f0,a4,a0_off(a7) - ii_lea_sub 9,f1,a4,a1_off(a7) - ii_lea_sub 9,f2,a4,a2 - ii_lea_sub 9,f3,a4,a3 - ii_lea_sub 9,f4,a4,a4 - ii_lea_sub 9,f5,a4,a5 - ii_lea_sub 9,f6,a4,a6 - ii_lea_sub 9,f7,a4,usp - ii_lea_sub b,f0,a5,a0_off(a7) - ii_lea_sub b,f1,a5,a1_off(a7) - ii_lea_sub b,f2,a5,a2 - ii_lea_sub b,f3,a5,a3 - ii_lea_sub b,f4,a5,a4 - ii_lea_sub b,f5,a5,a5 - ii_lea_sub b,f6,a5,a6 - ii_lea_sub b,f7,a6,usp - ii_lea_sub d,f0,a6,a0_off(a7) - ii_lea_sub d,f1,a6,a1_off(a7) - ii_lea_sub d,f2,a6,a2 - ii_lea_sub d,f3,a6,a3 - ii_lea_sub d,f4,a6,a4 - ii_lea_sub d,f5,a6,a5 - ii_lea_sub d,f6,a6,a6 - ii_lea_sub d,f7,a6,usp - ii_lea_sub f,f0,usp,a0_off(a7) - ii_lea_sub f,f1,usp,a1_off(a7) - ii_lea_sub f,f2,usp,a2 - ii_lea_sub f,f3,usp,a3 - ii_lea_sub f,f4,usp,a4 - ii_lea_sub f,f5,usp,a5 - ii_lea_sub f,f6,usp,a6 - ii_lea_sub f,f7,usp,usp -// lea d8(pc,dy.w),az - ii_lea_sub 1,fb,a0_off(a7),a0 - ii_lea_sub 3,fb,a1_off(a7),a0 - ii_lea_sub 5,fb,a2,a0 - ii_lea_sub 7,fb,a3,a0 - ii_lea_sub 9,fb,a4,a0 - ii_lea_sub b,fb,a5,a0 - ii_lea_sub d,fb,a6,a0 - ii_lea_sub f,fb,usp,a0 -.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_macro.h b/BaS_GNU/sources/ii_macro.h deleted file mode 100644 index 5db7460..0000000 --- a/BaS_GNU/sources/ii_macro.h +++ /dev/null @@ -1,144 +0,0 @@ -/*******************************************************/ -// constanten -/*******************************************************/ -.extern ___RAMBAR1 -.extern _rt_cacr -.extern _rt_mod -.extern _rt_ssp -.extern _rt_usp -.extern _rt_vbr -.extern _d0_save -.extern _a7_save - -ii_ss = 16 -d0_off = 0 -d1_off = 4 -a0_off = 8 -a1_off = 12 -format_off = 16 -sr_off = 18 -ccr_off = 19 -pc_off = 20 - -#define table 0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle -> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle - -/*******************************************************/ -// allgemeine macros -/*******************************************************/ -ii_end: .macro - move.l a0,pc_off(a7) - movem.l (a7),d0/d1/a0/a1 - lea ii_ss(a7),a7 - rte - .endm; - -set_cc0:.macro - move.w ccr,d0 - move.b d0,ccr_off(a7) - .endm; - -ii_esr: .macro // geht nicht!!?? - movem.l (a7),d0/d1/a0/a1 - lea ii_ss+8(a7),a7 // stack erhöhen - move.w d0,_d0_save // d0.w sicheren - move.w -6(a7),d0 // sr holen - move.w d0,sr // sr setzen - nop - move.w _d0_save,d0 // d0.w zurück - .endm; - -ii_end_mvm:.macro - move.l a0_off(a7),a0 - lea 16(a7),a7 - rte - .endm; - -ii_endj:.macro - movem.l (a7),d0/d1/a0/a1 // register zurück - lea ii_ss(a7),a7 // korr - rte // ende - .endm; - -set_nzvc:.macro // set ccr bits nzvc - move.w ccr,d1 - bclr #4,d1 - btst #4,ccr_off(a7) - beq snzvc2\@ - bset #4,d1 -snzvc2\@: - move.b d1,ccr_off(a7) - .endm; - -set_cc1:.macro - move.w ccr,d1 - move.b d1,ccr_off(a7) - .endm; - -set_cc_b:.macro - move.w ccr,d1 - btst #7,d0 // byt negativ? - beq set_cc_b2\@ - bset #3,d1 // make negativ -set_cc_b2\@: - move.b d1,ccr_off(a7) - .endm; - -set_cc_w:.macro - move.w ccr,d1 - btst #15,d0 // byt negativ? - beq set_cc_w2\@ - bset #3,d1 // make negativ -set_cc_w2\@: - move.b d1,ccr_off(a7) - .endm; - -get_pc: .macro - lea.l (a0),a1 - .endm; - -//-------------------------------------------------------------------- -ii_lset:.macro - lea table+\1*4,a0 - move.l #ii_\1,(a0) - .endm; -ii_lset_dx:.macro // 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 - ii_lset_dxg \1,\2 - ii_lset_dxu \1,\2 - .endm; -ii_lset_dxg:.macro // gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 - lea table+0x\10\2*4,a0 - move.l #ii_0x\10\2,(a0) - lea 0x800(a0),a0 // 4 * 0x200 - move.l #ii_0x\12\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\14\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\16\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\18\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\1a\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\1c\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\1e\2,(a0) - .endm; -ii_lset_dxu:.macro // ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40 - lea table+0x\11\2*4,a0 - move.l #ii_0x\11\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\13\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\15\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\17\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\19\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\1b\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\1d\2,(a0) - lea 0x800(a0),a0 - move.l #ii_0x\1f\2,(a0) - .endm; - diff --git a/BaS_GNU/sources/ii_move.h b/BaS_GNU/sources/ii_move.h deleted file mode 100644 index 1ae8213..0000000 --- a/BaS_GNU/sources/ii_move.h +++ /dev/null @@ -1,1271 +0,0 @@ -//------------------------------------------------------------------- -// move -//------------------------------------------------------------------- -.extern ewf - -.text -ii_move_lset:.macro -//------------------------------------------------------------------------- -// 0x1000 move.b -//------------------------------------------------------------------------- -// move.x d16(ax),xxx.w 1=size 2=adress register - ii_lset_opeau 11,e -// move.x d16(ax),xxx.l - ii_lset_opeau 13,e -// move.x d16(pc),xxx.w - ii_lset 0x11fa -// move.x d16(pc),xxx.l - ii_lset 0x13fa -// move.x xxx.w,d16(ax) - ii_lset_dxu 1,78 -// move.x xxx.l,d16(ax) - ii_lset_dxu 1,79 -// move.x #xx,d16(ax) - ii_lset_dxu 1,7c -// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code - ii_lset 0x11f8 -// move.x xxx.l,xxx.w - ii_lset 0x11f9 -// move.x xxx.w,xxx.l - ii_lset 0x13f8 -// move.x xxx.l,xxx.l - ii_lset 0x13f9 -// move.x #xx,xxx.w //1=size 2=size dest adr 3=code - ii_lset 0x11fc -// move.x #xx,xxx.l //1=size 2=size dest adr 3=code - ii_lset 0x13fc -//--------------------------------------------------------------------- -// move.x ea,d8(ax,dy) ------------------------------------------- -//--------------------------------------------------------------------- -// move.x dx,d8(a0-a7,dy) - ii_lset_opeag 11,8 - ii_lset_opeag 13,8 - ii_lset_opeag 15,8 - ii_lset_opeag 17,8 - ii_lset_opeag 19,8 - ii_lset_opeag 1b,8 - ii_lset_opeag 1d,8 - ii_lset_opeag 1f,8 -// move.x (ax),d8(a0-a7,dy) -// move.x (ax)+,d8(a0-a7,dy) - ii_lset_opea 11,9 - ii_lset_opea 13,9 - ii_lset_opea 15,9 - ii_lset_opea 17,9 - ii_lset_opea 19,9 - ii_lset_opea 1b,9 - ii_lset_opea 1d,9 - ii_lset_opea 1f,9 -// move.x -(ax),d8(a0-a7,dy) - ii_lset_opeag 11,a - ii_lset_opeag 13,a - ii_lset_opeag 15,a - ii_lset_opeag 17,a - ii_lset_opeag 19,a - ii_lset_opeag 1b,a - ii_lset_opeag 1d,a - ii_lset_opeag 1f,a -//--------------------------------------------------------------------- -// move.x ea,d8(pc,dy) ------------------------------------------- -//--------------------------------------------------------------------- -// move.x dx,d8(pc,dy) - ii_lset_opeag 17,c -// move.x (ax),d8(pc,dy) -// move.x (ax)+,d8(pc,dy) - ii_lset_opea 17,d -// move.x -(ax),d8(pc,dy) - ii_lset_opeag 17,e -//--------------------------------------------------------------------- -// move.x d8(ax,dy),ea -------------------------------------------- -//--------------------------------------------------------------------- -// move.x d8(ax,dy),d0-d7 - ii_lset_opeag 10,3 - ii_lset_opeag 12,3 - ii_lset_opeag 14,3 - ii_lset_opeag 16,3 - ii_lset_opeag 18,3 - ii_lset_opeag 1a,3 - ii_lset_opeag 1c,3 - ii_lset_opeag 1e,3 -// move.x d8(ax,dy),a0-a7 - ii_lset_opeag 10,7 - ii_lset_opeag 12,7 - ii_lset_opeag 14,7 - ii_lset_opeag 16,7 - ii_lset_opeag 18,7 - ii_lset_opeag 1a,7 - ii_lset_opeag 1c,7 - ii_lset_opeag 1e,7 -// move.x d8(ax,dy),(a0)-(a7) - ii_lset_opeag 10,b - ii_lset_opeag 12,b - ii_lset_opeag 14,b - ii_lset_opeag 16,b - ii_lset_opeag 18,b - ii_lset_opeag 1a,b - ii_lset_opeag 1c,b - ii_lset_opeag 1e,b -// move.x d8(ax,dy),(a0)+-(a7)+ - ii_lset_opeag 10,f - ii_lset_opeag 12,f - ii_lset_opeag 14,f - ii_lset_opeag 16,f - ii_lset_opeag 18,f - ii_lset_opeag 1a,f - ii_lset_opeag 1c,f - ii_lset_opeag 1e,f -// move.x d8(ax,dy),-(a0) bis -(a7) - ii_lset_opeag 11,3 - ii_lset_opeag 13,3 - ii_lset_opeag 15,3 - ii_lset_opeag 17,3 - ii_lset_opeag 19,3 - ii_lset_opeag 1b,3 - ii_lset_opeag 1d,3 - ii_lset_opeag 1f,3 -//--------------------------------------------------------------------- -// move.x d8(pc,dy),ea -------------------------------------------- -//--------------------------------------------------------------------- -// move.x d8(pc,dy),d0-d7 - ii_lset_dxg 1,3b -// move.x d8(pc,dy),a0-a7 - ii_lset_dxg 1,7b -// move.x d8(pc,dy),(a0-a7) - ii_lset_dxg 1,bb -// move.x d8(pc,dy),(a0-a7)+ - ii_lset_dxg 1,fb -// move.x d8(pc,dy),(a0-a7)+ - ii_lset_dxu 1,3b -//------------------------------------------------------------------------- -// 0x2000 move.l -//------------------------------------------------------------------------- -// move.x d16(ax),xxx.w 1=size 2=adress register - ii_lset_opeau 21,e -// move.x d16(ax),xxx.l - ii_lset_opeau 23,e -// move.x d16(pc),xxx.w - ii_lset 0x21fa -// move.x d16(pc),xxx.l - ii_lset 0x23fa -// move.x xxx.w,d16(ax) - ii_lset_dxu 2,78 -// move.x xxx.l,d16(ax) - ii_lset_dxu 2,79 -// move.x #xx,d16(ax) - ii_lset_dxu 2,7c -// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code - ii_lset 0x21f8 -// move.x xxx.l,xxx.w - ii_lset 0x21f9 -// move.x xxx.w,xxx.l - ii_lset 0x23f8 -// move.x xxx.l,xxx.l - ii_lset 0x23f9 -// move.x #xx,xxx.w //1=size 2=size dest adr 3=code - ii_lset 0x21fc -// move.x #xx,xxx.l //1=size 2=size dest adr 3=code - ii_lset 0x23fc -// move.x ea,d8(ax,dy) ------------------------------------------- -// move.x dx,d8(a0-a7,dy) - ii_lset_opeag 21,8 - ii_lset_opeag 23,8 - ii_lset_opeag 25,8 - ii_lset_opeag 27,8 - ii_lset_opeag 29,8 - ii_lset_opeag 2b,8 - ii_lset_opeag 2d,8 - ii_lset_opeag 2f,8 -// move.x (ax),d8(a0-a7,dy) -// move.x (ax)+,d8(a0-a7,dy) - ii_lset_opea 21,9 - ii_lset_opea 23,9 - ii_lset_opea 25,9 - ii_lset_opea 27,9 - ii_lset_opea 29,9 - ii_lset_opea 2b,9 - ii_lset_opea 2d,9 - ii_lset_opea 2f,9 -// move.x -(ax),d8(a0-a7,dy) - ii_lset_opeag 21,a - ii_lset_opeag 23,a - ii_lset_opeag 25,a - ii_lset_opeag 27,a - ii_lset_opeag 29,a - ii_lset_opeag 2b,a - ii_lset_opeag 2d,a - ii_lset_opeag 2f,a -//--------------------------------------------------------------------- -// move.x ea,d8(pc,dy) ------------------------------------------- -//--------------------------------------------------------------------- -// move.x dx,d8(pc,dy) -// move.x ax,d8(pc,dy) - ii_lset_opea 27,c -// move.x (ax),d8(pc,dy) -// move.x (ax)+,d8(pc,dy) - ii_lset_opea 27,d -// move.x -(ax),d8(pc,dy) - ii_lset_opeag 27,e -//--------------------------------------------------------------------- -// move.x d8(ax,dy),ea -------------------------------------------- -//--------------------------------------------------------------------- -// move.x d8(ax,dy),d0-d7 - ii_lset_opeag 20,3 - ii_lset_opeag 22,3 - ii_lset_opeag 24,3 - ii_lset_opeag 26,3 - ii_lset_opeag 28,3 - ii_lset_opeag 2a,3 - ii_lset_opeag 2c,3 - ii_lset_opeag 2e,3 -// move.x d8(ax,dy),a0-a7 - ii_lset_opeag 20,7 - ii_lset_opeag 22,7 - ii_lset_opeag 24,7 - ii_lset_opeag 26,7 - ii_lset_opeag 28,7 - ii_lset_opeag 2a,7 - ii_lset_opeag 2c,7 - ii_lset_opeag 2e,7 -// move.x d8(ax,dy),(a0)-(a7) - ii_lset_opeag 20,b - ii_lset_opeag 22,b - ii_lset_opeag 24,b - ii_lset_opeag 26,b - ii_lset_opeag 28,b - ii_lset_opeag 2a,b - ii_lset_opeag 2c,b - ii_lset_opeag 2e,b -// move.x d8(ax,dy),(a0)+-(a7)+ - ii_lset_opeag 20,f - ii_lset_opeag 22,f - ii_lset_opeag 24,f - ii_lset_opeag 26,f - ii_lset_opeag 28,f - ii_lset_opeag 2a,f - ii_lset_opeag 2c,f - ii_lset_opeag 2e,f -// move.x d8(ax,dy),-(a0) bis -(a7) - ii_lset_opeag 21,3 - ii_lset_opeag 23,3 - ii_lset_opeag 25,3 - ii_lset_opeag 27,3 - ii_lset_opeag 29,3 - ii_lset_opeag 2b,3 - ii_lset_opeag 2d,3 - ii_lset_opeag 2f,3 -//--------------------------------------------------------------------- -// move.x d8(pc,dy),ea -------------------------------------------- -//--------------------------------------------------------------------- -// move.x d8(pc,dy),d0-d7 - ii_lset_dxg 2,3b -// move.x d8(pc,dy),a0-a7 - ii_lset_dxg 2,7b -// move.x d8(pc,dy),(a0-a7) - ii_lset_dxg 2,bb -// move.x d8(pc,dy),(a0-a7)+ - ii_lset_dxg 2,fb -// move.x d8(pc,dy),(a0-a7)+ - ii_lset_dxu 2,3b -//------------------------------------------------------------------------- -// 0x3000 move.w -///------------------------------------------------------------------------- -// move.x d16(ax),xxx.w 1=size 2=adress register - ii_lset_opeau 31,e -// move.x d16(ax),xxx.l - ii_lset_opeau 33,e -// move.x d16(pc),xxx.w - ii_lset 0x31fa -// move.x d16(pc),xxx.l - ii_lset 0x33fa -// move.x xxx.w,d16(ax) - ii_lset_dxu 3,78 -// move.x xxx.l,d16(ax) - ii_lset_dxu 3,79 -// move.x #xx,d16(ax) - ii_lset_dxu 3,7c -// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code - ii_lset 0x31f8 -// move.x xxx.l,xxx.w - ii_lset 0x31f9 -// move.x xxx.w,xxx.l - ii_lset 0x33f8 -// move.x xxx.l,xxx.l - ii_lset 0x33f9 -// move.x #xx,xxx.w //1=size 2=size dest adr 3=code - ii_lset 0x31fc -// move.x #xx,xxx.l //1=size 2=size dest adr 3=code - ii_lset 0x33fc -// move.x ea,d8(ax,dy) ------------------------------------------- -// move.x dx,d8(a0-a7,dy) - ii_lset_opeag 31,8 - ii_lset_opeag 33,8 - ii_lset_opeag 35,8 - ii_lset_opeag 37,8 - ii_lset_opeag 39,8 - ii_lset_opeag 3b,8 - ii_lset_opeag 3d,8 - ii_lset_opeag 3f,8 -// move.x (ax),d8(a0-a7,dy) -// move.x (ax)+,d8(a0-a7,dy) - ii_lset_opea 31,9 - ii_lset_opea 33,9 - ii_lset_opea 35,9 - ii_lset_opea 37,9 - ii_lset_opea 39,9 - ii_lset_opea 3b,9 - ii_lset_opea 3d,9 - ii_lset_opea 3f,9 -// move.x -(ax),d8(a0-a7,dy) - ii_lset_opeag 31,a - ii_lset_opeag 33,a - ii_lset_opeag 35,a - ii_lset_opeag 37,a - ii_lset_opeag 39,a - ii_lset_opeag 3b,a - ii_lset_opeag 3d,a - ii_lset_opeag 3f,a -//--------------------------------------------------------------------- -// move.x ea,d8(pc,dy) ------------------------------------------- -//--------------------------------------------------------------------- -// move.x dx,d8(pc,dy) -// move.x ax,d8(pc,dy) - ii_lset_opea 37,c -// move.x (ax),d8(pc,dy) -// move.x (ax)+,d8(pc,dy) - ii_lset_opea 37,d -// move.x -(ax),d8(pc,dy) - ii_lset_opeag 37,e -//--------------------------------------------------------------------- -// move.x d8(ax,dy),ea -------------------------------------------- -//--------------------------------------------------------------------- -// move.x d8(ax,dy),d0-d7 - ii_lset_opeag 30,3 - ii_lset_opeag 32,3 - ii_lset_opeag 34,3 - ii_lset_opeag 36,3 - ii_lset_opeag 38,3 - ii_lset_opeag 3a,3 - ii_lset_opeag 3c,3 - ii_lset_opeag 3e,3 -// move.x d8(ax,dy),a0-a7 - ii_lset_opeag 30,7 - ii_lset_opeag 32,7 - ii_lset_opeag 34,7 - ii_lset_opeag 36,7 - ii_lset_opeag 38,7 - ii_lset_opeag 3a,7 - ii_lset_opeag 3c,7 - ii_lset_opeag 3e,7 -// move.x d8(ax,dy),(a0)-(a7) - ii_lset_opeag 30,b - ii_lset_opeag 32,b - ii_lset_opeag 34,b - ii_lset_opeag 36,b - ii_lset_opeag 38,b - ii_lset_opeag 3a,b - ii_lset_opeag 3c,b - ii_lset_opeag 3e,b -// move.x d8(ax,dy),(a0)+-(a7)+ - ii_lset_opeag 30,f - ii_lset_opeag 32,f - ii_lset_opeag 34,f - ii_lset_opeag 36,f - ii_lset_opeag 38,f - ii_lset_opeag 3a,f - ii_lset_opeag 3c,f - ii_lset_opeag 3e,f -// move.x d8(ax,dy),-(a0) bis -(a7) - ii_lset_opeag 31,3 - ii_lset_opeag 33,3 - ii_lset_opeag 35,3 - ii_lset_opeag 37,3 - ii_lset_opeag 39,3 - ii_lset_opeag 3b,3 - ii_lset_opeag 3d,3 - ii_lset_opeag 3f,3 -//--------------------------------------------------------------------- -// move.x d8(pc,dy),ea -------------------------------------------- -//--------------------------------------------------------------------- -// move.x d8(pc,dy),d0-d7 - ii_lset_dxg 3,3b -// move.x d8(pc,dy),a0-a7 - ii_lset_dxg 3,7b -// move.x d8(pc,dy),(a0-a7) - ii_lset_dxg 3,bb -// move.x d8(pc,dy),(a0-a7)+ - ii_lset_dxg 3,fb -// move.x d8(pc,dy),(a0-a7)+ - ii_lset_dxu 3,3b -.endm -//--------------------------------------------------------------------------------------------- -// function -//--------------------------------------------------------------------------------------------- -ii_move_op:.macro -// move.x d16(ax),xxx.w 1=size 2=adress register - ii_move_d16ax_xxx 1e8,a0_off(a7),w - ii_move_d16ax_xxx 1e9,a1_off(a7),w - ii_move_d16ax_xxx 1ea,a2,w - ii_move_d16ax_xxx 1eb,a3,w - ii_move_d16ax_xxx 1ec,a4,w - ii_move_d16ax_xxx 1ed,a5,w - ii_move_d16ax_xxx 1ee,a6,w - ii_move_d16ax_xxx 1ef,usp,w -// move.x d16(ax),xxx.l - ii_move_d16ax_xxx 3e8,a0_off(a7),l - ii_move_d16ax_xxx 3e9,a1_off(a7),l - ii_move_d16ax_xxx 3ea,a2,l - ii_move_d16ax_xxx 3eb,a3,l - ii_move_d16ax_xxx 3ec,a4,l - ii_move_d16ax_xxx 3ed,a5,l - ii_move_d16ax_xxx 3ee,a6,l - ii_move_d16ax_xxx 3ef,usp,l -// move.x d16(pc),xxx.w - ii_move_d16ax_xxx 1fa,a0,w -// move.x d16(pc),xxx.l - ii_move_d16ax_xxx 3fa,a0,l -// move.x xxx.w,d16(ax) -// move.x xxx.l,d16(ax) -// move.x #xx,d16(ax) - ii_move_xxx_d16ax 1,a0_off(a7) - ii_move_xxx_d16ax 3,a1_off(a7) - ii_move_xxx_d16ax 5,a2 - ii_move_xxx_d16ax 7,a3 - ii_move_xxx_d16ax 9,a4 - ii_move_xxx_d16ax b,a5 - ii_move_xxx_d16ax d,a6 - ii_move_xxx_d16ax f,usp -// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code - ii_move_xxx_xxx b,w,w,11f8 - ii_move_xxx_xxx l,w,w,21f8 - ii_move_xxx_xxx w,w,w,31f8 -// move.x xxx.l,xxx.w - ii_move_xxx_xxx b,l,w,11f9 - ii_move_xxx_xxx l,l,w,21f9 - ii_move_xxx_xxx w,l,w,31f9 -// move.x xxx.w,xxx.l - ii_move_xxx_xxx b,w,l,13f8 - ii_move_xxx_xxx l,w,l,23f8 - ii_move_xxx_xxx w,w,l,33f8 -// move.x xxx.l,xxx.l - ii_move_xxx_xxx b,l,l,13f9 - ii_move_xxx_xxx l,l,l,23f9 - ii_move_xxx_xxx w,l,l,33f9 -// move.x #xx,xxx.w //1=size 2=size dest adr 3=code - ii_move_im_xxx b,w,11fc - ii_move_im_xxx l,w,21fc - ii_move_im_xxx w,w,31fc -// move.x #xx,xxx.l //1=size 2=size dest adr 3=code - ii_move_im_xxx b,l,13fc - ii_move_im_xxx l,l,23fc - ii_move_im_xxx w,l,33fc -//--------------------------------------------------------------------- -// move.x ea,d8(ax,dy) ------------------------------------------- -//--------------------------------------------------------------------- -// move.x dx,d8(ax/pc,dy) - ii_move_dxxia d0_off(a7),80,id,d,c0 - ii_move_dxxia d1_off(a7),81,id,d,c1 - ii_move_dxxia d2,82,d,d,c2 - ii_move_dxxia d3,83,d,d,c3 - ii_move_dxxia d4,84,d,d,c4 - ii_move_dxxia d5,85,d,d,c5 - ii_move_dxxia d6,86,d,d,c6 - ii_move_dxxia d7,87,d,d,c7 -// move.x ax,d8(ax/pc,dy) - ii_move_dxxia a0_off(a7),88,id,d,c8 - ii_move_dxxia a1_off(a7),89,id,d,c9 - ii_move_dxxia a2,8a,d,da,ca - ii_move_dxxia a3,8b,d,da,cb - ii_move_dxxia a4,8c,d,da,cc - ii_move_dxxia a5,8d,d,da,cd - ii_move_dxxia a6,8e,d,da,ce - ii_move_dxxia a7,8f,a7,da,cf -// move.x (ax),d8(ax/pc,dy) - ii_move_dxxia a0_off(a7),90,ia,d,d0 - ii_move_dxxia a1_off(a7),91,ia,d,d1 - ii_move_dxxia (a2),92,d,d,d2 - ii_move_dxxia (a3),93,d,d,d3 - ii_move_dxxia (a4),94,d,d,d4 - ii_move_dxxia (a5),95,d,d,d5 - ii_move_dxxia (a6),96,d,d,d6 - ii_move_dxxia (a7),97,a7,d,d7 -// move.x (ax)+,d8(ax/pc,dy) - ii_move_dxxia a0_off(a7),98,iap,d,d8 - ii_move_dxxia a1_off(a7),99,iap,d,d9 - ii_move_dxxia (a2)+,9a,d,d,da - ii_move_dxxia (a3)+,9b,d,d,db - ii_move_dxxia (a4)+,9c,d,d,dc - ii_move_dxxia (a5)+,9d,d,d,dd - ii_move_dxxia (a6)+,9e,d,d,de - ii_move_dxxia (a7)+,9f,a7,d,df -// move.x -(ax),d8(ax/pc,dy) - ii_move_dxxia a0_off(a7),a0,iam,d,e0 - ii_move_dxxia a1_off(a7),a1,iam,d,e1 - ii_move_dxxia -(a2),a2,d,d,e2 - ii_move_dxxia -(a3),a3,d,d,e3 - ii_move_dxxia -(a4),a4,d,d,e4 - ii_move_dxxia -(a5),a5,d,d,e5 - ii_move_dxxia -(a6),a6,d,d,e6 - ii_move_dxxia -(a7),a7,a7,d,e7 -//--------------------------------------------------------------------- -// move.x d8(ax/pc,dy),ea -------------------------------------------- -//--------------------------------------------------------------------- -// move.x d8(ax/pc,dy),dz - ii_move_d8_dest d0,id,03,dx - ii_move_d8_dest d1,id,23,dx - ii_move_d8_dest d2,d,43,dx - ii_move_d8_dest d3,d,63,dx - ii_move_d8_dest d4,d,83,dx - ii_move_d8_dest d5,d,a3,dx - ii_move_d8_dest d6,d,c3,dx - ii_move_d8_dest d7,d,e3,dx -// move.x d8(ax/pc,dy),az - ii_move_d8_dest a0,id,07,ax - ii_move_d8_dest a1,id,27,ax - ii_move_d8_dest a2,d,47,ax - ii_move_d8_dest a3,d,67,ax - ii_move_d8_dest a4,d,87,ax - ii_move_d8_dest a5,d,a7,ax - ii_move_d8_dest a6,d,c7,ax - ii_move_d8_dest usp,id,e7,ax -// move.x d8(ax/pc,dy),(az) - ii_move_d8_dest a0_off(a7),id,0b,ia - ii_move_d8_dest a1_off(a7),id,2b,ia - ii_move_d8_dest (a2),d,4b,ia - ii_move_d8_dest (a3),d,6b,ia - ii_move_d8_dest (a4),d,8b,ia - ii_move_d8_dest (a5),d,ab,ia - ii_move_d8_dest (a6),d,cb,ia - ii_move_d8_dest usp,id,eb,ia -// move.x d8(ax/pc,dy),(az)+ - ii_move_d8_dest a0_off(a7),id,0f,iap - ii_move_d8_dest a1_off(a7),id,2f,iap - ii_move_d8_dest (a2)+,d,4f,iap - ii_move_d8_dest (a3)+,d,6f,iap - ii_move_d8_dest (a4)+,d,8f,iap - ii_move_d8_dest (a5)+,d,af,iap - ii_move_d8_dest (a6)+,d,cf,iap - ii_move_d8_dest usp,id,ef,iap -// move.x d8(ax/pc,dy),-(az) - ii_move_d8_dest a0_off(a7),id,13,iam - ii_move_d8_dest a1_off(a7),id,33,iam - ii_move_d8_dest -(a2),d,53,iam - ii_move_d8_dest -(a3),d,73,iam - ii_move_d8_dest -(a4),d,93,iam - ii_move_d8_dest -(a5),d,b3,iam - ii_move_d8_dest -(a6),d,d3,iam - ii_move_d8_dest usp,id,f3,iam -.endm //end function -//==================================================================== -// subs ---------------------------------------------------------- -//==================================================================== -// move.x d16(ax),xxx.w/l 1=code 2=adress register 3=dest adr size -ii_move_d16ax_xxx:.macro -ii_0x1\1: //byt: -#ifdef halten_move - halt -#endif - mvs.w (a0)+,d0 - move.l \2,a1 - add.l d0,a1 - move.b (a1),d0 - move.\3 (a0)+,a1 - move.b d0,(a1) - set_cc0 - ii_end -ii_0x2\1: //long: -#ifdef halten_move - halt -#endif - mvs.w (a0)+,d0 - move.l \2,a1 - add.l d0,a1 - move.l (a1),d0 - move.\3 (a0)+,a1 - move.l d0,(a1) - set_cc0 - ii_end -ii_0x3\1: //word: -#ifdef halten_move - halt -#endif - mvs.w (a0)+,d0 - move.l \2,a1 - add.l d0,a1 - move.w (a1),d0 - move.\3 (a0)+,a1 - move.w d0,(a1) - set_cc0 - ii_end -.endm -//---------------------------------------- -// move.x xxx.w,d16(ax) -// move.x xxx.l,d16(ax) -// move.x #xx,d16(ax) -ii_move_xxx_d16ax:.macro //1=code 2=adress register -ii_0x1\178: //byt xxx.w -#ifdef halten_move - halt -#endif - move.w (a0)+,a1 - move.b (a1),d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - move.b d0,(a1) - set_cc0 - ii_end -ii_0x1\179: //byt xxx.l -#ifdef halten_move - halt -#endif - move.l (a0)+,a1 - move.b (a1),d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - move.b d0,(a1) - set_cc0 - ii_end -ii_0x1\17c: //byt #x -#ifdef halten_move - halt -#endif - mvs.b (a0)+,d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - move.b d0,(a1) - set_cc0 - ii_end -ii_0x2\178: //long xxx.w -#ifdef halten_move - halt -#endif - move.w (a0)+,a1 - move.l (a1),d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - move.l d0,(a1) - set_cc0 - ii_end -ii_0x2\179: //long xxx.l -#ifdef halten_move - halt -#endif - move.l (a0)+,a1 - move.l (a1),d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - move.l d0,(a1) - set_cc0 - ii_end -ii_0x2\17c: //long #x -#ifdef halten_move - halt -#endif - move.l (a0)+,d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - move.l d0,(a1) - set_cc0 - ii_end - ii_end -ii_0x3\178: //word xxx.w -#ifdef halten_move - halt -#endif - move.w (a0)+,a1 - move.w (a1),d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - move.w d0,(a1) - set_cc0 - ii_end -ii_0x3\179: //word xxx.l -#ifdef halten_move - halt -#endif - move.l (a0)+,a1 - move.w (a1),d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - move.w d0,(a1) - set_cc0 - ii_end -ii_0x3\17c: //word #x -#ifdef halten_move - halt -#endif - move.w (a0)+,d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - move.w d0,(a1) - set_cc0 - ii_end -.endm -// move.x xxx,xxx -ii_move_xxx_xxx:.macro //1=size 2=size source adr 3=size dest adr 4=code -ii_0x\4: -#ifdef halten_move - halt -#endif - move.\2 (a0)+,a1 - move.\1 (a1),d0 - move.\3 (a0)+,d1 - move.\1 d0,(a1) - set_cc0 - ii_end -.endm -// move.x im,xxx -ii_move_im_xxx:.macro //1=size 2=size dest adr 3=code -ii_0x\3: -#ifdef halten_move - halt -#endif -.ifc 1,b - move.w (a0)+,d0 -.else - move.\1 (a0)+,d0 -.endif - move.\2 (a0)+,a1 - move.\1 d0,(a1) - set_cc0 - ii_end -.endm -//--------------------------------------------------------------------- -// move.x ea,d8(ax,dy) ------------------------------------------- -//--------------------------------------------------------------------- -// ea=dx,ax,(ax),(ax)+,-(ax) -//--------------------------------------------------------------------- -ii_move_dxxia:.macro //1=source 2=code 1.stelle 3=code 2 letzte Stellen 4=art 5=code d8(pc,dy) -.ifc \3,id - ii_move_dxxi b,\1+3,1,\2,\3,\5 - ii_move_dxxi w,\1+2,2,\2,\3,\5 - ii_move_dxxi l,\1,3,\2,\3,\5 -.else - .ifc \4,da - ii_move_dxxi w,\1,2,\2,\3,\5 - ii_move_dxxi l,\1,3,\2,\3,\5 - .else - ii_move_dxxi b,\1,1,\2,\3,\5 - ii_move_dxxi w,\1,2,\2,\3,\5 - ii_move_dxxi l,\1,3,\2,\3,\5 - .endif -.endif -.endm - -ii_move_dxxi:.macro -ii_0x\31\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen -#ifdef halten_move - halt -#endif - move.l a0_off(a7),a1 - move_end \1,\2,\5 -ii_0x\33\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen -#ifdef halten_move - halt -#endif - move.l a1_off(a7),a1 - move_end \1,\2,\5 -ii_0x\35\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen -#ifdef halten_move - halt -#endif - move.l a2,a1 - move_end \1,\2,\5 -ii_0x\37\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen -#ifdef halten_move - halt -#endif - move.l a3,a1 - move_end \1,\2,\5 -ii_0x\39\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen -#ifdef halten_move - halt -#endif - move.l a4,a1 - move_end \1,\2,\5 -ii_0x\3b\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen -#ifdef halten_move - halt -#endif - move.l a5,a1 - move_end \1,\2,\5 -ii_0x\3d\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen -#ifdef halten_move - halt -#endif - move.l a6,a1 - move_end \1,\2,\5 -ii_0x\3f\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen -#ifdef halten_move - halt -#endif - move.l usp,a1 - move_end \1,\2,\5 -ii_0x\37\6: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen -#ifdef halten_move - halt -#endif - move.l a0,a1 - move_end \1,\2,\5 -.endm -//------------------------------------ -move_end:.macro - jsr ewf -.ifc 3,a7 - move.l a7,d1 // a7 sichern - move.l usp,a7 // a7 holen -.endif -.ifc 3,ia - move.l a2,d1 // a2 sichern - move.l \2,a2 - move.\2 (a2),(a1) - move.l d1,a2 // a2 zurück -.else - .ifc 3,iap - move.l a2,d1 // a2 sichern - move.l \2,a2 - move.\2 (a2)+,(a1) - .else - .ifc 3,iam - move.l a2,d1 // a2 sichern - move.l \2,a2 - move.\2 -(a2),(a1) - .else - move.\1 \2,(a1) - .endif - .endif -.endif -.ifc 3,a7 - movea.l a7,usp // a7 zurück - movea.l d1,a7 // a7 setzen -.endif - set_cc0 -.ifc 3,iap - move.l d1,a2 // a2 zurück -.endif -.ifc 3,iam - move.l d1,a2 // a2 zurück -.endif - ii_end -.endm -//--------------------------------------------------------------------- -// move.x ea,d8(pc,dy) -//--------------------------------------------------------------------- - -//--------------------------------------------------------------------- -// move.x d8(ax,dy),ea --------------------------------------------- -//--------------------------------------------------------------------- -ii_move_d8_dest:.macro //1=dest 2=art 3=code 2.+3.stelle 4=art adresse -//byt -ii_0x1\30: -#ifdef halten_move - halt -#endif - move.l a0_off(a7),a1 - moveb_a1_src\4 \1,\2 -ii_0x1\31: -#ifdef halten_move - halt -#endif - move.l a1_off(a7),a1 - moveb_a1_src\4 \1,\2 -ii_0x1\32: -#ifdef halten_move - halt -#endif - move.l a2,a1 - moveb_a1_src\4 \1,\2 -ii_0x1\33: -#ifdef halten_move - halt -#endif - move.l a3,a1 - moveb_a1_src\4 \1,\2 -ii_0x1\34: -#ifdef halten_move - halt -#endif - move.l a4,a1 - moveb_a1_src\4 \1,\2 -ii_0x1\35: -#ifdef halten_move - halt -#endif - move.l a5,a1 - moveb_a1_src\4 \1,\2 -ii_0x1\36: -#ifdef halten_move - halt -#endif - move.l a6,a1 - moveb_a1_src\4 \1,\2 -ii_0x1\37: -#ifdef halten_move - halt -#endif - move.l usp,a1 - moveb_a1_src\4 \1,\2 -ii_0x1\3b: -#ifdef halten_move - halt -#endif - move.l a0,a1 - moveb_a1_src\4 \1,\2 -//long -ii_0x2\30: -#ifdef halten_move - halt -#endif - move.l a0_off(a7),a1 - movel_a1_src\4 \1,\2 -ii_0x2\31: -#ifdef halten_move - halt -#endif - move.l a1_off(a7),a1 - movel_a1_src\4 \1,\2 -ii_0x2\32: -#ifdef halten_move - halt -#endif - move.l a2,a1 - movel_a1_src\4 \1,\2 -ii_0x2\33: -#ifdef halten_move - halt -#endif - move.l a3,a1 - movel_a1_src\4 \1,\2 -ii_0x2\34: -#ifdef halten_move - halt -#endif - move.l a4,a1 - movel_a1_src\4 \1,\2 -ii_0x2\35: -#ifdef halten_move - halt -#endif - move.l a5,a1 - movel_a1_src\4 \1,\2 -ii_0x2\36: -#ifdef halten_move - halt -#endif - move.l a6,a1 - movel_a1_src\4 \1,\2 -ii_0x2\37: -#ifdef halten_move - halt -#endif - move.l usp,a1 - movel_a1_src\4 \1,\2 -ii_0x2\3b: -#ifdef halten_move - halt -#endif - move.l a0,a1 - moveb_a1_src\4 \1,\2 -//word -ii_0x3\30: -#ifdef halten_move - halt -#endif - move.l a0_off(a7),a1 - movew_a1_src\4 \1,\2 -ii_0x3\31: -#ifdef halten_move - halt -#endif - move.l a1_off(a7),a1 - movew_a1_src\4 \1,\2 -ii_0x3\32: -#ifdef halten_move - halt -#endif - move.l a2,a1 - movew_a1_src\4 \1,\2 -ii_0x3\33: -#ifdef halten_move - halt -#endif - move.l a3,a1 - movew_a1_src\4 \1,\2 -ii_0x3\34: -#ifdef halten_move - halt -#endif - move.l a4,a1 - movew_a1_src\4 \1,\2 -ii_0x3\35: -#ifdef halten_move - halt -#endif - move.l a5,a1 - movew_a1_src\4 \1,\2 -ii_0x3\36: -#ifdef halten_move - halt -#endif - move.l a6,a1 - movew_a1_src\4 \1,\2 -ii_0x3\37: -#ifdef halten_move - halt -#endif - move.l usp,a1 - movew_a1_src\4 \1,\2 -ii_0x3\3b: -#ifdef halten_move - halt -#endif - move.l a0,a1 - moveb_a1_src\4 \1,\2 -.endm -//--------------------------------------------------------------------- -//dx -moveb_a1_srcdx:.macro - jsr ewf -.ifc \2,id - move.b (a1),\1_off+3(a7) -.else - move.b (a1),\1 -.endif - set_cc0 - ii_end -.endm -movel_a1_srcdx:.macro - jsr ewf -.ifc \2,id - move.l (a1),\1_off(a7) -.else - move.l (a1),\1 -.endif - set_cc0 - ii_end -.endm -movew_a1_srcdx:.macro - jsr ewf -.ifc \2,id - move.w (a1),\1_off+2(a7) -.else - move.w (a1),\1 -.endif - set_cc0 - ii_end -.endm -// ax -moveb_a1_srcax:.macro - jsr ewf -.ifc \2,id - .ifc \1,usp - move.w (a1),a1 - move.l a1,usp - .else - move.w (a1),\1_off+2(a7) - .endif -.else - move.w (a1),\1 -.endif - set_cc0 - ii_end -.endm -movel_a1_srcax:.macro - jsr ewf -.ifc \2,id - .ifc \1,usp - move.l (a1),a1 - move.l a1,usp - .else - move.l (a1),\1_off(a7) - .endif -.else - move.l (a1),\1 -.endif - set_cc0 - ii_end -.endm -movew_a1_srcax:.macro - jsr ewf -.ifc \2,id - .ifc \1,usp - move.w (a1),a1 - move.l a1,usp - .else - move.w (a1),\1_off+2(a7) - .endif -.else - move.w (a1),\1 -.endif - set_cc0 - ii_end -.endm -// (ax) -moveb_a1_srcia:.macro - jsr ewf -.ifc \2,id - move.b (a1),d0 - move.l \1,a1 - move.b d0,(a1) -.else - move.b (a1),\1 -.endif - set_cc0 - ii_end -.endm -movel_a1_srcia:.macro - jsr ewf -.ifc \2,id - move.l (a1),d0 - move.l \1,a1 - move.l d0,(a1) -.else - move.l (a1),\1 -.endif - set_cc0 - ii_end -.endm -movew_a1_srcia:.macro - jsr ewf -.ifc \2,id - move.w (a1),d0 - move.l \1,a1 - move.w d0,(a1) -.else - move.w (a1),\1 -.endif - set_cc0 - ii_end -.endm -// (ax)+ -moveb_a1_srciap:.macro - jsr ewf -.ifc \2,id - move.b (a1),d0 - move.l \1,a1 - move.b d0,(a1)+ - move.l a1,\1 -.else - move.b (a1),\1 -.endif - set_cc0 - ii_end -.endm -movel_a1_srciap:.macro - jsr ewf -.ifc \2,id - move.l (a1),d0 - move.l \1,a1 - move.l d0,(a1)+ - move.l a1,\1 -.else - move.l (a1),\1 -.endif - set_cc0 - ii_end -.endm -movew_a1_srciap:.macro - jsr ewf -.ifc \2,id - move.w (a1),d0 - move.l \1,a1 - move.w d0,(a1)+ - move.l a1,\1 -.else - move.w (a1),\1 -.endif - set_cc0 - ii_end -.endm -// -(ax) -moveb_a1_srciam:.macro - jsr ewf -.ifc \2,id - move.b (a1),d0 - move.l \1,a1 - move.b d0,-(a1) - move.l a1,\1 -.else - move.b (a1),\1 -.endif - set_cc0 - ii_end -.endm -movel_a1_srciam:.macro - jsr ewf -.ifc \2,id - move.l (a1),d0 - move.l \1,a1 - move.l d0,-(a1) - move.l a1,\1 -.else - move.l (a1),\1 -.endif - set_cc0 - ii_end -.endm -movew_a1_srciam:.macro - jsr ewf -.ifc \2,id - move.w (a1),d0 - move.l \1,a1 - move.w d0,-(a1) - move.l a1,\1 -.else - move.w (a1),\1 -.endif - set_cc0 - ii_end -.endm - -//--------------------------------------------------------------------- -// move.x d8(pc,dy),ea -//--------------------------------------------------------------------- - - - -/*============================================================ -// move.w dx,(a0,dx.w*SF) - ii_lset 0x3180 - ii_lset 0x3181 - ii_lset 0x3182 - ii_lset 0x3183 - ii_lset 0x3184 - ii_lset 0x3185 - ii_lset 0x3186 - ii_lset 0x3187 - -//-------------------------------------------------------------------- -// // move.w dx,d(ay,dz.w*sf) -//-------------------------------------------------------------------- -movew_ewfw:.macro - move.l \2,a1 - jsr ewf - move.w \1,(a1) - set_cc0 - ii_end - .endm -ii_0x3180: - movew_ewfw d0_off+2(a7),a0_off(a7) -ii_0x3181: - movew_ewfw d0_off+2(a7),a0_off(a7) -ii_0x3182: - movew_ewfw d2,a0_off(a7) -ii_0x3183: - movew_ewfw d3,a0_off(a7) -ii_0x3184: - movew_ewfw d4,a0_off(a7) -ii_0x3185: - movew_ewfw d5,a0_off(a7) -ii_0x3186: - movew_ewfw d6,a0_off(a7) -ii_0x3187: - movew_ewfw d7,a0_off(a7) diff --git a/BaS_GNU/sources/ii_movem.h b/BaS_GNU/sources/ii_movem.h deleted file mode 100644 index 5e8a470..0000000 --- a/BaS_GNU/sources/ii_movem.h +++ /dev/null @@ -1,374 +0,0 @@ -//***********************************************************************************/ -// movem -//***********************************************************************************/ -ii_movem_lset: .macro -// movem.l rx,xxx.L - ii_lset 0x48f9 -// movem.l xxx.L,rx - ii_lset 0x4cf9 -// movem.w rx,xxx.L - ii_lset 0x48b9 -// movem.w xxx.L,rx - ii_lset 0x4cb9 -// movem.l rx,-(ax) - ii_lset 0x48e0 - ii_lset 0x48e1 - ii_lset 0x48e2 - ii_lset 0x48e3 - ii_lset 0x48e4 - ii_lset 0x48e5 - ii_lset 0x48e6 - ii_lset 0x48e7 -// movem.l (ax)+,rx - ii_lset 0x4cd8 - ii_lset 0x4cd9 - ii_lset 0x4cda - ii_lset 0x4cdb - ii_lset 0x4cdc - ii_lset 0x4cdd - ii_lset 0x4cde - ii_lset 0x4cdf -.endm -//***********************************************************************************/ -ii_movem_func: .macro -//------------------------------------------------------------------- -// movem.l -//-------------------------------------------------------------------- -// movem.l (ax)+,reg -//-------------------------------------------------------------------- - .long 0 -az_reg_table: - .byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f - .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f - .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f - .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50 - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60 - .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70 - .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90 - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0 - .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0 - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0 - .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0 - .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0 - .byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0 -//------------------------------------------------------------------------------- -ii_0x48e0: // movem.l reglist,-(a0) - mvm_mem_macro 0x48d0,a0_off(a7),2 -ii_0x48e1: // movem.l reglist,-(a1) - mvm_mem_macro 0x48d1,a1_off(a7),2 -ii_0x48e2: // movem.l reglist,-(a2) - mvm_mem_macro 0x48d2,a2,2 -ii_0x48e3: // movem.l reglist,-(a3) - mvm_mem_macro 0x48d3,a3,2 -ii_0x48e4: // movem.l reglist,-(a4) - mvm_mem_macro 0x48d4,a4,2 -ii_0x48e5: // movem.l reglist,-(a5) - mvm_mem_macro 0x48d5,a5,2 -ii_0x48e6: // movem.l reglist,-(a6) - mvm_mem_macro 0x48d6,a6,2 -ii_0x48e7: // movem.l reglist,-(a7) - mvm_mem_macro 0x48d7,usp,2 -//------------------------------------------------------------------------------- -ii_0x4cd8: // movem.l (a0)+,reglist - mvm_reg_macro 0x4cd0,0x41e8,2 -ii_0x4cd9: // movem.l (a1)+,reglist - mvm_reg_macro 0x4cd1,0x43e9,2 -ii_0x4cda: // movem.l (a2)+,reglist - mvm_reg_macro 0x4cd2,0x45ea,2 -ii_0x4cdb: // movem.l (a3)+,reglist - mvm_reg_macro 0x4cd3,0x47eb,2 -ii_0x4cdc: // movem.l (a4)+,reglist - mvm_reg_macro 0x4cd4,0x49ec,2 -ii_0x4cdd: // movem.l (a5)+,reglist - mvm_reg_macro 0x4cd5,0x4bed,2 -ii_0x4cde: // movem.l (a6)+,reglist - mvm_reg_macro 0x4cd6,0x4dee,2 -ii_0x4cdf: // movem.l (a7)+,reglist - mvm_reg_macro 0x4cd7,0x4fef,2 -//---------------------------------------------------------------------------- -ii_0x48f9: // movem.l reg,xxx.L -#ifdef halten_movem - halt -#endif - move.w (a0)+,d0 - move.l (a0)+,a1 - movemrm_macro l -//--------------------------------------------------------------------------------------------- -ii_0x4cf9: // movem.l xxx.L,reg -#ifdef halten_movem - halt -#endif - move.w (a0)+,d0 - move.l (a0)+,a1 - movemmr_macro l -//---------------------------------------------------------------------------- -ii_0x48b9: // movem.w reg,xxx.L -#ifdef halten_movem - halt -#endif - move.w (a0)+,d0 - move.l (a0)+,a1 - movemrm_macro w -//--------------------------------------------------------------------------------------------- -ii_0x4cb9: // movem.w xxx.L,reg -#ifdef halten_movem - halt -#endif - move.w (a0)+,d0 - move.l (a0)+,a1 - movemmr_macro w -.endm -//============================================================== -mvm_mem_macro:.macro -#ifdef halten_movem - halt -#endif - lea az_reg_table,a1 - mvz.b (a0),d1 - mvz.b 0(a1,d1)+,d0 - mvz.b 1(a0),d1 - mvz.b 0(a1,d1)+,d1 - add.l d0,d1 - lsl.l #\3,d1 // * anzahl byts pro wert - move.l \2,a1 - sub.l d1,a1 // ax-anzahl byts - move.l a1,\2 - lea ___RAMBAR1,a1 - move.l a1,pc_off(a7) - move.l a1,d0 - addq.l #1,d0 - movec d0,RAMBAR1 - move.w #\1,(a1)+ // movem.x reg_list,-(a7) - move.w (a0)+,(a1)+ // register list - move.w #0x4ef9,(a1)+ // jmp.l - move.l a0,(a1) // rücksprungadresse - move.l #___RAMBAR1 + 0x81,d0 // instruction - movec d0,RAMBAR1 - movem.l (a7),d0/d1/a0/a1 - lea ii_ss(a7),a7 // stack erhöhen - rte -.endm -//--------------------------------------------------------------------------------- -mvm_reg_macro:.macro -#ifdef halten_movem - halt -#endif - lea az_reg_table,a1 - mvz.b (a0),d1 - mvz.b 0(a1,d1)+,d0 - mvz.b 1(a0),d1 - mvz.b 0(a1,d1)+,d1 - add.l d0,d1 - lea ___RAMBAR1,a1 - move.l a1,pc_off(a7) - move.l a1,d0 - addq.l #1,d0 - movec d0,RAMBAR1 - move.w #\1,(a1)+ // movem.x (ax),reg_list - move.w (a0)+,(a1)+ // register list - move.w #\2,(a1)+ // lea 0(ax),ax - lsl.l #\3,d1 // * anzahl byts pro wert - move.w d1,(a1)+ // offset von lea - move.w #0x4ef9,(a1)+ // jmp.l - move.l a0,(a1) // rücksprungadresse - move.l #___RAMBAR1 + 0x81,d0 // instruction - movec d0,RAMBAR1 - movem.l (a7),d0/d1/a0/a1 - lea ii_ss(a7),a7 // stack erhöhen - rte -.endm -//--------------------------------------------------------------------------------- -movemrm_macro:.macro // in d0 register liste, in a1 zieladresse -#ifdef halten_movem - halt -#endif - tst.b d0 // datenregister zu verschieben? - bne mrm_dx\@ // ja-> - lsr.l #8,d0 // sonst zu addressregister - jmp mmrm_nd7\@ // -> -mrm_dx\@: - lsr.l #1,d0 - bcc mmrm_nd0\@ -.ifc 1,l - move.l d0_off(a7),(a1)+ -.else - move.w d0_off+2(a7),(a1)+ -.endif -mmrm_nd0\@: - lsr.l #1,d0 - bcc mmrm_nd1\@ -.ifc 1,l - move.l d1_off(a7),(a1)+ -.else - move.w d1_off+2(a7),(a1)+ -.endif -mmrm_nd1\@: - lsr.l #1,d0 - bcc mmrm_nd2\@ - move.\1 d2,(a1)+ -mmrm_nd2\@: - lsr.l #1,d0 - bcc mmrm_nd3\@ - move.\1 d3,(a1)+ -mmrm_nd3\@: - lsr.l #1,d0 - bcc mmrm_nd4\@ - move.\1 d4,(a1)+ -mmrm_nd4\@: - lsr.l #1,d0 - bcc mmrm_nd5\@ - move.\1 d5,(a1)+ -mmrm_nd5\@: - lsr.l #1,d0 - bcc mmrm_nd6\@ - move.l d6,(a1)+ -mmrm_nd6\@: - lsr.l #1,d0 - bcc mmrm_nd7\@ - move.\1 d7,(a1)+ -mmrm_nd7\@: - tst.b d0 // addressregister zu verschieben? - beq mmrm_na7\@ - lsr.l #1,d0 - bcc mmrm_na0\@ -.ifc 1,l - move.l a0_off(a7),(a1)+ -.else - move.w a0_off+2(a7),(a1)+ -.endif -mmrm_na0\@: - lsr.l #1,d0 - bcc mmrm_na1\@ -.ifc 1,l - move.l a1_off(a7),(a1)+ -.else - move.w a1_off+2(a7),(a1)+ -.endif -mmrm_na1\@: - lsr.l #1,d0 - bcc mmrm_na2\@ - move.\1 a2,(a1)+ -mmrm_na2\@: - lsr.l #1,d0 - bcc mmrm_na3\@ - move.\1 a3,(a1)+ -mmrm_na3\@: - lsr.l #1,d0 - bcc mmrm_na4\@ - move.\1 a4,(a1)+ -mmrm_na4\@: - lsr.l #1,d0 - bcc mmrm_na5\@ - move.\1 a5,(a1)+ -mmrm_na5\@: - lsr.l #1,d0 - bcc mmrm_na6\@ - move.\1 a6,(a1)+ -mmrm_na6\@: - lsr.l #1,d0 - bcc mmrm_na7\@ - move.l a0,d1 // sichern - move.l usp,a0 // ist ja usp - move.\1 a0,(a1)+ // nach a0 - move.l d1,a0 // pc zurück -mmrm_na7\@: - ii_end - .endm -//--------------------------------------------------------------------------------------------- -movemmr_macro:.macro // in d0 register liste, in a1 source adr -#ifdef halten_movem - halt -#endif - tst.b d0 // datenregister zu verschieben? - bne mmr_dx\@ // ja-> - lsr.l #8,d0 // sonst zu addressregister - bra mmmr_nd7\@ // -> -mmr_dx\@: - lsr.l #1,d0 - bcc mmmr_nd0\@ -.ifc 1,l - move.l (a1)+,d0_off(a7) -.else - move.w (a1)+,d0_off+2(a7) -.endif -mmmr_nd0\@: - lsr.l #1,d0 - bcc mmmr_nd1\@ -.ifc 1,l - move.l (a1)+,d1_off(a7) -.else - move.w (a1)+,d1_off+2(a7) -.endif -mmmr_nd1\@: - lsr.l #1,d0 - bcc mmmr_nd2\@ - move.\1 (a1)+,d2 -mmmr_nd2\@: - lsr.l #1,d0 - bcc mmmr_nd3\@ - move.\1 (a1)+,d3 -mmmr_nd3\@: - lsr.l #1,d0 - bcc mmmr_nd4\@ - move.\1 (a1)+,d4 -mmmr_nd4\@: - lsr.l #1,d0 - bcc mmmr_nd5\@ - move.\1 (a1)+,d5 -mmmr_nd5\@: - lsr.l #1,d0 - bcc mmmr_nd6\@ - move.\1 (a1)+,d6 -mmmr_nd6\@: - lsr.l #1,d0 - bcc mmmr_nd7\@ - move.\1 (a1)+,d7 -mmmr_nd7\@: - tst.b d0 // addressregister zu verschieben? - beq mmmr_na7\@ // nein-> - lsr.l #1,d0 - bcc mmmr_na0\@ -.ifc 1,l - move.l (a1)+,a0_off(a7) -.else - move.w (a1)+,a0_off+2(a7) -.endif -mmmr_na0\@: - lsr.l #1,d0 - bcc mmmr_na1\@ -.ifc 1,l - move.l (a1)+,a1_off(a7) -.else - move.w (a1)+,a1_off+2(a7) -.endif -mmmr_na1\@: - lsr.l #1,d0 - bcc mmmr_na2\@ - move.\1 (a1)+,a2 -mmmr_na2\@: - lsr.l #1,d0 - bcc mmmr_na3\@ - move.\1 (a1)+,a3 -mmmr_na3\@: - lsr.l #1,d0 - bcc mmmr_na4\@ - move.\1 (a1)+,a4 -mmmr_na4\@: - lsr.l #1,d0 - bcc mmmr_na5\@ - move.\1 (a1)+,a5 -mmmr_na5\@: - lsr.l #1,d0 - bcc mmmr_na6\@ - move.\1 (a1)+,a6 -mmmr_na6\@: - lsr.l #1,d0 - bcc mmmr_na7\@ - move.\1 (a1)+,a1 // nach a0 - move.l a1,usp // war ja usp -mmmr_na7\@: - ii_end - .endm diff --git a/BaS_GNU/sources/ii_movep.h b/BaS_GNU/sources/ii_movep.h deleted file mode 100644 index 830fdf7..0000000 --- a/BaS_GNU/sources/ii_movep.h +++ /dev/null @@ -1,179 +0,0 @@ -//-------------------------------------------------------------------- -// movep -//-------------------------------------------------------------------- -.text -ii_movep_lset:.macro - ii_lset_opeau 01,0 //movep.w d(a0-7),d0 - ii_lset_opeau 03,0 //movep.w d(a0-7),d1 - ii_lset_opeau 05,0 //movep.w d(a0-7),d2 - ii_lset_opeau 07,0 //movep.w d(a0-7),d3 - ii_lset_opeau 09,0 //movep.w d(a0-7),d4 - ii_lset_opeau 0b,0 //movep.w d(a0-7),d5 - ii_lset_opeau 0d,0 //movep.w d(a0-7),d6 - ii_lset_opeau 0f,0 //movep.w d(a0-7),d7 - - ii_lset_opeau 01,4 //movep.w d0,d(a0-7) - ii_lset_opeau 03,4 //movep.w d1,d(a0-7) - ii_lset_opeau 05,4 //movep.w d2,d(a0-7) - ii_lset_opeau 07,4 //movep.w d3,d(a0-7) - ii_lset_opeau 09,4 //movep.w d4,d(a0-7) - ii_lset_opeau 0b,4 //movep.w d5,d(a0-7) - ii_lset_opeau 0d,4 //movep.w d6,d(a0-7) - ii_lset_opeau 0f,4 //movep.w d7,d(a0-7) - - ii_lset_opeau 01,8 //movep.l d(a0-7),d0 - ii_lset_opeau 03,8 //movep.l d(a0-7),d1 - ii_lset_opeau 05,8 //movep.l d(a0-7),d2 - ii_lset_opeau 07,8 //movep.l d(a0-7),d3 - ii_lset_opeau 09,8 //movep.l d(a0-7),d4 - ii_lset_opeau 0b,8 //movep.l d(a0-7),d5 - ii_lset_opeau 0d,8 //movep.l d(a0-7),d6 - ii_lset_opeau 0f,8 //movep.l d(a0-7),d7 - - ii_lset_opeau 01,c //movep.l d0,d(a0-7) - ii_lset_opeau 03,c //movep.l d1,d(a0-7) - ii_lset_opeau 05,c //movep.l d2,d(a0-7) - ii_lset_opeau 07,c //movep.l d3,d(a0-7) - ii_lset_opeau 09,c //movep.l d4,d(a0-7) - ii_lset_opeau 0b,c //movep.l d5,d(a0-7) - ii_lset_opeau 0d,c //movep.l d6,d(a0-7) - ii_lset_opeau 0f,c //movep.l d7,d(a0-7) -.endm -//--------------------------------------------------------------------------------------------- -ii_movep_func:.macro -//movep.w d(a0-7),d0-7 - ii_movep 010,d0_off(a7),wad - ii_movep 030,d1_off(a7),wad - ii_movep 050,d2,wad - ii_movep 070,d3,wad - ii_movep 090,d4,wad - ii_movep 0b0,d5,wad - ii_movep 0d0,d6,wad - ii_movep 0f0,d7,wad -//movep.w d0-7,d(a0-7) - ii_movep 014,d0_off(a7),wda - ii_movep 034,d1_off(a7),wda - ii_movep 054,d2,wda - ii_movep 074,d3,wda - ii_movep 094,d4,wda - ii_movep 0b4,d5,wda - ii_movep 0d4,d6,wda - ii_movep 0f4,d7,wda -//movep.l d(a0-7),d0-7 - ii_movep 018,d0_off(a7),lad - ii_movep 038,d1_off(a7),lad - ii_movep 058,d2,lad - ii_movep 078,d3,lad - ii_movep 098,d4,lad - ii_movep 0b8,d5,lad - ii_movep 0d8,d6,lad - ii_movep 0f8,d7,lad -//movep.l d0-7,d(a0-7) - ii_movep 01c,d0_off(a7),lda - ii_movep 03c,d1_off(a7),lda - ii_movep 05c,d2,lda - ii_movep 07c,d3,lda - ii_movep 09c,d4,lda - ii_movep 0bc,d5,lda - ii_movep 0dc,d6,lda - ii_movep 0fc,d7,lda -.endm -//--------------------------------------------------------------------------------------------- -ii_movep:.macro //1=code ziffer 1-3 2=register 3=art -ii_0x\18: -#ifdef halten_movep - halt -#endif - move.l a0_off(a7),a1 - ii_movep\3_up1 \2 -ii_0x\19: -#ifdef halten_movep - halt -#endif - move.l a1_off(a7),a1 - ii_movep\3_up1 \2 -ii_0x\1a: -#ifdef halten_movep - halt -#endif - move.l a2,a1 - ii_movep\3_up1 \2 -ii_0x\1b: -#ifdef halten_movep - halt -#endif - move.l a3,a1 - ii_movep\3_up1 \2 -ii_0x\1c: -#ifdef halten_movep - halt -#endif - move.l a4,a1 - ii_movep\3_up1 \2 -ii_0x\1d: -#ifdef halten_movep - halt -#endif - move.l a5,a1 - ii_movep\3_up1 \2 -ii_0x\1e: -#ifdef halten_movep - halt -#endif - move.l a6,a1 - ii_movep\3_up1 \2 -ii_0x\1f: -#ifdef halten_movep - halt -#endif - move.l usp,a1 - ii_movep\3_up1 \2 -.endm - -ii_movepwad_up1:.macro - mvs.w (a0)+,d1 - add.l d1,a1 - move.b (a1),d0 - lsl.l #8,d0 - move.b 2(a1,d1.l),d0 - move.w d0,\1 - ii_end -.endm - -ii_movepwda_up1:.macro - mvs.w (a0)+,d1 - add.l d1,a1 - move.w \1,d0 - move.b d0,2(a1) - lsr.l #8,d0 - move.b d0,(a1) - ii_end -.endm - -ii_moveplad_up1:.macro - mvs.w (a0)+,d1 - add.l d1,a1 - move.b (a1),d0 - lsl.l #8,d0 - move.b 2(a1),d0 - lsl.l #8,d0 - move.b 4(a1),d0 - lsl.l #8,d0 - move.b 6(a1),d0 - move.l d0,\1 - ii_end -.endm - -ii_moveplda_up1:.macro - mvs.w (a0)+,d1 - add.l d1,a1 - move.l \1,d0 - move.b d0,6(a1) - lsr.l #8,d0 - move.b d0,4(a1) - lsr.l #8,d0 - move.b d0,2(a1) - lsr.l #8,d0 - move.b d0,(a1) - ii_end -.endm diff --git a/BaS_GNU/sources/ii_op.h b/BaS_GNU/sources/ii_op.h deleted file mode 100644 index a3fc0cf..0000000 --- a/BaS_GNU/sources/ii_op.h +++ /dev/null @@ -1,661 +0,0 @@ -/*****************************************************************************************/ -// opertionen -/*****************************************************************************************/ -ii_lset_op:.macro -//byt - ii_lset_opea \1,0 // dx,ax - ii_lset_opea \1,1 // (ax), (ax)+ - ii_lset_opea \1,2 // -(ax),d16(ax) - ii_lset_opeag \1,3 // d8(ax,dy) - lea table+0x\1\238*4,a0 - move.l #ii_0x\138,(a0)+ // xxx.w - move.l #ii_0x\139,(a0)+ // xxx.l -//word - ii_lset_opea \1,4 // dx,ax - ii_lset_opea \1,5 // (ax), (ax)+ - ii_lset_opea \1,6 // -(ax),d16(ax) - ii_lset_opeag \1,7 // d8(ax,dy) - lea table+0x\178*4,a0 - move.l #ii_0x\178,(a0)+ // xxx.w - move.l #ii_0x\179,(a0)+ // xxx.l -//long - ii_lset_opea \1,8 // dx,ax - ii_lset_opea \1,9 // (ax), (ax)+ - ii_lset_opea \1,a // -(ax),d16(ax) - ii_lset_opeag \1,b // d8(ax,dy) - lea table+0x\1b8*4,a0 - move.l #ii_0x\1b8,(a0)+ // xxx.w - move.l #ii_0x\1b9,(a0)+ // xxx.l - .endm - -ii_lset_opeag:.macro // 0x1120-0x1127 - lea table+0x\1\20*4,a0 - move.l #ii_0x\1\20,(a0)+ - move.l #ii_0x\1\21,(a0)+ - move.l #ii_0x\1\22,(a0)+ - move.l #ii_0x\1\23,(a0)+ - move.l #ii_0x\1\24,(a0)+ - move.l #ii_0x\1\25,(a0)+ - move.l #ii_0x\1\26,(a0)+ - move.l #ii_0x\1\27,(a0)+ - .endm; - -ii_lset_opeau:.macro // 0x1128-0x112f - lea table+0x\1\28*4,a0 - move.l #ii_0x\1\28,(a0)+ - move.l #ii_0x\1\29,(a0)+ - move.l #ii_0x\1\2a,(a0)+ - move.l #ii_0x\1\2b,(a0)+ - move.l #ii_0x\1\2c,(a0)+ - move.l #ii_0x\1\2d,(a0)+ - move.l #ii_0x\1\2e,(a0)+ - move.l #ii_0x\1\2f,(a0)+ - .endm; - -ii_lset_opea:.macro - ii_lset_opeag \1,\2 - ii_lset_opeau \1,\2 - .endm -/******************************************************/ -ii_op:.macro // 1=code 2=operation 3 = normal oder immediat/quick -// byt - opdx \1,\2,b,0,\3 // dx,ax - opia \1,\2,b,1,\3 // (ax),(ax)+ - opdia \1,\2,b,2,\3 // -(ax),d16(ax) - opd8a \1,\2,b,3,\3 // d8(ax),xxx -// word - opdx \1,\2,w,4,\3 // dx,ax - opia \1,\2,w,5,\3 // (ax),(ax)+ - opdia \1,\2,w,6,\3 // -(ax),d16(ax) - opd8a \1,\2,w,7,\3 // d8(ax),xxx -// long - opdx \1,\2,l,8,\3 // dx,ax - opia \1,\2,l,9,\3 // (ax),(ax)+ - opdia \1,\2,l,a,\3 // -(ax),d16(ax) - opd8a \1,\2,l,b,\3 // d8(ax),xxx - .endm -/******************************************************/ -// byt word long -/******************************************************/ -opdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal -ii_0x\1\40: - .ifc \3,b - op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 - .else - .ifc \3,w - op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 - .else - op\5smd \2,d0_off(a7),d0_off(a7),\3 - .endif - .endif -ii_0x\1\41: - .ifc \3,b - op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 - .else - .ifc \3,w - op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 - .else - op\5smd \2,d1_off(a7),d1_off(a7),\3 - .endif -.endif -ii_0x\1\42: - op\5smd \2,d2,d2,\3 -ii_0x\1\43: - op\5smd \2,d3,d3,\3 -ii_0x\1\44: - op\5smd \2,d4,d4,\3 -ii_0x\1\45: - op\5smd \2,d5,d5,\3 -ii_0x\1\46: - op\5smd \2,d6,d6,\3 -ii_0x\1\47: - op\5smd \2,d7,d7,\3 -//ax -ii_0x\1\48: - opa\5smd \2,a0_off(a7),a0_off(a7),\3 -ii_0x\1\49: - opa\5smd \2,a1_off(a7),a1_off(a7),\3 -ii_0x\1\4a: - opa\5smd \2,a2,a2,\3 -ii_0x\1\4b: - opa\5smd \2,a3,a3,\3 -ii_0x\1\4c: - opa\5smd \2,a4,a4,\3 -ii_0x\1\4d: - opa\5smd \2,a5,a5,\3 -ii_0x\1\4e: - opa\5smd \2,a6,a6,\3 -ii_0x\1\4f: - opa\5smd \2,usp,usp,\3 -.endm; -//----------------------------------------------- -opia: .macro // (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal -//(ax) -ii_0x\1\40: - op\5sia \2,a0_off(a7),(a1),(a1),\3 -ii_0x\1\41: - op\5sia \2,a1_off(a7),(a1),(a1),\3 -ii_0x\1\42: - op\5smd \2,(a2),(a2),\3 -ii_0x\1\43: - op\5smd \2,(a3),(a3),\3 -ii_0x\1\44: - op\5smd \2,(a4),(a4),\3 -ii_0x\1\45: - op\5smd \2,(a5),(a5),\3 -ii_0x\1\46: - op\5smd \2,(a6),(a6),\3 -ii_0x\1\47: - op\5sia \2,usp,(a1),(a1),\3 -//(ax)+ -ii_0x\1\48: - op\5sia \2,a0_off(a7),(a1),(a1)+,\3 -ii_0x\1\49: - op\5sia \2,a1_off(a7),(a1),(a1)+,\3 -ii_0x\1\4a: - op\5smd \2,(a2),(a2)+,\3 -ii_0x\1\4b: - op\5smd \2,(a3),(a3)+,\3 -ii_0x\1\4c: - op\5smd \2,(a4),(a4)+,\3 -ii_0x\1\4d: - op\5smd \2,(a5),(a5)+,\3 -ii_0x\1\4e: - op\5smd \2,(a6),(a6)+,\3 -ii_0x\1\4f: - op\5sia \2,usp,(a1),(a1)+,\3 -.endm; -//----------------------------------------------- -opdia: .macro // -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal -ii_0x\1\40: - op\5sia \2,a0_off(a7),-(a1),(a1),\3 -ii_0x\1\41: - op\5sia \2,a1_off(a7),-(a1),(a1),\3 -ii_0x\1\42: - op\5smd \2,-(a2),(a2),\3 -ii_0x\1\43: - op\5smd \2,-(a3),(a3),\3 -ii_0x\1\44: - op\5smd \2,-(a4),(a4),\3 -ii_0x\1\45: - op\5smd \2,-(a5),(a5),\3 -ii_0x\1\46: - op\5smd \2,-(a6),(a6),\3 -ii_0x\1\47: - op\5sia \2,usp,-(a1),(a1),\3 - -ii_0x\1\48: - op\5sd16a \2,a0_off(a7),\3 -ii_0x\1\49: - op\5sd16a \2,a1_off(a7),\3 -ii_0x\1\4a: - op\5sd16a \2,a2,\3 -ii_0x\1\4b: - op\5sd16a \2,a3,\3 -ii_0x\1\4c: - op\5sd16a \2,a4,\3 -ii_0x\1\4d: - op\5sd16a \2,a5,\3 -ii_0x\1\4e: - op\5sd16a \2,a6,\3 -ii_0x\1\4f: - op\5sd16a \2,usp,\3 -.endm; -//----------------------------------------------- -opd8a: .macro // d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal -ii_0x\1\40: - op\5sd8a \2,a0_off(a7),\3 -ii_0x\1\41: - op\5sd8a \2,a1_off(a7),\3 -ii_0x\1\42: - op\5sd8a \2,a2,\3 -ii_0x\1\43: - op\5sd8a \2,a3,\3 -ii_0x\1\44: - op\5sd8a \2,a4,\3 -ii_0x\1\45: - op\5sd8a \2,a5,\3 -ii_0x\1\46: - op\5sd8a \2,a6,\3 -ii_0x\1\47: - op\5sd8a \2,usp,\3 - -ii_0x\1\48: - op\5sxx \2,\3,w -ii_0x\1\49: - op\5sxx \2,\3,l -.endm; -//----------------------------------------------- -opnsmd:.macro // direct dx: 1=operation 2=ea src 3=ea dest 4=size -#ifdef halten_op - halt -#endif -.ifc \4,l - move.l \2,d1 -.else - mvs.\4 \2,d1 -.endif - .ifc \1,negx - move.b sr_off+1(a7),d1 //ccr holen - move d1,ccr //setzen - .endif - \1 d1 - set_cc0 - move.\4 d1,\3 - ii_end - .endm; - -opansmd:.macro // direct ax: 1=operation 2=ea src 3=ea dest 4=size -#ifdef halten_op - halt -#endif - -.ifc \2,usp - move.l usp,a1 - move.l a1,d1 -.else - move.l \2,d1 -.endif - \1 d1 -.ifc \3,usp - move.l d1,a1 - move.l a1,usp -.else - move.l d1,\3 -.endif - ii_end -.endm; - -opnsia:.macro // indirect: 1=operation 2=adress register 3= src 4=dest 5=size -#ifdef halten_op - halt -#endif - move.l \2,a1 -.ifc \5,l - move.l \3,d1 -.else - mvs.\5 \3,d1 -.endif - .ifc \1,negx - move.b sr_off+1(a7),d1 //ccr holen - move d1,ccr //setzen - .endif - \1 d1 - set_cc0 - move.\5 d1,\4 - ii_end - .endm; - -opnsd16a:.macro // indirect: 1=operation 2=adress register 3=size -#ifdef halten_op - halt -#endif - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 -.ifc \3,l - move.l (a1),d1 -.else - mvs.\3 (a1),d1 -.endif - .ifc \1,negx - move.b sr_off+1(a7),d1 //ccr holen - move d1,ccr //setzen - .endif - \1 d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; - -opnsd8a:.macro // indirect: 1=operation 2=adress register 3=size -#ifdef halten_op - halt -#endif - move.l \2,a1 - jsr ewf -.ifc \3,l - move.l (a1),d1 -.else - mvs.\3 (a1),d1 -.endif - .ifc \1,negx - move.b sr_off+1(a7),d1 //ccr holen - move d1,ccr //setzen - .endif - \1 d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; - -opnsxx:.macro // indirect: 1=operation 2=size 3=size adresse -#ifdef halten_op - halt -#endif - -.ifc \2,l - move.l (a1),d1 -.else - mvs.\2 (a1),d1 -.endif - move.\3 (a0)+,a1 - .ifc \1,negx - move.b sr_off+1(a7),d1 //ccr holen - move d1,ccr //setzen - .endif - \1 d1 - set_cc0 - move.\2 d1,(a1) - ii_end - .endm; -//*******************************************************************************3 -opismd:.macro // immediate dx: 1=opieration 2=ea src 3=ea dest 4=size -#ifdef halten_op - halt -#endif - -.ifc \4,l - move.l (a0)+,d0 -.else - .ifc \4,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif -.ifc \4,l - move.l \2,d1 -.else - mvs.\4 \2,d1 -.endif - \1 d0,d1 - set_cc0 -.ifnc \1,cmp.l - move.\4 d1,\3 -.endif - ii_end -.endm; - -opaismd:.macro // immediate ax: 1=opieration 2=ea src 3=ea dest 4=size -#ifdef halten_op - halt -#endif - -.ifc \4,l - move.l (a0)+,d0 -.else - .ifc \4,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif -.ifc \2,usp - move.l usp,a1 - move.l a1,d1 -.else - move.l \2,d1 -.endif - \1 d0,d1 -.ifnc \1,cmp.l -.ifc \3,usp - move.l d1,a1 - move.l a1,usp -.else - move.l d1,\3 -.endif -.endif - ii_end -.endm; - -opisia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size -#ifdef halten_op - halt -#endif - -.ifc \5,l - move.l (a0)+,d0 -.else - .ifc \5,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif - move.l \2,a1 -.ifc \5,l - move.l \3,d1 -.else - mvs.\5 \3,d1 -.endif - \1 d0,d1 - set_cc0 -.ifnc \1,cmp.l - move.\5 d1,\4 -.endif - ii_end -.endm; - -opisd16a:.macro // indirect: 1=opieration 2=adress register 3=size -#ifdef halten_op - halt -#endif - -.ifc \3,l - move.l (a0)+,d0 -.else - .ifc \3,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 -.ifc \3,l - move.l (a1),d1 -.else - mvs.\3 (a1),d1 -.endif - \1 d0,d1 - set_cc0 -.ifnc \1,cmp.l - move.\3 d1,(a1) -.endif - ii_end - .endm; - -opisd8a:.macro // indirect: 1=opieration 2=adress register 3=size -#ifdef halten_op - halt -#endif - -.ifc \3,l - move.l (a0)+,d0 -.else - .ifc \3,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif - move.l d0,_d0_save - move.l \2,a1 - jsr ewf - move.l _d0_save,d0 -.ifc \3,l - move.l (a1),d1 -.else - mvs.\3 (a1),d1 -.endif - \1 d0,d1 - set_cc0 -.ifnc \1,cmp.l - move.\3 d1,(a1) -.endif - ii_end - .endm; - -opisxx:.macro // immediate: 1=opieration 2=size 3=size adresse -.ifc \2,l - move.l (a0)+,d0 -.else - .ifc \2,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif - move.\3 (a0)+,a1 -.ifc \2,l - move.l (a1),d1 -.else - mvs.\2 (a1),d1 -.endif - \1 d0,d1 - set_cc0 -.ifnc \1,cmp.l - move.\2 d1,(a1) -.endif - ii_end - .endm; -//*******************************************************************************3 -opqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size -.ifc \4,l - move.l \2,d1 -.else - mvs.\4 \2,d1 -.endif -.ifc \1,eor.l d0 - move.l d0_off(a7),d0 -.endif -.ifc \1,eor.l d1 - move.l d1_off(a7),d1 -.endif - \1 ,d1 - set_cc0 - move.\4 d1,\3 - ii_end - .endm; - -opaqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size -.ifc \2,usp - move.l usp,a1 - move.l a1,d1 -.else - move.l \2,d1 -.endif - \1 ,d1 -.ifc \3,usp - move.l d1,a1 - move.l a1,usp -.else - move.l d1,\3 -.endif - ii_end - .endm; - -opqsia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size -#ifdef halten_op - halt -#endif - - move.l \2,a1 -.ifc \5,l - move.l \3,d1 -.else - mvs.\5 \3,d1 -.endif -.ifc \1,eor.l d0 - move.l d0_off(a7),d0 -.endif -.ifc \1,eor.l d1 - move.l d1_off(a7),d1 -.endif - \1 ,d1 - set_cc0 - move.\5 d1,\4 - ii_end - .endm; - -opqsd16a:.macro // indirect: 1=opieration 2=adress register 3=size -#ifdef halten_op - halt -#endif - - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 -.ifc \3,l - move.l (a1),d1 -.else - mvs.\3 (a1),d1 -.endif -.ifc \1,eor.l d0 - move.l d0_off(a7),d0 -.endif -.ifc \1,eor.l d1 - move.l d1_off(a7),d1 -.endif - \1 ,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; - -opqsd8a:.macro // indirect: 1=opieration 2=adress register 3=size -#ifdef halten_op - halt -#endif - - move.l d0,_d0_save - move.l \2,a1 - jsr ewf - move.l _d0_save,d0 -.ifc \3,l - move.l (a1),d1 -.else - mvs.\3 (a1),d1 -.endif -.ifc \1,eor.l d0 - move.l d0_off(a7),d0 -.endif -.ifc \1,eor.l d1 - move.l d1_off(a7),d1 -.endif - \1 ,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; - -opqsxx:.macro // quick: 1=opieration 2=size 3=size adresse -#ifdef halten_op - halt -#endif - - move.\3 (a0)+,a1 -.ifc \2,l - move.l (a1),d1 -.else - mvs.\2 (a1),d1 -.endif -.ifc \1,eor.l d0 - move.l d0_off(a7),d0 -.endif -.ifc \1,eor.l d1 - move.l d1_off(a7),d1 -.endif - \1 ,d1 - set_cc0 - move.\2 d1,(a1) - ii_end - .endm; diff --git a/BaS_GNU/sources/ii_opc.h b/BaS_GNU/sources/ii_opc.h deleted file mode 100644 index 8b887ce..0000000 --- a/BaS_GNU/sources/ii_opc.h +++ /dev/null @@ -1,263 +0,0 @@ -/*****************************************************************************************/ -// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax -// zusammen mit op.h -/*****************************************************************************************/ -ii_lset_opc:.macro - ii_lset_opeag \1,c // dx,ax - ii_lset_opea \1,d // (ax), (ax)+ - ii_lset_opea \1,e // -(ax),d16(ax) - ii_lset_opeag \1,f // d8(ax,dy) - lea table+0x\1b8*4,a0 - move.l #ii_0x\1b8,(a0)+ // xxx.w - move.l #ii_0x\1b9,(a0)+ // xxx.l - .endm - -/******************************************************/ -ii_opc:.macro // 1=code 2=operation 3 = normal oder immediat - opcdx \1,\2,l,c,\3 // dx,ax - opia \1,\2,l,d,\3 // (ax),(ax)+ - opdia \1,\2,l,e,\3 // -(ax),d16(ax) - opd8a \1,\2,l,f,\3 // d8(ax),xxx - .endm -//*******************************************************************************3 -/******************************************************/ -// byt word long -/******************************************************/ -opcdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal -ii_0x\1\40: -#ifdef halten_opc - halt -#endif - .ifc \3,b - op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 - .else - .ifc \3,w - op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 - .else - op\5smd \2,d0_off(a7),d0_off(a7),\3 - .endif - .endif -ii_0x\1\41: - .ifc \3,b - op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 - .else - .ifc \3,w - op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 - .else - op\5smd \2,d1_off(a7),d1_off(a7),\3 - .endif -.endif -ii_0x\1\42: - op\5smd \2,d2,d2,\3 -ii_0x\1\43: - op\5smd \2,d3,d3,\3 -ii_0x\1\44: - op\5smd \2,d4,d4,\3 -ii_0x\1\45: - op\5smd \2,d5,d5,\3 -ii_0x\1\46: - op\5smd \2,d6,d6,\3 -ii_0x\1\47: - op\5smd \2,d7,d7,\3 -.endm -//----------------------------------------------------- -opcsmd:.macro // dx: 1=opieration 2=ea src 3=ea dest 4=size -#ifdef halten_opc - halt -#endif - -.ifc \4,l - move.l (a0)+,d0 -.else - .ifc \4,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif -.ifc \4,l - move.l \2,d1 -.else - mvs.\4 \2,d1 -.endif -.ifc \1,eor.l d0 - move.l d0_off(a7),d1 -.endif -.ifc \1,eor.l d1 - move.l d1_off(a7),d1 -.endif - \1 d1 - set_cc0 - move.\4 d1,\3 - ii_end - .endm; - -opacsmd:.macro // ax: 1=opieration 2=ea src 3=ea dest 4=size -#ifdef halten_opc - halt -#endif - -.ifc \4,l - move.l (a0)+,d0 -.else - .ifc \4,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif -.ifc \2,usp - move.l usp,a1 - move.l a1,d1 -.else - move.l \2,d1 -.endif - \1 d1 - set_cc0 -.ifc \3,usp - move.l d1,a1 - move.l a1,usp -.else - move.l d1,\3 -.endif - ii_end - .endm; - -opcsia:.macro // (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size -#ifdef halten_opc - halt -#endif - -.ifc \4,l - move.l (a0)+,d0 -.else - .ifc \4,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif - move.l \2,a1 -.ifc \5,l - move.l \3,d1 -.else - mvs.\5 \3,d1 -.endif -.ifc \1,eor.l d0 - move.l d0_off(a7),d1 -.endif -.ifc \1,eor.l d1 - move.l d1_off(a7),d1 -.endif - \1 d1 - set_cc0 - move.\5 d1,\4 - ii_end - .endm; - -opcsd16a:.macro // d16(ax): 1=opieration 2=adress register 3=size -#ifdef halten_opc - halt -#endif - -.ifc \4,l - move.l (a0)+,d0 -.else - .ifc \4,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 -.ifc \3,l - move.l (a1),d1 -.else - mvs.\3 (a1),d1 -.endif -.ifc \1,eor.l d0 - move.l d0_off(a7),d1 -.endif -.ifc \1,eor.l d1 - move.l d1_off(a7),d1 -.endif - \1 d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; - -opcsd8a:.macro // indirect: 1=opieration 2=adress register 3=size -#ifdef halten_opc - halt -#endif - -.ifc \4,l - move.l (a0)+,d0 -.else - .ifc \4,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif - move.l d0,_d0_save - move.l \2,a1 - jsr ewf - move.l _d0_save,d0 -.ifc \3,l - move.l (a1),d1 -.else - mvs.\3 (a1),d1 -.endif -.ifc \1,eor.l d0 - move.l d0_off(a7),d1 -.endif -.ifc \1,eor.l d1 - move.l d1_off(a7),d1 -.endif - \1 d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; - -opcsxx:.macro // indirect: 1=opieration 2=size 3=size adresse -#ifdef halten_opc - halt -#endif - -.ifc \2,l - move.l (a0)+,d0 -.else - .ifc \2,w - mvs.w (a0)+,d0 - .else - move.w (a0)+,d0 - extb.l d0 - .endif -.endif - move.\3 (a0)+,a1 -.ifc \2,l - move.l (a1),d1 -.else - mvs.\2 (a1),d1 -.endif -.ifc \1,eor.l d0 - move.l d0_off(a7),d1 -.endif -.ifc \1,eor.l d1 - move.l d1_off(a7),d1 -.endif - \1 d1 - set_cc0 - move.\2 d1,(a1) - ii_end - .endm; diff --git a/BaS_GNU/sources/ii_or.h b/BaS_GNU/sources/ii_or.h deleted file mode 100644 index dfe4450..0000000 --- a/BaS_GNU/sources/ii_or.h +++ /dev/null @@ -1,442 +0,0 @@ -//-------------------------------------------------------------------- -// or -//-------------------------------------------------------------------- -/*****************************************************************************************/ -//-------------------------------------------------------------------- -// byt -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// or.b #im,dx -//-------------------------------------------------------------------- -orbir_macro:.macro -#ifdef halten_or - halt -#endif - move.w (a0)+,d0 - extb.l d0 - mvs.b \2,d1 - or.l d0,d1 - set_cc0 - move.b d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or ea,dx -//-------------------------------------------------------------------- -ordd:.macro -#ifdef halten_or - halt -#endif - mvs.\3 \1,d0 - mvs.\3 \2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or ea(l)->dy(w),dx z.B. für USP -//-------------------------------------------------------------------- -orddd:.macro -#ifdef halten_or - halt -#endif - move.l \1,a1 - mvs.\3 a1,d0 - mvs.\3 \2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or (ea)->dy,dx -//-------------------------------------------------------------------- -ordda:.macro -#ifdef halten_or - halt -#endif - move.l \1,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or ea->ay,(ay)+,dx -//-------------------------------------------------------------------- -orddai:.macro -#ifdef halten_or - halt -#endif - move.l \1,a1 - mvs.\3 (a1)+,d0 - move.l a1,\1 - mvs.\3 \2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or ea->ay,-(ay),dx -//-------------------------------------------------------------------- -orddad:.macro -#ifdef halten_or - halt -#endif - move.l \1,a1 - mvs.\3 -(a1),d0 - move.l a1,\1 - mvs.\3 \2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or d16(ay),dx -//-------------------------------------------------------------------- -ord16ad:.macro -#ifdef halten_or - halt -#endif - move.l \1,a1 - mvs.w (a0)+,d0 - add.l d0,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or d8(ay,dy),dx -//-------------------------------------------------------------------- -ord8ad:.macro -#ifdef halten_or - halt -#endif - move.l \1,a1 - jsr ewf -.ifc \3,l - move.l (a1),d0 - move.l \2,d1 -.else - mvs.\3 (a1),d0 - mvs.\3 \2,d1 -.endif - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or xxx.w,dx -//-------------------------------------------------------------------- -orxwd:.macro -#ifdef halten_or - halt -#endif - move.w (a0)+,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or xxx.l,dx -//-------------------------------------------------------------------- -orxld:.macro -#ifdef halten_or - halt -#endif - move.l (a0)+,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or d16(pc),dx -//-------------------------------------------------------------------- -ord16pcd:.macro - halt - move.l a0,a1 - mvs.w (a0)+,d0 - add.l d0,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or d8(pc,dy),dx -//-------------------------------------------------------------------- -ord8pcd:.macro -#ifdef halten_or - halt -#endif - move.l a0,a1 - jsr ewf -.ifc \3,l - move.l (a1),d0 - move.l \2,d1 -.else - mvs.\3 (a1),d0 - mvs.\3 \2,d1 -.endif - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// or dy,ea -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// // or (ea)->dy,dx -//-------------------------------------------------------------------- -oreda:.macro -#ifdef halten_or - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 (a1),d1 - or.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // or dx,ea->ay,(ay)+ -//-------------------------------------------------------------------- -oredai:.macro -#ifdef halten_or - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 (a1),d1 - or.l d0,d1 - set_cc0 - move.\3 d1,(a1)+ - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or dx,ea->ay,(ay)+ -//-------------------------------------------------------------------- -oredaid:.macro -#ifdef halten_or - halt -#endif - mvs.\3 \1,d0 - mvs.\3 \2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2+ - ii_end - .endm; -//-------------------------------------------------------------------- -// // or dx,ea->ay,-(ay) -//-------------------------------------------------------------------- -oredad:.macro -#ifdef halten_or - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 -(a1),d1 - move.l a1,\2 - or.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // or dx,ea->ay,-(ay) -//-------------------------------------------------------------------- -oredadd:.macro -#ifdef halten_or - halt -#endif - mvs.\3 \1,d0 - mvs.\3 -\2,d1 - or.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // or dx,d16(ay) -//-------------------------------------------------------------------- -ore16ad:.macro -#ifdef halten_or - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - mvs.\3 (a1),d1 - or.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // or.w dx,d8(ay,dy) -//-------------------------------------------------------------------- -ore8ad:.macro -#ifdef halten_or - halt -#endif - move.l \2,a1 - jsr ewf -.ifc \3,l - move.l (a1),d1 - move.l \1,d0 -.else - mvs.\3 (a1),d1 - mvs.\3 \1,d0 -.endif - or.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // or dx,xxx.w -//-------------------------------------------------------------------- -orxwe:.macro -#ifdef halten_or - halt -#endif - mvs.\3 \1,d0 - move.w (a0)+,a1 - mvs.\3 (a1),d1 - or.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // or dx,xxx.l -//-------------------------------------------------------------------- -orxle:.macro -#ifdef halten_or - halt -#endif - mvs.\3 \1,d0 - move.l (a0)+,a1 - mvs.\3 (a1),d1 - or.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // ora.w ea,ax -//-------------------------------------------------------------------- -oraw:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// or.w ea,usp -//-------------------------------------------------------------------- -orawa7:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // ora.w usp?,ax -//-------------------------------------------------------------------- -orawu:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // ora.w usp?,usp -//-------------------------------------------------------------------- -orawua7:.macro - orawu \1,\2 - .endm; -//-------------------------------------------------------------------- -// // ora.w d16(ay),ax -//-------------------------------------------------------------------- -orawd16a:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // ora.w d8(ay,dy),ax -//-------------------------------------------------------------------- -orawd8a:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // ora.w xxx.w,ax -//-------------------------------------------------------------------- -orawxwax:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // ora.w xxx.l,ax -//-------------------------------------------------------------------- -orawxlax:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // ora.w d16(pc),ax -//-------------------------------------------------------------------- -orawd16pcax:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // ora.w d8(pc,dy),ax -//-------------------------------------------------------------------- -orawd8pcax:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // ora.w #im,ax -//-------------------------------------------------------------------- -orawim:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // ora.l d8(ay,dy),ax -//-------------------------------------------------------------------- -orald8a:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // ora.l d8(pc,dy),ax -//-------------------------------------------------------------------- -orald8pcax:.macro - jmp ii_error - .endm; -//***************************************************************************************** -// spezial addx subx etc. -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// // addx dy,dx -//-------------------------------------------------------------------- -ordx:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- -// // addx -(ay),-(ax) -//-------------------------------------------------------------------- -ordax:.macro - jmp ii_error - .endm; -//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_pea.h b/BaS_GNU/sources/ii_pea.h deleted file mode 100644 index 69f69d0..0000000 --- a/BaS_GNU/sources/ii_pea.h +++ /dev/null @@ -1,74 +0,0 @@ -//-------------------------------------------------------------------- -// pea -//-------------------------------------------------------------------- -.text -ii_pea_lset:.macro - ii_lset_opeag 48,7 - ii_lset 0x487b -.endm -//--------------------------------------------------------------------------------------------- -ii_pea_func:.macro -ii_0x4870: -#ifdef halten_pea - halt -#endif - move.l a0_off(a7),a1 - pea_macro -ii_0x4871: -#ifdef halten_pea - halt -#endif - move.l a1_off(a7),a1 - pea_macro -ii_0x4872: -#ifdef halten_pea - halt -#endif - move.l a2,a1 - pea_macro -ii_0x4873: -#ifdef halten_pea - halt -#endif - move.l a3,a1 - pea_macro -ii_0x4874: -#ifdef halten_pea - halt -#endif - move.l a4,a1 - pea_macro -ii_0x4875: -#ifdef halten_pea - halt -#endif - move.l a5,a1 - pea_macro -ii_0x4876: -#ifdef halten_pea - halt -#endif - move.l a6,a1 - pea_macro -ii_0x4877: -#ifdef halten_pea - halt -#endif - move.l usp,a1 - pea_macro -ii_0x487b: -#ifdef halten_pea - halt -#endif - move.l a0,a1 - pea_macro -.endm -//--------------------------------------------------------------------------------------------- -pea_macro:.macro - jsr ewf - move.l (a1),d0 - move.l usp,a1 - move.l d0,-(a1) - move.l a1,usp - ii_end -.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_shd.h b/BaS_GNU/sources/ii_shd.h deleted file mode 100644 index ecace29..0000000 --- a/BaS_GNU/sources/ii_shd.h +++ /dev/null @@ -1,247 +0,0 @@ -/*****************************************************************************************/ -// opertionen -/*****************************************************************************************/ -ii_lset_shd:.macro - ii_lset_shdx e0 //r d0 - ii_lset_shdx e2 //r d1 - ii_lset_shdx e4 //r d2 - ii_lset_shdx e6 //r d3 - ii_lset_shdx e8 //r d4 - ii_lset_shdx ea //r d5 - ii_lset_shdx ec //r d6 - ii_lset_shdx ee //r d7 - - ii_lset_shdx e1 //l d0 - ii_lset_shdx e3 //l d1 - ii_lset_shdx e4 //l d2 - ii_lset_shdx e5 //l d3 - ii_lset_shdx e9 //l d4 - ii_lset_shdx eb //l d5 - ii_lset_shdx ed //l d6 - ii_lset_shdx ef //l d7 - .endm - -ii_lset_shdx:.macro -//byt - ii_lset_opea \1,0 // as,ls #im,dx - ii_lset_opea \1,1 // rox,ro #im,dx - ii_lset_opea \1,2 // as,ls dy,dx - ii_lset_opea \1,3 // rox,ro dy,dx -//word - ii_lset_opea \1,4 // as,ls #im,dx - ii_lset_opea \1,5 // rox,ro #im,dx - ii_lset_opea \1,6 // as,ls dy,dx - ii_lset_opea \1,7 // rox,ro dy,dx -//long -// ii_lset_opea \1,8 // as,ls #im,dx -> vorhanden - ii_lset_opea \1,9 // rox,ro #im,dx -// ii_lset_opea \1,a // as,ls dy,dx -> vorhanden - ii_lset_opea \1,b // rox,ro dy,dx - .endm -/******************************************************/ -ii_shd:.macro // 1=code 2=operation 3 = normal, direct oder immediat -// byt - opdx \1,\2,b,0,\3 // dx -// word - opdx \1,\2,w,4,\3 // dx -// long - opdx \1,\2,l,8,\3 // dx - .endm -/******************************************************/ -// byt word long routinen -/******************************************************/ -sh_asr: .macro // asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w - mvs.\4 \2,d1 - sh_shal \1,\2,\3,\4 - .endm - -sh_lsr: .macro // asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w - mvz.\4 \2,d1 - sh_shal \1,\2,\3,\4 - .endm - -sh_shal:.macro - move.w \3,d0 - \1.l d0,d1 - set_cc0 - move.\4 d1,\2 - .endm - -sh_all: .macro // asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w - mvz.\4 \2,d1 -.ifc \4,b - byterev.l d1 -.else - swap.w d1 -.endif - sh_asr \1,\2,\3,\4 - .endm - -sh_ror: .macro // ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l - move.\4 \2,d1 / - move.w \3,d0 -.ifc \4,b - lsl.l #8,d1 - move.b \2,d1 - and.l #0x7,d0 - lsr.l d0,d1 -.else - .ifc \4,w - swap.w d1 - move.w \2,d1 - and.l #0xf,d0 - lsr.l d0,d1 - .else - and.l #0x1f,d0 - lsr.l d0,d1 - move.l d1,a1 - move.l \2,d1 - sub.l #32,d0 - neg.l d0 - lsl.l d0,d1 - add.l a1,d1 - .endif -.endif - move.\4 d1,\2 - move.w ccr,d0 - and.l #1,d1 // ist auch carry bit - or.l d1,d0 - move.b d0,ccr_off(a7) - .endm - -sh_rol: .macro // rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l - move.\4 \2,d1 - move.w \3,d0 -.ifc \4,b - lsl.l #8,d1 - move.b \2,d1 - and.l #0x7,d0 - lsl.l d0,d1 - lsr.l #8,d1 - moveq #7,d0 -.else - .ifc \4,w - swap.w d1 - move.w \2,d1 - and.l #0xf,d0 - lsr.l d0,d1 - swap.w d1 - moveq #15,d0 - .else - and.l #0x1f,d0 - lsl.l d0,d1 - move.l d1,a1 - move.l \2,d1 - sub.l #32,d0 - neg.l d0 - lsr.l d0,d1 - add.l a1,d1 - moveq #31,d0 - .endif -.endif - move.\4 d1,\2 - lsr.l d0,d1 // carry bit schieben - move.w ccr,d0 - and.l #1,d1 - or.l d1,d0 - move.b d0,ccr_off(a7) - .endm - -sh_roxr: .macro // roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l - clr.l d0 - addx.l d0,d0 -ifc \4,b - mvz.b \2,d1 - lsl.l #1,d1 - add.l d0,d1 - lsl.l #8,d1 - move.b \2,d1 - move.w \3,d0 - and.l #0x7,d0 - lsr.l d0,d1 - set_cc0 -else - .ifc \4,w - mvz.b \2,d1 - lsl.l #1,d1 - add.l d0,d1 - lsl.l #8,d1 - lsl.l #8,d1 - move.w \2,d1 - move.w \3,d0 - and.l #0xf,d0 - lsr.l d0,d1 - set_cc0 - .else - bitrev.l d0 - move.l \2,d1 - lsr.l #1,d1 - add.l d0,d1 - move.w \3,d0 - subq.l #1,d0 - and.l #0x1f,d0 - lsr.l d0,d1 - move.l d1,a1 - set_cc1 - move.l \2,d1 - sub.l #32,d0 - neg.l d0 - lsl.l d0,d1 - add.l a1,d1 - .endif -.endif - move.\4 d1,\2 - .endm - -sh_roxl: .macro // roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l - clr.l d0 - addx.l d0,d0 -ifc \4,b - mvz.b \2,d1 - lsl.l #1,d1 - add.l d0,d1 - lsl.l #8,d1 - move.b \2,d1 - lsl.l #8,d1 - lsl.l #7,d1 - move.w \3,d0 - and.l #0x7,d0 - lsl.l d0,d1 - set_cc0 - byterev.l d1 -else - .ifc \4,w - mvz.b \2,d1 - lsl.l #1,d1 - add.l d0,d1 - lsl.l #8,d1 - lsl.l #7,d1 - mvz.w \2,d0 - lsr.l #1,d0 - add.l d0,d1 - move.w \3,d0 - and.l #0xf,d0 - lsl.l d0,d1 - set_cc0 - swap.w d1 - .else - move.l \2,d1 - lsl.l #1,d1 - add.l d0,d1 - move.w \3,d0 - subq.l #1,d0 - and.l #0x1f,d0 - lsl.l d0,d1 - move.l d1,a1 - set_cc1 - move.l \2,d1 - sub.l #32,d0 - neg.l d0 - lsr.l d0,d1 - add.l a1,d1 - .endif -.endif - move.\4 d1,\2 - .endm - - \ No newline at end of file diff --git a/BaS_GNU/sources/ii_shift.h b/BaS_GNU/sources/ii_shift.h deleted file mode 100644 index f83bfcb..0000000 --- a/BaS_GNU/sources/ii_shift.h +++ /dev/null @@ -1,687 +0,0 @@ -/*****************************************************************************************/ -// opertionen -/*****************************************************************************************/ -ii_shift_lset:.macro -/******************************************************/ -// byt -/******************************************************/ -// asx.b #,dx - ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c - ii_lset_dx \1,01 - ii_lset_dx \1,02 - ii_lset_dx \1,03 - ii_lset_dx \1,04 - ii_lset_dx \1,05 - ii_lset_dx \1,06 - ii_lset_dx \1,07 -// lsx.b #,dx - ii_lset_dxu \1,08 - ii_lset_dxu \1,09 - ii_lset_dxu \1,0a - ii_lset_dxu \1,0b - ii_lset_dxu \1,0c - ii_lset_dxu \1,0d - ii_lset_dxu \1,0e - ii_lset_dxu \1,0f -// roxx.b #,dx - ii_lset_dx \1,10 - ii_lset_dx \1,11 - ii_lset_dx \1,12 - ii_lset_dx \1,13 - ii_lset_dx \1,14 - ii_lset_dx \1,15 - ii_lset_dx \1,16 - ii_lset_dx \1,17 -// rox.b #,dx - ii_lset_dx \1,18 - ii_lset_dx \1,19 - ii_lset_dx \1,1a - ii_lset_dx \1,1b - ii_lset_dx \1,1c - ii_lset_dx \1,1d - ii_lset_dx \1,1e - ii_lset_dx \1,1f -// asx.b dy,dx - ii_lset_dx \1,20 - ii_lset_dx \1,21 - ii_lset_dx \1,22 - ii_lset_dx \1,23 - ii_lset_dx \1,24 - ii_lset_dx \1,25 - ii_lset_dx \1,26 - ii_lset_dx \1,27 -// lsx.b dy,dx - ii_lset_dx \1,28 - ii_lset_dx \1,29 - ii_lset_dx \1,2a - ii_lset_dx \1,2b - ii_lset_dx \1,2c - ii_lset_dx \1,2d - ii_lset_dx \1,2e - ii_lset_dx \1,2f -// roxx.dy,dx - ii_lset_dx \1,30 - ii_lset_dx \1,31 - ii_lset_dx \1,32 - ii_lset_dx \1,33 - ii_lset_dx \1,34 - ii_lset_dx \1,35 - ii_lset_dx \1,36 - ii_lset_dx \1,37 -// rox.b dy,dx - ii_lset_dx \1,38 - ii_lset_dx \1,39 - ii_lset_dx \1,3a - ii_lset_dx \1,3b - ii_lset_dx \1,3c - ii_lset_dx \1,3d - ii_lset_dx \1,3e - ii_lset_dx \1,3f -/******************************************************/ -// word -/******************************************************/ -// asx.w #x,dx - ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c - ii_lset_dx \1,41 - ii_lset_dx \1,42 - ii_lset_dx \1,43 - ii_lset_dx \1,44 - ii_lset_dx \1,45 - ii_lset_dx \1,46 - ii_lset_dx \1,47 -// lsx.w #,dx - ii_lset_dx \1,48 - ii_lset_dx \1,49 - ii_lset_dx \1,4a - ii_lset_dx \1,4b - ii_lset_dx \1,4c - ii_lset_dx \1,4d - ii_lset_dx \1,4e - ii_lset_dx \1,4f -// roxx.w #,dx - ii_lset_dx \1,50 - ii_lset_dx \1,51 - ii_lset_dx \1,52 - ii_lset_dx \1,53 - ii_lset_dx \1,54 - ii_lset_dx \1,55 - ii_lset_dx \1,56 - ii_lset_dx \1,57 -// rox.w #xdx - ii_lset_dx \1,58 - ii_lset_dx \1,59 - ii_lset_dx \1,5a - ii_lset_dx \1,5b - ii_lset_dx \1,5c - ii_lset_dx \1,5d - ii_lset_dx \1,5e - ii_lset_dx \1,5f -// asx.w dy,dx - ii_lset_dx \1,60 - ii_lset_dx \1,61 - ii_lset_dx \1,62 - ii_lset_dx \1,63 - ii_lset_dx \1,64 - ii_lset_dx \1,65 - ii_lset_dx \1,66 - ii_lset_dx \1,67 -// lsx.w dy,dx - ii_lset_dx \1,68 - ii_lset_dx \1,69 - ii_lset_dx \1,6a - ii_lset_dx \1,6b - ii_lset_dx \1,6c - ii_lset_dx \1,6d - ii_lset_dx \1,6e - ii_lset_dx \1,6f -// roxx.w dy,dx - ii_lset_dx \1,70 - ii_lset_dx \1,71 - ii_lset_dx \1,72 - ii_lset_dx \1,73 - ii_lset_dx \1,74 - ii_lset_dx \1,75 - ii_lset_dx \1,76 - ii_lset_dx \1,77 -// rox.w dy,dx - ii_lset_dx \1,78 - ii_lset_dx \1,79 - ii_lset_dx \1,7a - ii_lset_dx \1,7b - ii_lset_dx \1,7c - ii_lset_dx \1,7d - ii_lset_dx \1,7e - ii_lset_dx \1,7f -/******************************************************/ -// long -/******************************************************/ -// roxx.l #,dx - ii_lset_dx \1,90 - ii_lset_dx \1,91 - ii_lset_dx \1,92 - ii_lset_dx \1,93 - ii_lset_dx \1,94 - ii_lset_dx \1,95 - ii_lset_dx \1,96 - ii_lset_dx \1,97 -// rox.l #xdx - ii_lset_dx \1,98 - ii_lset_dx \1,99 - ii_lset_dx \1,9a - ii_lset_dx \1,9b - ii_lset_dx \1,9c - ii_lset_dx \1,9d - ii_lset_dx \1,9e - ii_lset_dx \1,9f -// roxx.l dy,dx - ii_lset_dx \1,b0 - ii_lset_dx \1,b1 - ii_lset_dx \1,b2 - ii_lset_dx \1,b3 - ii_lset_dx \1,b4 - ii_lset_dx \1,b5 - ii_lset_dx \1,b6 - ii_lset_dx \1,b7 -// rox.l dy,dx - ii_lset_dx \1,b8 - ii_lset_dx \1,b9 - ii_lset_dx \1,ba - ii_lset_dx \1,bb - ii_lset_dx \1,bc - ii_lset_dx \1,bd - ii_lset_dx \1,be - ii_lset_dx \1,bf -//-------------------------------------------------------------------- -// asr.w ea - ii_lset_opea \10,d // (ax), (ax)+ - ii_lset_opea \10,e // -(ax),d16(ax) - ii_lset_opeag \10,f // d8(ax,dy) - lea table+0x\10\2f8*4,a0 - move.l #ii_0x\10f8,(a0)+ // xxx.w - move.l #ii_0x\10f9,(a0)+ // xxx.l -// asl.w ea - ii_lset_opea \11,d // (ax), (ax)+ - ii_lset_opea \11,e // -(ax),d16(ax) - ii_lset_opeag \11,f // d8(ax,dy) - lea table+0x\11\2f8*4,a0 - move.l #ii_0x\11f8,(a0)+ // xxx.w - move.l #ii_0x\11f9,(a0)+ // xxx.l -// lsr.w ea - ii_lset_opea \12,d // (ax), (ax)+ - ii_lset_opea \12,e // -(ax),d16(ax) - ii_lset_opeag \12,f // d8(ax,dy) - lea table+0x\12\2f8*4,a0 - move.l #ii_0x\12f8,(a0)+ // xxx.w - move.l #ii_0x\12f9,(a0)+ // xxx.l -// lsr.w ea - ii_lset_opea \13,d // (ax), (ax)+ - ii_lset_opea \13,e // -(ax),d16(ax) - ii_lset_opeag \13,f // d8(ax,dy) - lea table+0x\13\2f8*4,a0 - move.l #ii_0x\13f8,(a0)+ // xxx.w - move.l #ii_0x\13f9,(a0)+ // xxx.l -// roxr.w ea - ii_lset_opea \14,d // (ax), (ax)+ - ii_lset_opea \14,e // -(ax),d16(ax) - ii_lset_opeag \14,f // d8(ax,dy) - lea table+0x\14\2f8*4,a0 - move.l #ii_0x\14f8,(a0)+ // xxx.w - move.l #ii_0x\14f9,(a0)+ // xxx.l -// roxl.w ea - ii_lset_opea \15,e // (ax), (ax)+ - ii_lset_opea \15,e // -(ax),d16(ax) - ii_lset_opeag \15,f // d8(ax,dy) - lea table+0x\15\2f8*4,a0 - move.l #ii_0x\15f8,(a0)+ // xxx.w - move.l #ii_0x\15f9,(a0)+ // xxx.l -// ror.w ea - ii_lset_opea \16,d // (ax), (ax)+ - ii_lset_opea \16,e // -(ax),d16(ax) - ii_lset_opeag \16,f // d8(ax,dy) - lea table+0x\16\2f8*4,a0 - move.l #ii_0x\16f8,(a0)+ // xxx.w - move.l #ii_0x\16f9,(a0)+ // xxx.l -// rol.w ea - ii_lset_opea \17,d // (ax), (ax)+ - ii_lset_opea \17,e // -(ax),d16(ax) - ii_lset_opeag \17,f // d8(ax,dy) - lea table+0x\17\2f8*4,a0 - move.l #ii_0x\17f8,(a0)+ // xxx.w - move.l #ii_0x\17f9,(a0)+ // xxx.l -// ende -.endm; -/******************************************************/ -ii_shift_op:.macro // 1=code -//byt------------------------------- -//asx.b #x,dx - ii_shift_op2agb 0,as,a -//lsx.b #x,dx - ii_shift_op2aub 0,ls,a -//roxx.b #x,dx - ii_shift_op2agb 1,rox,a -//rox.b #x,dx - ii_shift_op2aub 1,ro,a -//asx.b dy,dx - ii_shift_op2agb 2,as,b -//lsx.b dy,dx - ii_shift_op2aub 2,ls,b -//roxx.b dy,dx - ii_shift_op2agb 3,rox,b -//rox.b dy,dx - ii_shift_op2aub 3,ro,b -// word --------------------------------------- -//asx.w #x,dx - ii_shift_op2agw 4,as,a -//lsx.w #x,dx - ii_shift_op2auw 4,ls,a -//roxx.w #x,dx - ii_shift_op2agw 5,rox,a -//rox.w #x,dx - ii_shift_op2auw 5,ro,a -//asx.w dy,dx - ii_shift_op2agw 6,as,b -//lsx.w dy,dx - ii_shift_op2auw 6,ls,b -//roxx.w dy,dx - ii_shift_op2agw 7,rox,b -//rox.w dy,dx - ii_shift_op2auw 7,ro,b -// long --------------------------------------- -//roxx.l #x,dx - ii_shift_op2agw 9,rox,a -//rox.l #x,dx - ii_shift_op2auw 9,ro,a -//roxx.l dy,dx - ii_shift_op2agw b,rox,b -//rox.l dy,dx - ii_shift_op2auw b,ro,b -// ea --------------------------------------- -//asr.w #1,ea - ii_shift_op2ea 0,asr -//asl.w #1,ea - ii_shift_op2ea 1,asl -//lsr.w #1,ea - ii_shift_op2ea 2,lsr, -//lsl.w #1,ea - ii_shift_op2ea 3,lsl -//roxr.w #1,ea - ii_shift_op2ea 4,roxr -//roxl.w #1,ea - ii_shift_op2ea 5,roxl -//ror.w #1,ea - ii_shift_op2ea 6,ror -//rol.w #1,ea - ii_shift_op2ea 7,rol -.endm -//byt ============================================ -ii_shift_op2agb:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) - ii_shift_op1\3b \1,0,\2,d0_off+3(a7) - ii_shift_op1\3b \1,1,\2,d1_off+3(a7) - ii_shift_op1\3b \1,2,\2,d2 - ii_shift_op1\3b \1,3,\2,d3 - ii_shift_op1\3b \1,4,\2,d4 - ii_shift_op1\3b \1,5,\2,d5 - ii_shift_op1\3b \1,6,\2,d6 - ii_shift_op1\3b \1,7,\2,d7 -.endm - -ii_shift_op2aub:.macro //byt: 1=code 2=operation - ii_shift_op1\3b \1,8,\2,d0_off+3(a7) - ii_shift_op1\3b \1,9,\2,d1_off+3(a7) - ii_shift_op1\3b \1,a,\2,d2 - ii_shift_op1\3b \1,b,\2,d3 - ii_shift_op1\3b \1,c,\2,d4 - ii_shift_op1\3b \1,d,\2,d5 - ii_shift_op1\3b \1,e,\2,d6 - ii_shift_op1\3b \1,f,\2,d7 -.endm - -ii_shift_op1ab:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx - ii_shift_op0 0\1\2,b,\3r,#8,\4 - ii_shift_op0 2\1\2,b,\3r,#1,\4 - ii_shift_op0 4\1\2,b,\3r,#2,\4 - ii_shift_op0 6\1\2,b,\3r,#3,\4 - ii_shift_op0 8\1\2,b,\3r,#4,\4 - ii_shift_op0 a\1\2,b,\3r,#5,\4 - ii_shift_op0 c\1\2,b,\3r,#6,\4 - ii_shift_op0 e\1\2,b,\3r,#7,\4 - ii_shift_op0 1\1\2,b,\3l,#8,\4 - ii_shift_op0 3\1\2,b,\3l,#1,\4 - ii_shift_op0 5\1\2,b,\3l,#2,\4 - ii_shift_op0 7\1\2,b,\3l,#3,\4 - ii_shift_op0 9\1\2,b,\3l,#4,\4 - ii_shift_op0 b\1\2,b,\3l,#5,\4 - ii_shift_op0 d\1\2,b,\3l,#6,\4 - ii_shift_op0 f\1\2,b,\3l,#7,\4 -.endm - -ii_shift_op1bb:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx - ii_shift_op0b 0\1\2,b,\3r,d0_off(a7),\4 - ii_shift_op0b 2\1\2,b,\3r,d1_off(a7),\4 - ii_shift_op0 4\1\2,b,\3r,d2,\4 - ii_shift_op0 6\1\2,b,\3r,d3,\4 - ii_shift_op0 8\1\2,b,\3r,d4,\4 - ii_shift_op0 a\1\2,b,\3r,d5,\4 - ii_shift_op0 c\1\2,b,\3r,d6,\4 - ii_shift_op0 e\1\2,b,\3r,d7,\4 - ii_shift_op0b 1\1\2,b,\3l,d0_off(a7),\4 - ii_shift_op0b 3\1\2,b,\3l,d1_off(a7),\4 - ii_shift_op0 5\1\2,b,\3l,d2,\4 - ii_shift_op0 7\1\2,b,\3l,d3,\4 - ii_shift_op0 9\1\2,b,\3l,d4,\4 - ii_shift_op0 b\1\2,b,\3l,d5,\4 - ii_shift_op0 d\1\2,b,\3l,d6,\4 - ii_shift_op0 f\1\2,b,\3l,d7,\4 -.endm -// word --------------------------------------- -ii_shift_op2agw:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) - ii_shift_op1\3w \1,0,\2,d0_off+2(a7) - ii_shift_op1\3w \1,1,\2,d1_off+2(a7) - ii_shift_op1\3w \1,2,\2,d2 - ii_shift_op1\3w \1,3,\2,d3 - ii_shift_op1\3w \1,4,\2,d4 - ii_shift_op1\3w \1,5,\2,d5 - ii_shift_op1\3w \1,6,\2,d6 - ii_shift_op1\3w \1,7,\2,d7 -.endm - -ii_shift_op2auw:.macro //byt: 1=code 2=operation - ii_shift_op1\3w \1,8,\2,d0_off+2(a7) - ii_shift_op1\3w \1,9,\2,d1_off+2(a7) - ii_shift_op1\3w \1,a,\2,d2 - ii_shift_op1\3w \1,b,\2,d3 - ii_shift_op1\3w \1,c,\2,d4 - ii_shift_op1\3w \1,d,\2,d5 - ii_shift_op1\3w \1,e,\2,d6 - ii_shift_op1\3w \1,f,\2,d7 -.endm - -ii_shift_op1aw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx - ii_shift_op0 0\1\2,w,\3r,#8,\4 - ii_shift_op0 2\1\2,w,\3r,#1,\4 - ii_shift_op0 4\1\2,w,\3r,#2,\4 - ii_shift_op0 6\1\2,w,\3r,#3,\4 - ii_shift_op0 8\1\2,w,\3r,#4,\4 - ii_shift_op0 a\1\2,w,\3r,#5,\4 - ii_shift_op0 c\1\2,w,\3r,#6,\4 - ii_shift_op0 e\1\2,w,\3r,#7,\4 - ii_shift_op0 1\1\2,w,\3l,#8,\4 - ii_shift_op0 3\1\2,w,\3l,#1,\4 - ii_shift_op0 5\1\2,w,\3l,#2,\4 - ii_shift_op0 7\1\2,w,\3l,#3,\4 - ii_shift_op0 9\1\2,w,\3l,#4,\4 - ii_shift_op0 b\1\2,w,\3l,#5,\4 - ii_shift_op0 d\1\2,w,\3l,#6,\4 - ii_shift_op0 f\1\2,w,\3l,#7,\4 -.endm - -ii_shift_op1bw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx - ii_shift_op0b 0\1\2,w,\3r,d0_off(a7),\4 - ii_shift_op0b 2\1\2,w,\3r,d1_off(a7),\4 - ii_shift_op0 4\1\2,w,\3r,d2,\4 - ii_shift_op0 6\1\2,w,\3r,d3,\4 - ii_shift_op0 8\1\2,w,\3r,d4,\4 - ii_shift_op0 a\1\2,w,\3r,d5,\4 - ii_shift_op0 c\1\2,w,\3r,d6,\4 - ii_shift_op0 e\1\2,w,\3r,d7,\4 - ii_shift_op0b 1\1\2,w,\3l,d0_off(a7),\4 - ii_shift_op0b 3\1\2,w,\3l,d1_off(a7),\4 - ii_shift_op0 5\1\2,w,\3l,d2,\4 - ii_shift_op0 7\1\2,w,\3l,d3,\4 - ii_shift_op0 9\1\2,w,\3l,d4,\4 - ii_shift_op0 b\1\2,w,\3l,d5,\4 - ii_shift_op0 d\1\2,w,\3l,d6,\4 - ii_shift_op0 f\1\2,w,\3l,d7,\4 -.endm -// long --------------------------------------- -ii_shift_op2agl:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) - ii_shift_op1\3l \1,0,\2,d0_off(a7) - ii_shift_op1\3l \1,1,\2,d1_off(a7) - ii_shift_op1\3l \1,2,\2,d2 - ii_shift_op1\3l \1,3,\2,d3 - ii_shift_op1\3l \1,4,\2,d4 - ii_shift_op1\3l \1,5,\2,d5 - ii_shift_op1\3l \1,6,\2,d6 - ii_shift_op1\3l \1,7,\2,d7 -.endm - -ii_shift_op2aul:.macro //byt: 1=code 2=operation - ii_shift_op1\3l \1,8,\2,d0_off(a7) - ii_shift_op1\3l \1,9,\2,d1_off(a7) - ii_shift_op1\3l \1,a,\2,d2 - ii_shift_op1\3l \1,b,\2,d3 - ii_shift_op1\3l \1,c,\2,d4 - ii_shift_op1\3l \1,d,\2,d5 - ii_shift_op1\3l \1,e,\2,d6 - ii_shift_op1\3l \1,f,\2,d7 -.endm - -ii_shift_op1al:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx - ii_shift_op0 0\1\2,l,\3r,#8,\4 - ii_shift_op0 2\1\2,l,\3r,#1,\4 - ii_shift_op0 4\1\2,l,\3r,#2,\4 - ii_shift_op0 6\1\2,l,\3r,#3,\4 - ii_shift_op0 8\1\2,l,\3r,#4,\4 - ii_shift_op0 a\1\2,l,\3r,#5,\4 - ii_shift_op0 c\1\2,l,\3r,#6,\4 - ii_shift_op0 e\1\2,l,\3r,#7,\4 - ii_shift_op0 1\1\2,l,\3l,#8,\4 - ii_shift_op0 3\1\2,l,\3l,#1,\4 - ii_shift_op0 5\1\2,l,\3l,#2,\4 - ii_shift_op0 7\1\2,l,\3l,#3,\4 - ii_shift_op0 9\1\2,l,\3l,#4,\4 - ii_shift_op0 b\1\2,l,\3l,#5,\4 - ii_shift_op0 d\1\2,l,\3l,#6,\4 - ii_shift_op0 f\1\2,l,\3l,#7,\4 -.endm - -ii_shift_op1bl:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx - ii_shift_op0b 0\1\2,l,\3r,d0_off(a7),\4 - ii_shift_op0b 2\1\2,l,\3r,d1_off(a7),\4 - ii_shift_op0 4\1\2,l,\3r,d2,\4 - ii_shift_op0 6\1\2,l,\3r,d3,\4 - ii_shift_op0 8\1\2,l,\3r,d4,\4 - ii_shift_op0 a\1\2,l,\3r,d5,\4 - ii_shift_op0 c\1\2,l,\3r,d6,\4 - ii_shift_op0 e\1\2,l,\3r,d7,\4 - ii_shift_op0b 1\1\2,l,\3l,d0_off(a7),\4 - ii_shift_op0b 3\1\2,l,\3l,d1_off(a7),\4 - ii_shift_op0 5\1\2,l,\3l,d2,\4 - ii_shift_op0 7\1\2,l,\3l,d3,\4 - ii_shift_op0 9\1\2,l,\3l,d4,\4 - ii_shift_op0 b\1\2,l,\3l,d5,\4 - ii_shift_op0 d\1\2,l,\3l,d6,\4 - ii_shift_op0 f\1\2,l,\3l,d7,\4 -.endm -// .word ea ============================================ -ii_shift_op2ea:.macro //1=code 2.ziffer 2=shiftart -// (a0) bis (a7) ---------------------------- -ii_0xe\1d0: - move.l a0_off(a7),a1 - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1d1: - move.l a1_off(a7),a1 - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1d2: - ii_shift_typ w,\2,#1,(a2),(a2). -ii_0xe\1d3: - ii_shift_typ w,\2,#1,(a3),(a3). -ii_0xe\1d4: - ii_shift_typ w,\2,#1,(a4),(a4). -ii_0xe\1d5: - ii_shift_typ w,\2,#1,(a5),(a5). -ii_0xe\1d6: - ii_shift_typ w,\2,#1,(a6),(a6). -ii_0xe\1d7: - move.l usp,a1 - ii_shift_typ w,\2,#1,(a1),(a1). -// (a0)+ bis (a7)+ ----------------------------- -ii_0xe\1d8: - move.l a0_off(a7),a1 - addq.l #2,a0_off(a7) - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1d9: - move.l a1_off(a7),a1 - addq.l #2,a0_off(a7) - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1da: - ii_shift_typ w,\2,#1,(a2),(a2)+. -ii_0xe\1db: - ii_shift_typ w,\2,#1,(a3),(a3)+ -ii_0xe\1dc: - ii_shift_typ w,\2,#1,(a4),(a4)+ -ii_0xe\1dd: - ii_shift_typ w,\2,#1,(a5),(a5)+ -ii_0xe\1de: - ii_shift_typ w,\2,#1,(a6),(a6)+ -ii_0xe\1df: - move.l usp,a1 - addq.l #2,a1 - move.l a1,usp - subq.l #2,a1 - ii_shift_typ w,\2,#1,(a1),(a1). -// -(a0) bis -(a7) ----------------------------- -ii_0xe\1e0: - move.l a0_off(a7),a1 - subq.l #2,a1 - move.l a1,a0_off(a7) - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1e1: - move.l a1_off(a7),a1 - subq.l #2,a1 - move.l a1,a1_off(a7) - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1e2: - ii_shift_typ w,\2,#1,-(a2),(a2). -ii_0xe\1e3: - ii_shift_typ w,\2,#1,-(a3),(a3) -ii_0xe\1e4: - ii_shift_typ w,\2,#1,-(a4),(a4) -ii_0xe\1e5: - ii_shift_typ w,\2,#1,-(a5),(a5) -ii_0xe\1e6: - ii_shift_typ w,\2,#1,-(a6),(a6) -ii_0xe\1e7: - move.l usp,a1 - subq.l #2,a1 - move.l a1,usp - ii_shift_typ w,\2,#1,(a1),(a1). -// d16(a0) bis d16(a7) ----------------------------- -ii_0xe\1e8: - move.w (a0)+,a1 - add.l a0_off(a7),a1 - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1e9: - move.w (a0)+,a1 - add.l a1_off(a7),a1 - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1ea: - move.w (a0)+,a1 - add.l a2,a1 - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1eb: - move.w (a0)+,a1 - add.l a3,a1 - ii_shift_typ w,\2,#1,(a1),(a1) -ii_0xe\1ec: - move.w (a0)+,a1 - add.l a4,a1 - ii_shift_typ w,\2,#1,(a1),(a1) -ii_0xe\1ed: - move.w (a0)+,a1 - add.l a5,a1 - ii_shift_typ w,\2,#1,(a1),(a1) -ii_0xe\1ee: - move.w (a0)+,a1 - add.l a6,a1 - ii_shift_typ w,\2,#1,(a1),(a1) -ii_0xe\1ef: - mvs.w (a0)+,d0 - move.l usp,a1 - add.l d0,a1 - ii_shift_typ w,\2,#1,(a1),(a1). -// d8(a0,dy) bis d8(a7,dy) ----------------------------- -ii_0xe\1f0: - move.l a0_off(a0),a1 - jsr ewf - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1f1: - move.l a1_off(a0),a1 - jsr ewf - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1f2: - move.l a2,a1 - jsr ewf - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1f3: - move.l a3,a1 - jsr ewf - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1f4: - move.l a4,a1 - jsr ewf - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1f5: - move.l a5,a1 - jsr ewf - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1f6: - move.l a6,a1 - jsr ewf - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1f7: - move.l usp,a1 - jsr ewf - ii_shift_typ w,\2,#1,(a1),(a1). -// xxx.w xxx.l -ii_0xe\1f8: - move.w (a0)+,a1 - ii_shift_typ w,\2,#1,(a1),(a1). -ii_0xe\1f9: - move.l (a0)+,a1 - ii_shift_typ w,\2,#1,(a1),(a1). -.endm -//============================================================================ -//subroutine -//------------------------------ -ii_shift_op0:.macro // shift: 1=code 2=size 3=shift art 4=shift wert 5=ea -ii_0xe\1: - ii_shift_typ \2,\3,\4,\5,\5 -.endm - -ii_shift_op0b:.macro // shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea -ii_0xe\1: - move.l \4,d0 - ii_shift_typ \2,\3,d0,\5,\5 -.endm - -ii_shift_typ:.macro //1=size 2=shift art 3=shift wert 4=source 5=dest -#ifdef halten - halt -#endif -.ifc asr,\2 - mvs.\1 \4,d1 -.else - mvz.\1 \4,d1 -.endif -.ifc roxr,\2 - nop -.else - .ifc roxl,\2 - nop - .else - .ifc ror,\2 - nop - .else - .ifc rol,\2 - nop - .else - \2.l \3,d1 - .endif - .endif - .endif -.endif - set_cc0 - move.\1 d1,\5 - ii_end -.endm diff --git a/BaS_GNU/sources/ii_sub.h b/BaS_GNU/sources/ii_sub.h deleted file mode 100644 index 1405e1a..0000000 --- a/BaS_GNU/sources/ii_sub.h +++ /dev/null @@ -1,584 +0,0 @@ -//-------------------------------------------------------------------- -// sub -//-------------------------------------------------------------------- -/*****************************************************************************************/ -//-------------------------------------------------------------------- -// byt -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// sub.b #im,dx -//-------------------------------------------------------------------- -subbir_macro:.macro -#ifdef halten_sub - halt -#endif - move.w (a0)+,d0 - extb.l d0 - mvs.b \2,d1 - sub.l d0,d1 - set_cc0 - move.b d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub ea,dx -//-------------------------------------------------------------------- -subdd:.macro -#ifdef halten_sub - halt -#endif - mvs.\3 \1,d0 - mvs.\3 \2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub ea(l)->dy(w),dx z.B. für USP -//-------------------------------------------------------------------- -subddd:.macro -#ifdef halten_sub - halt -#endif - move.l \1,a1 - mvs.\3 a1,d0 - mvs.\3 \2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub (ea)->dy,dx -//-------------------------------------------------------------------- -subdda:.macro -#ifdef halten_sub - halt -#endif - move.l \1,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub ea->ay,(ay)+,dx -//-------------------------------------------------------------------- -subddai:.macro -#ifdef halten_sub - halt -#endif - move.l \1,a1 - mvs.\3 (a1)+,d0 - move.l a1,\1 - mvs.\3 \2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub ea->ay,-(ay),dx -//-------------------------------------------------------------------- -subddad:.macro -#ifdef halten_sub - halt -#endif - move.l \1,a1 - mvs.\3 -(a1),d0 - move.l a1,\1 - mvs.\3 \2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub d16(ay),dx -//-------------------------------------------------------------------- -subd16ad:.macro -#ifdef halten_sub - halt -#endif - move.l \1,a1 - mvs.w (a0)+,d0 - add.l d0,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub d8(ay,dy),dx -//-------------------------------------------------------------------- -subd8ad:.macro -#ifdef halten_sub - halt -#endif - move.l \1,a1 - jsr ewf -.ifc \3,l - move.l (a1),d0 - move.l \2,d1 -.else - mvs.\3 (a1),d0 - mvs.\3 \2,d1 -.endif - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub xxx.w,dx -//-------------------------------------------------------------------- -subxwd:.macro -#ifdef halten_sub - halt -#endif - move.w (a0)+,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub xxx.l,dx -//-------------------------------------------------------------------- -subxld:.macro -#ifdef halten_sub - halt -#endif - move.l (a0)+,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub d16(pc),dx -//-------------------------------------------------------------------- -subd16pcd:.macro -#ifdef halten_sub - halt -#endif - move.l a0,a1 - mvs.w (a0)+,d0 - add.l d0,a1 - mvs.\3 (a1),d0 - mvs.\3 \2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub d8(pc,dy),dx -//-------------------------------------------------------------------- -subd8pcd:.macro -#ifdef halten_sub - halt -#endif - move.l a0,a1 - jsr ewf -.ifc \3,l - move.l (a1),d0 - move.l \2,d1 -.else - mvs.\3 (a1),d0 - mvs.\3 \2,d1 -.endif - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// sub dy,ea -//-------------------------------------------------------------------- -//-------------------------------------------------------------------- -// // sub (ea)->dy,dx -//-------------------------------------------------------------------- -subeda:.macro -#ifdef halten_sub - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 (a1),d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub dx,ea->ay,(ay)+ -//-------------------------------------------------------------------- -subedai:.macro -#ifdef halten_sub - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 (a1),d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,(a1)+ - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub dx,ea->ay,(ay)+ -//-------------------------------------------------------------------- -subedaid:.macro -#ifdef halten_sub - halt -#endif - mvs.\3 \1,d0 - mvs.\3 \2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2+ - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub dx,ea->ay,-(ay) -//-------------------------------------------------------------------- -subedad:.macro -#ifdef halten_sub - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.\3 -(a1),d1 - move.l a1,\2 - sub.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub dx,ea->ay,-(ay) -//-------------------------------------------------------------------- -subedadd:.macro -#ifdef halten_sub - halt -#endif - mvs.\3 \1,d0 - mvs.\3 -\2,d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub dx,d16(ay) -//-------------------------------------------------------------------- -sube16ad:.macro -#ifdef halten_sub - halt -#endif - mvs.\3 \1,d0 - move.l \2,a1 - mvs.w (a0)+,d1 - add.l d1,a1 - mvs.\3 (a1),d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub dx,d8(ay,dy) -//-------------------------------------------------------------------- -sube8ad:.macro -#ifdef halten_sub - halt -#endif - move.l \2,a1 - jsr ewf -.ifc \3,l - move.l (a1),d1 - move.l \1,d0 -.else - mvs.\3 (a1),d1 - mvs.\3 \1,d0 -.endif - sub.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub dx,xxx.w -//-------------------------------------------------------------------- -subxwe:.macro -#ifdef halten_sub - halt -#endif - mvs.\3 \1,d0 - move.w (a0)+,a1 - mvs.\3 (a1),d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- -// // sub dx,xxx.l -//-------------------------------------------------------------------- -subxle:.macro -#ifdef halten_sub - halt -#endif - mvs.\3 \1,d0 - move.l (a0)+,a1 - mvs.\3 (a1),d1 - sub.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -/******************************************************/ -// adress register -/******************************************************/ -//-------------------------------------------------------------------- -// // suba.w ea,ax -//-------------------------------------------------------------------- -subaw:.macro -#ifdef halten_sub - halt -#endif - move.l a0,pc_off(a7) // pc auf next - movem.l (a7),d0/d1/a0/a1 // register zurpück - mvs.w \1,d0 - suba.l d0,\2 - move.l d0_off(a7),d0 - lea ii_ss(a7),a7 // stack erhöhen - rte - .endm; -//-------------------------------------------------------------------- -// sub.w ea,usp -//-------------------------------------------------------------------- -subawa7:.macro -#ifdef halten_sub - halt -#endif - mvs.w \1,d0 - move.l usp,a1 - sub.l d0,a1 - move.l a1,usp - ii_end - .endm; -//-------------------------------------------------------------------- -// // suba.w usp?,ax -//-------------------------------------------------------------------- -subawu:.macro -#ifdef halten_sub - halt -#endif - move.l a0,pc_off(a7) // pc auf next - movem.l (a7),d0/d1/a0/a1 // register zurpück - move.l a7,_a7_save - move.l usp,a7 - move.l \1,d0 - suba.l d0,\2 - move.l a7,usp - move.l _a7_save,a7 - move.l d0_off(a7),d0 - lea ii_ss(a7),a7 // stack erhöhen - rte - .endm; -//-------------------------------------------------------------------- -// // suba.w usp?,usp -//-------------------------------------------------------------------- -subawua7:.macro - subawu \1,\2 - .endm; -//-------------------------------------------------------------------- -// // suba.w d16(ay),ax -//-------------------------------------------------------------------- -subawd16a:.macro -#ifdef halten_sub - halt -#endif - move.l \1,a1 - mvs.w (a0)+,d0 - adda.l d0,a1 - mvs.w (a1),d0 - move.l \2,a1 - sub.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // suba.w d8(ay,dy),ax -//-------------------------------------------------------------------- -subawd8a:.macro -#ifdef halten_sub - halt -#endif - move.l \1,a1 - jsr ewf - mvs.w (a1),d0 - move.l \2,a1 - sub.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // suba.w xxx.w,ax -//-------------------------------------------------------------------- -subawxwax:.macro -#ifdef halten_sub - halt -#endif - move.w (a0)+,a1 - mvs.w (a1),d0 - move.l \2,a1 - suba.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // suba.w xxx.l,ax -//-------------------------------------------------------------------- -subawxlax:.macro -#ifdef halten_sub - halt -#endif - move.l (a0)+,a1 - mvs.w (a1),d0 - move.l \2,a1 - suba.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // suba.w d16(pc),ax -//-------------------------------------------------------------------- -subawd16pcax:.macro -#ifdef halten_sub - halt -#endif - move.w (a0)+,a1 - adda.l a0,a1 - mvs.w (a1),d0 - move.l \2,a1 - suba.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // suba.w d8(pc,dy),ax -//-------------------------------------------------------------------- -subawd8pcax:.macro -#ifdef halten_sub - halt -#endif - move.l a0,a1 - jsr ewf - mvs.w (a1),d0 - move.l \2,a1 - sub.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // suba.w #im,ax -//-------------------------------------------------------------------- -subawim:.macro -#ifdef halten_sub - halt -#endif - mvs.w \1,d0 - move.l \2,a1 - sub.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // suba.l d8(ay,dy),ax -//-------------------------------------------------------------------- -subald8a:.macro -#ifdef halten_sub - halt -#endif - move.l \1,a1 - jsr ewf - move.l (a1),d0 - move.l \2,a1 - sub.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//-------------------------------------------------------------------- -// // suba.l d8(pc,dy),ax -//-------------------------------------------------------------------- -subakd8pcax:.macro -#ifdef halten_sub - halt -#endif - move.l a0,a1 - jsr ewf - move.l (a1),d0 - move.l \2,a1 - sub.l d0,a1 - move.l a1,\2 - ii_end - .endm; -//***************************************************************************************** -// subx -//***************************************************************************************** -//-------------------------------------------------------------------- -// // subx dy,dx -//-------------------------------------------------------------------- -subdx:.macro -#ifdef halten_sub - halt -#endif - move.b sr_off+1(a7),d0 //ccr holen - move d0,ccr //setzen - mvs.\3 \2,d0 - mvs.\3 \1,d1 - subx.l d0,d1 - set_cc0 - move.\3 d1,\1 - ii_end - .endm; -//-------------------------------------------------------------------- -// // subx -(ay),-(ax) -//-------------------------------------------------------------------- -subdax:.macro -#ifdef halten_sub - halt -#endif - move.b sr_off+1(a7),d0 //ccr holen - move d0,ccr //setzen - move.l \1,a1 -.ifc \3,l - move.l -(a1),d0 -.else - mvs.\3 -(a1),d0 -.endif - move.l \2,a1 -.ifc \3,l - move.l -(a1),d0 -.else - mvs.\3 -(a1),d1 -.endif - subx.l d0,d1 - set_cc0 - move.\3 d1,(a1) - ii_end - .endm; -//-------------------------------------------------------------------- From fb6f975c3c22de0c7d2c675e61dd2aa43a73ffe1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 16:16:06 +0000 Subject: [PATCH 033/276] --- BaS_GNU/sources/{mmu.s => mmu.S} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename BaS_GNU/sources/{mmu.s => mmu.S} (100%) diff --git a/BaS_GNU/sources/mmu.s b/BaS_GNU/sources/mmu.S similarity index 100% rename from BaS_GNU/sources/mmu.s rename to BaS_GNU/sources/mmu.S From 1141456b52f3fa31af4f34622fc850116e31f5c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 12 Oct 2012 19:24:48 +0000 Subject: [PATCH 034/276] --- BaS_GNU/Makefile | 2 +- BaS_GNU/sources/illegal_instruction.s | 328 -------------------------- BaS_GNU/sources/mmu.S | 30 +-- BaS_GNU/sources/movem.h | 256 -------------------- BaS_GNU/sources/sysinit.h | 8 +- 5 files changed, 20 insertions(+), 604 deletions(-) delete mode 100644 BaS_GNU/sources/illegal_instruction.s delete mode 100644 BaS_GNU/sources/movem.h diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index fa070ee..ff2d2cb 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -53,4 +53,4 @@ $(OBJDIR)/%.o:$(SRCDIR)/%.c $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ $(OBJDIR)/%.o:$(SRCDIR)/%.S - $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ + $(CC) -c $(CFLAGS) -Wa,--bitwise-or $(INCLUDE) $< -o $@ diff --git a/BaS_GNU/sources/illegal_instruction.s b/BaS_GNU/sources/illegal_instruction.s deleted file mode 100644 index 21461b3..0000000 --- a/BaS_GNU/sources/illegal_instruction.s +++ /dev/null @@ -1,328 +0,0 @@ -.public _illegal_instruction -.public _illegal_table_make - -.include "startcf.h" -.include "ii_macro.h" -.include "ii_func.h" -.include "ii_op.h" -.include "ii_opc.h" -.include "ii_add.h" -.include "ii_sub.h" -.include "ii_or.h" -.include "ii_and.h" -.include "ii_dbcc.h" -.include "ii_shd.h" -.include "ii_movem.h" -.include "ii_lea.h" -.include "ii_shift.h" -.include "ii_exg.h" -.include "ii_movep.h" -.include "ii_ewf.h" -.include "ii_move.h" - -.extern _ii_shift_vec -.extern ewf - -/*******************************************************/ -.text -ii_error: - nop - halt - nop - nop - -_illegal_instruction: -#ifdef ii_on - move.w #0x2700,sr - lea -ii_ss(a7),a7 - movem.l d0/d1/a0/a1,(a7) - move.l pc_off(a7),a0 // pc - mvz.w (a0)+,d0 // code - lea table,a1 - move.l 0(a1,d0*4),a1 - jmp (a1) -/*************************************************************************************************/ -#endif -_illegal_table_make: -#ifdef ii_on - lea table,a0 - moveq #0,d0 -_itm_loop: - move.l #ii_error,(a0)+ - addq.l #1,d0 - cmp.l #0xF000,d0 - bne _itm_loop -//------------------------------------------------------------------------- - ii_ewf_lset // diverse fehlende adressierungn -//------------------------------------------------------------------------- -// 0x0000 -// ori - ii_lset_op 00 -// andi - ii_lset_op 02 -// subi - ii_lset_op 04 -// addi - ii_lset_op 06 -// eori - ii_lset_op 0a -// cmpi - ii_lset_op 0c -// movep - ii_movep_lset -//------------------------------------------------------------------------- -// 0x1000 move.b -// 0x2000 move.l -// 0x3000 move.w - ii_move_lset -//------------------------------------------------------------------------- -// 0x4000 -//------------------------------------------------------------------------- -// negx - ii_lset_op 40 -// neg - ii_lset_op 44 -// not - ii_lset_op 46 -//--------------------------------------------------------------------------------------------- -// lea d8(ax,dy.w),az; d8(pc,dy.w),az -//------------------------------------------------------------------- - ii_lea_lset -//------------------------------------------------------------------- -// movem -//------------------------------------------------------------------- - ii_movem_lset -//------------------------------------------------------------------------- -// 0x5000 -//------------------------------------------------------------------------- -// addq, subq - ii_lset_op 50 - ii_lset_op 51 - ii_lset_op 52 - ii_lset_op 53 - ii_lset_op 54 - ii_lset_op 55 - ii_lset_op 56 - ii_lset_op 57 - ii_lset_op 58 - ii_lset_op 59 - ii_lset_op 5a - ii_lset_op 5b - ii_lset_op 5c - ii_lset_op 5d - ii_lset_op 5e - ii_lset_op 5f -// dbcc - ii_lset_dbcc -// scc - ii_lset_opc 50 - ii_lset_opc 51 - ii_lset_opc 52 - ii_lset_opc 53 - ii_lset_opc 54 - ii_lset_opc 55 - ii_lset_opc 56 - ii_lset_opc 57 - ii_lset_opc 58 - ii_lset_opc 59 - ii_lset_opc 5a - ii_lset_opc 5b - ii_lset_opc 5c - ii_lset_opc 5d - ii_lset_opc 5e - ii_lset_opc 5f -//------------------------------------------------------------------------- -// 0x8000 or -//------------------------------------------------------------------------- - ii_lset_func 8 -//------------------------------------------------------------------------- -// 0x9000 sub -//------------------------------------------------------------------------- - ii_lset_func 9 -//------------------------------------------------------------------------- -// 0xb000 -//------------------------------------------------------------------------- -// eor - ii_lset_op b1 - ii_lset_op b3 - ii_lset_op b5 - ii_lset_op b7 - ii_lset_op b9 - ii_lset_op bb - ii_lset_op bd - ii_lset_op bf -//------------------------------------------------------------------------- -// 0xc000 -//------------------------------------------------------------------------- -// and - ii_lset_func c -// exg - ii_exg_lset -//------------------------------------------------------------------------- -// 0xd000 add -//------------------------------------------------------------------------- - ii_lset_func d -//------------------------------------------------------------------------- -// 0xe000 -//------------------------------------------------------------------------- -// shift register - ii_shift_lset e -//------------------------------------------------- -// differenz zwischen orginal und gemoved korrigieren - lea ii_error(pc),a1 - move.l a1,d1 - sub.l #ii_error,d1 - lea table,a0 - moveq #0,d0 -_itkorr_loop: - add.l d1,(a0)+ - addq.l #1,d0 - cmp.l #0xF000,d0 - bne _itkorr_loop -#endif - rts -#ifdef ii_on -//***********************************************************************************/ -//------------------------------------------------------------------------- - ii_ewf_func // diverse fehlende adressierungn -//------------------------------------------------------------------------- -//--------------------------------------------------------------------------------------------- -// 0x0000 -//-------------------------------------------------------------------- -// ori 00 - ii_op 00,or.l,i -//-------------------------------------------------------------------- -// andi 02 - ii_op 02,and.l,i -//-------------------------------------------------------------------- -// subi 04 - ii_op 04,and.l,i -//-------------------------------------------------------------------- -// addi 06 - ii_op 06,add.l,i -//-------------------------------------------------------------------- -// eori 0a - ii_op 0a,eor.l,i -//-------------------------------------------------------------------- -// cmpi 0c - ii_op 0c,cmp.l,i -//-------------------------------------------------------------------- -// movep - ii_movep_func -///--------------------------------------------------------------------------------------------- -// 0x1000 move.b -// 0x2000 move.l -// 0x3000 move.w - ii_move_op -//--------------------------------------------------------------------------------------------- -// 0x4000 -//--------------------------------------------------------------------------------------------- -// neg 0x40.. - ii_op 40,negx.l,n -//--------------------------------------------------------------------------------------------- -// neg 0x44.. - ii_op 44,neg.l,n -//--------------------------------------------------------------------------------------------- -// not 0x46.. - ii_op 46,not.l,n -//--------------------------------------------------------------------------------------------- -// lea d8(ax,dy.w),az; d8(pc,dy.w),az -//------------------------------------------------------------------- - ii_lea_func -//------------------------------------------------------------------- -// movem -//-------------------------------------------------------------------- -ii_movem_func -//--------------------------------------------------------------------------------------------- -// 0x5000 -//--------------------------------------------------------------------------------------------- -//dbcc - ii_dbcc_func -// addq 0x5... - ii_op 50,addq.l #8,q - ii_op 52,addq.l #1,q - ii_op 54,addq.l #2,q - ii_op 56,addq.l #3,q - ii_op 58,addq.l #4,q - ii_op 5a,addq.l #5,q - ii_op 5c,addq.l #6,q - ii_op 5e,addq.l #7,q -//--------------------------------------------------------------------------------------------- -// subq 0x5... - ii_op 51,subq.l #8,q - ii_op 53,subq.l #1,q - ii_op 55,subq.l #2,q - ii_op 57,subq.l #3,q - ii_op 59,subq.l #4,q - ii_op 5b,subq.l #5,q - ii_op 5d,subq.l #6,q - ii_op 5f,subq.l #7,q -//--------------------------------------------------------------------------------------------- -// 0x5... scc - ii_opc 50,st,c - ii_opc 51,sf,c - ii_opc 52,shi,c - ii_opc 53,sls,c - ii_opc 54,scc,c - ii_opc 55,scs,c - ii_opc 56,sne,c - ii_opc 57,seq,c - ii_opc 58,svc,c - ii_opc 59,svs,c - ii_opc 5a,spl,c - ii_opc 5b,smi,c - ii_opc 5c,sge,c - ii_opc 5d,slt,c - ii_opc 5e,sgt,c - ii_opc 5f,sle,c -//--------------------------------------------------------------------------------------------- -// 0x6000 -//-------------------------------------------------------------------- -//--------------------------------------------------------------------------------------------- -// 0x7000 -//-------------------------------------------------------------------- -//--------------------------------------------------------------------------------------------- -// 0x8000 -//--------------------------------------------------------------------------------------------- -// or - ii_func 8,or -//--------------------------------------------------------------------------------------------- -// 0x9000 -//--------------------------------------------------------------------------------------------- -// sub - ii_func 9,sub -//--------------------------------------------------------------------------------------------- -// 0xa000 -//-------------------------------------------------------------------- -//--------------------------------------------------------------------------------------------- -// 0xb000 -//--------------------------------------------------------------------------------------------- -// eor - ii_op b1,eor.l d0,q - ii_op b3,eor.l d1,q - ii_op b5,eor.l d2,q - ii_op b7,eor.l d3,q - ii_op b9,eor.l d4,q - ii_op bb,eor.l d5,q - ii_op bd,eor.l d6,q - ii_op bf,eor.l d7,q -//--------------------------------------------------------------------------------------------- -// 0xc000 -//--------------------------------------------------------------------------------------------- -// and - ii_func c,and -// exg - ii_exg_func -//--------------------------------------------------------------------------------------------- -// 0xd000 -//--------------------------------------------------------------------------------------------- -// add - ii_func d,add -//--------------------------------------------------------------------------------------------- -// 0xe000 shift -//-------------------------------------------------------------------- - ii_shift_op -//-------------------------------------------------------------------- -// 0xf000 -//-------------------------------------------------------------------- -#endif \ No newline at end of file diff --git a/BaS_GNU/sources/mmu.S b/BaS_GNU/sources/mmu.S index 0d3fade..9c668f7 100644 --- a/BaS_GNU/sources/mmu.S +++ b/BaS_GNU/sources/mmu.S @@ -2,20 +2,20 @@ /* INIT ACR und MMU /* /********************************************************************/ -.include "startcf.h" +#include "startcf.h" -.extern _rt_vbr -.extern _rt_cacr -.extern _rt_asid -.extern _rt_acr0 -.extern _rt_acr1 -.extern _rt_acr2 -.extern _rt_acr3 -.extern _rt_mmubar -.extern ___MMUBAR -.extern cpusha -.extern _video_tlb -.extern _video_sbt + .extern _rt_vbr + .extern _rt_cacr + .extern _rt_asid + .extern _rt_acr0 + .extern _rt_acr1 + .extern _rt_acr2 + .extern _rt_acr3 + .extern _rt_mmubar + .extern ___MMUBAR + .extern cpusha + .extern _video_tlb + .extern _video_sbt /* Register read/write macros */ #define MCF_MMU_MMUCR ___MMUBAR @@ -74,8 +74,8 @@ #define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) #define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) -.public _mmu_init -.public _mmutr_miss + .global _mmu_init + .global _mmutr_miss .text _mmu_init: diff --git a/BaS_GNU/sources/movem.h b/BaS_GNU/sources/movem.h deleted file mode 100644 index b79349d..0000000 --- a/BaS_GNU/sources/movem.h +++ /dev/null @@ -1,256 +0,0 @@ -// movem -_ii_movem_lset: .macro -// movem rx,xxx.L - ii_lset 0x48f9 -// movem rx,-(ax) - -// movem (ax)+,rx - ii_lset 0x4cd8 - ii_lset 0x4cd9 - ii_lset 0x4cda - ii_lset 0x4cdb - ii_lset 0x4cdc - ii_lset 0x4cdd - ii_lset 0x4cde - ii_lset 0x4cdf -// movem xxx.L,rx - ii_lset 0x4cf9 -.endm -//***********************************************************************************/ -_ii_movem_func: .macro -//------------------------------------------------------------------- -// movem.l -//-------------------------------------------------------------------- -// movem.l (ax)+,reg -//-------------------------------------------------------------------- -//------------------------------------------------------------------------------- -ii_0x4cd8: // movem.l (a0)+,reglist - mvm_macro 0x4cd0,0x41e8,2 -ii_0x4cd9: // movem.l (a1)+,reglist - mvm_macro 0x4cd1,0x43e9,2 -ii_0x4cda: // movem.l (a2)+,reglist - mvm_macro 0x4cd2,0x45ea,2 -ii_0x4cdb: // movem.l (a3)+,reglist - mvm_macro 0x4cd3,0x47eb,2 -ii_0x4cdc: // movem.l (a4)+,reglist - mvm_macro 0x4cd4,0x49ec,2 -ii_0x4cdd: // movem.l (a5)+,reglist - mvm_macro 0x4cd5,0x4bed,2 -ii_0x4cde: // movem.l (a6)+,reglist - mvm_macro 0x4cd6,0x4dee,2 -ii_0x4cdf: // movem.l (a7)+,reglist - mvm_macro 0x4cd7,0x4fef,2 -//---------------------------------------------------------------------------- -ii_0x48f9: // movem.l reg,xxx.L - move.w (a0)+,d0 - move.l (a0)+,a1 - movemrm_macro - ii_end -//--------------------------------------------------------------------------------------------- -ii_0x4cf9: // movem.l xxx.L,reg - move.w (a0)+,d0 - move.l (a0)+,a1 - movemmr_macro - ii_end -.endm -//============================================================== -mvm_macro:.macro -halt - lea az_reg_table,a1 - mvz.b (a0),d1 - mvz.b 0(a1,d1)+,d0 - mvz.b 1(a0),d1 - mvz.b 0(a1,d1)+,d1 - add.l d0,d1 - lea ___RAMBAR1,a1 - move.l a1,pc_off(a7) - move.l a1,d0 - addq.l #1,d0 - movec d0,RAMBAR1 - move.w #\1,(a1)+ // movem.x (ax),reg_list - move.w (a0)+,(a1)+ // register list - move.w #\2,(a1)+ // lea 0(ax),ax - lsl.l #\3,d1 // * anzahl byts pro wert - move.w d1,(a1)+ // offset von lea - move.w #0x4ef9,(a1)+ // jmp.l - move.l a0,(a1) // rücksprungadresse - move.l #___RAMBAR1 + 0x81,d0 // instruction - movec d0,RAMBAR1 - movem.l (a7),d0/d1/a0/a1 - lea ii_ss(a7),a7 // stack erhöhen - rte - .endm - .long 0 -az_reg_table: - .byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f - .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f - .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f - .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50 - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60 - .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70 - .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90 - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0 - .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0 - .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0 - .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0 - .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0 - .byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0 -//--------------------------------------------------------------------------------- -movemrm_macro:.macro // in d0 register liste, in a1 zieladresse -halt - tst.b d0 // datenregister zu verschieben? - bne mrm_dx // ja-> - lsr.l #8,d0 // sonst zu addressregister - jmp mmrm_nd7 // -> -mrm_dx: - lsr.l #1,d0 - bcc mmrm_nd0 - move.l d0_off(a7),(a1)+ -mmrm_nd0: - lsr.l #1,d0 - bcc mmrm_nd1 - move.l d1_off(a7),(a1)+ -mmrm_nd1: - lsr.l #1,d0 - bcc mmrm_nd2 - move.l d2,(a1)+ -mmrm_nd2: - lsr.l #1,d0 - bcc mmrm_nd3 - move.l d3,(a1)+ -mmrm_nd3: - lsr.l #1,d0 - bcc mmrm_nd4 - move.l d4,(a1)+ -mmrm_nd4: - lsr.l #1,d0 - bcc mmrm_nd5 - move.l d5,(a1)+ -mmrm_nd5: - lsr.l #1,d0 - bcc mmrm_nd6 - move.l d6,(a1)+ -mmrm_nd6: - lsr.l #1,d0 - bcc mmrm_nd7 - move.l d7,(a1)+ -mmrm_nd7: - tst.b d0 // addressregister zu verschieben? - beq mmrm_na7 - lsr.l #1,d0 - bcc mmrm_na0 - move.l a0_off(a7),(a1)+ -mmrm_na0: - lsr.l #1,d0 - bcc mmrm_na1 - move.l a1_off(a7),(a1)+ -mmrm_na1: - lsr.l #1,d0 - bcc mmrm_na2 - move.l a2,(a1)+ -mmrm_na2: - lsr.l #1,d0 - bcc mmrm_na3 - move.l a3,(a1)+ -mmrm_na3: - lsr.l #1,d0 - bcc mmrm_na4 - move.l a4,(a1)+ -mmrm_na4: - lsr.l #1,d0 - bcc mmrm_na5 - move.l a5,(a1)+ -mmrm_na5: - lsr.l #1,d0 - bcc mmrm_na6 - move.l a6,(a1)+ -mmrm_na6: - lsr.l #1,d0 - bcc mmrm_na7 - move.l a0,d1 // sichern - move.l usp,a0 // ist ja usp - move.l a0,(a1)+ // nach a0 - move.l d1,a0 // pc zurück -mmrm_na7: - .endm -//--------------------------------------------------------------------------------------------- -movemmr_macro:.macro // in d0 register liste, in a1 source adr -halt - tst.b d0 // datenregister zu verschieben? - bne mmr_dx // ja-> - lsr.l #8,d0 // sonst zu addressregister - bra mmmr_nd7 // -> -mmr_dx: - lsr.l #1,d0 - bcc mmmr_nd0 - move.l (a1)+,d0_off(a7) -mmmr_nd0: - lsr.l #1,d0 - bcc mmmr_nd1 - move.l (a1)+,d1_off(a7) -mmmr_nd1: - lsr.l #1,d0 - bcc mmmr_nd2 - move.l (a1)+,d2 -mmmr_nd2: - lsr.l #1,d0 - bcc mmmr_nd3 - move.l (a1)+,d3 -mmmr_nd3: - lsr.l #1,d0 - bcc mmmr_nd4 - move.l (a1)+,d4 -mmmr_nd4: - lsr.l #1,d0 - bcc mmmr_nd5 - move.l (a1)+,d5 -mmmr_nd5: - lsr.l #1,d0 - bcc mmmr_nd6 - move.l (a1)+,d6 -mmmr_nd6: - lsr.l #1,d0 - bcc mmmr_nd7 - move.l (a1)+,d7 -mmmr_nd7: - tst.b d0 // addressregister zu verschieben? - beq mmmr_na7 // nein-> - lsr.l #1,d0 - bcc mmmr_na0 - move.l (a1)+,a0_off(a7) -mmmr_na0: - lsr.l #1,d0 - bcc mmmr_na1 - move.l (a1)+,a1_off(a7) -mmmr_na1: - lsr.l #1,d0 - bcc mmmr_na2 - move.l (a1)+,a2 -mmmr_na2: - lsr.l #1,d0 - bcc mmmr_na3 - move.l (a1)+,a3 -mmmr_na3: - lsr.l #1,d0 - bcc mmmr_na4 - move.l (a1)+,a4 -mmmr_na4: - lsr.l #1,d0 - bcc mmmr_na5 - move.l (a1)+,a5 -mmmr_na5: - lsr.l #1,d0 - bcc mmmr_na6 - move.l (a1)+,a6 -mmmr_na6: - lsr.l #1,d0 - bcc mmmr_na7 - move.l a0,d1 // sichern - move.l (a1)+,a0 // nach a0 - move.l a0,usp // war ja usp - move.l d1,a0 // pc zurück -mmmr_na7: - .endm diff --git a/BaS_GNU/sources/sysinit.h b/BaS_GNU/sources/sysinit.h index b7a6c50..2150663 100644 --- a/BaS_GNU/sources/sysinit.h +++ b/BaS_GNU/sources/sysinit.h @@ -36,11 +36,11 @@ * __SDRAM,__SDRAM_SIZE, __FLASH, __FLASH_SIZE linker * symbols must be defined in the linker command file. */ -extern __declspec(system) uint8 __BOOT_FLASH[]; -extern __declspec(system) uint8 __BOOT_FLASH_SIZE[]; +extern __declspec(system) uint8_t __BOOT_FLASH[]; +extern __declspec(system) uint8_t __BOOT_FLASH_SIZE[]; -extern __declspec(system) uint8 __SDRAM[]; -extern __declspec(system) uint8 __SDRAM_SIZE[]; +extern __declspec(system) uint8_t __SDRAM[]; +extern __declspec(system) uint8_t __SDRAM_SIZE[]; #define BOOT_FLASH_ADDRESS (uint32)__BOOT_FLASH From 8b8e6028ce9e8a74ca70f15c7f8e91297ac9b70e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 05:26:03 +0000 Subject: [PATCH 035/276] introduced a (very ugly) macro to enable gnu as to deal with multi-character constants --- .../sources/{exceptions.s => exceptions.S} | 76 +++++++++++++------ 1 file changed, 54 insertions(+), 22 deletions(-) rename BaS_GNU/sources/{exceptions.s => exceptions.S} (91%) diff --git a/BaS_GNU/sources/exceptions.s b/BaS_GNU/sources/exceptions.S similarity index 91% rename from BaS_GNU/sources/exceptions.s rename to BaS_GNU/sources/exceptions.S index e0494c0..b34d94a 100644 --- a/BaS_GNU/sources/exceptions.s +++ b/BaS_GNU/sources/exceptions.S @@ -2,7 +2,7 @@ /* exception vectoren intialisieren /********************************************************/ -.include "startcf.h" +#include "startcf.h" .extern ___Bas_base .extern ___SUP_SP @@ -44,7 +44,7 @@ #define MCF_PSC3_PSCRB_8BIT ___MBAR+0x890C #define MCF_PSC3_PSCTB_8BIT ___MBAR+0x890C -.public _vec_init + .global _vec_init //mmu --------------------------------------------------- /* Register read/write macros */ @@ -124,7 +124,12 @@ /**********************************************************/ // macros /**********************************************************/ -irq: .macro vector,int_mask,clr_int + .altmacro + .macro irq vector,int_mask,clr_int + local irq_protect + local sev_supint + local irq_end + move.w #0x2700,sr // disable interrupt subq.l #8,a7 movem.l d0/a5,(a7) // register sichern @@ -133,17 +138,17 @@ irq: .macro vector,int_mask,clr_int // test auf protect mode --------------------- move.b DIP_SWITCHa,d0 btst #7,d0 - bne @irq_protect // ja-> + bne irq_protect // ja-> // ------------------------------------------- movem.l (a7),d0/a5 // register zurück addq.l #8,a7 - move.l vector,-(a7) - move #0x2\200,sr + move.l \vector,-(a7) + move #0x2200,sr rts -@irq_protect: +irq_protect: move.l usp,a5 // usp holen tst.b _rt_mod // supervisor? - bne @sev_supint // ja -> + bne sev_supint // ja -> mov3q.l #-1,_rt_mod // auf supervisor setzen move.l a5,_rt_usp // rt_usp speichern move.l _rt_ssp,a5 // rt_ssp holen @@ -155,8 +160,8 @@ irq: .macro vector,int_mask,clr_int move.l 12(a7),-(a5) // pc verschieben move.w 10(a7),-(a5) // sr verschieben #endif - bra @irq_end -@sev_supint: + bra irq_end +sev_supint: #ifdef cf_stack move.l 12(a7),-(a5) // pc transferieren move.l 8(a7),-(a5) // sr,vec @@ -167,17 +172,36 @@ irq: .macro vector,int_mask,clr_int move.w 10(a7),-(a5) // sr verschieben bset #5,(a5) // auf super #endif -@irq_end: +irq_end: move.l a5,usp // usp setzen lea vector,a5 adda.l _rt_vbr,a5 move.l (a5),12(a7) // vectoradresse eintragen - move.b #int_mask,10(a7) // intmaske setzen + move.b #\int_mask,10(a7) // intmaske setzen movem.l (a7),d0/a5 // register zurück addq.l #8,a7 rte // und weg .endm -/*********************************************************/ + +/* + * FIXME: ugly, but I'm just unable to come up with any better solution currently + * + * GNU as does not support multi-character constants. At least I don't know of any way it would. + * The following might look more than strange, but I considered the statement + * + * mchar move.l, 'T,'E,'S,'T,-(SP) + * + * somewhat more readable than + * + * move.l #1413829460,-(SP) + * + * If anybody knows of any better way on how to do this - please do! + * + */ + .macro mchar st,a,b,c,d,tgt + \st #\a << 24|\b<<16|\c<<8|\d,\tgt + .endm + .text _vec_init: mov3q.l #-1,_rt_mod // rt_mod auf super @@ -588,13 +612,16 @@ blinker:.long 0 /**************************************************/ /* pseudo dma */ /**************************************************/ -acsi_dma: // atari dma +acsi_dma: // atari dma move.l a1,-(a7) move.l d1,-(a7) - lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr - move.l #'DMA ',(a1) - move.l #'INT!',(a1) + lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr + mchar move.l, 'D,'M','A,'\ ,(a1) + //move.l #"DMA ",(a1) + + mchar move.l, 'I,'N,'T,'!,(a1) + //move.l #'INT!',(a1) lea 0xf0020110,a5 // fifo daten acsi_dma_start: @@ -682,11 +709,16 @@ psc3: cmp.b #2,d1 // anforderung rtc daten? bne psc3_fertig - lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr - move.l #'PIC ',(a0) - move.l #'INT ',(a0) - move.l #'RTC!',(a0) - move.l #0x0d0a,(a0) + lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr + + mchar move.l, 'P,'I,'C','\ ,(a0) + // move.l #'PIC ',(a0) + mchar move.l, 'I,'N,'T,'\ ,(a0) + // move.l #'INT ',(a0) + mchar move.l,'R,'T,'C,'\ ,(a0) + // move.l #'RTC!',(a0) + mchar move.l,'\r,'\n,0,0,(a0) + // move.l #0x0d0a,(a0) lea 0xffff8961,a0 lea MCF_PSC3_PSCTB_8BIT,a3 From 5b76177a83b1a017aed78a803708478ca760bc7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 05:27:00 +0000 Subject: [PATCH 036/276] --- BaS_GNU/sources/exceptions.S | 831 ----------------------------------- 1 file changed, 831 deletions(-) delete mode 100644 BaS_GNU/sources/exceptions.S diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S deleted file mode 100644 index b34d94a..0000000 --- a/BaS_GNU/sources/exceptions.S +++ /dev/null @@ -1,831 +0,0 @@ -/********************************************************/ -/* exception vectoren intialisieren -/********************************************************/ - -#include "startcf.h" - -.extern ___Bas_base -.extern ___SUP_SP -.extern ___BOOT_FLASH -.extern ___RAMBAR0 -.extern _rt_cacr -.extern _rt_mod -.extern _rt_ssp -.extern _rt_usp -.extern _rt_vbr -.extern _illegal_instruction -.extern _privileg_violation -.extern _mmutr_miss -.extern ___MBAR -.extern ___MMUBAR -.extern _video_tlb -.extern _video_sbt -.extern cpusha - -/* Register read/write macros */ -#define MCF_MMU_MMUCR ___MMUBAR -#define MCF_MMU_MMUOR ___MMUBAR+0x04 -#define MCF_MMU_MMUSR ___MMUBAR+0x08 -#define MCF_MMU_MMUAR ___MMUBAR+0x10 -#define MCF_MMU_MMUTR ___MMUBAR+0x14 -#define MCF_MMU_MMUDR ___MMUBAR+0x18 - -#define MCF_EPORT_EPPAR ___MBAR+0xF00 -#define MCF_EPORT_EPDDR ___MBAR+0xF04 -#define MCF_EPORT_EPIER ___MBAR+0xF05 -#define MCF_EPORT_EPDR ___MBAR+0xF08 -#define MCF_EPORT_EPPDR ___MBAR+0xF09 -#define MCF_EPORT_EPFR ___MBAR+0xF0C - -#define MCF_GPIO_PODR_FEC1L ___MBAR+0xA07 - -#define MCF_PSC0_PSCTB_8BIT ___MBAR+0x860C - -#define MCF_PSC3_PSCRB_8BIT ___MBAR+0x890C -#define MCF_PSC3_PSCTB_8BIT ___MBAR+0x890C - - .global _vec_init - -//mmu --------------------------------------------------- -/* Register read/write macros */ -#define MCF_MMU_MMUCR ___MMUBAR -#define MCF_MMU_MMUOR ___MMUBAR+0x04 -#define MCF_MMU_MMUSR ___MMUBAR+0x08 -#define MCF_MMU_MMUAR ___MMUBAR+0x10 -#define MCF_MMU_MMUTR ___MMUBAR+0x14 -#define MCF_MMU_MMUDR ___MMUBAR+0x18 - - -/* Bit definitions and macros for MCF_MMU_MMUCR */ -#define MCF_MMU_MMUCR_EN (0x1) -#define MCF_MMU_MMUCR_ASM (0x2) - -/* Bit definitions and macros for MCF_MMU_MMUOR */ -#define MCF_MMU_MMUOR_UAA (0x1) -#define MCF_MMU_MMUOR_ACC (0x2) -#define MCF_MMU_MMUOR_RW (0x4) -#define MCF_MMU_MMUOR_ADR (0x8) -#define MCF_MMU_MMUOR_ITLB (0x10) -#define MCF_MMU_MMUOR_CAS (0x20) -#define MCF_MMU_MMUOR_CNL (0x40) -#define MCF_MMU_MMUOR_CA (0x80) -#define MCF_MMU_MMUOR_STLB (0x100) -#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) - -/* Bit definitions and macros for MCF_MMU_MMUSR */ -#define MCF_MMU_MMUSR_HIT (0x2) -#define MCF_MMU_MMUSR_WF (0x8) -#define MCF_MMU_MMUSR_RF (0x10) -#define MCF_MMU_MMUSR_SPF (0x20) - -/* Bit definitions and macros for MCF_MMU_MMUAR */ -#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_MMU_MMUTR */ -#define MCF_MMU_MMUTR_V (0x1) -#define MCF_MMU_MMUTR_SG (0x2) -#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) -#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) - -/* Bit definitions and macros for MCF_MMU_MMUDR */ -#define MCF_MMU_MMUDR_LK (0x2) -#define MCF_MMU_MMUDR_X (0x4) -#define MCF_MMU_MMUDR_W (0x8) -#define MCF_MMU_MMUDR_R (0x10) -#define MCF_MMU_MMUDR_SP (0x20) -#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) -#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) -#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) - -#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V) -#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) -#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) -#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) -#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) -#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) -//--------------------------------------------------- -/********************************************************************* -* -* General Purpose Timers (GPT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPT0_GMS ___MBAR+0x800 - -/********************************************************************* -* -* Slice Timers (SLT) -* -*********************************************************************/ - -#define MCF_SLT0_SCNT ___MBAR+0x908 - -/**********************************************************/ -// macros -/**********************************************************/ - .altmacro - .macro irq vector,int_mask,clr_int - local irq_protect - local sev_supint - local irq_end - - move.w #0x2700,sr // disable interrupt - subq.l #8,a7 - movem.l d0/a5,(a7) // register sichern - lea MCF_EPORT_EPFR,a5 - move.b #clr_int,(a5) // clear int pending -// test auf protect mode --------------------- - move.b DIP_SWITCHa,d0 - btst #7,d0 - bne irq_protect // ja-> -// ------------------------------------------- - movem.l (a7),d0/a5 // register zurück - addq.l #8,a7 - move.l \vector,-(a7) - move #0x2200,sr - rts -irq_protect: - move.l usp,a5 // usp holen - tst.b _rt_mod // supervisor? - bne sev_supint // ja -> - mov3q.l #-1,_rt_mod // auf supervisor setzen - move.l a5,_rt_usp // rt_usp speichern - move.l _rt_ssp,a5 // rt_ssp holen -#ifdef cf_stack - move.l 12(a7),-(a5) // pc transferieren - move.l 8(a7),-(a5) // sr,vec -#else - move.w 8(a7),-(a5) // vector nr. - move.l 12(a7),-(a5) // pc verschieben - move.w 10(a7),-(a5) // sr verschieben -#endif - bra irq_end -sev_supint: -#ifdef cf_stack - move.l 12(a7),-(a5) // pc transferieren - move.l 8(a7),-(a5) // sr,vec - bset #5,2(a5) // auf super setzen -#else - move.w 8(a7),-(a5) // vector nr. - move.l 12(a7),-(a5) // pc verschieben - move.w 10(a7),-(a5) // sr verschieben - bset #5,(a5) // auf super -#endif -irq_end: - move.l a5,usp // usp setzen - lea vector,a5 - adda.l _rt_vbr,a5 - move.l (a5),12(a7) // vectoradresse eintragen - move.b #\int_mask,10(a7) // intmaske setzen - movem.l (a7),d0/a5 // register zurück - addq.l #8,a7 - rte // und weg - .endm - -/* - * FIXME: ugly, but I'm just unable to come up with any better solution currently - * - * GNU as does not support multi-character constants. At least I don't know of any way it would. - * The following might look more than strange, but I considered the statement - * - * mchar move.l, 'T,'E,'S,'T,-(SP) - * - * somewhat more readable than - * - * move.l #1413829460,-(SP) - * - * If anybody knows of any better way on how to do this - please do! - * - */ - .macro mchar st,a,b,c,d,tgt - \st #\a << 24|\b<<16|\c<<8|\d,\tgt - .endm - -.text -_vec_init: - mov3q.l #-1,_rt_mod // rt_mod auf super - clr.l _rt_ssp - clr.l _rt_usp - clr.l _rt_vbr - move.l #___RAMBAR0,d0 // sind in rambar0 - movec d0,VBR - move.l d0,a0 - move.l a0,a2 -init_vec: - move.l #256,d0 - lea std_exc_vec(pc),a1 // standard vector -init_vec_loop: - move.l a1,(a2)+ // mal standard vector für alle setzen - subq.l #1,d0 - bne init_vec_loop - - move.l #___SUP_SP,(a0) - lea reset_vector(pc),a1 - move.l a1,0x04(a0) - lea acess(pc),a1 - move.l a1,0x08(a0) - - move.b DIP_SWITCHa,d0 // ++ vr - btst #7,d0 - beq no_protect_vectors - - lea _illegal_instruction(pc),a1 - move.l a1,0x0c(a0) - lea _illegal_instruction(pc),a1 - move.l a1,0x10(a0) - lea zero_divide(pc),a1 - move.l a1,0x14(a0) - lea _privileg_violation(pc),a1 - move.l a1,0x20(a0) - lea linea(pc),a1 - move.l a1,0x28(a0) - lea linef(pc),a1 - move.l a1,0x2c(a0) - lea format(pc),a1 - move.l a1,0x38(a0) - - // floating point overflow - lea flpoow(pc),a1 - move.l a1,0xc0(a0) - lea flpoow(pc),a1 - move.l a1,0xc4(a0) - lea flpoow(pc),a1 - move.l a1,0xc8(a0) - lea flpoow(pc),a1 - move.l a1,0xcc(a0) - lea flpoow(pc),a1 - move.l a1,0xd0(a0) - lea flpoow(pc),a1 - move.l a1,0xd4(a0) - lea flpoow(pc),a1 - move.l a1,0xd8(a0) - lea flpoow(pc),a1 - move.l a1,0xdc(a0) -no_protect_vectors: - - -// int 1-7 - lea irq1(pc),a1 - move.l a1,0x104(a0) - lea irq2(pc),a1 - move.l a1,0x108(a0) - lea irq3(pc),a1 - move.l a1,0x10c(a0) - lea irq4(pc),a1 - move.l a1,0x110(a0) - lea irq5(pc),a1 - move.l a1,0x114(a0) - lea irq6(pc),a1 - move.l a1,0x118(a0) - lea irq7(pc),a1 - move.l a1,0x11c(a0) -//psc_vectors - lea psc3(pc),a1 - move.l a1,0x180(a0) -//timer 1 vectors - lea timer0(pc),a1 - move.l a1,0x1f8(a0) - rts -/********************************************************/ -/* exception vector routinen -/********************************************************/ -vector_table_start: -std_exc_vec: - move.w #0x2700,sr // disable interrupt - subq.l #8,a7 - movem.l d0/a5,(a7) // register sichern -// test auf protect mode ------------------------------- - move.b DIP_SWITCHa,d0 - btst #7,d0 - bne stv_protect // ja-> -//------------------------------------------------------ - move.w 8(a7),d0 // vector holen - and.l #0x3fc,d0 // vector nummer ausmaskieren - add.l _rt_vbr,d0 // + basis - move.l d0,a5 - move.l (a5),d0 - move.l 4(a7),a5 // a5 zurück - move.l d0,4(a7) - move.w 10(a7),d0 - bset #13,d0 // super - move.w d0,sr // orginal sr wert in super setzen - move.l (a7)+,d0 // d0 zurück - rts -stv_protect: - move.l usp,a5 // usp holen - tst.b _rt_mod // supervisor? - bne sev_sup // ja -> - mov3q.l #-1,_rt_mod // auf supervisor setzen - move.l a5,_rt_usp // rt_usp speichern - move.l _rt_ssp,a5 // rt_ssp holen -#ifdef cf_stack - move.l 12(a7),-(a5) // pc transferieren - move.l 8(a7),d0 // sr holen - move.l d0,-(a5) // sr transferieren - swap d0 // vec -> lw -#else - move.w 8(a7),d0 // vector holen - move.w d0,-(a5) // ablegen - move.l 12(a7),-(a5) // pc transferieren - move.w 10(a7),-(a5) // sr transferieren -#endif - move.l a5,usp // usp setzen - and.l #0x3fc,d0 // vector nummer ausmaskieren - add.l _rt_vbr,d0 // + basis - move.l d0,a5 - move.l (a5),12(a7) // hier geht's weiter - movem.l (a7),d0/a5 // register zurück - addq.l #8,a7 - rte // und weg -sev_sup: -#ifdef cf_stack - move.l 12(a7),-(a5) // pc transferieren - move.l 8(a7),d0 // sr holen - bset #13,d0 // war aus rt super - move.l d0,-(a5) // sr transferieren - swap d0 // vec -> lw -#else - move.w 8(a7),d0 // vector holen - move.w d0,-(a5) // ablegen - move.l 12(a7),-(a5) // pc transferieren - move.w 10(a7),-(a5) // sr transferieren - bset #5,(a5) // war aus super -#endif - move.l a5,usp // usp setzen - and.l #0x3fc,d0 // vector nummer ausmaskieren - add.l _rt_vbr,d0 // + basis - move.l d0,a5 - move.l (a5),12(a7) // hier geht's weiter - movem.l (a7),d0/a5 // register zurück - addq.l #8,a7 - rte // und weg -//******************************************* -reset_vector: - move.w #0x2700,sr // disable interrupt - move.l #0x31415926,d0 - cmp.l 0x426,d0 // reset vector gültg? - beq std_exc_vec // ja-> - jmp ___BOOT_FLASH // sonst kaltstart -acess: - move.w #0x2700,sr // disable interrupt - move.l d0,-(sp) // ++ vr - move.w 4(sp),d0 - andi.l #0x0c03,d0 - cmpi.l #0x0401,d0 - beq access_mmu - cmpi.l #0x0402,d0 - beq access_mmu - cmpi.l #0x0802,d0 - beq access_mmu - cmpi.l #0x0c02,d0 - beq access_mmu - bra bus_error -access_mmu: - move.l MCF_MMU_MMUSR,d0 - btst #1,d0 - bne bus_error - move.l MCF_MMU_MMUAR,d0 - cmp.l #___Bas_base,d0 // max User RAM Bereich - bge bus_error // grösser -> bus error - bra _mmutr_miss -bus_error: - move.l (sp)+,d0 - bra std_exc_vec - -zero_divide: - move.w #0x2700,sr // disable interrupt - move.l a0,-(a7) - move.l d0,-(a7) - move.l 12(a7),a0 // pc - move.w (a0)+,d0 // befehlscode - btst #7,d0 // long? - beq zd_word // nein-> - addq.l #2,a0 -zd_word: - and.l 0x3f,d0 // ea ausmaskieren - cmp.w #0x08,d0 // -(ax) oder weniger - ble zd_end - addq.l #2,a0 - cmp.w #0x39,d0 // xxx.L - bne zd_nal - addq.l #2,a0 - bra zd_end -zd_nal: cmp.w #0x3c,d0 // immediate? - bne zd_end // nein-> - btst #7,d0 // long? - beq zd_end // nein - addq.l #2,a0 -zd_end: - move.l a0,12(a7) - move.l (a7)+,d0 - move.l (a7)+,a0 - rte - -linea: - move.w #0x2700,sr // disable interrupt - halt - nop - nop -linef: - move.w #0x2700,sr // disable interrupt - halt - nop - nop -format: - move.w #0x2700,sr // disable interrupt - halt - nop - nop -//floating point -flpoow: - move.w #0x2700,sr // disable interrupt - halt - nop - nop -irq1: - irq 0x64,1,0x02 -irq2: // hbl - // move.b #3,2(a7) - // rte - irq 0x68,2,0x04 -irq3: - irq 0x6c,3,0x08 -irq4: // vbl - irq 0x70,4,0x10 -irq5: // acp - irq 0x74,5,0x20 -irq6: // mfp - move.w #0x2700,sr // disable interrupt - subq.l #8,a7 - movem.l d0/a5,(a7) // register sichern - lea MCF_EPORT_EPFR,a5 - move.b #0x40,(a5) // clear int6 -// test auf timeout screen adr change ------------------------------------------------------- - move.l _video_sbt,d0 - beq irq6_non_sca // wenn 0 nichts zu tun - sub.l #0x70000000,d0 // 14 sec abzählen - lea MCF_SLT0_SCNT,a5 - cmp.l (a5),d0 // aktuelle zeit weg - ble irq6_non_sca // noch nicht abgelaufen - lea -28(a7),a7 - movem.l d0-d4/a0-a1,(a7) // register sichern - clr.l d3 // beginn mit 0 - bsr cpusha // cache leeren - // eintrag suchen - irq6_next_sca: - move.l d3,d0 - move.l d0,MCF_MMU_MMUAR // addresse - move.l #0x106,d4 - move.l d4,MCF_MMU_MMUOR // suchen -> - nop - move.l MCF_MMU_MMUOR,d4 - clr.w d4 - swap d4 - move.l d4,MCF_MMU_MMUAR - mvz.w #0x10e,d4 - move.l d4,MCF_MMU_MMUOR // einträge holen aus mmu - nop - move.l MCF_MMU_MMUTR,d4 // ID holen - lsr.l #2,d4 // bit 9 bis 2 - cmp.w #sca_page_ID,d4 // ist screen change ID? - bne irq6_sca_pn // nein -> page keine screen area next -// eintrag ändern - add.l #std_mmutr,d0 - move.l d3,d1 // page 0? - beq irq6_sca_pn0 // ja -> - add.l #cb_mmudr,d1 // sonst page cb - bra irq6_sca_pn1c -irq6_sca_pn0: - add.l #wt_mmudr|MCF_MMU_MMUDR_LK,d1 // page wt and locked -irq6_sca_pn1c: - mvz.w #0x10b,d2 // MMU update - move.l d0,MCF_MMU_MMUTR - move.l d1,MCF_MMU_MMUDR - move.l d2,MCF_MMU_MMUOR // setze tlb data only - nop -// page copy - move.l d3,a0 - add.l #0x60000000,a0 - move.l d3,a1 - move.l #0x10000,d4 // die ganze page -irq6_vcd0_loop: - move.l (a0)+,(a1)+ // page copy - move.l (a0)+,(a1)+ - move.l (a0)+,(a1)+ - move.l (a0)+,(a1)+ - subq.l #1,d4 - bne irq6_vcd0_loop - nop -irq6_sca_pn: - add.l #0x00100000,d3 // next - cmp.l #0x00d00000,d3 // ende? - blt irq6_next_sca // nein-> - - move.l #0x2000,d0 - move.l d0,_video_tlb // anfangszustand wieder herstellen - clr.l _video_sbt // zeit löschen - - movem.l (a7),d0-d4/a0-a1 // register zurück - lea 28(a7),a7 -irq6_non_sca: -// test auf acsi dma ----------------------------------------------------------------- - lea 0xfffffa0b,a5 - bset #7,-4(a5) // int ena - btst.b #7,(a5) // acsi dma int? - beq non_acsi_dma - bsr acsi_dma -non_acsi_dma: -// ---------------------------------------------------------------------------------- - tst.b (a5) - bne irq6_1 - tst.b 2(a5) - bne irq6_1 - movem.l (a7),d0/a5 - addq.l #8,a7 - rte -irq6_1: - lea MCF_GPIO_PODR_FEC1L,a5 - bclr.b #4,(a5) // led on - lea blinker(pc),a5 - addq.l #1,(a5) // +1 - move.l (a5),d0 - and.l #0x80,d0 - bne irq6_2 - lea MCF_GPIO_PODR_FEC1L,a5 - bset.b #4,(a5) // led off -irq6_2: -// test auf protect mode --------------------- - move.b DIP_SWITCHa,d0 - btst #7,d0 - bne irq6_3 // ja-> -// ------------------------------------------- - move.l 0xF0020000,a5 // vector holen - add.l _rt_vbr,a5 // basis - move.l (a5),d0 // vector holen - move.l 4(a7),a5 // a5 zurück - move.l d0,4(a7) // vector eintragen - move.l (a7)+,d0 // d0 zurück - move #0x2600,sr - rts -irq6_3: - move.l usp,a5 // usp holen - tst.b _rt_mod // supervisor? - bne sev_sup6 // ja -> - mov3q.l #-1,_rt_mod // auf supervisor setzen - move.l a5,_rt_usp // rt_usp speichern - move.l _rt_ssp,a5 // rt_ssp holen -#ifdef cf_stack - move.l 12(a7),-(a5) // pc transferieren - move.l 8(a7),-(a5) // sr transferieren -#else - move.w 8(a7),-(a5) // vector transferieren - move.l 12(a7),-(a5) // pc transferieren - move.w 10(a7),-(a5) // sr transferieren -#endif - move.l a5,usp // usp setzen - move.l 0xF0020000,a5 // vector holen: intack routine - add.l _rt_vbr,a5 // virtuelle VBR des Systems - move.l (a5),12(a7) // hier gehts weiter - movem.l (a7),d0/a5 // register zurück - addq.l #8,a7 - move.b #6,2(a7) // intmaske setzen - rte // und weg -sev_sup6: -#ifdef cf_stack - move.l 12(a7),-(a5) // pc transferieren - move.l 8(a7),-(a5) // sr,vec - bset #5,2(a5) // auf super setzen -#else - move.w 8(a7),-(a5) // vector nr. - move.l 12(a7),-(a5) // pc verschieben - move.w 10(a7),-(a5) // sr verschieben - bset #5,(a5) // auf super -#endif - move.l a5,usp // usp setzen - move.l 0xF0020000,a5 // vector holen: intack routine - add.l _rt_vbr,a5 // virtuelle VBR des Systems - move.l (a5),12(a7) // hier gehts weiter - movem.l (a7),d0/a5 // register zurück - rts -blinker:.long 0 -/**************************************************/ -/* pseudo dma */ -/**************************************************/ -acsi_dma: // atari dma - move.l a1,-(a7) - move.l d1,-(a7) - - lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr - mchar move.l, 'D,'M','A,'\ ,(a1) - //move.l #"DMA ",(a1) - - mchar move.l, 'I,'N,'T,'!,(a1) - //move.l #'INT!',(a1) - - lea 0xf0020110,a5 // fifo daten -acsi_dma_start: - move.l -12(a5),a1 // dma adresse - move.l -8(a5),d0 // byt counter - ble acsi_dma_end - btst.b #0,-16(a5) // write? (dma modus reg) - bne acsi_dma_wl // ja-> -acsi_dma_rl: - tst.b -4(a5) // dma req? - bpl acsi_dma_fertig // nein-> - move.l (a5),(a1)+ // read 4 bytes - move.l (a5),(a1)+ // read 4 bytes - move.l (a5),(a1)+ // read 4 bytes - move.l (a5),(a1)+ // read 4 bytes - - moveq #'.',d1 - move.b d1,MCF_PSC0_PSCTB_8BIT - - sub.l #16,d0 // byt counter -16 - bpl acsi_dma_rl - bra acsi_dma_fertig -acsi_dma_wl: - tst.b -4(a5) // dma req? - bpl acsi_dma_fertig // nein-> - move.l (a1)+,(a5) // write 4 byts - move.l (a1)+,(a5) // write 4 byts - move.l (a1)+,(a5) // write 4 byts - move.l (a1)+,(a5) // write 4 byts - - moveq #'.',d1 - move.b d1,MCF_PSC0_PSCTB_8BIT - - sub.l #16,d0 // byt counter -16 - bpl acsi_dma_wl -acsi_dma_fertig: - move.l a1,-12(a5) // adresse zurück - move.l d0,-8(a5) // byt counter zurück -acsi_dma_end: - tst.b -4(a5) // dma req? - bmi acsi_dma_start // ja-> - lea 0xfffffa0b,a5 - bclr.b #7,4(a5) // clear int in service mfp - bclr.b #7,(a5) // clear int pending mfp 0xfffffa0b - - move.w #0x0d0a,d1 - move.w d1,MCF_PSC0_PSCTB_8BIT - - move.l (a7)+,d1 - move.l (a7)+,a1 - rts -/**************************************************/ -/* irq 7 = pseudo bus error */ -/**************************************************/ -irq7: - lea -12(sp),sp - movem.l d0/a0,(sp) - - move.l ___RAMBAR0+0x008,a0 // Real Access Error handler - move.l a0,8(sp) // This will be the return address for rts - - move.w 12(sp),d0 // Format/Vector word - andi.l #0xf000,d0 // Keep only the Format - ori.l #2*4,d0 // Simulate Vector #2, no Fault - move.w d0,12(sp) - - // TODO: Inside an interrupt handler, 16(sp) is the return address. - // For an Access Error, it should be the address of the fault instruction instead - - lea MCF_EPORT_EPFR,a0 - move.b #0x80,(a0) // clear int7 - move.l (sp)+,d0 - move.l (sp)+,a0 - rts // Forward to the Access Error handler - -/**************************************************/ -/* psc3 com PIC MCF */ -/**************************************************/ -psc3: - move.w #0x2700,sr // disable interrupt - lea -20(a7),a7 - movem.l d0-d2/a0/a3,(a7) - lea MCF_PSC3_PSCRB_8BIT,a3 - move.b (a3),d1 - cmp.b #2,d1 // anforderung rtc daten? - bne psc3_fertig - - lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr - - mchar move.l, 'P,'I,'C','\ ,(a0) - // move.l #'PIC ',(a0) - mchar move.l, 'I,'N,'T,'\ ,(a0) - // move.l #'INT ',(a0) - mchar move.l,'R,'T,'C,'\ ,(a0) - // move.l #'RTC!',(a0) - mchar move.l,'\r,'\n,0,0,(a0) - // move.l #0x0d0a,(a0) - - lea 0xffff8961,a0 - lea MCF_PSC3_PSCTB_8BIT,a3 - clr.l d1 - moveq #64,d2 - move.b #0x82,(a3) // header: rtcd mcf->pic -loop_sr2: - move.b d1,(a0) - move.b 2(a0),d0 - move.b d0,(a3) - addq.l #1,d1 - cmp.b d1,d2 - bne loop_sr2 -psc3_fertig: - movem.l (a7),d0-d2/a0/a3 // register zurück - lea 20(a7),a7 - RTE -/**************************************************/ -/* timer 0: video change later also others -/**************************************************/ -timer0: - move #0x2700,sr -// halt - lea -28(a7),a7 - movem.l d0-d4/a0-a1,(a7) - mvz.b 0xffff8201,d0 // löschen und high byt - cmp.w #2,d0 - blt video_chg_end - cmp.w #0xd0,d0 // normale addresse - blt sca_other // nein-> - lea MCF_SLT0_SCNT,a0 - move.l (a0),d4 - move.l d4,_video_sbt // time sichern -sca_other: - lsl.l #8,d0 - move.b 0xffff8203,d0 // mid byt - lsl.l #8,d0 - move.b 0xffff820d,d0 // low byt - move.l d0,d3 -video_chg_1page: -// test ob page schon gesetzt - moveq #20,d4 - move.l d0,d2 - lsr.l d4,d2 // neue page - move.l _video_tlb,d4 - bset.l d2,d4 // setzen als geändert - bne video_chg_2page // schon gesetzt gewesen? ja->weg - move.l d4,_video_tlb - bsr cpusha // cache leeren -// daten copieren -video_copy_data: - move.l d4,_video_tlb - and.l #0x00f00000,d0 - move.l d0,a0 - move.l a0,a1 - add.l #0x60000000,a1 - move.l #0x10000,d4 // die ganze page -video_copy_data_loop: - move.l (a0)+,(a1)+ - move.l (a0)+,(a1)+ - move.l (a0)+,(a1)+ - move.l (a0)+,(a1)+ - subq.l #1,d4 - bne video_copy_data_loop -// eintrag suchen - move.l d0,MCF_MMU_MMUAR // addresse - move.l #0x106,d4 - move.l d4,MCF_MMU_MMUOR // suchen -> schlägt neuen vor wenn keiner - nop - move.l MCF_MMU_MMUOR,d4 - clr.w d4 - swap d4 - move.l d4,MCF_MMU_MMUAR - move.l d0,d1 - add.l #MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 - add.l #0x60000000|wt_mmudr|MCF_MMU_MMUDR_LK,d1 - mvz.w #0x10b,d2 // MMU update - move.l d0,MCF_MMU_MMUTR - move.l d1,MCF_MMU_MMUDR - move.l d2,MCF_MMU_MMUOR // setzen vidoe maped to 60xxx only data - nop -video_chg_2page: -// test ob evt. anschliessende page gesetzt werden muss - move.l d3,d0 - mvz.w 0xffff8210,d4 // byts pro zeile - mvz.w 0xffff82aa,d2 // zeilen ende - mvz.w 0xffff82a8,d1 // zeilenstart - sub.l d1,d2 // differenz = anzahl zeilen - mulu d2,d4 // maximal 480 zeilen - add.l d4,d0 // video grösse - cmp.l #0xe00000,d0 // maximale addresse - bge video_chg_end // wenn gleich oder grösser -> fertig - moveq #20,d4 - move.l d0,d2 - lsr.l d4,d2 // neue page - move.l _video_tlb,d4 - bset.l d2,d4 // setzen als geändert - beq video_copy_data // nein nochmal -video_chg_end: -// int pending löschen - lea MCF_GPT0_GMS,a0 - bclr.b #0,3(a0) - nop - bset.b #0,3(a0) - - movem.l (a7),d0-d4/a0-a1 - lea 28(a7),a7 -//-------------------------------------------------------------------------------------------------------- - RTE - From dfc24ddd9b058e5046b382609c9cb82cad8a2c40 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 05:33:26 +0000 Subject: [PATCH 037/276] got lost somehow --- BaS_GNU/sources/exceptions.S | 799 +++++++++++++++++++++++++++++++++++ 1 file changed, 799 insertions(+) create mode 100644 BaS_GNU/sources/exceptions.S diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S new file mode 100644 index 0000000..fa101d6 --- /dev/null +++ b/BaS_GNU/sources/exceptions.S @@ -0,0 +1,799 @@ +/********************************************************/ +/* exception vectoren intialisieren +/********************************************************/ + +#include "startcf.h" + +.extern ___Bas_base +.extern ___SUP_SP +.extern ___BOOT_FLASH +.extern ___RAMBAR0 +.extern _rt_cacr +.extern _rt_mod +.extern _rt_ssp +.extern _rt_usp +.extern _rt_vbr +.extern _illegal_instruction +.extern _privileg_violation +.extern _mmutr_miss +.extern ___MBAR +.extern ___MMUBAR +.extern _video_tlb +.extern _video_sbt +.extern cpusha + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + +#define MCF_EPORT_EPPAR ___MBAR+0xF00 +#define MCF_EPORT_EPDDR ___MBAR+0xF04 +#define MCF_EPORT_EPIER ___MBAR+0xF05 +#define MCF_EPORT_EPDR ___MBAR+0xF08 +#define MCF_EPORT_EPPDR ___MBAR+0xF09 +#define MCF_EPORT_EPFR ___MBAR+0xF0C + +#define MCF_GPIO_PODR_FEC1L ___MBAR+0xA07 + +#define MCF_PSC0_PSCTB_8BIT ___MBAR+0x860C + +#define MCF_PSC3_PSCRB_8BIT ___MBAR+0x890C +#define MCF_PSC3_PSCTB_8BIT ___MBAR+0x890C + +.public _vec_init + +//mmu --------------------------------------------------- +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + +#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V) +#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +//--------------------------------------------------- +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS ___MBAR+0x800 + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +#define MCF_SLT0_SCNT ___MBAR+0x908 + +/**********************************************************/ +// macros +/**********************************************************/ +irq: .macro vector,int_mask,clr_int + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern + lea MCF_EPORT_EPFR,a5 + move.b #clr_int,(a5) // clear int pending +// test auf protect mode --------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne @irq_protect // ja-> +// ------------------------------------------- + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + move.l vector,-(a7) + move #0x2\200,sr + rts +@irq_protect: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne @sev_supint // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben +#endif + bra @irq_end +@sev_supint: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec + bset #5,2(a5) // auf super setzen +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif +@irq_end: + move.l a5,usp // usp setzen + lea vector,a5 + adda.l _rt_vbr,a5 + move.l (a5),12(a7) // vectoradresse eintragen + move.b #int_mask,10(a7) // intmaske setzen + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg + .endm +/*********************************************************/ +.text +_vec_init: + mov3q.l #-1,_rt_mod // rt_mod auf super + clr.l _rt_ssp + clr.l _rt_usp + clr.l _rt_vbr + move.l #___RAMBAR0,d0 // sind in rambar0 + movec d0,VBR + move.l d0,a0 + move.l a0,a2 +init_vec: + move.l #256,d0 + lea std_exc_vec(pc),a1 // standard vector +init_vec_loop: + move.l a1,(a2)+ // mal standard vector für alle setzen + subq.l #1,d0 + bne init_vec_loop + + move.l #___SUP_SP,(a0) + lea reset_vector(pc),a1 + move.l a1,0x04(a0) + lea acess(pc),a1 + move.l a1,0x08(a0) + + move.b DIP_SWITCHa,d0 // ++ vr + btst #7,d0 + beq no_protect_vectors + + lea _illegal_instruction(pc),a1 + move.l a1,0x0c(a0) + lea _illegal_instruction(pc),a1 + move.l a1,0x10(a0) + lea zero_divide(pc),a1 + move.l a1,0x14(a0) + lea _privileg_violation(pc),a1 + move.l a1,0x20(a0) + lea linea(pc),a1 + move.l a1,0x28(a0) + lea linef(pc),a1 + move.l a1,0x2c(a0) + lea format(pc),a1 + move.l a1,0x38(a0) + + // floating point overflow + lea flpoow(pc),a1 + move.l a1,0xc0(a0) + lea flpoow(pc),a1 + move.l a1,0xc4(a0) + lea flpoow(pc),a1 + move.l a1,0xc8(a0) + lea flpoow(pc),a1 + move.l a1,0xcc(a0) + lea flpoow(pc),a1 + move.l a1,0xd0(a0) + lea flpoow(pc),a1 + move.l a1,0xd4(a0) + lea flpoow(pc),a1 + move.l a1,0xd8(a0) + lea flpoow(pc),a1 + move.l a1,0xdc(a0) +no_protect_vectors: + + +// int 1-7 + lea irq1(pc),a1 + move.l a1,0x104(a0) + lea irq2(pc),a1 + move.l a1,0x108(a0) + lea irq3(pc),a1 + move.l a1,0x10c(a0) + lea irq4(pc),a1 + move.l a1,0x110(a0) + lea irq5(pc),a1 + move.l a1,0x114(a0) + lea irq6(pc),a1 + move.l a1,0x118(a0) + lea irq7(pc),a1 + move.l a1,0x11c(a0) +//psc_vectors + lea psc3(pc),a1 + move.l a1,0x180(a0) +//timer 1 vectors + lea timer0(pc),a1 + move.l a1,0x1f8(a0) + rts +/********************************************************/ +/* exception vector routinen +/********************************************************/ +vector_table_start: +std_exc_vec: + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern +// test auf protect mode ------------------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne stv_protect // ja-> +//------------------------------------------------------ + move.w 8(a7),d0 // vector holen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),d0 + move.l 4(a7),a5 // a5 zurück + move.l d0,4(a7) + move.w 10(a7),d0 + bset #13,d0 // super + move.w d0,sr // orginal sr wert in super setzen + move.l (a7)+,d0 // d0 zurück + rts +stv_protect: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_sup // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),d0 // sr holen + move.l d0,-(a5) // sr transferieren + swap d0 // vec -> lw +#else + move.w 8(a7),d0 // vector holen + move.w d0,-(a5) // ablegen + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren +#endif + move.l a5,usp // usp setzen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),12(a7) // hier geht's weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg +sev_sup: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),d0 // sr holen + bset #13,d0 // war aus rt super + move.l d0,-(a5) // sr transferieren + swap d0 // vec -> lw +#else + move.w 8(a7),d0 // vector holen + move.w d0,-(a5) // ablegen + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren + bset #5,(a5) // war aus super +#endif + move.l a5,usp // usp setzen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),12(a7) // hier geht's weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + rte // und weg +//******************************************* +reset_vector: + move.w #0x2700,sr // disable interrupt + move.l #0x31415926,d0 + cmp.l 0x426,d0 // reset vector gültg? + beq std_exc_vec // ja-> + jmp ___BOOT_FLASH // sonst kaltstart +acess: + move.w #0x2700,sr // disable interrupt + move.l d0,-(sp) // ++ vr + move.w 4(sp),d0 + andi.l #0x0c03,d0 + cmpi.l #0x0401,d0 + beq access_mmu + cmpi.l #0x0402,d0 + beq access_mmu + cmpi.l #0x0802,d0 + beq access_mmu + cmpi.l #0x0c02,d0 + beq access_mmu + bra bus_error +access_mmu: + move.l MCF_MMU_MMUSR,d0 + btst #1,d0 + bne bus_error + move.l MCF_MMU_MMUAR,d0 + cmp.l #___Bas_base,d0 // max User RAM Bereich + bge bus_error // grösser -> bus error + bra _mmutr_miss +bus_error: + move.l (sp)+,d0 + bra std_exc_vec + +zero_divide: + move.w #0x2700,sr // disable interrupt + move.l a0,-(a7) + move.l d0,-(a7) + move.l 12(a7),a0 // pc + move.w (a0)+,d0 // befehlscode + btst #7,d0 // long? + beq zd_word // nein-> + addq.l #2,a0 +zd_word: + and.l 0x3f,d0 // ea ausmaskieren + cmp.w #0x08,d0 // -(ax) oder weniger + ble zd_end + addq.l #2,a0 + cmp.w #0x39,d0 // xxx.L + bne zd_nal + addq.l #2,a0 + bra zd_end +zd_nal: cmp.w #0x3c,d0 // immediate? + bne zd_end // nein-> + btst #7,d0 // long? + beq zd_end // nein + addq.l #2,a0 +zd_end: + move.l a0,12(a7) + move.l (a7)+,d0 + move.l (a7)+,a0 + rte + +linea: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +linef: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +format: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +//floating point +flpoow: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +irq1: + irq 0x64,1,0x02 +irq2: // hbl + // move.b #3,2(a7) + // rte + irq 0x68,2,0x04 +irq3: + irq 0x6c,3,0x08 +irq4: // vbl + irq 0x70,4,0x10 +irq5: // acp + irq 0x74,5,0x20 +irq6: // mfp + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern + lea MCF_EPORT_EPFR,a5 + move.b #0x40,(a5) // clear int6 +// test auf timeout screen adr change ------------------------------------------------------- + move.l _video_sbt,d0 + beq irq6_non_sca // wenn 0 nichts zu tun + sub.l #0x70000000,d0 // 14 sec abzählen + lea MCF_SLT0_SCNT,a5 + cmp.l (a5),d0 // aktuelle zeit weg + ble irq6_non_sca // noch nicht abgelaufen + lea -28(a7),a7 + movem.l d0-d4/a0-a1,(a7) // register sichern + clr.l d3 // beginn mit 0 + bsr cpusha // cache leeren + // eintrag suchen + irq6_next_sca: + move.l d3,d0 + move.l d0,MCF_MMU_MMUAR // addresse + move.l #0x106,d4 + move.l d4,MCF_MMU_MMUOR // suchen -> + nop + move.l MCF_MMU_MMUOR,d4 + clr.w d4 + swap d4 + move.l d4,MCF_MMU_MMUAR + mvz.w #0x10e,d4 + move.l d4,MCF_MMU_MMUOR // einträge holen aus mmu + nop + move.l MCF_MMU_MMUTR,d4 // ID holen + lsr.l #2,d4 // bit 9 bis 2 + cmp.w #sca_page_ID,d4 // ist screen change ID? + bne irq6_sca_pn // nein -> page keine screen area next +// eintrag ändern + add.l #std_mmutr,d0 + move.l d3,d1 // page 0? + beq irq6_sca_pn0 // ja -> + add.l #cb_mmudr,d1 // sonst page cb + bra irq6_sca_pn1c +irq6_sca_pn0: + add.l #wt_mmudr|MCF_MMU_MMUDR_LK,d1 // page wt and locked +irq6_sca_pn1c: + mvz.w #0x10b,d2 // MMU update + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setze tlb data only + nop +// page copy + move.l d3,a0 + add.l #0x60000000,a0 + move.l d3,a1 + move.l #0x10000,d4 // die ganze page +irq6_vcd0_loop: + move.l (a0)+,(a1)+ // page copy + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + subq.l #1,d4 + bne irq6_vcd0_loop + nop +irq6_sca_pn: + add.l #0x00100000,d3 // next + cmp.l #0x00d00000,d3 // ende? + blt irq6_next_sca // nein-> + + move.l #0x2000,d0 + move.l d0,_video_tlb // anfangszustand wieder herstellen + clr.l _video_sbt // zeit löschen + + movem.l (a7),d0-d4/a0-a1 // register zurück + lea 28(a7),a7 +irq6_non_sca: +// test auf acsi dma ----------------------------------------------------------------- + lea 0xfffffa0b,a5 + bset #7,-4(a5) // int ena + btst.b #7,(a5) // acsi dma int? + beq non_acsi_dma + bsr acsi_dma +non_acsi_dma: +// ---------------------------------------------------------------------------------- + tst.b (a5) + bne irq6_1 + tst.b 2(a5) + bne irq6_1 + movem.l (a7),d0/a5 + addq.l #8,a7 + rte +irq6_1: + lea MCF_GPIO_PODR_FEC1L,a5 + bclr.b #4,(a5) // led on + lea blinker(pc),a5 + addq.l #1,(a5) // +1 + move.l (a5),d0 + and.l #0x80,d0 + bne irq6_2 + lea MCF_GPIO_PODR_FEC1L,a5 + bset.b #4,(a5) // led off +irq6_2: +// test auf protect mode --------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne irq6_3 // ja-> +// ------------------------------------------- + move.l 0xF0020000,a5 // vector holen + add.l _rt_vbr,a5 // basis + move.l (a5),d0 // vector holen + move.l 4(a7),a5 // a5 zurück + move.l d0,4(a7) // vector eintragen + move.l (a7)+,d0 // d0 zurück + move #0x2600,sr + rts +irq6_3: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_sup6 // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr transferieren +#else + move.w 8(a7),-(a5) // vector transferieren + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren +#endif + move.l a5,usp // usp setzen + move.l 0xF0020000,a5 // vector holen: intack routine + add.l _rt_vbr,a5 // virtuelle VBR des Systems + move.l (a5),12(a7) // hier gehts weiter + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + move.b #6,2(a7) // intmaske setzen + rte // und weg +sev_sup6: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec + bset #5,2(a5) // auf super setzen +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif + move.l a5,usp // usp setzen + move.l 0xF0020000,a5 // vector holen: intack routine + add.l _rt_vbr,a5 // virtuelle VBR des Systems + move.l (a5),12(a7) // hier gehts weiter + movem.l (a7),d0/a5 // register zurück + rts +blinker:.long 0 +/**************************************************/ +/* pseudo dma */ +/**************************************************/ +acsi_dma: // atari dma + move.l a1,-(a7) + move.l d1,-(a7) + + lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr + move.l #'DMA ',(a1) + move.l #'INT!',(a1) + + lea 0xf0020110,a5 // fifo daten +acsi_dma_start: + move.l -12(a5),a1 // dma adresse + move.l -8(a5),d0 // byt counter + ble acsi_dma_end + btst.b #0,-16(a5) // write? (dma modus reg) + bne acsi_dma_wl // ja-> +acsi_dma_rl: + tst.b -4(a5) // dma req? + bpl acsi_dma_fertig // nein-> + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + + moveq #'.',d1 + move.b d1,MCF_PSC0_PSCTB_8BIT + + sub.l #16,d0 // byt counter -16 + bpl acsi_dma_rl + bra acsi_dma_fertig +acsi_dma_wl: + tst.b -4(a5) // dma req? + bpl acsi_dma_fertig // nein-> + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + + moveq #'.',d1 + move.b d1,MCF_PSC0_PSCTB_8BIT + + sub.l #16,d0 // byt counter -16 + bpl acsi_dma_wl +acsi_dma_fertig: + move.l a1,-12(a5) // adresse zurück + move.l d0,-8(a5) // byt counter zurück +acsi_dma_end: + tst.b -4(a5) // dma req? + bmi acsi_dma_start // ja-> + lea 0xfffffa0b,a5 + bclr.b #7,4(a5) // clear int in service mfp + bclr.b #7,(a5) // clear int pending mfp 0xfffffa0b + + move.w #0x0d0a,d1 + move.w d1,MCF_PSC0_PSCTB_8BIT + + move.l (a7)+,d1 + move.l (a7)+,a1 + rts +/**************************************************/ +/* irq 7 = pseudo bus error */ +/**************************************************/ +irq7: + lea -12(sp),sp + movem.l d0/a0,(sp) + + move.l ___RAMBAR0+0x008,a0 // Real Access Error handler + move.l a0,8(sp) // This will be the return address for rts + + move.w 12(sp),d0 // Format/Vector word + andi.l #0xf000,d0 // Keep only the Format + ori.l #2*4,d0 // Simulate Vector #2, no Fault + move.w d0,12(sp) + + // TODO: Inside an interrupt handler, 16(sp) is the return address. + // For an Access Error, it should be the address of the fault instruction instead + + lea MCF_EPORT_EPFR,a0 + move.b #0x80,(a0) // clear int7 + move.l (sp)+,d0 + move.l (sp)+,a0 + rts // Forward to the Access Error handler + +/**************************************************/ +/* psc3 com PIC MCF */ +/**************************************************/ +psc3: + move.w #0x2700,sr // disable interrupt + lea -20(a7),a7 + movem.l d0-d2/a0/a3,(a7) + lea MCF_PSC3_PSCRB_8BIT,a3 + move.b (a3),d1 + cmp.b #2,d1 // anforderung rtc daten? + bne psc3_fertig + + lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr + move.l #'PIC ',(a0) + move.l #'INT ',(a0) + move.l #'RTC!',(a0) + move.l #0x0d0a,(a0) + + lea 0xffff8961,a0 + lea MCF_PSC3_PSCTB_8BIT,a3 + clr.l d1 + moveq #64,d2 + move.b #0x82,(a3) // header: rtcd mcf->pic +loop_sr2: + move.b d1,(a0) + move.b 2(a0),d0 + move.b d0,(a3) + addq.l #1,d1 + cmp.b d1,d2 + bne loop_sr2 +psc3_fertig: + movem.l (a7),d0-d2/a0/a3 // register zurück + lea 20(a7),a7 + RTE +/**************************************************/ +/* timer 0: video change later also others +/**************************************************/ +timer0: + move #0x2700,sr +// halt + lea -28(a7),a7 + movem.l d0-d4/a0-a1,(a7) + mvz.b 0xffff8201,d0 // löschen und high byt + cmp.w #2,d0 + blt video_chg_end + cmp.w #0xd0,d0 // normale addresse + blt sca_other // nein-> + lea MCF_SLT0_SCNT,a0 + move.l (a0),d4 + move.l d4,_video_sbt // time sichern +sca_other: + lsl.l #8,d0 + move.b 0xffff8203,d0 // mid byt + lsl.l #8,d0 + move.b 0xffff820d,d0 // low byt + move.l d0,d3 +video_chg_1page: +// test ob page schon gesetzt + moveq #20,d4 + move.l d0,d2 + lsr.l d4,d2 // neue page + move.l _video_tlb,d4 + bset.l d2,d4 // setzen als geändert + bne video_chg_2page // schon gesetzt gewesen? ja->weg + move.l d4,_video_tlb + bsr cpusha // cache leeren +// daten copieren +video_copy_data: + move.l d4,_video_tlb + and.l #0x00f00000,d0 + move.l d0,a0 + move.l a0,a1 + add.l #0x60000000,a1 + move.l #0x10000,d4 // die ganze page +video_copy_data_loop: + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + subq.l #1,d4 + bne video_copy_data_loop +// eintrag suchen + move.l d0,MCF_MMU_MMUAR // addresse + move.l #0x106,d4 + move.l d4,MCF_MMU_MMUOR // suchen -> schlägt neuen vor wenn keiner + nop + move.l MCF_MMU_MMUOR,d4 + clr.w d4 + swap d4 + move.l d4,MCF_MMU_MMUAR + move.l d0,d1 + add.l #MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 + add.l #0x60000000|wt_mmudr|MCF_MMU_MMUDR_LK,d1 + mvz.w #0x10b,d2 // MMU update + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen vidoe maped to 60xxx only data + nop +video_chg_2page: +// test ob evt. anschliessende page gesetzt werden muss + move.l d3,d0 + mvz.w 0xffff8210,d4 // byts pro zeile + mvz.w 0xffff82aa,d2 // zeilen ende + mvz.w 0xffff82a8,d1 // zeilenstart + sub.l d1,d2 // differenz = anzahl zeilen + mulu d2,d4 // maximal 480 zeilen + add.l d4,d0 // video grösse + cmp.l #0xe00000,d0 // maximale addresse + bge video_chg_end // wenn gleich oder grösser -> fertig + moveq #20,d4 + move.l d0,d2 + lsr.l d4,d2 // neue page + move.l _video_tlb,d4 + bset.l d2,d4 // setzen als geändert + beq video_copy_data // nein nochmal +video_chg_end: +// int pending löschen + lea MCF_GPT0_GMS,a0 + bclr.b #0,3(a0) + nop + bset.b #0,3(a0) + + movem.l (a7),d0-d4/a0-a1 + lea 28(a7),a7 +//-------------------------------------------------------------------------------------------------------- + RTE + From dc40e0c3a679e5afd0acaaed0f011f1c898cd6aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 05:42:48 +0000 Subject: [PATCH 038/276] added (very ugly) mchar macro --- BaS_GNU/sources/exceptions.S | 71 ++++++++++++++++++++++++++---------- 1 file changed, 51 insertions(+), 20 deletions(-) diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S index fa101d6..343037b 100644 --- a/BaS_GNU/sources/exceptions.S +++ b/BaS_GNU/sources/exceptions.S @@ -44,7 +44,7 @@ #define MCF_PSC3_PSCRB_8BIT ___MBAR+0x890C #define MCF_PSC3_PSCTB_8BIT ___MBAR+0x890C -.public _vec_init + .global _vec_init //mmu --------------------------------------------------- /* Register read/write macros */ @@ -124,7 +124,12 @@ /**********************************************************/ // macros /**********************************************************/ -irq: .macro vector,int_mask,clr_int + .altmacro + .macro irq vector,int_mask,clr_int + local irq_protect + local sev_supint + local irq_end + move.w #0x2700,sr // disable interrupt subq.l #8,a7 movem.l d0/a5,(a7) // register sichern @@ -133,17 +138,17 @@ irq: .macro vector,int_mask,clr_int // test auf protect mode --------------------- move.b DIP_SWITCHa,d0 btst #7,d0 - bne @irq_protect // ja-> + bne irq_protect // ja-> // ------------------------------------------- movem.l (a7),d0/a5 // register zurück addq.l #8,a7 - move.l vector,-(a7) - move #0x2\200,sr + move.l \vector,-(a7) + move #0x2200,sr rts -@irq_protect: +irq_protect: move.l usp,a5 // usp holen tst.b _rt_mod // supervisor? - bne @sev_supint // ja -> + bne sev_supint // ja -> mov3q.l #-1,_rt_mod // auf supervisor setzen move.l a5,_rt_usp // rt_usp speichern move.l _rt_ssp,a5 // rt_ssp holen @@ -155,8 +160,8 @@ irq: .macro vector,int_mask,clr_int move.l 12(a7),-(a5) // pc verschieben move.w 10(a7),-(a5) // sr verschieben #endif - bra @irq_end -@sev_supint: + bra irq_end +sev_supint: #ifdef cf_stack move.l 12(a7),-(a5) // pc transferieren move.l 8(a7),-(a5) // sr,vec @@ -167,17 +172,37 @@ irq: .macro vector,int_mask,clr_int move.w 10(a7),-(a5) // sr verschieben bset #5,(a5) // auf super #endif -@irq_end: +irq_end: move.l a5,usp // usp setzen lea vector,a5 adda.l _rt_vbr,a5 move.l (a5),12(a7) // vectoradresse eintragen - move.b #int_mask,10(a7) // intmaske setzen + move.b #\int_mask,10(a7) // intmaske setzen movem.l (a7),d0/a5 // register zurück addq.l #8,a7 rte // und weg .endm /*********************************************************/ + +/* + * FIXME: ugly, but I just can't come up with any smarter solution + * + * GNU as does not support multi-character constants. At least I don't know of any way it would. + * The following might look more than strange, but I considered the statement + * + * mchar move.l, 'T,'E,'S,'T,-(SP) + * + * somewhat more readable than + * + * move.l #1413829460,-(SP) + * + * If anybody knows of any better way on how to do this - please do! + * + */ + .macro mchar st,a,b,c,d,tgt + \st #\a << 24|\b<<16|\c<<8|\d,\tgt + .endm + .text _vec_init: mov3q.l #-1,_rt_mod // rt_mod auf super @@ -588,13 +613,15 @@ blinker:.long 0 /**************************************************/ /* pseudo dma */ /**************************************************/ -acsi_dma: // atari dma +acsi_dma: // atari dma move.l a1,-(a7) move.l d1,-(a7) - lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr - move.l #'DMA ',(a1) - move.l #'INT!',(a1) + lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr + mchar move.l, 'D,'M','A,'\ ,(a1) + //move.l #"DMA ",(a1) + mchar move.l,'I,'N,'T,'!,(a1) + // move.l #'INT!',(a1) lea 0xf0020110,a5 // fifo daten acsi_dma_start: @@ -682,11 +709,15 @@ psc3: cmp.b #2,d1 // anforderung rtc daten? bne psc3_fertig - lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr - move.l #'PIC ',(a0) - move.l #'INT ',(a0) - move.l #'RTC!',(a0) - move.l #0x0d0a,(a0) + lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr + mchar move.l,'\P,'\I,'C,' ,(a0) + // move.l #'PIC ',(a0) + mchar move.l,'I,'N,'T,'\ ,(a0) + // move.l #'INT ',(a0) + mchar move.l,'R,'T,'C,'!,(a0) + // move.l #'RTC!',(a0) + mchar move.l,0x0d,0x0a,0,0,(a0) + //move.l #0x0d0a,(a0) lea 0xffff8961,a0 lea MCF_PSC3_PSCTB_8BIT,a3 From f703ec45a3137e2dea8f2735a305373492b67723 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 07:04:59 +0000 Subject: [PATCH 039/276] everything compiles nicely. Next will be linker scripts. --- BaS_GNU/sources/ii_or.h | 442 +++++++++++++++++ BaS_GNU/sources/ii_pea.h | 74 +++ BaS_GNU/sources/ii_shd.h | 247 +++++++++ BaS_GNU/sources/ii_shift.h | 687 ++++++++++++++++++++++++++ BaS_GNU/sources/ii_sub.h | 584 ++++++++++++++++++++++ BaS_GNU/sources/illegal_instruction.S | 328 ++++++++++++ 6 files changed, 2362 insertions(+) create mode 100644 BaS_GNU/sources/ii_or.h create mode 100644 BaS_GNU/sources/ii_pea.h create mode 100644 BaS_GNU/sources/ii_shd.h create mode 100644 BaS_GNU/sources/ii_shift.h create mode 100644 BaS_GNU/sources/ii_sub.h create mode 100644 BaS_GNU/sources/illegal_instruction.S diff --git a/BaS_GNU/sources/ii_or.h b/BaS_GNU/sources/ii_or.h new file mode 100644 index 0000000..dfe4450 --- /dev/null +++ b/BaS_GNU/sources/ii_or.h @@ -0,0 +1,442 @@ +//-------------------------------------------------------------------- +// or +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// or.b #im,dx +//-------------------------------------------------------------------- +orbir_macro:.macro +#ifdef halten_or + halt +#endif + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + or.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea,dx +//-------------------------------------------------------------------- +ordd:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +orddd:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or (ea)->dy,dx +//-------------------------------------------------------------------- +ordda:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +orddai:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea->ay,-(ay),dx +//-------------------------------------------------------------------- +orddad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d16(ay),dx +//-------------------------------------------------------------------- +ord16ad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d8(ay,dy),dx +//-------------------------------------------------------------------- +ord8ad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or xxx.w,dx +//-------------------------------------------------------------------- +orxwd:.macro +#ifdef halten_or + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or xxx.l,dx +//-------------------------------------------------------------------- +orxld:.macro +#ifdef halten_or + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d16(pc),dx +//-------------------------------------------------------------------- +ord16pcd:.macro + halt + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d8(pc,dy),dx +//-------------------------------------------------------------------- +ord8pcd:.macro +#ifdef halten_or + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// or dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // or (ea)->dy,dx +//-------------------------------------------------------------------- +oreda:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +oredai:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +oredaid:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +oredad:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +oredadd:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,d16(ay) +//-------------------------------------------------------------------- +ore16ad:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or.w dx,d8(ay,dy) +//-------------------------------------------------------------------- +ore8ad:.macro +#ifdef halten_or + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,xxx.w +//-------------------------------------------------------------------- +orxwe:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,xxx.l +//-------------------------------------------------------------------- +orxle:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // ora.w ea,ax +//-------------------------------------------------------------------- +oraw:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// or.w ea,usp +//-------------------------------------------------------------------- +orawa7:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w usp?,ax +//-------------------------------------------------------------------- +orawu:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w usp?,usp +//-------------------------------------------------------------------- +orawua7:.macro + orawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // ora.w d16(ay),ax +//-------------------------------------------------------------------- +orawd16a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d8(ay,dy),ax +//-------------------------------------------------------------------- +orawd8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w xxx.w,ax +//-------------------------------------------------------------------- +orawxwax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w xxx.l,ax +//-------------------------------------------------------------------- +orawxlax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d16(pc),ax +//-------------------------------------------------------------------- +orawd16pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d8(pc,dy),ax +//-------------------------------------------------------------------- +orawd8pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w #im,ax +//-------------------------------------------------------------------- +orawim:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.l d8(ay,dy),ax +//-------------------------------------------------------------------- +orald8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.l d8(pc,dy),ax +//-------------------------------------------------------------------- +orald8pcax:.macro + jmp ii_error + .endm; +//***************************************************************************************** +// spezial addx subx etc. +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +ordx:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +ordax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_pea.h b/BaS_GNU/sources/ii_pea.h new file mode 100644 index 0000000..69f69d0 --- /dev/null +++ b/BaS_GNU/sources/ii_pea.h @@ -0,0 +1,74 @@ +//-------------------------------------------------------------------- +// pea +//-------------------------------------------------------------------- +.text +ii_pea_lset:.macro + ii_lset_opeag 48,7 + ii_lset 0x487b +.endm +//--------------------------------------------------------------------------------------------- +ii_pea_func:.macro +ii_0x4870: +#ifdef halten_pea + halt +#endif + move.l a0_off(a7),a1 + pea_macro +ii_0x4871: +#ifdef halten_pea + halt +#endif + move.l a1_off(a7),a1 + pea_macro +ii_0x4872: +#ifdef halten_pea + halt +#endif + move.l a2,a1 + pea_macro +ii_0x4873: +#ifdef halten_pea + halt +#endif + move.l a3,a1 + pea_macro +ii_0x4874: +#ifdef halten_pea + halt +#endif + move.l a4,a1 + pea_macro +ii_0x4875: +#ifdef halten_pea + halt +#endif + move.l a5,a1 + pea_macro +ii_0x4876: +#ifdef halten_pea + halt +#endif + move.l a6,a1 + pea_macro +ii_0x4877: +#ifdef halten_pea + halt +#endif + move.l usp,a1 + pea_macro +ii_0x487b: +#ifdef halten_pea + halt +#endif + move.l a0,a1 + pea_macro +.endm +//--------------------------------------------------------------------------------------------- +pea_macro:.macro + jsr ewf + move.l (a1),d0 + move.l usp,a1 + move.l d0,-(a1) + move.l a1,usp + ii_end +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_shd.h b/BaS_GNU/sources/ii_shd.h new file mode 100644 index 0000000..ecace29 --- /dev/null +++ b/BaS_GNU/sources/ii_shd.h @@ -0,0 +1,247 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_lset_shd:.macro + ii_lset_shdx e0 //r d0 + ii_lset_shdx e2 //r d1 + ii_lset_shdx e4 //r d2 + ii_lset_shdx e6 //r d3 + ii_lset_shdx e8 //r d4 + ii_lset_shdx ea //r d5 + ii_lset_shdx ec //r d6 + ii_lset_shdx ee //r d7 + + ii_lset_shdx e1 //l d0 + ii_lset_shdx e3 //l d1 + ii_lset_shdx e4 //l d2 + ii_lset_shdx e5 //l d3 + ii_lset_shdx e9 //l d4 + ii_lset_shdx eb //l d5 + ii_lset_shdx ed //l d6 + ii_lset_shdx ef //l d7 + .endm + +ii_lset_shdx:.macro +//byt + ii_lset_opea \1,0 // as,ls #im,dx + ii_lset_opea \1,1 // rox,ro #im,dx + ii_lset_opea \1,2 // as,ls dy,dx + ii_lset_opea \1,3 // rox,ro dy,dx +//word + ii_lset_opea \1,4 // as,ls #im,dx + ii_lset_opea \1,5 // rox,ro #im,dx + ii_lset_opea \1,6 // as,ls dy,dx + ii_lset_opea \1,7 // rox,ro dy,dx +//long +// ii_lset_opea \1,8 // as,ls #im,dx -> vorhanden + ii_lset_opea \1,9 // rox,ro #im,dx +// ii_lset_opea \1,a // as,ls dy,dx -> vorhanden + ii_lset_opea \1,b // rox,ro dy,dx + .endm +/******************************************************/ +ii_shd:.macro // 1=code 2=operation 3 = normal, direct oder immediat +// byt + opdx \1,\2,b,0,\3 // dx +// word + opdx \1,\2,w,4,\3 // dx +// long + opdx \1,\2,l,8,\3 // dx + .endm +/******************************************************/ +// byt word long routinen +/******************************************************/ +sh_asr: .macro // asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvs.\4 \2,d1 + sh_shal \1,\2,\3,\4 + .endm + +sh_lsr: .macro // asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvz.\4 \2,d1 + sh_shal \1,\2,\3,\4 + .endm + +sh_shal:.macro + move.w \3,d0 + \1.l d0,d1 + set_cc0 + move.\4 d1,\2 + .endm + +sh_all: .macro // asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvz.\4 \2,d1 +.ifc \4,b + byterev.l d1 +.else + swap.w d1 +.endif + sh_asr \1,\2,\3,\4 + .endm + +sh_ror: .macro // ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + move.\4 \2,d1 / + move.w \3,d0 +.ifc \4,b + lsl.l #8,d1 + move.b \2,d1 + and.l #0x7,d0 + lsr.l d0,d1 +.else + .ifc \4,w + swap.w d1 + move.w \2,d1 + and.l #0xf,d0 + lsr.l d0,d1 + .else + and.l #0x1f,d0 + lsr.l d0,d1 + move.l d1,a1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsl.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + move.w ccr,d0 + and.l #1,d1 // ist auch carry bit + or.l d1,d0 + move.b d0,ccr_off(a7) + .endm + +sh_rol: .macro // rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + move.\4 \2,d1 + move.w \3,d0 +.ifc \4,b + lsl.l #8,d1 + move.b \2,d1 + and.l #0x7,d0 + lsl.l d0,d1 + lsr.l #8,d1 + moveq #7,d0 +.else + .ifc \4,w + swap.w d1 + move.w \2,d1 + and.l #0xf,d0 + lsr.l d0,d1 + swap.w d1 + moveq #15,d0 + .else + and.l #0x1f,d0 + lsl.l d0,d1 + move.l d1,a1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsr.l d0,d1 + add.l a1,d1 + moveq #31,d0 + .endif +.endif + move.\4 d1,\2 + lsr.l d0,d1 // carry bit schieben + move.w ccr,d0 + and.l #1,d1 + or.l d1,d0 + move.b d0,ccr_off(a7) + .endm + +sh_roxr: .macro // roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + clr.l d0 + addx.l d0,d0 +ifc \4,b + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + move.b \2,d1 + move.w \3,d0 + and.l #0x7,d0 + lsr.l d0,d1 + set_cc0 +else + .ifc \4,w + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + lsl.l #8,d1 + move.w \2,d1 + move.w \3,d0 + and.l #0xf,d0 + lsr.l d0,d1 + set_cc0 + .else + bitrev.l d0 + move.l \2,d1 + lsr.l #1,d1 + add.l d0,d1 + move.w \3,d0 + subq.l #1,d0 + and.l #0x1f,d0 + lsr.l d0,d1 + move.l d1,a1 + set_cc1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsl.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + .endm + +sh_roxl: .macro // roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + clr.l d0 + addx.l d0,d0 +ifc \4,b + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + move.b \2,d1 + lsl.l #8,d1 + lsl.l #7,d1 + move.w \3,d0 + and.l #0x7,d0 + lsl.l d0,d1 + set_cc0 + byterev.l d1 +else + .ifc \4,w + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + lsl.l #7,d1 + mvz.w \2,d0 + lsr.l #1,d0 + add.l d0,d1 + move.w \3,d0 + and.l #0xf,d0 + lsl.l d0,d1 + set_cc0 + swap.w d1 + .else + move.l \2,d1 + lsl.l #1,d1 + add.l d0,d1 + move.w \3,d0 + subq.l #1,d0 + and.l #0x1f,d0 + lsl.l d0,d1 + move.l d1,a1 + set_cc1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsr.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + .endm + + \ No newline at end of file diff --git a/BaS_GNU/sources/ii_shift.h b/BaS_GNU/sources/ii_shift.h new file mode 100644 index 0000000..f83bfcb --- /dev/null +++ b/BaS_GNU/sources/ii_shift.h @@ -0,0 +1,687 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_shift_lset:.macro +/******************************************************/ +// byt +/******************************************************/ +// asx.b #,dx + ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,01 + ii_lset_dx \1,02 + ii_lset_dx \1,03 + ii_lset_dx \1,04 + ii_lset_dx \1,05 + ii_lset_dx \1,06 + ii_lset_dx \1,07 +// lsx.b #,dx + ii_lset_dxu \1,08 + ii_lset_dxu \1,09 + ii_lset_dxu \1,0a + ii_lset_dxu \1,0b + ii_lset_dxu \1,0c + ii_lset_dxu \1,0d + ii_lset_dxu \1,0e + ii_lset_dxu \1,0f +// roxx.b #,dx + ii_lset_dx \1,10 + ii_lset_dx \1,11 + ii_lset_dx \1,12 + ii_lset_dx \1,13 + ii_lset_dx \1,14 + ii_lset_dx \1,15 + ii_lset_dx \1,16 + ii_lset_dx \1,17 +// rox.b #,dx + ii_lset_dx \1,18 + ii_lset_dx \1,19 + ii_lset_dx \1,1a + ii_lset_dx \1,1b + ii_lset_dx \1,1c + ii_lset_dx \1,1d + ii_lset_dx \1,1e + ii_lset_dx \1,1f +// asx.b dy,dx + ii_lset_dx \1,20 + ii_lset_dx \1,21 + ii_lset_dx \1,22 + ii_lset_dx \1,23 + ii_lset_dx \1,24 + ii_lset_dx \1,25 + ii_lset_dx \1,26 + ii_lset_dx \1,27 +// lsx.b dy,dx + ii_lset_dx \1,28 + ii_lset_dx \1,29 + ii_lset_dx \1,2a + ii_lset_dx \1,2b + ii_lset_dx \1,2c + ii_lset_dx \1,2d + ii_lset_dx \1,2e + ii_lset_dx \1,2f +// roxx.dy,dx + ii_lset_dx \1,30 + ii_lset_dx \1,31 + ii_lset_dx \1,32 + ii_lset_dx \1,33 + ii_lset_dx \1,34 + ii_lset_dx \1,35 + ii_lset_dx \1,36 + ii_lset_dx \1,37 +// rox.b dy,dx + ii_lset_dx \1,38 + ii_lset_dx \1,39 + ii_lset_dx \1,3a + ii_lset_dx \1,3b + ii_lset_dx \1,3c + ii_lset_dx \1,3d + ii_lset_dx \1,3e + ii_lset_dx \1,3f +/******************************************************/ +// word +/******************************************************/ +// asx.w #x,dx + ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,41 + ii_lset_dx \1,42 + ii_lset_dx \1,43 + ii_lset_dx \1,44 + ii_lset_dx \1,45 + ii_lset_dx \1,46 + ii_lset_dx \1,47 +// lsx.w #,dx + ii_lset_dx \1,48 + ii_lset_dx \1,49 + ii_lset_dx \1,4a + ii_lset_dx \1,4b + ii_lset_dx \1,4c + ii_lset_dx \1,4d + ii_lset_dx \1,4e + ii_lset_dx \1,4f +// roxx.w #,dx + ii_lset_dx \1,50 + ii_lset_dx \1,51 + ii_lset_dx \1,52 + ii_lset_dx \1,53 + ii_lset_dx \1,54 + ii_lset_dx \1,55 + ii_lset_dx \1,56 + ii_lset_dx \1,57 +// rox.w #xdx + ii_lset_dx \1,58 + ii_lset_dx \1,59 + ii_lset_dx \1,5a + ii_lset_dx \1,5b + ii_lset_dx \1,5c + ii_lset_dx \1,5d + ii_lset_dx \1,5e + ii_lset_dx \1,5f +// asx.w dy,dx + ii_lset_dx \1,60 + ii_lset_dx \1,61 + ii_lset_dx \1,62 + ii_lset_dx \1,63 + ii_lset_dx \1,64 + ii_lset_dx \1,65 + ii_lset_dx \1,66 + ii_lset_dx \1,67 +// lsx.w dy,dx + ii_lset_dx \1,68 + ii_lset_dx \1,69 + ii_lset_dx \1,6a + ii_lset_dx \1,6b + ii_lset_dx \1,6c + ii_lset_dx \1,6d + ii_lset_dx \1,6e + ii_lset_dx \1,6f +// roxx.w dy,dx + ii_lset_dx \1,70 + ii_lset_dx \1,71 + ii_lset_dx \1,72 + ii_lset_dx \1,73 + ii_lset_dx \1,74 + ii_lset_dx \1,75 + ii_lset_dx \1,76 + ii_lset_dx \1,77 +// rox.w dy,dx + ii_lset_dx \1,78 + ii_lset_dx \1,79 + ii_lset_dx \1,7a + ii_lset_dx \1,7b + ii_lset_dx \1,7c + ii_lset_dx \1,7d + ii_lset_dx \1,7e + ii_lset_dx \1,7f +/******************************************************/ +// long +/******************************************************/ +// roxx.l #,dx + ii_lset_dx \1,90 + ii_lset_dx \1,91 + ii_lset_dx \1,92 + ii_lset_dx \1,93 + ii_lset_dx \1,94 + ii_lset_dx \1,95 + ii_lset_dx \1,96 + ii_lset_dx \1,97 +// rox.l #xdx + ii_lset_dx \1,98 + ii_lset_dx \1,99 + ii_lset_dx \1,9a + ii_lset_dx \1,9b + ii_lset_dx \1,9c + ii_lset_dx \1,9d + ii_lset_dx \1,9e + ii_lset_dx \1,9f +// roxx.l dy,dx + ii_lset_dx \1,b0 + ii_lset_dx \1,b1 + ii_lset_dx \1,b2 + ii_lset_dx \1,b3 + ii_lset_dx \1,b4 + ii_lset_dx \1,b5 + ii_lset_dx \1,b6 + ii_lset_dx \1,b7 +// rox.l dy,dx + ii_lset_dx \1,b8 + ii_lset_dx \1,b9 + ii_lset_dx \1,ba + ii_lset_dx \1,bb + ii_lset_dx \1,bc + ii_lset_dx \1,bd + ii_lset_dx \1,be + ii_lset_dx \1,bf +//-------------------------------------------------------------------- +// asr.w ea + ii_lset_opea \10,d // (ax), (ax)+ + ii_lset_opea \10,e // -(ax),d16(ax) + ii_lset_opeag \10,f // d8(ax,dy) + lea table+0x\10\2f8*4,a0 + move.l #ii_0x\10f8,(a0)+ // xxx.w + move.l #ii_0x\10f9,(a0)+ // xxx.l +// asl.w ea + ii_lset_opea \11,d // (ax), (ax)+ + ii_lset_opea \11,e // -(ax),d16(ax) + ii_lset_opeag \11,f // d8(ax,dy) + lea table+0x\11\2f8*4,a0 + move.l #ii_0x\11f8,(a0)+ // xxx.w + move.l #ii_0x\11f9,(a0)+ // xxx.l +// lsr.w ea + ii_lset_opea \12,d // (ax), (ax)+ + ii_lset_opea \12,e // -(ax),d16(ax) + ii_lset_opeag \12,f // d8(ax,dy) + lea table+0x\12\2f8*4,a0 + move.l #ii_0x\12f8,(a0)+ // xxx.w + move.l #ii_0x\12f9,(a0)+ // xxx.l +// lsr.w ea + ii_lset_opea \13,d // (ax), (ax)+ + ii_lset_opea \13,e // -(ax),d16(ax) + ii_lset_opeag \13,f // d8(ax,dy) + lea table+0x\13\2f8*4,a0 + move.l #ii_0x\13f8,(a0)+ // xxx.w + move.l #ii_0x\13f9,(a0)+ // xxx.l +// roxr.w ea + ii_lset_opea \14,d // (ax), (ax)+ + ii_lset_opea \14,e // -(ax),d16(ax) + ii_lset_opeag \14,f // d8(ax,dy) + lea table+0x\14\2f8*4,a0 + move.l #ii_0x\14f8,(a0)+ // xxx.w + move.l #ii_0x\14f9,(a0)+ // xxx.l +// roxl.w ea + ii_lset_opea \15,e // (ax), (ax)+ + ii_lset_opea \15,e // -(ax),d16(ax) + ii_lset_opeag \15,f // d8(ax,dy) + lea table+0x\15\2f8*4,a0 + move.l #ii_0x\15f8,(a0)+ // xxx.w + move.l #ii_0x\15f9,(a0)+ // xxx.l +// ror.w ea + ii_lset_opea \16,d // (ax), (ax)+ + ii_lset_opea \16,e // -(ax),d16(ax) + ii_lset_opeag \16,f // d8(ax,dy) + lea table+0x\16\2f8*4,a0 + move.l #ii_0x\16f8,(a0)+ // xxx.w + move.l #ii_0x\16f9,(a0)+ // xxx.l +// rol.w ea + ii_lset_opea \17,d // (ax), (ax)+ + ii_lset_opea \17,e // -(ax),d16(ax) + ii_lset_opeag \17,f // d8(ax,dy) + lea table+0x\17\2f8*4,a0 + move.l #ii_0x\17f8,(a0)+ // xxx.w + move.l #ii_0x\17f9,(a0)+ // xxx.l +// ende +.endm; +/******************************************************/ +ii_shift_op:.macro // 1=code +//byt------------------------------- +//asx.b #x,dx + ii_shift_op2agb 0,as,a +//lsx.b #x,dx + ii_shift_op2aub 0,ls,a +//roxx.b #x,dx + ii_shift_op2agb 1,rox,a +//rox.b #x,dx + ii_shift_op2aub 1,ro,a +//asx.b dy,dx + ii_shift_op2agb 2,as,b +//lsx.b dy,dx + ii_shift_op2aub 2,ls,b +//roxx.b dy,dx + ii_shift_op2agb 3,rox,b +//rox.b dy,dx + ii_shift_op2aub 3,ro,b +// word --------------------------------------- +//asx.w #x,dx + ii_shift_op2agw 4,as,a +//lsx.w #x,dx + ii_shift_op2auw 4,ls,a +//roxx.w #x,dx + ii_shift_op2agw 5,rox,a +//rox.w #x,dx + ii_shift_op2auw 5,ro,a +//asx.w dy,dx + ii_shift_op2agw 6,as,b +//lsx.w dy,dx + ii_shift_op2auw 6,ls,b +//roxx.w dy,dx + ii_shift_op2agw 7,rox,b +//rox.w dy,dx + ii_shift_op2auw 7,ro,b +// long --------------------------------------- +//roxx.l #x,dx + ii_shift_op2agw 9,rox,a +//rox.l #x,dx + ii_shift_op2auw 9,ro,a +//roxx.l dy,dx + ii_shift_op2agw b,rox,b +//rox.l dy,dx + ii_shift_op2auw b,ro,b +// ea --------------------------------------- +//asr.w #1,ea + ii_shift_op2ea 0,asr +//asl.w #1,ea + ii_shift_op2ea 1,asl +//lsr.w #1,ea + ii_shift_op2ea 2,lsr, +//lsl.w #1,ea + ii_shift_op2ea 3,lsl +//roxr.w #1,ea + ii_shift_op2ea 4,roxr +//roxl.w #1,ea + ii_shift_op2ea 5,roxl +//ror.w #1,ea + ii_shift_op2ea 6,ror +//rol.w #1,ea + ii_shift_op2ea 7,rol +.endm +//byt ============================================ +ii_shift_op2agb:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3b \1,0,\2,d0_off+3(a7) + ii_shift_op1\3b \1,1,\2,d1_off+3(a7) + ii_shift_op1\3b \1,2,\2,d2 + ii_shift_op1\3b \1,3,\2,d3 + ii_shift_op1\3b \1,4,\2,d4 + ii_shift_op1\3b \1,5,\2,d5 + ii_shift_op1\3b \1,6,\2,d6 + ii_shift_op1\3b \1,7,\2,d7 +.endm + +ii_shift_op2aub:.macro //byt: 1=code 2=operation + ii_shift_op1\3b \1,8,\2,d0_off+3(a7) + ii_shift_op1\3b \1,9,\2,d1_off+3(a7) + ii_shift_op1\3b \1,a,\2,d2 + ii_shift_op1\3b \1,b,\2,d3 + ii_shift_op1\3b \1,c,\2,d4 + ii_shift_op1\3b \1,d,\2,d5 + ii_shift_op1\3b \1,e,\2,d6 + ii_shift_op1\3b \1,f,\2,d7 +.endm + +ii_shift_op1ab:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,b,\3r,#8,\4 + ii_shift_op0 2\1\2,b,\3r,#1,\4 + ii_shift_op0 4\1\2,b,\3r,#2,\4 + ii_shift_op0 6\1\2,b,\3r,#3,\4 + ii_shift_op0 8\1\2,b,\3r,#4,\4 + ii_shift_op0 a\1\2,b,\3r,#5,\4 + ii_shift_op0 c\1\2,b,\3r,#6,\4 + ii_shift_op0 e\1\2,b,\3r,#7,\4 + ii_shift_op0 1\1\2,b,\3l,#8,\4 + ii_shift_op0 3\1\2,b,\3l,#1,\4 + ii_shift_op0 5\1\2,b,\3l,#2,\4 + ii_shift_op0 7\1\2,b,\3l,#3,\4 + ii_shift_op0 9\1\2,b,\3l,#4,\4 + ii_shift_op0 b\1\2,b,\3l,#5,\4 + ii_shift_op0 d\1\2,b,\3l,#6,\4 + ii_shift_op0 f\1\2,b,\3l,#7,\4 +.endm + +ii_shift_op1bb:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,b,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,b,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,b,\3r,d2,\4 + ii_shift_op0 6\1\2,b,\3r,d3,\4 + ii_shift_op0 8\1\2,b,\3r,d4,\4 + ii_shift_op0 a\1\2,b,\3r,d5,\4 + ii_shift_op0 c\1\2,b,\3r,d6,\4 + ii_shift_op0 e\1\2,b,\3r,d7,\4 + ii_shift_op0b 1\1\2,b,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,b,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,b,\3l,d2,\4 + ii_shift_op0 7\1\2,b,\3l,d3,\4 + ii_shift_op0 9\1\2,b,\3l,d4,\4 + ii_shift_op0 b\1\2,b,\3l,d5,\4 + ii_shift_op0 d\1\2,b,\3l,d6,\4 + ii_shift_op0 f\1\2,b,\3l,d7,\4 +.endm +// word --------------------------------------- +ii_shift_op2agw:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3w \1,0,\2,d0_off+2(a7) + ii_shift_op1\3w \1,1,\2,d1_off+2(a7) + ii_shift_op1\3w \1,2,\2,d2 + ii_shift_op1\3w \1,3,\2,d3 + ii_shift_op1\3w \1,4,\2,d4 + ii_shift_op1\3w \1,5,\2,d5 + ii_shift_op1\3w \1,6,\2,d6 + ii_shift_op1\3w \1,7,\2,d7 +.endm + +ii_shift_op2auw:.macro //byt: 1=code 2=operation + ii_shift_op1\3w \1,8,\2,d0_off+2(a7) + ii_shift_op1\3w \1,9,\2,d1_off+2(a7) + ii_shift_op1\3w \1,a,\2,d2 + ii_shift_op1\3w \1,b,\2,d3 + ii_shift_op1\3w \1,c,\2,d4 + ii_shift_op1\3w \1,d,\2,d5 + ii_shift_op1\3w \1,e,\2,d6 + ii_shift_op1\3w \1,f,\2,d7 +.endm + +ii_shift_op1aw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,w,\3r,#8,\4 + ii_shift_op0 2\1\2,w,\3r,#1,\4 + ii_shift_op0 4\1\2,w,\3r,#2,\4 + ii_shift_op0 6\1\2,w,\3r,#3,\4 + ii_shift_op0 8\1\2,w,\3r,#4,\4 + ii_shift_op0 a\1\2,w,\3r,#5,\4 + ii_shift_op0 c\1\2,w,\3r,#6,\4 + ii_shift_op0 e\1\2,w,\3r,#7,\4 + ii_shift_op0 1\1\2,w,\3l,#8,\4 + ii_shift_op0 3\1\2,w,\3l,#1,\4 + ii_shift_op0 5\1\2,w,\3l,#2,\4 + ii_shift_op0 7\1\2,w,\3l,#3,\4 + ii_shift_op0 9\1\2,w,\3l,#4,\4 + ii_shift_op0 b\1\2,w,\3l,#5,\4 + ii_shift_op0 d\1\2,w,\3l,#6,\4 + ii_shift_op0 f\1\2,w,\3l,#7,\4 +.endm + +ii_shift_op1bw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,w,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,w,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,w,\3r,d2,\4 + ii_shift_op0 6\1\2,w,\3r,d3,\4 + ii_shift_op0 8\1\2,w,\3r,d4,\4 + ii_shift_op0 a\1\2,w,\3r,d5,\4 + ii_shift_op0 c\1\2,w,\3r,d6,\4 + ii_shift_op0 e\1\2,w,\3r,d7,\4 + ii_shift_op0b 1\1\2,w,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,w,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,w,\3l,d2,\4 + ii_shift_op0 7\1\2,w,\3l,d3,\4 + ii_shift_op0 9\1\2,w,\3l,d4,\4 + ii_shift_op0 b\1\2,w,\3l,d5,\4 + ii_shift_op0 d\1\2,w,\3l,d6,\4 + ii_shift_op0 f\1\2,w,\3l,d7,\4 +.endm +// long --------------------------------------- +ii_shift_op2agl:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3l \1,0,\2,d0_off(a7) + ii_shift_op1\3l \1,1,\2,d1_off(a7) + ii_shift_op1\3l \1,2,\2,d2 + ii_shift_op1\3l \1,3,\2,d3 + ii_shift_op1\3l \1,4,\2,d4 + ii_shift_op1\3l \1,5,\2,d5 + ii_shift_op1\3l \1,6,\2,d6 + ii_shift_op1\3l \1,7,\2,d7 +.endm + +ii_shift_op2aul:.macro //byt: 1=code 2=operation + ii_shift_op1\3l \1,8,\2,d0_off(a7) + ii_shift_op1\3l \1,9,\2,d1_off(a7) + ii_shift_op1\3l \1,a,\2,d2 + ii_shift_op1\3l \1,b,\2,d3 + ii_shift_op1\3l \1,c,\2,d4 + ii_shift_op1\3l \1,d,\2,d5 + ii_shift_op1\3l \1,e,\2,d6 + ii_shift_op1\3l \1,f,\2,d7 +.endm + +ii_shift_op1al:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,l,\3r,#8,\4 + ii_shift_op0 2\1\2,l,\3r,#1,\4 + ii_shift_op0 4\1\2,l,\3r,#2,\4 + ii_shift_op0 6\1\2,l,\3r,#3,\4 + ii_shift_op0 8\1\2,l,\3r,#4,\4 + ii_shift_op0 a\1\2,l,\3r,#5,\4 + ii_shift_op0 c\1\2,l,\3r,#6,\4 + ii_shift_op0 e\1\2,l,\3r,#7,\4 + ii_shift_op0 1\1\2,l,\3l,#8,\4 + ii_shift_op0 3\1\2,l,\3l,#1,\4 + ii_shift_op0 5\1\2,l,\3l,#2,\4 + ii_shift_op0 7\1\2,l,\3l,#3,\4 + ii_shift_op0 9\1\2,l,\3l,#4,\4 + ii_shift_op0 b\1\2,l,\3l,#5,\4 + ii_shift_op0 d\1\2,l,\3l,#6,\4 + ii_shift_op0 f\1\2,l,\3l,#7,\4 +.endm + +ii_shift_op1bl:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,l,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,l,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,l,\3r,d2,\4 + ii_shift_op0 6\1\2,l,\3r,d3,\4 + ii_shift_op0 8\1\2,l,\3r,d4,\4 + ii_shift_op0 a\1\2,l,\3r,d5,\4 + ii_shift_op0 c\1\2,l,\3r,d6,\4 + ii_shift_op0 e\1\2,l,\3r,d7,\4 + ii_shift_op0b 1\1\2,l,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,l,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,l,\3l,d2,\4 + ii_shift_op0 7\1\2,l,\3l,d3,\4 + ii_shift_op0 9\1\2,l,\3l,d4,\4 + ii_shift_op0 b\1\2,l,\3l,d5,\4 + ii_shift_op0 d\1\2,l,\3l,d6,\4 + ii_shift_op0 f\1\2,l,\3l,d7,\4 +.endm +// .word ea ============================================ +ii_shift_op2ea:.macro //1=code 2.ziffer 2=shiftart +// (a0) bis (a7) ---------------------------- +ii_0xe\1d0: + move.l a0_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d1: + move.l a1_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d2: + ii_shift_typ w,\2,#1,(a2),(a2). +ii_0xe\1d3: + ii_shift_typ w,\2,#1,(a3),(a3). +ii_0xe\1d4: + ii_shift_typ w,\2,#1,(a4),(a4). +ii_0xe\1d5: + ii_shift_typ w,\2,#1,(a5),(a5). +ii_0xe\1d6: + ii_shift_typ w,\2,#1,(a6),(a6). +ii_0xe\1d7: + move.l usp,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// (a0)+ bis (a7)+ ----------------------------- +ii_0xe\1d8: + move.l a0_off(a7),a1 + addq.l #2,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d9: + move.l a1_off(a7),a1 + addq.l #2,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1da: + ii_shift_typ w,\2,#1,(a2),(a2)+. +ii_0xe\1db: + ii_shift_typ w,\2,#1,(a3),(a3)+ +ii_0xe\1dc: + ii_shift_typ w,\2,#1,(a4),(a4)+ +ii_0xe\1dd: + ii_shift_typ w,\2,#1,(a5),(a5)+ +ii_0xe\1de: + ii_shift_typ w,\2,#1,(a6),(a6)+ +ii_0xe\1df: + move.l usp,a1 + addq.l #2,a1 + move.l a1,usp + subq.l #2,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// -(a0) bis -(a7) ----------------------------- +ii_0xe\1e0: + move.l a0_off(a7),a1 + subq.l #2,a1 + move.l a1,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e1: + move.l a1_off(a7),a1 + subq.l #2,a1 + move.l a1,a1_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e2: + ii_shift_typ w,\2,#1,-(a2),(a2). +ii_0xe\1e3: + ii_shift_typ w,\2,#1,-(a3),(a3) +ii_0xe\1e4: + ii_shift_typ w,\2,#1,-(a4),(a4) +ii_0xe\1e5: + ii_shift_typ w,\2,#1,-(a5),(a5) +ii_0xe\1e6: + ii_shift_typ w,\2,#1,-(a6),(a6) +ii_0xe\1e7: + move.l usp,a1 + subq.l #2,a1 + move.l a1,usp + ii_shift_typ w,\2,#1,(a1),(a1). +// d16(a0) bis d16(a7) ----------------------------- +ii_0xe\1e8: + move.w (a0)+,a1 + add.l a0_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e9: + move.w (a0)+,a1 + add.l a1_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1ea: + move.w (a0)+,a1 + add.l a2,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1eb: + move.w (a0)+,a1 + add.l a3,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ec: + move.w (a0)+,a1 + add.l a4,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ed: + move.w (a0)+,a1 + add.l a5,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ee: + move.w (a0)+,a1 + add.l a6,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ef: + mvs.w (a0)+,d0 + move.l usp,a1 + add.l d0,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// d8(a0,dy) bis d8(a7,dy) ----------------------------- +ii_0xe\1f0: + move.l a0_off(a0),a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f1: + move.l a1_off(a0),a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f2: + move.l a2,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f3: + move.l a3,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f4: + move.l a4,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f5: + move.l a5,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f6: + move.l a6,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f7: + move.l usp,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +// xxx.w xxx.l +ii_0xe\1f8: + move.w (a0)+,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f9: + move.l (a0)+,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +.endm +//============================================================================ +//subroutine +//------------------------------ +ii_shift_op0:.macro // shift: 1=code 2=size 3=shift art 4=shift wert 5=ea +ii_0xe\1: + ii_shift_typ \2,\3,\4,\5,\5 +.endm + +ii_shift_op0b:.macro // shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea +ii_0xe\1: + move.l \4,d0 + ii_shift_typ \2,\3,d0,\5,\5 +.endm + +ii_shift_typ:.macro //1=size 2=shift art 3=shift wert 4=source 5=dest +#ifdef halten + halt +#endif +.ifc asr,\2 + mvs.\1 \4,d1 +.else + mvz.\1 \4,d1 +.endif +.ifc roxr,\2 + nop +.else + .ifc roxl,\2 + nop + .else + .ifc ror,\2 + nop + .else + .ifc rol,\2 + nop + .else + \2.l \3,d1 + .endif + .endif + .endif +.endif + set_cc0 + move.\1 d1,\5 + ii_end +.endm diff --git a/BaS_GNU/sources/ii_sub.h b/BaS_GNU/sources/ii_sub.h new file mode 100644 index 0000000..1405e1a --- /dev/null +++ b/BaS_GNU/sources/ii_sub.h @@ -0,0 +1,584 @@ +//-------------------------------------------------------------------- +// sub +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// sub.b #im,dx +//-------------------------------------------------------------------- +subbir_macro:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + sub.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea,dx +//-------------------------------------------------------------------- +subdd:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +subddd:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub (ea)->dy,dx +//-------------------------------------------------------------------- +subdda:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +subddai:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea->ay,-(ay),dx +//-------------------------------------------------------------------- +subddad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d16(ay),dx +//-------------------------------------------------------------------- +subd16ad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d8(ay,dy),dx +//-------------------------------------------------------------------- +subd8ad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub xxx.w,dx +//-------------------------------------------------------------------- +subxwd:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub xxx.l,dx +//-------------------------------------------------------------------- +subxld:.macro +#ifdef halten_sub + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d16(pc),dx +//-------------------------------------------------------------------- +subd16pcd:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d8(pc,dy),dx +//-------------------------------------------------------------------- +subd8pcd:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// sub dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // sub (ea)->dy,dx +//-------------------------------------------------------------------- +subeda:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +subedai:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +subedaid:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +subedad:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +subedadd:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,d16(ay) +//-------------------------------------------------------------------- +sube16ad:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,d8(ay,dy) +//-------------------------------------------------------------------- +sube8ad:.macro +#ifdef halten_sub + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,xxx.w +//-------------------------------------------------------------------- +subxwe:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,xxx.l +//-------------------------------------------------------------------- +subxle:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// // suba.w ea,ax +//-------------------------------------------------------------------- +subaw:.macro +#ifdef halten_sub + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + mvs.w \1,d0 + suba.l d0,\2 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// sub.w ea,usp +//-------------------------------------------------------------------- +subawa7:.macro +#ifdef halten_sub + halt +#endif + mvs.w \1,d0 + move.l usp,a1 + sub.l d0,a1 + move.l a1,usp + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w usp?,ax +//-------------------------------------------------------------------- +subawu:.macro +#ifdef halten_sub + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + move.l a7,_a7_save + move.l usp,a7 + move.l \1,d0 + suba.l d0,\2 + move.l a7,usp + move.l _a7_save,a7 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// // suba.w usp?,usp +//-------------------------------------------------------------------- +subawua7:.macro + subawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // suba.w d16(ay),ax +//-------------------------------------------------------------------- +subawd16a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + adda.l d0,a1 + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d8(ay,dy),ax +//-------------------------------------------------------------------- +subawd8a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w xxx.w,ax +//-------------------------------------------------------------------- +subawxwax:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w xxx.l,ax +//-------------------------------------------------------------------- +subawxlax:.macro +#ifdef halten_sub + halt +#endif + move.l (a0)+,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d16(pc),ax +//-------------------------------------------------------------------- +subawd16pcax:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + adda.l a0,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d8(pc,dy),ax +//-------------------------------------------------------------------- +subawd8pcax:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w #im,ax +//-------------------------------------------------------------------- +subawim:.macro +#ifdef halten_sub + halt +#endif + mvs.w \1,d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.l d8(ay,dy),ax +//-------------------------------------------------------------------- +subald8a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.l d8(pc,dy),ax +//-------------------------------------------------------------------- +subakd8pcax:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//***************************************************************************************** +// subx +//***************************************************************************************** +//-------------------------------------------------------------------- +// // subx dy,dx +//-------------------------------------------------------------------- +subdx:.macro +#ifdef halten_sub + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + mvs.\3 \2,d0 + mvs.\3 \1,d1 + subx.l d0,d1 + set_cc0 + move.\3 d1,\1 + ii_end + .endm; +//-------------------------------------------------------------------- +// // subx -(ay),-(ax) +//-------------------------------------------------------------------- +subdax:.macro +#ifdef halten_sub + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + move.l \1,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d0 +.endif + move.l \2,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d1 +.endif + subx.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/illegal_instruction.S b/BaS_GNU/sources/illegal_instruction.S new file mode 100644 index 0000000..25b3f70 --- /dev/null +++ b/BaS_GNU/sources/illegal_instruction.S @@ -0,0 +1,328 @@ +.global _illegal_instruction +.global _illegal_table_make + +#include "startcf.h" +#include "ii_macro.h" +#include "ii_func.h" +#include "ii_op.h" +#include "ii_opc.h" +#include "ii_add.h" +#include "ii_sub.h" +#include "ii_or.h" +#include "ii_and.h" +#include "ii_dbcc.h" +#include "ii_shd.h" +#include "ii_movem.h" +#include "ii_lea.h" +#include "ii_shift.h" +#include "ii_exg.h" +#include "ii_movep.h" +#include "ii_ewf.h" +#include "ii_move.h" + +.extern _ii_shift_vec +.extern ewf + +/*******************************************************/ +.text +ii_error: + nop + halt + nop + nop + +_illegal_instruction: +#ifdef ii_on + move.w #0x2700,sr + lea -ii_ss(a7),a7 + movem.l d0/d1/a0/a1,(a7) + move.l pc_off(a7),a0 // pc + mvz.w (a0)+,d0 // code + lea table,a1 + move.l 0(a1,d0*4),a1 + jmp (a1) +/*************************************************************************************************/ +#endif +_illegal_table_make: +#ifdef ii_on + lea table,a0 + moveq #0,d0 +_itm_loop: + move.l #ii_error,(a0)+ + addq.l #1,d0 + cmp.l #0xF000,d0 + bne _itm_loop +//------------------------------------------------------------------------- + ii_ewf_lset // diverse fehlende adressierungn +//------------------------------------------------------------------------- +// 0x0000 +// ori + ii_lset_op 00 +// andi + ii_lset_op 02 +// subi + ii_lset_op 04 +// addi + ii_lset_op 06 +// eori + ii_lset_op 0a +// cmpi + ii_lset_op 0c +// movep + ii_movep_lset +//------------------------------------------------------------------------- +// 0x1000 move.b +// 0x2000 move.l +// 0x3000 move.w + ii_move_lset +//------------------------------------------------------------------------- +// 0x4000 +//------------------------------------------------------------------------- +// negx + ii_lset_op 40 +// neg + ii_lset_op 44 +// not + ii_lset_op 46 +//--------------------------------------------------------------------------------------------- +// lea d8(ax,dy.w),az; d8(pc,dy.w),az +//------------------------------------------------------------------- + ii_lea_lset +//------------------------------------------------------------------- +// movem +//------------------------------------------------------------------- + ii_movem_lset +//------------------------------------------------------------------------- +// 0x5000 +//------------------------------------------------------------------------- +// addq, subq + ii_lset_op 50 + ii_lset_op 51 + ii_lset_op 52 + ii_lset_op 53 + ii_lset_op 54 + ii_lset_op 55 + ii_lset_op 56 + ii_lset_op 57 + ii_lset_op 58 + ii_lset_op 59 + ii_lset_op 5a + ii_lset_op 5b + ii_lset_op 5c + ii_lset_op 5d + ii_lset_op 5e + ii_lset_op 5f +// dbcc + ii_lset_dbcc +// scc + ii_lset_opc 50 + ii_lset_opc 51 + ii_lset_opc 52 + ii_lset_opc 53 + ii_lset_opc 54 + ii_lset_opc 55 + ii_lset_opc 56 + ii_lset_opc 57 + ii_lset_opc 58 + ii_lset_opc 59 + ii_lset_opc 5a + ii_lset_opc 5b + ii_lset_opc 5c + ii_lset_opc 5d + ii_lset_opc 5e + ii_lset_opc 5f +//------------------------------------------------------------------------- +// 0x8000 or +//------------------------------------------------------------------------- + ii_lset_func 8 +//------------------------------------------------------------------------- +// 0x9000 sub +//------------------------------------------------------------------------- + ii_lset_func 9 +//------------------------------------------------------------------------- +// 0xb000 +//------------------------------------------------------------------------- +// eor + ii_lset_op b1 + ii_lset_op b3 + ii_lset_op b5 + ii_lset_op b7 + ii_lset_op b9 + ii_lset_op bb + ii_lset_op bd + ii_lset_op bf +//------------------------------------------------------------------------- +// 0xc000 +//------------------------------------------------------------------------- +// and + ii_lset_func c +// exg + ii_exg_lset +//------------------------------------------------------------------------- +// 0xd000 add +//------------------------------------------------------------------------- + ii_lset_func d +//------------------------------------------------------------------------- +// 0xe000 +//------------------------------------------------------------------------- +// shift register + ii_shift_lset e +//------------------------------------------------- +// differenz zwischen orginal und gemoved korrigieren + lea ii_error(pc),a1 + move.l a1,d1 + sub.l #ii_error,d1 + lea table,a0 + moveq #0,d0 +_itkorr_loop: + add.l d1,(a0)+ + addq.l #1,d0 + cmp.l #0xF000,d0 + bne _itkorr_loop +#endif + rts +#ifdef ii_on +//***********************************************************************************/ +//------------------------------------------------------------------------- + ii_ewf_func // diverse fehlende adressierungn +//------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x0000 +//-------------------------------------------------------------------- +// ori 00 + ii_op 00,or.l,i +//-------------------------------------------------------------------- +// andi 02 + ii_op 02,and.l,i +//-------------------------------------------------------------------- +// subi 04 + ii_op 04,and.l,i +//-------------------------------------------------------------------- +// addi 06 + ii_op 06,add.l,i +//-------------------------------------------------------------------- +// eori 0a + ii_op 0a,eor.l,i +//-------------------------------------------------------------------- +// cmpi 0c + ii_op 0c,cmp.l,i +//-------------------------------------------------------------------- +// movep + ii_movep_func +///--------------------------------------------------------------------------------------------- +// 0x1000 move.b +// 0x2000 move.l +// 0x3000 move.w + ii_move_op +//--------------------------------------------------------------------------------------------- +// 0x4000 +//--------------------------------------------------------------------------------------------- +// neg 0x40.. + ii_op 40,negx.l,n +//--------------------------------------------------------------------------------------------- +// neg 0x44.. + ii_op 44,neg.l,n +//--------------------------------------------------------------------------------------------- +// not 0x46.. + ii_op 46,not.l,n +//--------------------------------------------------------------------------------------------- +// lea d8(ax,dy.w),az; d8(pc,dy.w),az +//------------------------------------------------------------------- + ii_lea_func +//------------------------------------------------------------------- +// movem +//-------------------------------------------------------------------- +ii_movem_func +//--------------------------------------------------------------------------------------------- +// 0x5000 +//--------------------------------------------------------------------------------------------- +//dbcc + ii_dbcc_func +// addq 0x5... + ii_op 50,addq.l #8,q + ii_op 52,addq.l #1,q + ii_op 54,addq.l #2,q + ii_op 56,addq.l #3,q + ii_op 58,addq.l #4,q + ii_op 5a,addq.l #5,q + ii_op 5c,addq.l #6,q + ii_op 5e,addq.l #7,q +//--------------------------------------------------------------------------------------------- +// subq 0x5... + ii_op 51,subq.l #8,q + ii_op 53,subq.l #1,q + ii_op 55,subq.l #2,q + ii_op 57,subq.l #3,q + ii_op 59,subq.l #4,q + ii_op 5b,subq.l #5,q + ii_op 5d,subq.l #6,q + ii_op 5f,subq.l #7,q +//--------------------------------------------------------------------------------------------- +// 0x5... scc + ii_opc 50,st,c + ii_opc 51,sf,c + ii_opc 52,shi,c + ii_opc 53,sls,c + ii_opc 54,scc,c + ii_opc 55,scs,c + ii_opc 56,sne,c + ii_opc 57,seq,c + ii_opc 58,svc,c + ii_opc 59,svs,c + ii_opc 5a,spl,c + ii_opc 5b,smi,c + ii_opc 5c,sge,c + ii_opc 5d,slt,c + ii_opc 5e,sgt,c + ii_opc 5f,sle,c +//--------------------------------------------------------------------------------------------- +// 0x6000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x7000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x8000 +//--------------------------------------------------------------------------------------------- +// or + ii_func 8,or +//--------------------------------------------------------------------------------------------- +// 0x9000 +//--------------------------------------------------------------------------------------------- +// sub + ii_func 9,sub +//--------------------------------------------------------------------------------------------- +// 0xa000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0xb000 +//--------------------------------------------------------------------------------------------- +// eor + ii_op b1,eor.l d0,q + ii_op b3,eor.l d1,q + ii_op b5,eor.l d2,q + ii_op b7,eor.l d3,q + ii_op b9,eor.l d4,q + ii_op bb,eor.l d5,q + ii_op bd,eor.l d6,q + ii_op bf,eor.l d7,q +//--------------------------------------------------------------------------------------------- +// 0xc000 +//--------------------------------------------------------------------------------------------- +// and + ii_func c,and +// exg + ii_exg_func +//--------------------------------------------------------------------------------------------- +// 0xd000 +//--------------------------------------------------------------------------------------------- +// add + ii_func d,add +//--------------------------------------------------------------------------------------------- +// 0xe000 shift +//-------------------------------------------------------------------- + ii_shift_op +//-------------------------------------------------------------------- +// 0xf000 +//-------------------------------------------------------------------- +#endif From 6602b30108fc0df858edac9a421145035feb1be9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 07:34:14 +0000 Subject: [PATCH 040/276] --- BaS_GNU/sources/supervisor.S | 585 +++++++++++++++++++++++++++++++++++ 1 file changed, 585 insertions(+) create mode 100644 BaS_GNU/sources/supervisor.S diff --git a/BaS_GNU/sources/supervisor.S b/BaS_GNU/sources/supervisor.S new file mode 100644 index 0000000..c9520c9 --- /dev/null +++ b/BaS_GNU/sources/supervisor.S @@ -0,0 +1,585 @@ +/********************************************************/ +/* user/supervisor handler +/********************************************************/ + +#include "startcf.h" + +.extern _rt_cacr; +.extern _rt_mod; +.extern _rt_ssp; +.extern _rt_usp; +.extern ___MMUBAR + +/* Register read/write macros */ +#define MCF_MMU_MMUCR ___MMUBAR +#define MCF_MMU_MMUOR ___MMUBAR+0x04 +#define MCF_MMU_MMUSR ___MMUBAR+0x08 +#define MCF_MMU_MMUAR ___MMUBAR+0x10 +#define MCF_MMU_MMUTR ___MMUBAR+0x14 +#define MCF_MMU_MMUDR ___MMUBAR+0x18 + +.global _privileg_violation +.global cpusha + +.text +_privileg_violation: + move.w #0x2700,sr + lea -12(a7),a7 + movem.l d0/a0/a5,(a7) +#ifndef cf_stack + lea 0x52f0,a0 + move.l #0x20,(a0) // set auf 68030 +#endif + lea _rt_mod,a0 // zugriff setzen + tst.b (a0) // vom rt_supervisormodus? + bne pv_work // ja-> +// tatsächlich privileg violation + mov3q.l #-1,(a0) // sr_mod setzen + move.l usp,a5 // usp holen + move.l a5,8(a0) // sichern + move.l 4(a0),a5 // rt_ssp holen +#ifdef cf_stack + move.l 16(a7),-(a5) // pc verschieben + move.l 12(a7),-(a5) // sr verschieben + bset #5,2(a5) // auf super setzen +#else + move.w 12(a7),-(a5) // vector nr. + move.l 16(a7),-(a5) // pc verschieben + move.w 14(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif + move.l a5,usp + move.l 12(a0),a5 // rt_vbr + lea 0x18(a5),a5 // vector + move.l (a5),16(a7) // vector privileg violation + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// privileg violation +pv_work: + move.l 16(a7),a5 // fault pc + move.b (a5),d0 // fault code + cmp.b #0x4e,d0 // 1.byt 0x4e + beq pv_4e // ja-> + cmp.b #0x46,d0 // 1.byt 0x46 + beq pv_46 // ja-> + cmp.b #0x40,d0 // 1.byt 0x40 + beq pv_40 // ja-> + cmp.b #0xf4,d0 // 0xf4? + beq pv_f4 + cmp.b #0xf3,d0 // 0xf3? + beq pv_f3 +// hierher sollt man nicht kommen + nop + halt + nop +// code 0x4exx ******************************************** +pv_4e: + move.b 1(a5),d0 + cmp.b #0x73,d0 //rte? + beq pv_rte //ja-> + cmp.b #0x72,d0 //stop? + beq pv_stop //ja-> + cmp.b #0x7B,d0 //movec? + beq pv_movec //ja-> +// move usp + btst #3,d0 // to or from + bne pv_usp_to_ax // usp -> ax +// move ax->usp + cmp.b #0x60,d0 //movec? + beq pv_a0_usp //ja-> + cmp.b #0x61,d0 //movec? + beq pv_a1_usp //ja-> + cmp.b #0x62,d0 //movec? + beq pv_a2_usp //ja-> + cmp.b #0x63,d0 //movec? + beq pv_a3_usp //ja-> + cmp.b #0x64,d0 //movec? + beq pv_a4_usp //ja-> + cmp.b #0x65,d0 //movec? + beq pv_a5_usp //ja-> + cmp.b #0x66,d0 //movec? + beq pv_a6_usp //ja-> + halt + bra pv_a7_usp //ja-> +// move usp->ax +pv_usp_to_ax: + move.l 8(a0),a5 //rt_usp holen + cmp.b #0x68,d0 //movec? + beq pv_usp_a0 //ja-> + cmp.b #0x69,d0 //movec? + beq pv_usp_a1 //ja-> + cmp.b #0x6a,d0 //movec? + beq pv_usp_a2 //ja-> + cmp.b #0x6b,d0 //movec? + beq pv_usp_a3 //ja-> + cmp.b #0x6c,d0 //movec? + beq pv_usp_a4 //ja-> + cmp.b #0x6d,d0 //movec? + beq pv_usp_a5 //ja-> + cmp.b #0x6e,d0 //movec? + beq pv_usp_a6 //ja-> +// usp->a7 + move.l a5,4(a0) // rt usp -> rt ssp + move.l a5,usp // und setzen + bra pv_usp_ax +// a0->usp +pv_a0_usp: move.l 4(a7),a5 + bra pv_ax_usp +// a1->usp +pv_a1_usp: move.l a1,a5 + bra pv_ax_usp +// a2->usp +pv_a2_usp: move.l a2,a5 + bra pv_ax_usp +// a3->usp +pv_a3_usp: move.l a3,a5 + bra pv_ax_usp +// a4->usp +pv_a4_usp: move.l a4,a5 + bra pv_ax_usp +// a5->usp +pv_a5_usp: move.l 8(a7),a5 + bra pv_ax_usp +// a6->usp +pv_a6_usp: move.l a6,a5 + bra pv_ax_usp +// a7->usp +pv_a7_usp: move.l 4(a0),a5 // rt_ssp -> a5 +pv_ax_usp: + move.l a5,8(a0) // usp -> rt_usp + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// usp->a0 +pv_usp_a0: + move.l a5,4(a7) + bra pv_usp_ax +pv_usp_a1: + move.l a5,a1 + bra pv_usp_ax +pv_usp_a2: + move.l a5,a2 + bra pv_usp_ax +pv_usp_a3: + move.l a5,a3 + bra pv_usp_ax +pv_usp_a4: + move.l a5,a4 + bra pv_usp_ax +pv_usp_a5: + move.l a5,8(a7) + bra pv_usp_ax +pv_usp_a6: + move.l a5,a6 +pv_usp_ax: + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// rte +pv_rte: + move.l usp,a5 +#ifdef cf_stack + move.l (a5)+,12(a7) // sr verschieben + move.l (a5)+,16(a7) // pc verschieben +#else + move.w (a5)+,14(a7) // sr verschieben + move.l (a5)+,16(a7) // pc verschieben + move.w (a5)+,12(a7) // vector +#endif + bclr #5,14(a7) // war es von super? + bne pv_rte_sup // ja-> + clr.l (a0) // rt_mod auf user + move.l a5,4(a0) // rt_ssp sichern + move.l 8(a0),a5 // rt_usp holen +pv_rte_sup: + move.l a5,usp // usp setzen + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// stop +pv_stop: + move.b 2(a5),d0 // sr wert + and.l #0x0700,d0 // int mask + cmp.w #0x700,d0 + beq stop7 + cmp.w #0x600,d0 + beq stop6 + cmp.w #0x500,d0 + beq stop5 + cmp.w #0x400,d0 + beq stop4 + cmp.w #0x300,d0 + beq stop3 + cmp.w #0x200,d0 + beq stop2 + cmp.w #0x100,d0 + beq stop1 + stop #0x2000 + bra stop_weiter +stop1: + stop #0x2100 + bra stop_weiter +stop2: + stop #0x2200 + bra stop_weiter +stop3: + stop #0x2300 + bra stop_weiter +stop4: + stop #0x2400 + bra stop_weiter +stop5: + stop #0x2500 + bra stop_weiter +stop6: + stop #0x2600 + bra stop_weiter +stop7: + stop #0x2700 +stop_weiter: + addq.l #4,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// movec ??????? +pv_movec: + move.w 2(a5),d0 // 2.word holen + and.l #0xf000,d0 + btst #15,d0 // addressregister? + bne pv_movec_ax // ja-> + tst.w d0 // d0? + bne pvm_d1 // nein-> + move.l (a7),-(a7) // d0 holen und sichern + bra pvm_me +pvm_d1: + cmp.w #0x1000,d0 // d1? + bne pvm_d2 // nein-> + move.l d1,-(a7) // d1 holen und sichern + bra pvm_me // fertig machen +pvm_d2: + cmp.w #0x2000,d0 // d1? + bne pvm_d3 // nein-> + move.l d2,-(a7) // d2 holen und sichern + bra pvm_me // fertig machen +pvm_d3: + cmp.w #0x3000,d0 // d1? + bne pvm_d4 // nein-> + move.l d3,-(a7) // d3 holen und sichern + bra pvm_me // fertig machen +pvm_d4: + cmp.w #0x4000,d0 // d1? + bne pvm_d5 // nein-> + move.l d4,-(a7) // d4 holen und sichern + bra pvm_me // fertig machen +pvm_d5: + cmp.w #0x5000,d0 // d1? + bne pvm_d6 // nein-> + move.l d5,-(a7) // d5 holen und sichern + bra pvm_me // fertig machen +pvm_d6: + cmp.w #0x6000,d0 // d1? + bne pvm_d7 // nein-> + move.l d6,-(a7) // d6 holen und sichern + bra pvm_me // fertig machen +pvm_d7: + move.l d7,-(a7) // d7 holen und sichern + bra pvm_me // fertig machen +pv_movec_ax: + cmp.w #0x8000,d0 // a0? + bne pvm_a1 // nein-> + move.l 4(a7),-(a7) // a0 holen und sichern + bra pvm_me // fertig machen +pvm_a1: + cmp.w #0x9000,d0 // a0? + bne pvm_a2 // nein-> + move.l a1,-(a7) // a1 holen und sichern + bra pvm_me // fertig machen +pvm_a2: + cmp.w #0xa000,d0 // a0? + bne pvm_a3 // nein-> + move.l a2,-(a7) // a2 holen und sichern + bra pvm_me // fertig machen +pvm_a3: + cmp.w #0xb000,d0 // a0? + bne pvm_a4 // nein-> + move.l a3,-(a7) // a3 holen und sichern + bra pvm_me // fertig machen +pvm_a4: + cmp.w #0xc000,d0 // a0? + bne pvm_a5 // nein-> + move.l a4,-(a7) // a4 holen und sichern + bra pvm_me // fertig machen +pvm_a5: + cmp.w #0xd000,d0 // a0? + bne pvm_a6 // nein-> + move.l 8(a7),-(a7) // a5 holen und sichern + bra pvm_me // fertig machen +pvm_a6: + cmp.w #0xe000,d0 // a0? + bne pvm_a7 // nein-> + move.l a6,-(a7) // a6 holen und sichern + bra pvm_me // fertig machen +pvm_a7: + move.l 4(a7),-(a7) // a7 holen und sichern +pvm_me: + move.w 2(a5),d0 // 2.word holen + andi.l #0xf,d0 // nur letzte 4 bits + move.l (a7)+,8(a0,d0*4) // start bei +8, *4 weil long + jsr cpusha // gesammten cache flushen + rte +// code 0x46xx ***************************************** +pv_46: + move.b 1(a5),d0 + cmp.b #0xfc,d0 //#d16->sr + beq im_sr //ja-> +//move dx->sr (sr und rt_mod ist supervisor sonst wäre es privileg violation + cmp.b #0xc0,d0 //d0->sr? + bne d1_sr //nein-> + move.w 2(a7),d0 //hier ist d0 gesichert + bra d0_sr +d1_sr: + cmp.b #0xc1,d0 //d1->sr? + bne d2_sr //nein-> + move.w d1,d0 + bra d0_sr +d2_sr: + cmp.b #0xc2,d0 //d2->sr? + bne d3_sr + move.w d2,d0 + bra d0_sr +d3_sr: + cmp.b #0xc3,d0 //d3->sr? + bne d4_sr + move.w d3,d0 + bra d0_sr +d4_sr: + cmp.b #0xc4,d0 //d4->sr? + bne d5_sr + move.w d4,d0 + bra d0_sr +d5_sr: + cmp.b #0xc5,d0 //d5->sr? + bne d6_sr + move.w d5,d0 + bra d0_sr +d6_sr: + cmp.b #0xc6,d0 //d6->sr? + bne d7_sr + move.w d6,d0 + bra d0_sr +d7_sr: + move.w d7,d0 // sonst d7->sr +d0_sr: + addq.l #2,16(a7) // next + bra pv_set_sr_end // fertig machen +// move #xxxx,sr +im_sr: + addq.l #4,16(a7) // next + move.w 2(a5),d0 // data +pv_set_sr_end: + bclr #13,d0 // war super? + bne pv_sre2 // ja -> + clr.l (a0) + move.l usp,a5 // usp + move.l a5,4(a0) // rt_ssp speichern + move.l 8(a0),a5 // rt_usp holen + move.l a5,usp // setzen +pv_sre2: + move.w d0,14(a7) // sr setzen + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// code 0x40xx ***************************************** +pv_40: + move.b 1(a5),d0 // 2.byt + cmp.b #0xe7,d0 + beq pv_strldsr +// move sr->dx + move.l 12(a7),a5 // sr holen + tst.b (a0) // super? + beq pv_40_user // nein? + lea 0x2000(a5),a5 // super zuaddieren +pv_40_user: + cmp.b #0xc0,d0 + bne nsr_d1 + move.w a5,2(a7) + bra sr_dx_end +nsr_d1: + cmp.b #0xc1,d0 + bne nsr_d2 + move.w a5,d1 + bra sr_dx_end +nsr_d2: + cmp.b #0xc2,d0 + bne nsr_d3 + move.w a5,d2 + bra sr_dx_end +nsr_d3: + cmp.b #0xc3,d0 + bne nsr_d4 + move.w a5,d3 + bra sr_dx_end +nsr_d4: + cmp.b #0xc4,d0 + bne nsr_d5 + move.w a5,d4 + bra sr_dx_end +nsr_d5: + cmp.b #0xc5,d0 + bne nsr_d6 + move.w a5,d5 + bra sr_dx_end +nsr_d6: + cmp.b #0xc6,d0 + bne nsr_d7 + move.w a5,d6 + bra sr_dx_end +nsr_d7: + move.w a5,d7 + halt +sr_dx_end: + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zurück + lea 12(a7),a7 + rte +// strldsr +pv_strldsr: + nop + halt + nop +// code 0xf4xx *********************************** +pv_f4: + addq.l #2,16(a7) // next instr + move.b 1(a5),d0 // 2.byt + bsr pv_ax_a0 // richtiges register + move.b 1(a5),d0 // 2.byt + cmp.b #0x30,d0 // >0xf430 + blo pv_intouch +// cpushl + cpushl bc,(a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +pv_intouch: + intouch a0 + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +// subroutine register ax->a0 +pv_ax_a0: + and.l #0x7,d0 // nur register nummer + subq.l #1,d0 + bmi pv_a0_a0 + subq.l #1,d0 + bmi pv_a1_a0 + subq.l #1,d0 + bmi pv_a2_a0 + subq.l #1,d0 + bmi pv_a3_a0 + subq.l #1,d0 + bmi pv_a4_a0 + subq.l #1,d0 + bmi pv_a5_a0 + subq.l #1,d0 + bmi pv_a6_a0 + move.l a7,a0 + rts +pv_a0_a0: + move.l 8(a7),a0 + rts +pv_a1_a0: + move.l a1,a0 + rts +pv_a2_a0: + move.l a2,a0 + rts +pv_a3_a0: + move.l a3,a0 + rts +pv_a4_a0: + move.l a4,a0 + rts +pv_a5_a0: + move.l 12(a7),a0 + rts +pv_a6_a0: + move.l a6,a0 + rts +// code 0xf4xx *********************************** +pv_f3: + addq.l #2,16(a7) // next instr + move.b 1(a5),d0 // 2. byt + cmp.b #0x40,d0 + bgt pv_frestore +//fsave (ax) oder d16(ax) + jsr pv_ax_a0 // richtiges register holen + move.b 1(a5),d0 + cmp.b #0x20,d0 +// +d16 + blt pv_f3_ax + addq.l #2,16(a7) // next instr + clr.l d0 + move.w 2(a0),d0 // d16 + add.l d0,a0 +pv_f3_ax: + fsave (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +pv_frestore: + cmp.b #0x7a,d0 + beq pv_f_d16pc +// frestore (ax) oder d16(ax) + jsr pv_ax_a0 // richtiges register holen + move.b 1(a5),d0 + cmp.b #0x60,d0 + blt pv_frestore_ax +pv_fend: + addq.l #2,16(a7) // next instr + clr.l d0 + move.w 2(a0),d0 // d16 + add.l d0,a0 +pv_frestore_ax: + frestore (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +// frestore d16(pc) +pv_f_d16pc: + move.l 16(a7),a0 // pc holen + bra pv_fend +//***************************************************** +cpusha: + lea -16(a7),a7 + movem.l d0-d2/a0,(a7) // register sichern + move sr,d2 + nop + move #0x2700,sr // no interrupts + + clr.l d0 + clr.l d1 + move.l d0,a0 +cfa_setloop: + cpushl bc,(a0) // flush + lea 0x10(a0),a0 // index+1 + addq.l #1,d1 // index+1 + cmpi.w #512,d1 // alle sets? + bne cfa_setloop // nein-> + clr.l d1 + addq.l #1,d0 + move.l d0,a0 + cmpi.w #4,d0 // all ways? + bne cfa_setloop // nein-> + nop + move.l _rt_cacr,d0 // holen + movec d0,cacr // setzen + move.w d2,sr // alte interrupt maske + movem.l (a7),d0-d2/a0 // register zurück + lea 16(a7),a7 + + rts +//*******************************************************33 + From be51183566825aaab619d931cf7fb2daa307467f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 07:34:40 +0000 Subject: [PATCH 041/276] --- BaS_GNU/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index ff2d2cb..bc350cc 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -15,7 +15,7 @@ CC=$(TCPREFIX)gcc LD=$(TCPREFIX)ld INCLUDE=-Iinclude -CFLAGS=-mcfv4e -Wno-multichar -Os -fomit-frame-pointer +CFLAGS=-mcfv4e -Wno-multichar -Os -Wa,-mcpu=547x -fomit-frame-pointer #CFLAGS=-mcfv4e -Wno-multichar -S -O3 -fomit-frame-pointer SRCDIR=sources OBJDIR=objs @@ -47,7 +47,7 @@ $(EXEC): $(OBJS) echo "generating executable" clean: - rm $(EXEC) *.o + rm $(EXEC) $(OBJS) $(OBJDIR)/%.o:$(SRCDIR)/%.c $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ From b650c7e9661c3b82d0aacfd3f9d6423edf24abe2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 07:35:21 +0000 Subject: [PATCH 042/276] --- BaS_GNU/sources/ewf.S | 1565 ++++++++++++++++++++++++++++++++++ BaS_GNU/sources/exceptions.S | 3 +- 2 files changed, 1566 insertions(+), 2 deletions(-) create mode 100644 BaS_GNU/sources/ewf.S diff --git a/BaS_GNU/sources/ewf.S b/BaS_GNU/sources/ewf.S new file mode 100644 index 0000000..5a4363b --- /dev/null +++ b/BaS_GNU/sources/ewf.S @@ -0,0 +1,1565 @@ +/*************************************************************************************************/ +// extension word format: a0 zeigt auf code, in a1 ist ay, d0/d1 wird zerstört +//------------------------------------------------------------------------------ + +#include "ii_macro.h" + +.global ewf +//----------------------------------------------------------- +.text +ewferr: + nop + halt + nop +//----------------------------------------------------------- +ewf: + mvz.b (a0)+,d1 // 1. byt ewf + mvs.w ewf_table-.-2(pc,d1*2),d1 + jmp ewf_table-.-2(pc,d1) +ewf_table: + .short ewf_00-ewf_table,ewf_01-ewf_table,ewf_02-ewf_table,ewf_03-ewf_table + .short ewf_04-ewf_table,ewf_05-ewf_table,ewf_06-ewf_table,ewf_07-ewf_table + .short ewferr-ewf_table,ewf_09-ewf_table,ewferr-ewf_table,ewf_0b-ewf_table + .short ewferr-ewf_table,ewf_0d-ewf_table,ewferr-ewf_table,ewf_0f-ewf_table + .short ewf_10-ewf_table,ewf_11-ewf_table,ewf_12-ewf_table,ewf_13-ewf_table + .short ewf_14-ewf_table,ewf_15-ewf_table,ewf_16-ewf_table,ewf_17-ewf_table + .short ewferr-ewf_table,ewf_19-ewf_table,ewferr-ewf_table,ewf_1b-ewf_table + .short ewferr-ewf_table,ewf_1d-ewf_table,ewferr-ewf_table,ewf_1f-ewf_table + .short ewf_20-ewf_table,ewf_21-ewf_table,ewf_22-ewf_table,ewf_23-ewf_table + .short ewf_24-ewf_table,ewf_25-ewf_table,ewf_26-ewf_table,ewf_27-ewf_table + .short ewferr-ewf_table,ewf_29-ewf_table,ewferr-ewf_table,ewf_2b-ewf_table + .short ewferr-ewf_table,ewf_2d-ewf_table,ewferr-ewf_table,ewf_2f-ewf_table + .short ewf_30-ewf_table,ewf_31-ewf_table,ewf_32-ewf_table,ewf_33-ewf_table + .short ewf_34-ewf_table,ewf_35-ewf_table,ewf_36-ewf_table,ewf_37-ewf_table + .short ewferr-ewf_table,ewf_39-ewf_table,ewferr-ewf_table,ewf_3b-ewf_table + .short ewferr-ewf_table,ewf_3d-ewf_table,ewferr-ewf_table,ewf_3f-ewf_table + .short ewf_40-ewf_table,ewf_41-ewf_table,ewf_42-ewf_table,ewf_43-ewf_table + .short ewf_44-ewf_table,ewf_45-ewf_table,ewf_46-ewf_table,ewf_47-ewf_table + .short ewferr-ewf_table,ewf_49-ewf_table,ewferr-ewf_table,ewf_4b-ewf_table + .short ewferr-ewf_table,ewf_4d-ewf_table,ewferr-ewf_table,ewf_4f-ewf_table + .short ewf_50-ewf_table,ewf_51-ewf_table,ewf_52-ewf_table,ewf_53-ewf_table + .short ewf_54-ewf_table,ewf_55-ewf_table,ewf_56-ewf_table,ewf_57-ewf_table + .short ewferr-ewf_table,ewf_59-ewf_table,ewferr-ewf_table,ewf_5b-ewf_table + .short ewferr-ewf_table,ewf_5d-ewf_table,ewferr-ewf_table,ewf_5f-ewf_table + .short ewf_60-ewf_table,ewf_61-ewf_table,ewf_62-ewf_table,ewf_63-ewf_table + .short ewf_64-ewf_table,ewf_65-ewf_table,ewf_66-ewf_table,ewf_67-ewf_table + .short ewferr-ewf_table,ewf_69-ewf_table,ewferr-ewf_table,ewf_6b-ewf_table + .short ewferr-ewf_table,ewf_6d-ewf_table,ewferr-ewf_table,ewf_6f-ewf_table + .short ewf_70-ewf_table,ewf_71-ewf_table,ewf_72-ewf_table,ewf_73-ewf_table + .short ewf_74-ewf_table,ewf_75-ewf_table,ewf_76-ewf_table,ewf_77-ewf_table + .short ewferr-ewf_table,ewf_79-ewf_table,ewferr-ewf_table,ewf_7b-ewf_table + .short ewferr-ewf_table,ewf_7d-ewf_table,ewferr-ewf_table,ewf_7f-ewf_table + .short ewf_80-ewf_table,ewf_81-ewf_table,ewf_82-ewf_table,ewf_83-ewf_table + .short ewf_84-ewf_table,ewf_85-ewf_table,ewf_86-ewf_table,ewf_87-ewf_table + .short ewferr-ewf_table,ewf_89-ewf_table,ewferr-ewf_table,ewf_8b-ewf_table + .short ewferr-ewf_table,ewf_8d-ewf_table,ewferr-ewf_table,ewf_8f-ewf_table + .short ewf_90-ewf_table,ewf_91-ewf_table,ewf_92-ewf_table,ewf_93-ewf_table + .short ewf_94-ewf_table,ewf_95-ewf_table,ewf_96-ewf_table,ewf_97-ewf_table + .short ewferr-ewf_table,ewf_99-ewf_table,ewferr-ewf_table,ewf_9b-ewf_table + .short ewferr-ewf_table,ewf_9d-ewf_table,ewferr-ewf_table,ewf_9f-ewf_table + .short ewf_a0-ewf_table,ewf_a1-ewf_table,ewf_a2-ewf_table,ewf_a3-ewf_table + .short ewf_a4-ewf_table,ewf_a5-ewf_table,ewf_a6-ewf_table,ewf_a7-ewf_table + .short ewferr-ewf_table,ewf_a9-ewf_table,ewferr-ewf_table,ewf_ab-ewf_table + .short ewferr-ewf_table,ewf_ad-ewf_table,ewferr-ewf_table,ewf_af-ewf_table + .short ewf_b0-ewf_table,ewf_b1-ewf_table,ewf_b2-ewf_table,ewf_b3-ewf_table + .short ewf_b4-ewf_table,ewf_b5-ewf_table,ewf_b6-ewf_table,ewf_b7-ewf_table + .short ewferr-ewf_table,ewf_b9-ewf_table,ewferr-ewf_table,ewf_bb-ewf_table + .short ewferr-ewf_table,ewf_bd-ewf_table,ewferr-ewf_table,ewf_bf-ewf_table + .short ewf_c0-ewf_table,ewf_c1-ewf_table,ewf_c2-ewf_table,ewf_c3-ewf_table + .short ewf_c4-ewf_table,ewf_c5-ewf_table,ewf_c6-ewf_table,ewf_c7-ewf_table + .short ewferr-ewf_table,ewf_c9-ewf_table,ewferr-ewf_table,ewf_cb-ewf_table + .short ewferr-ewf_table,ewf_cd-ewf_table,ewferr-ewf_table,ewf_cf-ewf_table + .short ewf_d0-ewf_table,ewf_d1-ewf_table,ewf_d2-ewf_table,ewf_d3-ewf_table + .short ewf_d4-ewf_table,ewf_d5-ewf_table,ewf_d6-ewf_table,ewf_d7-ewf_table + .short ewferr-ewf_table,ewf_d9-ewf_table,ewferr-ewf_table,ewf_db-ewf_table + .short ewferr-ewf_table,ewf_dd-ewf_table,ewferr-ewf_table,ewf_df-ewf_table + .short ewf_e0-ewf_table,ewf_e1-ewf_table,ewf_e2-ewf_table,ewf_e3-ewf_table + .short ewf_e4-ewf_table,ewf_e5-ewf_table,ewf_e6-ewf_table,ewf_e7-ewf_table + .short ewferr-ewf_table,ewf_e9-ewf_table,ewferr-ewf_table,ewf_eb-ewf_table + .short ewferr-ewf_table,ewf_ed-ewf_table,ewferr-ewf_table,ewf_ef-ewf_table + .short ewf_f0-ewf_table,ewf_f1-ewf_table,ewf_f2-ewf_table,ewf_f3-ewf_table + .short ewf_f4-ewf_table,ewf_f5-ewf_table,ewf_f6-ewf_table,ewf_f7-ewf_table + .short ewferr-ewf_table,ewf_f9-ewf_table,ewferr-ewf_table,ewf_fb-ewf_table + .short ewferr-ewf_table,ewf_fd-ewf_table,ewferr-ewf_table,ewf_ff-ewf_table +//d0.w * 1 +ewf_00: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_01: + mvs.w d0_off+6(a7),d0 + bra ewf_full +//d0.w * 2 +ewf_02: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_03: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d0.w * 4 +ewf_04: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_05: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d0.w * 8 +ewf_06: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_07: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 1 +ewf_09: + move.l d0_off+4(a7),d0 + bra ewf_full +//d0.l * 2 +ewf_0b: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 4 +ewf_0d: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 8 +ewf_0f: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 1 +ewf_10: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_11: + mvs.w d1_off+6(a7),d0 + bra ewf_full +//d1.w * 2 +ewf_12: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_13: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 4 +ewf_14: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_15: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 8 +ewf_16: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_17: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 1 +ewf_19: + move.l d1_off+4(a7),d0 + bra ewf_full +//d1.l * 2 +ewf_1b: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 4 +ewf_1d: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 8 +ewf_1f: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 1 +ewf_20: + mvs.b (a0)+,d1 + mvs.w d2,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_21: + mvs.w d2,d0 + bra ewf_full +//d2.w * 2 +ewf_22: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_23: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 4 +ewf_24: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_25: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 8 +ewf_26: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_27: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 1 +ewf_29: + move.l d2,d0 + bra ewf_full +//d2.l * 2 +ewf_2b: + move.l d2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 4 +ewf_2d: + move.l d2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 8 +ewf_2f: + move.l d2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 1 +ewf_30: + mvs.b (a0)+,d1 + mvs.w d3,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_31: + mvs.w d3,d0 + bra ewf_full +//d3.w * 2 +ewf_32: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_33: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 4 +ewf_34: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_35: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 8 +ewf_36: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_37: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 1 +ewf_39: + move.l d3,d0 + bra ewf_full +//d3.l * 3 +ewf_3b: + move.l d3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 4 +ewf_3d: + move.l d3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 8 +ewf_3f: + move.l d3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 1 +ewf_40: + mvs.b (a0)+,d1 + mvs.w d4,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_41: + mvs.w d4,d0 + bra ewf_full +//d4.w * 2 +ewf_42: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_43: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 4 +ewf_44: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_45: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 8 +ewf_46: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_47: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 1 +ewf_49: + move.l d4,d0 + bra ewf_full +//d4.l * 4 +ewf_4b: + move.l d4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 4 +ewf_4d: + move.l d4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 8 +ewf_4f: + move.l d4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 1 +ewf_50: + mvs.b (a0)+,d1 + mvs.w d5,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_51: + mvs.w d5,d0 + bra ewf_full +//d5.w * 2 +ewf_52: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_53: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 4 +ewf_54: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_55: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 8 +ewf_56: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_57: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 1 +ewf_59: + move.l d5,d0 + bra ewf_full +//d5.l * 5 +ewf_5b: + move.l d5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 4 +ewf_5d: + move.l d5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 8 +ewf_5f: + move.l d5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 1 +ewf_60: + mvs.b (a0)+,d1 + mvs.w d6,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_61: + mvs.w d6,d0 + bra ewf_full +//d6.w * 2 +ewf_62: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_63: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 4 +ewf_64: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_65: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 8 +ewf_66: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_67: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 1 +ewf_69: + move.l d6,d0 + bra ewf_full +//d6.l * 6 +ewf_6b: + move.l d6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 4 +ewf_6d: + move.l d6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 8 +ewf_6f: + move.l d6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 1 +ewf_70: + mvs.b (a0)+,d1 + mvs.w d7,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_71: + mvs.w d7,d0 + bra ewf_full +//d7.w * 2 +ewf_72: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_73: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 4 +ewf_74: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_75: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 8 +ewf_76: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_77: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 1 +ewf_79: + move.l d7,d0 + bra ewf_full +//d7.l * 7 +ewf_7b: + move.l d7,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 4 +ewf_7d: + move.l d7,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 8 +ewf_7f: + move.l d7,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 1 +ewf_80: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_81: + mvs.w a0_off+6(a7),d0 + bra ewf_full +//a0.w * 2 +ewf_82: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_83: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 4 +ewf_84: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_85: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 8 +ewf_86: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_87: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 1 +ewf_89: + move.l a0_off+4(a7),d0 + bra ewf_full +//a0.l * 2 +ewf_8b: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 4 +ewf_8d: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 8 +ewf_8f: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 1 +ewf_90: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_91: + mvs.w a1_off+6(a7),d0 + bra ewf_full +//a1.w * 2 +ewf_92: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_93: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 4 +ewf_94: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_95: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 8 +ewf_96: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_97: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 1 +ewf_99: + move.l a1_off+4(a7),d0 + bra ewf_full +//a1.l * 2 +ewf_9b: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 4 +ewf_9d: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 8 +ewf_9f: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 1 +ewf_a0: + mvs.b (a0)+,d1 + mvs.w a2,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_a1: + mvs.w a2,d0 + bra ewf_full +//a2.w * 2 +ewf_a2: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_a3: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 4 +ewf_a4: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_a5: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 8 +ewf_a6: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_a7: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 1 +ewf_a9: + move.l a2,d0 + bra ewf_full +//a2.l * 2 +ewf_ab: + move.l a2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 4 +ewf_ad: + move.l a2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 8 +ewf_af: + move.l a2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 1 +ewf_b0: + mvs.b (a0)+,d1 + mvs.w a3,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_b1: + mvs.w a3,d0 + bra ewf_full +//a3.w * 2 +ewf_b2: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_b3: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 4 +ewf_b4: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_b5: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 8 +ewf_b6: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_b7: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 1 +ewf_b9: + move.l a3,d0 + bra ewf_full +//a3.l * 3 +ewf_bb: + move.l a3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 4 +ewf_bd: + move.l a3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 8 +ewf_bf: + move.l a3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 1 +ewf_c0: + mvs.b (a0)+,d1 + mvs.w a4,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_c1: + mvs.w a4,d0 + bra ewf_full +//a4.w * 2 +ewf_c2: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_c3: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 4 +ewf_c4: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_c5: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 8 +ewf_c6: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_c7: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 1 +ewf_c9: + move.l a4,d0 + bra ewf_full +//a4.l * 4 +ewf_cb: + move.l a4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 4 +ewf_cd: + move.l a4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 8 +ewf_cf: + move.l a4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 1 +ewf_d0: + mvs.b (a0)+,d1 + mvs.w a5,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_d1: + mvs.w a5,d0 + bra ewf_full +//a5.w * 2 +ewf_d2: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_d3: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 4 +ewf_d4: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_d5: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 8 +ewf_d6: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_d7: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 1 +ewf_d9: + move.l a5,d0 + bra ewf_full +//a5.l * 5 +ewf_db: + move.l a5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 4 +ewf_dd: + move.l a5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 8 +ewf_df: + move.l a5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 1 +ewf_e0: + mvs.b (a0)+,d1 + mvs.w a6,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_e1: + mvs.w a6,d0 + bra ewf_full +//a6.w * 2 +ewf_e2: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_e3: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 4 +ewf_e4: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_e5: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 8 +ewf_e6: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_e7: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 1 +ewf_e9: + move.l a6,d0 + bra ewf_full +//a6.l * 6 +ewf_eb: + move.l a6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 4 +ewf_ed: + move.l a6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 8 +ewf_ef: + move.l a6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 1 +ewf_f0: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + add.l d1,a1 + rts +ewf_f1: + move.l a1,-(a7) + move.l usp,a1 + mvs.w a1,d0 + move.l (a7)+,a1 + bra ewf_full +//usp.w * 2 +ewf_f2: + mvs.b (a0)+,d1 + move.l usp,a1 + mvs.w a1,d0 + move.l (a7)+,a1 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_f3: + move.l usp,a1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 4 +ewf_f4: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_f5: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 8 +ewf_f6: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_f7: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 1 +ewf_f9: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + bra ewf_full +//usp.l * 7 +ewf_fb: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 4 +ewf_fd: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 8 +ewf_ff: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//----------------------------------------------------------------------------------- +// extension full format rest von ewf +//-------------------------------------------------------------------- +ewf_full: + mvz.b (a0)+,d1 + mvs.w ewff_table-.-2(pc,d1*2),d1 + jmp ewff_table-.-2(pc,d1) +ewff_table: + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //00 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //10 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsw-ewff_table,ewff_w0v-ewff_table,ewff_wwv-ewff_table,ewff_wlv-ewff_table //20 + .short ewff_end-ewff_table,ewff_w0n-ewff_table,ewff_wwn-ewff_table,ewff_wln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsl-ewff_table,ewff_l0v-ewff_table,ewff_lwv-ewff_table,ewff_llv-ewff_table //30 + .short ewff_end-ewff_table,ewff_l0n-ewff_table,ewff_lwn-ewff_table,ewff_lln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //40 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //50 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsw-ewff_table,ewff_wi0-ewff_table,ewff_wiw-ewff_table,ewff_wil-ewff_table //60 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsl-ewff_table,ewff_li0-ewff_table,ewff_liw-ewff_table,ewff_lil-ewff_table //70 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //80 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //90 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //a0 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //b0 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //c0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //d0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //e0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //f0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table +ewff_end: + rts +ewff_bsw: + mvs.w (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_bsl: + move.l (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_i0v: + add.l d0,a1 + move.l (a1),a1 + rts +ewff_iwv: + add.l d0,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_ilv: + add.l d0,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_i0n: + move.l (a1),a1 + add.l d0,a1 + rts +ewff_iwn: + move.l (a1),a1 + add.l d0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_iln: + move.l (a1),a1 + add.l d0,a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_mi0: + add.l d0,a1 + rts +ewff_miw: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_mil: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_wi0: + mvs.w (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_wiw: + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_wil: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_li0: + move.l (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_liw: + move.l (a0)+,d1 + add.l d1,a1 + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_lil: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_w0v: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + rts +ewff_wwv: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_wlv: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_l0v: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + rts +ewff_lwv: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_llv: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_w0n: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + add.l d0,a1 + rts +ewff_wwn: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_wln: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_l0n: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + add.l d0,a1 + rts +ewff_lwn: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_lln: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts + + diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S index 343037b..9c2120a 100644 --- a/BaS_GNU/sources/exceptions.S +++ b/BaS_GNU/sources/exceptions.S @@ -182,10 +182,9 @@ irq_end: addq.l #8,a7 rte // und weg .endm -/*********************************************************/ /* - * FIXME: ugly, but I just can't come up with any smarter solution + * FIXME: this is a GNU gas kludge. Ugly, but I just can't come up with any smarter solution * * GNU as does not support multi-character constants. At least I don't know of any way it would. * The following might look more than strange, but I considered the statement From dfe88156e160b4b57c8096b8a6b53cb313e20efa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 07:36:44 +0000 Subject: [PATCH 043/276] --- BaS_GNU/sources/ii_add.h | 581 +++++++++++++++++ BaS_GNU/sources/ii_and.h | 441 +++++++++++++ BaS_GNU/sources/ii_dbcc.h | 117 ++++ BaS_GNU/sources/ii_ewf.h | 181 +++++ BaS_GNU/sources/ii_exg.h | 120 ++++ BaS_GNU/sources/ii_func.h | 945 +++++++++++++++++++++++++++ BaS_GNU/sources/ii_jmp.h | 59 ++ BaS_GNU/sources/ii_lea.h | 105 +++ BaS_GNU/sources/ii_macro.h | 144 ++++ BaS_GNU/sources/ii_move.h | 1270 ++++++++++++++++++++++++++++++++++++ BaS_GNU/sources/ii_movem.h | 374 +++++++++++ BaS_GNU/sources/ii_movep.h | 179 +++++ BaS_GNU/sources/ii_op.h | 661 +++++++++++++++++++ BaS_GNU/sources/ii_opc.h | 263 ++++++++ 14 files changed, 5440 insertions(+) create mode 100644 BaS_GNU/sources/ii_add.h create mode 100644 BaS_GNU/sources/ii_and.h create mode 100644 BaS_GNU/sources/ii_dbcc.h create mode 100644 BaS_GNU/sources/ii_ewf.h create mode 100644 BaS_GNU/sources/ii_exg.h create mode 100644 BaS_GNU/sources/ii_func.h create mode 100644 BaS_GNU/sources/ii_jmp.h create mode 100644 BaS_GNU/sources/ii_lea.h create mode 100644 BaS_GNU/sources/ii_macro.h create mode 100644 BaS_GNU/sources/ii_move.h create mode 100644 BaS_GNU/sources/ii_movem.h create mode 100644 BaS_GNU/sources/ii_movep.h create mode 100644 BaS_GNU/sources/ii_op.h create mode 100644 BaS_GNU/sources/ii_opc.h diff --git a/BaS_GNU/sources/ii_add.h b/BaS_GNU/sources/ii_add.h new file mode 100644 index 0000000..bc23f63 --- /dev/null +++ b/BaS_GNU/sources/ii_add.h @@ -0,0 +1,581 @@ +//-------------------------------------------------------------------- +// add +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// add.b #im,dx +//-------------------------------------------------------------------- +addbir_macro:.macro + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + add.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add ea,dx +//-------------------------------------------------------------------- +adddd:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add ea,dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddd:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add (ea),dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +adddda:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add (ay)+,dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddai:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add -(ay),dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d16(ay),dx +//-------------------------------------------------------------------- +addd16ad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d8(ay,dy),dx +//-------------------------------------------------------------------- +addd8ad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add xxx.w,dx +//-------------------------------------------------------------------- +addxwd:.macro +#ifdef halten_add + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add xxx.l,dx +//-------------------------------------------------------------------- +addxld:.macro +#ifdef halten_add + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d16(pc),dx +//-------------------------------------------------------------------- +addd16pcd:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d8(pc,dy),dx +//-------------------------------------------------------------------- +addd8pcd:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// add dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // add dx,(ay) (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addeda:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,(ay)+ (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addedai:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,(ay)+ +//-------------------------------------------------------------------- +addedaid:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,-(ay) +//-------------------------------------------------------------------- +addedad:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,-(ay) +//-------------------------------------------------------------------- +addedadd:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,d16(ay) +//-------------------------------------------------------------------- +adde16ad:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add.w d8(ay,dy),dx +//-------------------------------------------------------------------- +adde8ad:.macro +#ifdef halten_add + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,xxx.w +//-------------------------------------------------------------------- +addxwe:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,xxx.l +//-------------------------------------------------------------------- +addxle:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// // adda.w ea,ax (ea = dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addaw:.macro +#ifdef halten_add + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + mvs.w \1,d0 + adda.l d0,\2 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// add.w ea,usp +//-------------------------------------------------------------------- +addawa7:.macro +#ifdef halten_add + halt +#endif + mvs.w \1,d0 + move.l usp,a1 + add.l d0,a1 + move.l a1,usp + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w ea,usp (ea = dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addawu:.macro +#ifdef halten_add + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + move.l a7,_a7_save + move.l usp,a7 + move.l \1,d0 + adda.l d0,\2 + move.l a7,usp + move.l _a7_save,a7 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// // adda.w ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addawua7:.macro + addawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // adda.w d16(ay),ax +//-------------------------------------------------------------------- +addawd16a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + adda.l d0,a1 + mvs.w (a1),d0 + move.l \2,a1 + add.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d8(ay,dy),ax +//-------------------------------------------------------------------- +addawd8a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + add.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w xxx.w,ax +//-------------------------------------------------------------------- +addawxwax:.macro +#ifdef halten_add + halt +#endif + move.w \1,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w xxx.l,ax +//-------------------------------------------------------------------- +addawxlax:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d16(pc),ax +//-------------------------------------------------------------------- +addawd16pcax:.macro +#ifdef halten_add + halt +#endif + move.w \1,a1 + adda.l a0,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d8(pc,dy),ax +//-------------------------------------------------------------------- +addawd8pcax:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w #im,ax +//-------------------------------------------------------------------- +addawim:.macro +#ifdef halten_add + halt +#endif + mvs.w \1,d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.l d8(ay,dy),ax +//-------------------------------------------------------------------- +addald8a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.l d8(pc,dy),ax +//-------------------------------------------------------------------- +addakd8pcax:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//***************************************************************************************** +// addx +//***************************************************************************************** +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +adddx:.macro +#ifdef halten_add + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + mvs.\3 \2,d0 + mvs.\3 \1,d1 + addx.l d0,d1 + set_cc0 + move.\3 d1,\1 + ii_end + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +adddax:.macro +#ifdef halten_add + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + move.l \1,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d0 +.endif + move.l \2,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d1 +.endif + addx.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_and.h b/BaS_GNU/sources/ii_and.h new file mode 100644 index 0000000..f74afde --- /dev/null +++ b/BaS_GNU/sources/ii_and.h @@ -0,0 +1,441 @@ +//-------------------------------------------------------------------- +// and +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// and.b #im,dx +//-------------------------------------------------------------------- +andbir_macro:.macro + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + and.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea,dx +//-------------------------------------------------------------------- +anddd:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +andddd:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and (ea)->dy,dx +//-------------------------------------------------------------------- +anddda:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +andddai:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea->ay,-(ay),dx +//-------------------------------------------------------------------- +andddad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d16(ay),dx +//-------------------------------------------------------------------- +andd16ad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d8(ay,dy),dx +//-------------------------------------------------------------------- +andd8ad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and xxx.w,dx +//-------------------------------------------------------------------- +andxwd:.macro +#ifdef halten_and + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and xxx.l,dx +//-------------------------------------------------------------------- +andxld:.macro +#ifdef halten_and + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d16(pc),dx +//-------------------------------------------------------------------- +andd16pcd:.macro +#ifdef halten_and + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d8(pc,dy),dx +//-------------------------------------------------------------------- +andd8pcd:.macro +#ifdef halten_and + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// and dx,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // and dx,(ea)->dy +//-------------------------------------------------------------------- +andeda:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +andedai:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +andedaid:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +andedad:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +andedadd:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,d16(ay) +//-------------------------------------------------------------------- +ande16ad:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and.w dx,d8(ay,dy) +//-------------------------------------------------------------------- +ande8ad:.macro +#ifdef halten_and + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,xxx.w +//-------------------------------------------------------------------- +andxwe:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,xxx.l +//-------------------------------------------------------------------- +andxle:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // anda.w ea,ax +//-------------------------------------------------------------------- +andaw:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// and.w ea,usp +//-------------------------------------------------------------------- +andawa7:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w usp?,ax +//-------------------------------------------------------------------- +andawu:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w usp?,usp +//-------------------------------------------------------------------- +andawua7:.macro + andawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // anda.w d16(ay),ax +//-------------------------------------------------------------------- +andawd16a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d8(ay,dy),ax +//-------------------------------------------------------------------- +andawd8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w xxx.w,ax +//-------------------------------------------------------------------- +andawxwax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w xxx.l,ax +//-------------------------------------------------------------------- +andawxlax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d16(pc),ax +//-------------------------------------------------------------------- +andawd16pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d8(pc,dy),ax +//-------------------------------------------------------------------- +andawd8pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w #im,ax +//-------------------------------------------------------------------- +andawim:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.l d8(ay,dy),ax +//-------------------------------------------------------------------- +andald8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.l d8(pc,dy),ax +//-------------------------------------------------------------------- +andald8pcax:.macro + jmp ii_error + .endm; +//***************************************************************************************** +// spezial addx subx etc. +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +anddx:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +anddax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_GNU/sources/ii_dbcc.h b/BaS_GNU/sources/ii_dbcc.h new file mode 100644 index 0000000..652cdbe --- /dev/null +++ b/BaS_GNU/sources/ii_dbcc.h @@ -0,0 +1,117 @@ +//-------------------------------------------------------------------- +// dbcc,trapcc +//-------------------------------------------------------------------- +.text +ii_lset_dbcc:.macro +// dbra + ii_lset_opeau 51,c + ii_lset_opeau 52,c + ii_lset_opeau 53,c + ii_lset_opeau 54,c + ii_lset_opeau 55,c + ii_lset_opeau 56,c + ii_lset_opeau 57,c + ii_lset_opeau 58,c + ii_lset_opeau 59,c + ii_lset_opeau 5a,c + ii_lset_opeau 5b,c + ii_lset_opeau 5c,c + ii_lset_opeau 5d,c + ii_lset_opeau 5e,c + ii_lset_opeau 5f,c +.endm + +ii_dbcc_func:.macro +ii_0x51c8: + dbra_macro d0_off+2(a7) +ii_0x51c9: + dbra_macro d1_off+2(a7) +ii_0x51ca: + dbra_macro d2 +ii_0x51cb: + dbra_macro d3 +ii_0x51cc: + dbra_macro d4 +ii_0x51cd: + dbra_macro d5 +ii_0x51ce: + dbra_macro d6 +ii_0x51cf: + dbra_macro d7 +//--------------------------------------------------------------------------------------------- +// dbcc dx +//--------------------------------------------------------------------------------------------- + ii_dbcc 2,hi + ii_dbcc 3,ls + ii_dbcc 4,cc + ii_dbcc 5,cs + ii_dbcc 6,ne + ii_dbcc 7,eq + ii_dbcc 8,vc + ii_dbcc 9,vs + ii_dbcc a,pl + ii_dbcc b,mi + ii_dbcc c,ge + ii_dbcc d,lt + ii_dbcc e,gt + ii_dbcc f,le +.endm +//--------------------------------------------------------------------------------------------- +// dbra dx +//--------------------------------------------------------------------------------------------- +dbra_macro:.macro +#ifdef halten_dbcc + halt +#endif + mvz.w \1,d1 // dx holen + subq.l #1,d1 // dx-1 + bcc dbra\@ // bra if plus? + addq.l #2,a0 // offset überspringen + move.w d1,\1 // dx sichern + ii_end +dbra\@: + move.w (a0),a1 // offset (wird auf long erweitert) + add.l a1,a0 // dazuadieren + move.w d1,\1 // dx sichern + ii_end +.endm +//--------------------------------------------------------------------------------------------- +// dbcc dx +//--------------------------------------------------------------------------------------------- +dbcc_macro:.macro +#ifdef halten_dbcc + halt +#endif + b\2 dbncc\@ + mvz.w \1,d1 // dx holen + subq.l #1,d1 // dx-1 + bcc dbcc\@ // bra if plus? +dbncc\@: + addq.l #2,a0 // offset überspringen + move.w d1,\1 // dx sichern + ii_end +dbcc\@: + move.w (a0),a1 // offset (wird auf long erweitert) + add.l a1,a0 // dazuadieren + move.w d1,\1 // dx sichern + ii_end +.endm +//db +ii_dbcc:.macro +ii_0x5\1c8: + dbcc_macro d0_off+2(a7),\2 +ii_0x5\1c9: + dbcc_macro d1_off+2(a7),\2 +ii_0x5\1ca: + dbcc_macro d2,\2 +ii_0x5\1cb: + dbcc_macro d3,\2 +ii_0x5\1cc: + dbcc_macro d4,\2 +ii_0x5\1cd: + dbcc_macro d5,\2 +ii_0x5\1ce: + dbcc_macro d6,\2 +ii_0x5\1cf: + dbcc_macro d7,\2 +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_ewf.h b/BaS_GNU/sources/ii_ewf.h new file mode 100644 index 0000000..34d2483 --- /dev/null +++ b/BaS_GNU/sources/ii_ewf.h @@ -0,0 +1,181 @@ +//-------------------------------------------------------------------- +// extension word format missing +//-------------------------------------------------------------------- +.text +ii_ewf_lset:.macro +// pea + ii_lset_opeag 48,7 + ii_lset 0x487b +// jmp + ii_lset_opeag 4e,f + ii_lset 0x4efb +// jsr + ii_lset_opeag 4e,b + ii_lset 0x4ebb +// tas + ii_lset_opeag 4a,f + ii_lset 0x4ebb +// tst.b + ii_lset_opeag 4a,3 + ii_lset 0x4ebb +// tst.w + ii_lset_opeag 4a,7 + ii_lset 0x4ebb +// tst.l + ii_lset_opeag 4a,b + ii_lset 0x4ebb +// clr.b + ii_lset_opeag 42,3 + ii_lset 0x423b +// clr.w + ii_lset_opeag 42,7 + ii_lset 0x423b +// clr.l + ii_lset_opeag 42,b + ii_lset 0x423b +.endm +//--------------------------------------------------------------------------------------------- +ii_ewf_func:.macro + ewf_func_macro pea,487 + ewf_func_macro jmp,4ef + ewf_func_macro jsr,4eb + ewf_func_macro tas,4af + ewf_func_macro tstb,4a3 + ewf_func_macro tstw,4a7 + ewf_func_macro tstl,4ab + ewf_func_macro clrb,423 + ewf_func_macro clrw,427 + ewf_func_macro clrl,42b +.endm +//--------------------------------------------------------------------------------------------- +pea_macro:.macro + jsr ewf + move.l (a1),d0 + move.l usp,a1 + move.l d0,-(a1) + move.l a1,usp + ii_end +.endm + +jmp_macro:.macro + jsr ewf + move.l a1,a0 + ii_end +.endm + +jsr_macro:.macro + jsr ewf + move.l a1,d0 + move.l usp,a1 + move.l a0,-(a1) + move.l a1,usp + move.l d0,a0 + ii_end +.endm + +tas_macro:.macro + jsr ewf + tas (a1) + set_cc0 + ii_end +.endm + +tstb_macro:.macro + jsr ewf + tst.b (a1) + set_cc0 + ii_end +.endm + +tstw_macro:.macro + jsr ewf + tst.w (a1) + set_cc0 + ii_end +.endm + +tstl_macro:.macro + jsr ewf + tst.l (a1) + set_cc0 + ii_end +.endm + +clrb_macro:.macro + jsr ewf + clr.b (a1) + set_cc0 + ii_end +.endm + +clrw_macro:.macro + jsr ewf + clr.w (a1) + set_cc0 + ii_end +.endm + +clrl_macro:.macro + jsr ewf + clr.l (a1) + set_cc0 + ii_end +.endm +//-------------------------------------------------------------------- +ewf_func_macro:.macro //1=art 2=code +ii_0x\20: +#ifdef halten_ewf + halt +#endif + move.l a0_off(a7),a1 + \1_macro +ii_0x\21: +#ifdef halten_ewf + halt +#endif + move.l a1_off(a7),a1 + \1_macro +ii_0x\22: +#ifdef halten_ewf + halt +#endif + move.l a2,a1 + \1_macro +ii_0x\23: +#ifdef halten_ewf + halt +#endif + move.l a3,a1 + \1_macro +ii_0x\24: +#ifdef halten_ewf + halt +#endif + move.l a4,a1 + \1_macro +ii_0x\25: +#ifdef halten_ewf + halt +#endif + move.l a5,a1 + \1_macro +ii_0x\26: +#ifdef halten_ewf + halt +#endif + move.l a6,a1 + \1_macro +ii_0x\27: +#ifdef halten_ewf + halt +#endif + move.l usp,a1 + \1_macro +ii_0x\2b: +#ifdef halten_ewf + halt +#endif + move.l a0,a1 + \1_macro +.endm + diff --git a/BaS_GNU/sources/ii_exg.h b/BaS_GNU/sources/ii_exg.h new file mode 100644 index 0000000..a0544af --- /dev/null +++ b/BaS_GNU/sources/ii_exg.h @@ -0,0 +1,120 @@ +//-------------------------------------------------------------------- +// exg +//-------------------------------------------------------------------- +.text +ii_exg_lset:.macro +/* ii_lset_dxu c,40 //dx,d0 + ii_lset_dxu c,41 //dx,d1 + ii_lset_dxu c,42 //dx,d2 + ii_lset_dxu c,43 //dx,d3 + ii_lset_dxu c,44 //dx,d4 + ii_lset_dxu c,45 //dx,d5 + ii_lset_dxu c,46 //dx,d6 + ii_lset_dxu c,47 //dx,d7 + ii_lset_dxu c,48 //ax,a0 + ii_lset_dxu c,49 //ax,a1 + ii_lset_dxu c,4a //ax,a2 + ii_lset_dxu c,4b //ax,a3 + ii_lset_dxu c,4c //ax,a4 + ii_lset_dxu c,4d //ax,a5 + ii_lset_dxu c,4e //ax,a6 + ii_lset_dxu c,4f //ax,a7 */ -->setting by "and" + ii_lset_dxu c,88 //dx,a0 + ii_lset_dxu c,89 //dx,a1 + ii_lset_dxu c,8a //dx,a2 + ii_lset_dxu c,8b //dx,a3 + ii_lset_dxu c,8c //dx,a4 + ii_lset_dxu c,8d //dx,a5 + ii_lset_dxu c,8e //dx,a6 + ii_lset_dxu c,8f //dx,a7 +.endm +//--------------------------------------------------------------------------------------------- +ii_exg_func:.macro +// exg dx,dy + ii_exg_dx_dx 14,d0_off(a7) + ii_exg_dx_dx 34,d1_off(a7) + ii_exg_dx_dx 54,d2 + ii_exg_dx_dx 74,d3 + ii_exg_dx_dx 94,d4 + ii_exg_dx_dx b4,d5 + ii_exg_dx_dx d4,d6 + ii_exg_dx_dx f4,d7 +// exg ax,ay + ii_exg_to_ax 14,a0_off(a7) + ii_exg_to_ax 34,a1_off(a7) + ii_exg_to_ax 54,a2 + ii_exg_to_ax 74,a3 + ii_exg_to_ax 94,a4 + ii_exg_to_ax b4,a5 + ii_exg_to_ax d4,a6 + ii_exg_to_ax f4,usp +// exg dx,ay + ii_exg_to_ax 18,d0_off(a7) + ii_exg_to_ax 38,d1_off(a7) + ii_exg_to_ax 58,d2 + ii_exg_to_ax 78,d3 + ii_exg_to_ax 98,d4 + ii_exg_to_ax b8,d5 + ii_exg_to_ax d8,d6 + ii_exg_to_ax f8,d7 +.endm +//--------------------------------------------------------------------------------------------- +exg_macro:.macro +#ifdef halten_exg + halt +#endif + move.l \1,a1 +.ifc \2,usp + move.l a1,d0 + move.l \2,a1 + move.l a1,\1 + move.l d0,a1 +.else + .ifc \1,usp + move.l a1,d0 + move.l \2,a1 + move.l a1,\1 + move.l d0,a1 + .else + move.l \2,\1 + .endif +.endif + move.l a1,\2 + ii_end +.endm +ii_exg_dx_dx:.macro +ii_0xc\10: + exg_macro \2,d0_off(a7) +ii_0xc\11: + exg_macro \2,d1_off(a7) +ii_0xc\12: + exg_macro \2,d2 +ii_0xc\13: + exg_macro \2,d3 +ii_0xc\14: + exg_macro \2,d4 +ii_0xc\15: + exg_macro \2,d5 +ii_0xc\16: + exg_macro \2,d6 +ii_0xc\17: + exg_macro \2,d7 +.endm +ii_exg_to_ax:.macro +ii_0xc\18: + exg_macro \2,a0_off(a7) +ii_0xc\19: + exg_macro \2,a1_off(a7) +ii_0xc\1a: + exg_macro \2,a2 +ii_0xc\1b: + exg_macro \2,a3 +ii_0xc\1c: + exg_macro \2,a4 +ii_0xc\1d: + exg_macro \2,a5 +ii_0xc\1e: + exg_macro \2,a6 +ii_0xc\1f: + exg_macro \2,usp +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_func.h b/BaS_GNU/sources/ii_func.h new file mode 100644 index 0000000..f545f47 --- /dev/null +++ b/BaS_GNU/sources/ii_func.h @@ -0,0 +1,945 @@ +//-------------------------------------------------------------------- +// functionen macros +//-------------------------------------------------------------------- +ii_lset_func:.macro +/******************************************************/ +// byt +/******************************************************/ +// func.b dy,dx + ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,01 + ii_lset_dx \1,02 + ii_lset_dx \1,03 + ii_lset_dx \1,04 + ii_lset_dx \1,05 + ii_lset_dx \1,06 + ii_lset_dx \1,07 +// func.b ax,dx + ii_lset_dxu \1,08 + ii_lset_dxu \1,09 + ii_lset_dxu \1,0a + ii_lset_dxu \1,0b + ii_lset_dxu \1,0c + ii_lset_dxu \1,0d + ii_lset_dxu \1,0e + ii_lset_dxu \1,0f +// func.b (ax),dx + ii_lset_dx \1,10 + ii_lset_dx \1,11 + ii_lset_dx \1,12 + ii_lset_dx \1,13 + ii_lset_dx \1,14 + ii_lset_dx \1,15 + ii_lset_dx \1,16 + ii_lset_dx \1,17 +// func.b (ax)+,dx + ii_lset_dx \1,18 + ii_lset_dx \1,19 + ii_lset_dx \1,1a + ii_lset_dx \1,1b + ii_lset_dx \1,1c + ii_lset_dx \1,1d + ii_lset_dx \1,1e + ii_lset_dx \1,1f +// func.b -(ax),dx + ii_lset_dx \1,20 + ii_lset_dx \1,21 + ii_lset_dx \1,22 + ii_lset_dx \1,23 + ii_lset_dx \1,24 + ii_lset_dx \1,25 + ii_lset_dx \1,26 + ii_lset_dx \1,27 +// func.b d16(ax),dx + ii_lset_dx \1,28 + ii_lset_dx \1,29 + ii_lset_dx \1,2a + ii_lset_dx \1,2b + ii_lset_dx \1,2c + ii_lset_dx \1,2d + ii_lset_dx \1,2e + ii_lset_dx \1,2f +// func.b dd8(ax,dy),dx + ii_lset_dx \1,30 + ii_lset_dx \1,31 + ii_lset_dx \1,32 + ii_lset_dx \1,33 + ii_lset_dx \1,34 + ii_lset_dx \1,35 + ii_lset_dx \1,36 + ii_lset_dx \1,37 +// func.b xxx.w,dx + ii_lset_dx \1,38 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b xxx.l,dx + ii_lset_dx \1,39 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b d16(pc),dx + ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b d8(pc,dy),dx + ii_lset_dxg \1,3b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b #im,dx + ii_lset_dxg \1,3c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// word +/******************************************************/ +// func.w dy,dx + ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,41 + ii_lset_dx \1,42 + ii_lset_dx \1,43 + ii_lset_dx \1,44 + ii_lset_dx \1,45 + ii_lset_dx \1,46 + ii_lset_dx \1,47 +// func.w ax,dx + ii_lset_dx \1,48 + ii_lset_dx \1,49 + ii_lset_dx \1,4a + ii_lset_dx \1,4b + ii_lset_dx \1,4c + ii_lset_dx \1,4d + ii_lset_dx \1,4e + ii_lset_dx \1,4f +// func.w (ax),dx + ii_lset_dx \1,50 + ii_lset_dx \1,51 + ii_lset_dx \1,52 + ii_lset_dx \1,53 + ii_lset_dx \1,54 + ii_lset_dx \1,55 + ii_lset_dx \1,56 + ii_lset_dx \1,57 +// func.w (ax)+,dx + ii_lset_dx \1,58 + ii_lset_dx \1,59 + ii_lset_dx \1,5a + ii_lset_dx \1,5b + ii_lset_dx \1,5c + ii_lset_dx \1,5d + ii_lset_dx \1,5e + ii_lset_dx \1,5f +// func.w -(ax),dx + ii_lset_dx \1,60 + ii_lset_dx \1,61 + ii_lset_dx \1,62 + ii_lset_dx \1,63 + ii_lset_dx \1,64 + ii_lset_dx \1,65 + ii_lset_dx \1,66 + ii_lset_dx \1,67 +// func.w d16(ax),dx + ii_lset_dx \1,68 + ii_lset_dx \1,69 + ii_lset_dx \1,6a + ii_lset_dx \1,6b + ii_lset_dx \1,6c + ii_lset_dx \1,6d + ii_lset_dx \1,6e + ii_lset_dx \1,6f +// func.w d8(ax,dy),dx + ii_lset_dx \1,70 + ii_lset_dx \1,71 + ii_lset_dx \1,72 + ii_lset_dx \1,73 + ii_lset_dx \1,74 + ii_lset_dx \1,75 + ii_lset_dx \1,76 + ii_lset_dx \1,77 +// func.w xxx.w,dx + ii_lset_dx \1,78 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w xxx.l,dx + ii_lset_dx \1,79 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w d16(pc),dx + ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w d8(pc,dy),dx + ii_lset_dxg \1,7b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w #im,dx + ii_lset_dxg \1,7c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// long +/******************************************************/ +// func.l ax,dx -> -(ay),-(ax) + ii_lset_dxu \1,c8 + ii_lset_dxu \1,c9 + ii_lset_dxu \1,ca + ii_lset_dxu \1,cb + ii_lset_dxu \1,cc + ii_lset_dxu \1,cd + ii_lset_dxu \1,ce + ii_lset_dxu \1,cf +// func.w d8(ax,dy),dx + ii_lset_dx \1,b0 + ii_lset_dx \1,b1 + ii_lset_dx \1,b2 + ii_lset_dx \1,b3 + ii_lset_dx \1,b4 + ii_lset_dx \1,b5 + ii_lset_dx \1,b6 + ii_lset_dx \1,b7 +// func.l d8(pc,dy),dx + ii_lset_dxg \1,bb // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// adress register +/******************************************************/ +//func.w dy,ax + ii_lset_dxg \1,c0 + ii_lset_dxg \1,c1 + ii_lset_dxg \1,c2 + ii_lset_dxg \1,c3 + ii_lset_dxg \1,c4 + ii_lset_dxg \1,c5 + ii_lset_dxg \1,c6 + ii_lset_dxg \1,c7 +//func.w ay,ax + ii_lset_dxg \1,c8 + ii_lset_dxg \1,c9 + ii_lset_dxg \1,ca + ii_lset_dxg \1,cb + ii_lset_dxg \1,cc + ii_lset_dxg \1,cd + ii_lset_dxg \1,ce + ii_lset_dxg \1,cf +//func.w (ay),ax + ii_lset_dxg \1,d0 + ii_lset_dxg \1,d1 + ii_lset_dxg \1,d2 + ii_lset_dxg \1,d3 + ii_lset_dxg \1,d4 + ii_lset_dxg \1,d5 + ii_lset_dxg \1,d6 + ii_lset_dxg \1,d7 +//func.w (ay)+,ax + ii_lset_dxg \1,d8 + ii_lset_dxg \1,d9 + ii_lset_dxg \1,da + ii_lset_dxg \1,db + ii_lset_dxg \1,dc + ii_lset_dxg \1,dd + ii_lset_dxg \1,de + ii_lset_dxg \1,df +//func.w -(ay),ax + ii_lset_dxg \1,e0 + ii_lset_dxg \1,e1 + ii_lset_dxg \1,e2 + ii_lset_dxg \1,e3 + ii_lset_dxg \1,e4 + ii_lset_dxg \1,e5 + ii_lset_dxg \1,e6 + ii_lset_dxg \1,e7 +//func.w d16(ay),ax + ii_lset_dxg \1,e8 + ii_lset_dxg \1,e9 + ii_lset_dxg \1,ea + ii_lset_dxg \1,eb + ii_lset_dxg \1,ec + ii_lset_dxg \1,ed + ii_lset_dxg \1,ee + ii_lset_dxg \1,ef +//func.w d8(ay,dy),ax + ii_lset_dxg \1,f0 + ii_lset_dxg \1,f1 + ii_lset_dxg \1,f2 + ii_lset_dxg \1,f3 + ii_lset_dxg \1,f4 + ii_lset_dxg \1,f5 + ii_lset_dxg \1,f6 + ii_lset_dxg \1,f7 +// func.w xxx.w,ax + ii_lset_dxg \1,f8 +// func.w xxx.l,ax + ii_lset_dxg \1,f9 +// func.w d16(pc),ax + ii_lset_dxg \1,fa +// func.w d8(pc,dy),ax + ii_lset_dxg \1,fb +// func.w #im,ax + ii_lset_dxg \1,fc +//-------------------------------------------------------------------- +// ende + .endm; +/*****************************************************************************************/ +ii_func:.macro +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.b ds,dx +//-------------------------------------------------------------------- + funcbeadx \1,00,\2dd,d0_off+3(a7) + funcbeadx \1,01,\2dd,d1_off+3(a7) + funcbeadx \1,02,\2dd,d2 + funcbeadx \1,03,\2dd,d3 + funcbeadx \1,04,\2dd,d4 + funcbeadx \1,05,\2dd,d5 + funcbeadx \1,06,\2dd,d6 + funcbeadx \1,07,\2dd,d7 +//-------------------------------------------------------------------- +// func.b (ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,10,\2dda,a0_off(a7) + funcbeadx \1,11,\2dda,a1_off(a7) + funcbeadx \1,12,\2dd,(a2) + funcbeadx \1,13,\2dd,(a3) + funcbeadx \1,14,\2dd,(a4) + funcbeadx \1,15,\2dd,(a5) + funcbeadx \1,16,\2dd,(a6) + funcbeadx \1,17,\2dda,usp +//-------------------------------------------------------------------- +// func.b (ax)+,dx +//-------------------------------------------------------------------- + funcbeadx \1,18,\2ddai,a0_off(a7) + funcbeadx \1,19,\2ddai,a1_off(a7) + funcbeadx \1,1a,\2dd,(a2)+ + funcbeadx \1,1b,\2dd,(a3)+ + funcbeadx \1,1c,\2dd,(a4)+ + funcbeadx \1,1d,\2dd,(a5)+ + funcbeadx \1,1e,\2dd,(a6)+ + funcbeadx \1,1f,\2ddai,usp +//-------------------------------------------------------------------- +// func.b -(ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,20,\2ddad,a0_off(a7) + funcbeadx \1,21,\2ddad,a1_off(a7) + funcbeadx \1,22,\2dd,-(a2) + funcbeadx \1,23,\2dd,-(a3) + funcbeadx \1,24,\2dd,-(a4) + funcbeadx \1,25,\2dd,-(a5) + funcbeadx \1,26,\2dd,-(a6) + funcbeadx \1,27,\2ddad,usp +//-------------------------------------------------------------------- +// func.b d16(ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,28,\2d16ad,a0_off(a7) + funcbeadx \1,29,\2d16ad,a1_off(a7) + funcbeadx \1,2a,\2d16ad,a2 + funcbeadx \1,2b,\2d16ad,a3 + funcbeadx \1,2c,\2d16ad,a4 + funcbeadx \1,2d,\2d16ad,a5 + funcbeadx \1,2e,\2d16ad,a6 + funcbeadx \1,2f,\2d16ad,usp +//-------------------------------------------------------------------- +// func.b d8(ax,dy),dx +//-------------------------------------------------------------------- + funcbeadx \1,30,\2d8ad,a0_off(a7) + funcbeadx \1,31,\2d8ad,a1_off(a7) + funcbeadx \1,32,\2d8ad,a2 + funcbeadx \1,33,\2d8ad,a3 + funcbeadx \1,34,\2d8ad,a4 + funcbeadx \1,35,\2d8ad,a5 + funcbeadx \1,36,\2d8ad,a6 + funcbeadx \1,37,\2d8ad,usp +//-------------------------------------------------------------------- +// func.b xxx.w,dx +//-------------------------------------------------------------------- + funcbeadx \1,38,\2xwd,(a0)+ +//-------------------------------------------------------------------- +// func.b xxx.w,dx +//-------------------------------------------------------------------- + funcbeadx \1,39,\2xld,(a0)+ +//-------------------------------------------------------------------- +// func.b d16(pc),dx +//-------------------------------------------------------------------- + funcbeadx \1,3a,\2d16pcd,(a0)+ +//-------------------------------------------------------------------- +// func.b d8(pc,dy),dx +//-------------------------------------------------------------------- + funcbeadx \1,3b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.b #im,dx +//-------------------------------------------------------------------- + funcbeadx \1,3c,\2bir_macro,(a0)+ +//-------------------------------------------------------------------- +// func.b dy,ea +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.b dx,dd -> addx subx etc. src und dest vertauscht! +//-------------------------------------------------------------------- + funcbdxea \1,00,\2dx,d0_off+3(a7) + funcbdxea \1,01,\2dx,d1_off+3(a7) + funcbdxea \1,02,\2dx,d2 + funcbdxea \1,03,\2dx,d3 + funcbdxea \1,04,\2dx,d4 + funcbdxea \1,05,\2dx,d5 + funcbdxea \1,06,\2dx,d6 + funcbdxea \1,07,\2dx,d7 +//-------------------------------------------------------------------- +// func.b -(ax),-(ay) addx subx etc. src und dest vertauscht! +//-------------------------------------------------------------------- + funcaxay \1,08,\2dax,a0_off(a7),b + funcaxay \1,09,\2dax,a1_off(a7).b + funcaxay \1,0a,\2dax,a2,b + funcaxay \1,0b,\2dax,a3,b + funcaxay \1,0c,\2dax,a4,b + funcaxay \1,0d,\2dax,a5,b + funcaxay \1,0e,\2dax,a6,b + funcaxay \1,0f,\2dax,usp,b +//-------------------------------------------------------------------- +// func.b dy,(ax) +//-------------------------------------------------------------------- + funcbdxea \1,10,\2eda,a0_off(a7) + funcbdxea \1,11,\2eda,a1_off(a7) + funcbdxea \1,12,\2dd,(a2) + funcbdxea \1,13,\2dd,(a3) + funcbdxea \1,14,\2dd,(a4) + funcbdxea \1,15,\2dd,(a5) + funcbdxea \1,16,\2dd,(a6) + funcbdxea \1,17,\2eda,usp +//-------------------------------------------------------------------- +// func.b dy,(ax)+ +//-------------------------------------------------------------------- + funcbdxea \1,18,\2edai,a0_off(a7) + funcbdxea \1,19,\2edai,a1_off(a7) + funcbdxea \1,1a,\2edaid,(a2) + funcbdxea \1,1b,\2edaid,(a3) + funcbdxea \1,1c,\2edaid,(a4) + funcbdxea \1,1d,\2edaid,(a5) + funcbdxea \1,1e,\2edaid,(a6) + funcbdxea \1,1f,\2edai,usp +//-------------------------------------------------------------------- +// func.b dy,-(ax) +//-------------------------------------------------------------------- + funcbdxea \1,20,\2edad,a0_off(a7) + funcbdxea \1,21,\2edad,a1_off(a7) + funcbdxea \1,22,\2edadd,(a2) + funcbdxea \1,23,\2edadd,(a3) + funcbdxea \1,24,\2edadd,(a4) + funcbdxea \1,25,\2edadd,(a5) + funcbdxea \1,26,\2edadd,(a6) + funcbdxea \1,27,\2edad,usp +//-------------------------------------------------------------------- +// func.b dy,d16(ax) +//-------------------------------------------------------------------- + funcbdxea \1,28,\2e16ad,a0_off(a7) + funcbdxea \1,29,\2e16ad,a1_off(a7) + funcbdxea \1,2a,\2e16ad,a2 + funcbdxea \1,2b,\2e16ad,a3 + funcbdxea \1,2c,\2e16ad,a4 + funcbdxea \1,2d,\2e16ad,a5 + funcbdxea \1,2e,\2e16ad,a6 + funcbdxea \1,2f,\2e16ad,usp +//-------------------------------------------------------------------- +// func.b dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcbdxea \1,30,\2e8ad,a0_off(a7) + funcbdxea \1,31,\2e8ad,a1_off(a7) + funcbdxea \1,32,\2e8ad,a2 + funcbdxea \1,33,\2e8ad,a3 + funcbdxea \1,34,\2e8ad,a4 + funcbdxea \1,35,\2e8ad,a5 + funcbdxea \1,36,\2e8ad,a6 + funcbdxea \1,37,\2e8ad,usp +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,38,\2xwe,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,39,\2xld,(a0)+ +/*****************************************************************************************/ +// word +/*****************************************************************************************/ +// func.w ds,dx +//-------------------------------------------------------------------- + funcweadx \1,40,\2dd,d0_off+2(a7) + funcweadx \1,41,\2dd,d1_off+2(a7) + funcweadx \1,42,\2dd,d2 + funcweadx \1,43,\2dd,d3 + funcweadx \1,44,\2dd,d4 + funcweadx \1,45,\2dd,d5 + funcweadx \1,46,\2dd,d6 + funcweadx \1,47,\2dd,d7 +//-------------------------------------------------------------------- +// func.w ax,dx +//-------------------------------------------------------------------- + funcweadx \1,48,\2dd,a0_off+2(a7) + funcweadx \1,49,\2dd,a1_off+2(a7) + funcweadx \1,4a,\2dd,a2 + funcweadx \1,4b,\2dd,a3 + funcweadx \1,4c,\2dd,a4 + funcweadx \1,4d,\2dd,a5 + funcweadx \1,4e,\2dd,a6 + funcweadx \1,4f,\2ddd,usp +//-------------------------------------------------------------------- +// func.w (ax),dx +//-------------------------------------------------------------------- + funcweadx \1,50,\2dda,a0_off(a7) + funcweadx \1,51,\2dda,a1_off(a7) + funcweadx \1,52,\2dd,(a2) + funcweadx \1,53,\2dd,(a3) + funcweadx \1,54,\2dd,(a4) + funcweadx \1,55,\2dd,(a5) + funcweadx \1,56,\2dd,(a6) + funcweadx \1,57,\2dda,usp +//-------------------------------------------------------------------- +// func.w (ax)+,dx +//-------------------------------------------------------------------- + funcweadx \1,58,\2ddai,a0_off(a7) + funcweadx \1,59,\2ddai,a1_off(a7) + funcweadx \1,5a,\2dd,(a2)+ + funcweadx \1,5b,\2dd,(a3)+ + funcweadx \1,5c,\2dd,(a4)+ + funcweadx \1,5d,\2dd,(a5)+ + funcweadx \1,5e,\2dd,(a6)+ + funcweadx \1,5f,\2ddai,usp +//-------------------------------------------------------------------- +// func.w -(ax),dx +//-------------------------------------------------------------------- + funcweadx \1,60,\2ddad,a0_off(a7) + funcweadx \1,61,\2ddad,a1_off(a7) + funcweadx \1,62,\2dd,-(a2) + funcweadx \1,63,\2dd,-(a3) + funcweadx \1,64,\2dd,-(a4) + funcweadx \1,65,\2dd,-(a5) + funcweadx \1,66,\2dd,-(a6) + funcweadx \1,67,\2ddad,usp +//-------------------------------------------------------------------- +// func.w d16(ax),dx +//-------------------------------------------------------------------- + funcweadx \1,68,\2d16ad,a0_off(a7) + funcweadx \1,69,\2d16ad,a1_off(a7) + funcweadx \1,6a,\2d16ad,a2 + funcweadx \1,6b,\2d16ad,a3 + funcweadx \1,6c,\2d16ad,a4 + funcweadx \1,6d,\2d16ad,a5 + funcweadx \1,6e,\2d16ad,a6 + funcweadx \1,6f,\2d16ad,usp +//-------------------------------------------------------------------- +// func.w d8(ax,dy),dx +//-------------------------------------------------------------------- + funcweadx \1,70,\2d8ad,a0_off(a7) + funcweadx \1,71,\2d8ad,a1_off(a7) + funcweadx \1,72,\2d8ad,a2 + funcweadx \1,73,\2d8ad,a3 + funcweadx \1,74,\2d8ad,a4 + funcweadx \1,75,\2d8ad,a5 + funcweadx \1,76,\2d8ad,a6 + funcweadx \1,77,\2d8ad,usp +//-------------------------------------------------------------------- +// func.w xxx.w,dx +//-------------------------------------------------------------------- + funcweadx \1,78,\2xwd,(a0)+ +//-------------------------------------------------------------------- +// func.w xxx.w,dx +//-------------------------------------------------------------------- + funcweadx \1,79,\2xld,(a0)+ +//-------------------------------------------------------------------- +// func.w d16(pc),dx +//-------------------------------------------------------------------- + funcweadx \1,7a,\2d16pcd,(a0)+ +//-------------------------------------------------------------------- +// func.w d8(pc,dy),dx +//-------------------------------------------------------------------- + funcweadx \1,7b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.w #im,dx +//-------------------------------------------------------------------- + funcweadx \1,7c,\2dd,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,ea +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.w dx,dd -> addx subx etc. +//-------------------------------------------------------------------- +.ifnc \2,and //platz für exg + funcwdxea \1,40,\2dx,d0_off+2(a7) + funcwdxea \1,41,\2dx,d1_off+2(a7) + funcwdxea \1,42,\2dx,d2 + funcwdxea \1,43,\2dx,d3 + funcwdxea \1,44,\2dx,d4 + funcwdxea \1,45,\2dx,d5 + funcwdxea \1,46,\2dx,d6 + funcwdxea \1,47,\2dx,d7 +//-------------------------------------------------------------------- +// func.w -(ax),-(ay) -> addx,subx +//-------------------------------------------------------------------- + funcaxay \1,48,\2dax,a0_off(a7),w + funcaxay \1,49,\2dax,a1_off(a7).w + funcaxay \1,4a,\2dax,a2,w + funcaxay \1,4b,\2dax,a3,w + funcaxay \1,4c,\2dax,a4,w + funcaxay \1,4d,\2dax,a5,w + funcaxay \1,4e,\2dax,a6,w + funcaxay \1,4f,\2dax,usp,w +.endif +//-------------------------------------------------------------------- +// func.w dy,(ax) +//-------------------------------------------------------------------- + funcwdxea \1,50,\2eda,a0_off(a7) + funcwdxea \1,51,\2eda,a1_off(a7) + funcwdxea \1,52,\2dd,(a2) + funcwdxea \1,53,\2dd,(a3) + funcwdxea \1,54,\2dd,(a4) + funcwdxea \1,55,\2dd,(a5) + funcwdxea \1,56,\2dd,(a6) + funcwdxea \1,57,\2eda,usp +//-------------------------------------------------------------------- +// func.w dy,(ax)+ +//-------------------------------------------------------------------- + funcwdxea \1,58,\2edai,a0_off(a7) + funcwdxea \1,59,\2edai,a1_off(a7) + funcwdxea \1,5a,\2edaid,(a2) + funcwdxea \1,5b,\2edaid,(a3) + funcwdxea \1,5c,\2edaid,(a4) + funcwdxea \1,5d,\2edaid,(a5) + funcwdxea \1,5e,\2edaid,(a6) + funcwdxea \1,5f,\2edai,usp +//-------------------------------------------------------------------- +// func.w dy,-(ax) +//-------------------------------------------------------------------- + funcwdxea \1,60,\2edad,a0_off(a7) + funcwdxea \1,61,\2edad,a1_off(a7) + funcwdxea \1,62,\2edadd,(a2) + funcwdxea \1,63,\2edadd,(a3) + funcwdxea \1,64,\2edadd,(a4) + funcwdxea \1,65,\2edadd,(a5) + funcwdxea \1,66,\2edadd,(a6) + funcwdxea \1,67,\2edad,usp +//-------------------------------------------------------------------- +// func.w dy,d16(ax) +//-------------------------------------------------------------------- + funcwdxea \1,68,\2e16ad,a0_off(a7) + funcwdxea \1,69,\2e16ad,a1_off(a7) + funcwdxea \1,6a,\2e16ad,a2 + funcwdxea \1,6b,\2e16ad,a3 + funcwdxea \1,6c,\2e16ad,a4 + funcwdxea \1,6d,\2e16ad,a5 + funcwdxea \1,6e,\2e16ad,a6 + funcwdxea \1,6f,\2e16ad,usp +//-------------------------------------------------------------------- +// func.w dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcwdxea \1,70,\2e8ad,a0_off(a7) + funcwdxea \1,71,\2e8ad,a1_off(a7) + funcwdxea \1,72,\2e8ad,a2 + funcwdxea \1,73,\2e8ad,a3 + funcwdxea \1,74,\2e8ad,a4 + funcwdxea \1,75,\2e8ad,a5 + funcwdxea \1,76,\2e8ad,a6 + funcwdxea \1,77,\2e8ad,usp +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,78,\2xwe,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,79,\2xld,(a0)+ +/*****************************************************************************************/ +// long +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// func.l -(ax),-(ay) +//-------------------------------------------------------------------- + funcaxay \1,c8,\2dax,a0_off(a7),l + funcaxay \1,c9,\2dax,a1_off(a7).l + funcaxay \1,ca,\2dax,a2,l + funcaxay \1,cb,\2dax,a3,l + funcaxay \1,cc,\2dax,a4,l + funcaxay \1,cd,\2dax,a5,l + funcaxay \1,ce,\2dax,a6,l + funcaxay \1,cf,\2dax,usp,l +//-------------------------------------------------------------------- +// func.l d8(ax,dy),dx +//-------------------------------------------------------------------- + funcleadx \1,b0,\2d8ad,a0_off(a7) + funcleadx \1,b1,\2d8ad,a1_off(a7) + funcleadx \1,b2,\2d8ad,a2 + funcleadx \1,b3,\2d8ad,a3 + funcleadx \1,b4,\2d8ad,a4 + funcleadx \1,b5,\2d8ad,a5 + funcleadx \1,b6,\2d8ad,a6 + funcleadx \1,b7,\2d8ad,usp +//-------------------------------------------------------------------- +// func.l d8(pc,dy),dx +//-------------------------------------------------------------------- + funcleadx \1,bb,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.l dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcldxea \1,b0,\2e8ad,a0_off(a7) + funcldxea \1,b1,\2e8ad,a1_off(a7) + funcldxea \1,b2,\2e8ad,a2 + funcldxea \1,b3,\2e8ad,a3 + funcldxea \1,b4,\2e8ad,a4 + funcldxea \1,b5,\2e8ad,a5 + funcldxea \1,b6,\2e8ad,a6 + funcldxea \1,b7,\2e8ad,usp +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// func.w ea,ax +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// func.w dx,ax +//-------------------------------------------------------------------- + funcweaax \1,c0,\2aw,d0 + funcweaax \1,c1,\2aw,d1 + funcweaax \1,c2,\2aw,d2 + funcweaax \1,c3,\2aw,d3 + funcweaax \1,c4,\2aw,d4 + funcweaax \1,c5,\2aw,d5 + funcweaax \1,c6,\2aw,d6 + funcweaax \1,c7,\2aw,d7 +//-------------------------------------------------------------------- +// func.w ay,ax +//-------------------------------------------------------------------- + funcweaax \1,c8,\2aw,a0 + funcweaax \1,c9,\2aw,a1 + funcweaax \1,ca,\2aw,a2 + funcweaax \1,cb,\2aw,a3 + funcweaax \1,cc,\2aw,a4 + funcweaax \1,cd,\2aw,a5 + funcweaax \1,ce,\2aw,a6 + funcweaax \1,cf,\2awu,a7 +//-------------------------------------------------------------------- +// func.w (ay),ax +//-------------------------------------------------------------------- + funcweaax \1,d0,\2aw,(a0) + funcweaax \1,d1,\2aw,(a1) + funcweaax \1,d2,\2aw,(a2) + funcweaax \1,d3,\2aw,(a3) + funcweaax \1,d4,\2aw,(a4) + funcweaax \1,d5,\2aw,(a5) + funcweaax \1,d6,\2aw,(a6) + funcweaax \1,d7,\2awu,(a7) +//-------------------------------------------------------------------- +// func.w (ay)+,ax +//-------------------------------------------------------------------- + funcweaax \1,d8,\2aw,(a0)+ + funcweaax \1,d9,\2aw,(a1)+ + funcweaax \1,da,\2aw,(a2)+ + funcweaax \1,db,\2aw,(a3)+ + funcweaax \1,dc,\2aw,(a4)+ + funcweaax \1,dd,\2aw,(a5)+ + funcweaax \1,de,\2aw,(a6)+ + funcweaax \1,df,\2awu,(a7)+ +//-------------------------------------------------------------------- +// func.w -(ay),ax +//-------------------------------------------------------------------- + funcweaax \1,e0,\2aw,-(a0) + funcweaax \1,e1,\2aw,-(a1) + funcweaax \1,e2,\2aw,-(a2) + funcweaax \1,e3,\2aw,-(a3) + funcweaax \1,e4,\2aw,-(a4) + funcweaax \1,e5,\2aw,-(a5) + funcweaax \1,e6,\2aw,-(a6) + funcweaax \1,e7,\2awu,-(a7) +//-------------------------------------------------------------------- +// func.w d16(ay),ax +//-------------------------------------------------------------------- + funcweaaxn \1,e8,\2awd16a,a0_off(a7) + funcweaaxn \1,e9,\2awd16a,a1_off(a7) + funcweaaxn \1,ea,\2awd16a,a2 + funcweaaxn \1,eb,\2awd16a,a3 + funcweaaxn \1,ec,\2awd16a,a4 + funcweaaxn \1,ed,\2awd16a,a5 + funcweaaxn \1,ee,\2awd16a,a6 + funcweaaxn \1,ef,\2awd16a,usp +//-------------------------------------------------------------------- +// func.w d8(ay,dy),ax +//-------------------------------------------------------------------- + funcweaaxn \1,f0,\2awd8a,a0_off(a7) + funcweaaxn \1,f1,\2awd8a,a1_off(a7) + funcweaaxn \1,f2,\2awd8a,a2 + funcweaaxn \1,f3,\2awd8a,a3 + funcweaaxn \1,f4,\2awd8a,a4 + funcweaaxn \1,f5,\2awd8a,a5 + funcweaaxn \1,f6,\2awd8a,a6 + funcweaaxn \1,f7,\2awd8a,usp +//-------------------------------------------------------------------- +// func.w xxx.w,ax +//-------------------------------------------------------------------- + funcweaaxn \1,f8,\2awxwax,(a0)+ +//-------------------------------------------------------------------- +// func.w xxxlw,ax +//-------------------------------------------------------------------- + funcweaaxn \1,f9,\2awxlax,(a0)+ +//-------------------------------------------------------------------- +// func.w d16(pc),ax +//-------------------------------------------------------------------- + funcweaaxn \1,fa,\2awd16pcax,(a0)+ +//-------------------------------------------------------------------- +// func.w d8(pc,dy),ax +//-------------------------------------------------------------------- + funcweaaxn \1,fb,\2awd8pcax,(a0)+ //(a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.w #im,ax +//-------------------------------------------------------------------- + funcweaaxn \1,fc,\2awim,(a0)+ +//-------------------------------------------------------------------- +// ende + .endm; +//-------------------------------------------------------------------- +// byt +funcbeadx:.macro // function byt: im,dx +ii_0x\10\2: + \3 \4,d0_off+3(a7),b +ii_0x\12\2: + \3 \4,d1_off+3(a7),b +ii_0x\14\2: + \3 \4,d2,b +ii_0x\16\2: + \3 \4,d3,b +ii_0x\18\2: + \3 \4,d4,b +ii_0x\1a\2: + \3 \4,d5,b +ii_0x\1c\2: + \3 \4,d6,b +ii_0x\1e\2: + \3 \4,d7,b + .endm; +funcbdxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off+3(a7),\4,b +ii_0x\13\2: + \3 d1_off+3(a7),\4,b +ii_0x\15\2: + \3 d2,\4,b +ii_0x\17\2: + \3 d3,\4,b +ii_0x\19\2: + \3 d4,\4,b +ii_0x\1b\2: + \3 d5,\4,b +ii_0x\1d\2: + \3 d6,\4,b +ii_0x\1f\2: + \3 d7,\4,b + .endm; +//-------------------------------------------------------------------- +// word +funcweadx:.macro // dx function(\3) ea(\4) -> dx +ii_0x\10\2: + \3 \4,d0_off+2(a7),w +ii_0x\12\2: + \3 \4,d1_off+2(a7),w +ii_0x\14\2: + \3 \4,d2,w +ii_0x\16\2: + \3 \4,d3,w +ii_0x\18\2: + \3 \4,d4,w +ii_0x\1a\2: + \3 \4,d5,w +ii_0x\1c\2: + \3 \4,d6,w +ii_0x\1e\2: + \3 \4,d7,w + .endm; +funcwdxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off+2(a7),\4,w +ii_0x\13\2: + \3 d1_off+2(a7),\4,w +ii_0x\15\2: + \3 d2,\4,w +ii_0x\17\2: + \3 d3,\4,w +ii_0x\19\2: + \3 d4,\4,w +ii_0x\1b\2: + \3 d5,\4,w +ii_0x\1d\2: + \3 d6,\4,w +ii_0x\1f\2: + \3 d7,\4,w + .endm; +//-------------------------------------------------------------------- +// long +funcleadx:.macro // dx function(\3) ea(\4) -> dx +ii_0x\10\2: + \3 \4,d0_off(a7),w +ii_0x\12\2: + \3 \4,d1_off(a7),w +ii_0x\14\2: + \3 \4,d2,w +ii_0x\16\2: + \3 \4,d3,w +ii_0x\18\2: + \3 \4,d4,w +ii_0x\1a\2: + \3 \4,d5,w +ii_0x\1c\2: + \3 \4,d6,w +ii_0x\1e\2: + \3 \4,d7,w + .endm; +funcldxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off(a7),\4,w +ii_0x\13\2: + \3 d1_off(a7),\4,w +ii_0x\15\2: + \3 d2,\4,w +ii_0x\17\2: + \3 d3,\4,w +ii_0x\19\2: + \3 d4,\4,w +ii_0x\1b\2: + \3 d5,\4,w +ii_0x\1d\2: + \3 d6,\4,w +ii_0x\1f\2: + \3 d7,\4,w + .endm; +//-------------------------------------------------------------- +// address +funcweaax:.macro // ax function(\3) ea(\4)(ext long!) -> ax +ii_0x\10\2: + \3 \4,a0 +ii_0x\12\2: + \3 \4,a1 +ii_0x\14\2: + \3 \4,a2 +ii_0x\16\2: + \3 \4,a3 +ii_0x\18\2: + \3 \4,a4 +ii_0x\1a\2: + \3 \4,a5 +ii_0x\1c\2: + \3 \4,a6 +ii_0x\1e\2: + \3a7 \4,a7 // "a7" beachten wegen usp + .endm; +funcweaaxn:.macro // ax function(\3) ea(\4)(ext long!) -> ax +ii_0x\10\2: + \3 \4,a0_off(a7) +ii_0x\12\2: + \3 \4,a1_off(a7) +ii_0x\14\2: + \3 \4,a2 +ii_0x\16\2: + \3 \4,a3 +ii_0x\18\2: + \3 \4,a4 +ii_0x\1a\2: + \3 \4,a5 +ii_0x\1c\2: + \3 \4,a6 +ii_0x\1e\2: + \3 \4,usp + .endm; +//-------------------------------------------------------------- +// byt, word, long +//-------------------------------------------------------------- +funcaxay:.macro // ea(\4) function(\3) dx -> ea,\5 = size +ii_0x\11\2: + \3 a0_off(a7),\4,\5 +ii_0x\13\2: + \3 a1_off(a7),\4,\5 +ii_0x\15\2: + \3 a2,\4,\5 +ii_0x\17\2: + \3 a3,\4,\5 +ii_0x\19\2: + \3 a4,\4,\5 +ii_0x\1b\2: + \3 a5,\4,\5 +ii_0x\1d\2: + \3 a6,\4,\5 +ii_0x\1f\2: + \3 usp,\4,\5 + .endm; diff --git a/BaS_GNU/sources/ii_jmp.h b/BaS_GNU/sources/ii_jmp.h new file mode 100644 index 0000000..1896118 --- /dev/null +++ b/BaS_GNU/sources/ii_jmp.h @@ -0,0 +1,59 @@ +//-------------------------------------------------------------------- +// extension word format missing +//-------------------------------------------------------------------- +ii_\1_func:.macro +ii_0x\20: +#ifdef halten_\1 + halt +#endif + move.l a0_off(a7),a1 + \1_macro +ii_0x\21: +#ifdef halten_\1 + halt +#endif + move.l a1_off(a7),a1 + \1_macro +ii_0x\22: +#ifdef halten_\1 + halt +#endif + move.l a2,a1 + \1_macro +ii_0x\23: +#ifdef halten_\1 + halt +#endif + move.l a3,a1 + \1_macro +ii_0x\24: +#ifdef halten_\1 + halt +#endif + move.l a4,a1 + \1_macro +ii_0x\25: +#ifdef halten_\1 + halt +#endif + move.l a5,a1 + \1_macro +ii_0x\26: +#ifdef halten_\1 + halt +#endif + move.l a6,a1 + \1_macro +ii_0x\27: +#ifdef halten_\1 + halt +#endif + move.l usp,a1 + \1_macro +ii_0x\2b: +#ifdef halten_\1 + halt +#endif + move.l a0,a1 + \1_macro +.endm diff --git a/BaS_GNU/sources/ii_lea.h b/BaS_GNU/sources/ii_lea.h new file mode 100644 index 0000000..7a422a7 --- /dev/null +++ b/BaS_GNU/sources/ii_lea.h @@ -0,0 +1,105 @@ +//------------------------------------------------------------------- +// lea +//------------------------------------------------------------------- +.text +ii_lea_lset:.macro + ii_lset_dxu 4,f0 // lea d8(a0,dy.w),a0-a7 + ii_lset_dxu 4,f1 // lea d8(a1,dy.w),a0-a7 + ii_lset_dxu 4,f2 // lea d8(a2,dy.w),a0-a7 + ii_lset_dxu 4,f3 // lea d8(a3,dy.w),a0-a7 + ii_lset_dxu 4,f4 // lea d8(a4,dy.w),a0-a7 + ii_lset_dxu 4,f5 // lea d8(a5,dy.w),a0-a7 + ii_lset_dxu 4,f6 // lea d8(a6,dy.w),a0-a7 + ii_lset_dxu 4,f7 // lea d8(a7,dy.w),a0-a7 + ii_lset_dxu 4,fb // lea d8(pc,dy.w),a0-a7 +.endm + +//--------------------------------------------------------------------------------------------- +// function +//--------------------------------------------------------------------------------------------- +ii_lea_sub:.macro +ii_0x4\1\2: +#ifdef halten_lea + halt +#endif + move.l \4,a1 + jsr ewf + move.l a1,\3 + ii_end +.endm +ii_lea_func:.macro +//lea d8(ax,dy.w),a0-a7 + ii_lea_sub 1,f0,a0_off(a7),a0_off(a7) + ii_lea_sub 1,f1,a0_off(a7),a1_off(a7) + ii_lea_sub 1,f2,a0_off(a7),a2 + ii_lea_sub 1,f3,a0_off(a7),a3 + ii_lea_sub 1,f4,a0_off(a7),a4 + ii_lea_sub 1,f5,a0_off(a7),a5 + ii_lea_sub 1,f6,a0_off(a7),a6 + ii_lea_sub 1,f7,a0_off(a7),usp + ii_lea_sub 3,f0,a1_off(a7),a0_off(a7) + ii_lea_sub 3,f1,a1_off(a7),a1_off(a7) + ii_lea_sub 3,f2,a1_off(a7),a2 + ii_lea_sub 3,f3,a1_off(a7),a3 + ii_lea_sub 3,f4,a1_off(a7),a4 + ii_lea_sub 3,f5,a1_off(a7),a5 + ii_lea_sub 3,f6,a1_off(a7),a6 + ii_lea_sub 3,f7,a1_off(a7),usp + ii_lea_sub 5,f0,a2,a0_off(a7) + ii_lea_sub 5,f1,a2,a1_off(a7) + ii_lea_sub 5,f2,a2,a2 + ii_lea_sub 5,f3,a2,a3 + ii_lea_sub 5,f4,a2,a4 + ii_lea_sub 5,f5,a2,a5 + ii_lea_sub 5,f6,a2,a6 + ii_lea_sub 5,f7,a2,usp + ii_lea_sub 7,f0,a3,a0_off(a7) + ii_lea_sub 7,f1,a3,a1_off(a7) + ii_lea_sub 7,f2,a3,a2 + ii_lea_sub 7,f3,a3,a3 + ii_lea_sub 7,f4,a3,a4 + ii_lea_sub 7,f5,a3,a5 + ii_lea_sub 7,f6,a3,a6 + ii_lea_sub 7,f7,a3,usp + ii_lea_sub 9,f0,a4,a0_off(a7) + ii_lea_sub 9,f1,a4,a1_off(a7) + ii_lea_sub 9,f2,a4,a2 + ii_lea_sub 9,f3,a4,a3 + ii_lea_sub 9,f4,a4,a4 + ii_lea_sub 9,f5,a4,a5 + ii_lea_sub 9,f6,a4,a6 + ii_lea_sub 9,f7,a4,usp + ii_lea_sub b,f0,a5,a0_off(a7) + ii_lea_sub b,f1,a5,a1_off(a7) + ii_lea_sub b,f2,a5,a2 + ii_lea_sub b,f3,a5,a3 + ii_lea_sub b,f4,a5,a4 + ii_lea_sub b,f5,a5,a5 + ii_lea_sub b,f6,a5,a6 + ii_lea_sub b,f7,a6,usp + ii_lea_sub d,f0,a6,a0_off(a7) + ii_lea_sub d,f1,a6,a1_off(a7) + ii_lea_sub d,f2,a6,a2 + ii_lea_sub d,f3,a6,a3 + ii_lea_sub d,f4,a6,a4 + ii_lea_sub d,f5,a6,a5 + ii_lea_sub d,f6,a6,a6 + ii_lea_sub d,f7,a6,usp + ii_lea_sub f,f0,usp,a0_off(a7) + ii_lea_sub f,f1,usp,a1_off(a7) + ii_lea_sub f,f2,usp,a2 + ii_lea_sub f,f3,usp,a3 + ii_lea_sub f,f4,usp,a4 + ii_lea_sub f,f5,usp,a5 + ii_lea_sub f,f6,usp,a6 + ii_lea_sub f,f7,usp,usp +// lea d8(pc,dy.w),az + ii_lea_sub 1,fb,a0_off(a7),a0 + ii_lea_sub 3,fb,a1_off(a7),a0 + ii_lea_sub 5,fb,a2,a0 + ii_lea_sub 7,fb,a3,a0 + ii_lea_sub 9,fb,a4,a0 + ii_lea_sub b,fb,a5,a0 + ii_lea_sub d,fb,a6,a0 + ii_lea_sub f,fb,usp,a0 +.endm \ No newline at end of file diff --git a/BaS_GNU/sources/ii_macro.h b/BaS_GNU/sources/ii_macro.h new file mode 100644 index 0000000..eca557e --- /dev/null +++ b/BaS_GNU/sources/ii_macro.h @@ -0,0 +1,144 @@ +/*******************************************************/ +// constanten +/*******************************************************/ +.extern ___RAMBAR1 +.extern _rt_cacr +.extern _rt_mod +.extern _rt_ssp +.extern _rt_usp +.extern _rt_vbr +.extern _d0_save +.extern _a7_save + +ii_ss = 16 +d0_off = 0 +d1_off = 4 +a0_off = 8 +a1_off = 12 +format_off = 16 +sr_off = 18 +ccr_off = 19 +pc_off = 20 + +#define table 0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle -> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle + +/*******************************************************/ +// allgemeine macros +/*******************************************************/ +ii_end: .macro + move.l a0,pc_off(a7) + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 + rte + .endm; + +set_cc0:.macro + move.w ccr,d0 + move.b d0,ccr_off(a7) + .endm; + +ii_esr: .macro // geht nicht!!?? + movem.l (a7),d0/d1/a0/a1 + lea ii_ss+8(a7),a7 // stack erhöhen + move.w d0,_d0_save // d0.w sicheren + move.w -6(a7),d0 // sr holen + move.w d0,sr // sr setzen + nop + move.w _d0_save,d0 // d0.w zurück + .endm; + +ii_end_mvm:.macro + move.l a0_off(a7),a0 + lea 16(a7),a7 + rte + .endm; + +ii_endj:.macro + movem.l (a7),d0/d1/a0/a1 // register zurück + lea ii_ss(a7),a7 // korr + rte // ende + .endm; + +set_nzvc:.macro // set ccr bits nzvc + move.w ccr,d1 + bclr #4,d1 + btst #4,ccr_off(a7) + beq snzvc2\@ + bset #4,d1 +snzvc2\@: + move.b d1,ccr_off(a7) + .endm; + +set_cc1:.macro + move.w ccr,d1 + move.b d1,ccr_off(a7) + .endm; + +set_cc_b:.macro + move.w ccr,d1 + btst #7,d0 // byt negativ? + beq set_cc_b2\@ + bset #3,d1 // make negativ +set_cc_b2\@: + move.b d1,ccr_off(a7) + .endm; + +set_cc_w:.macro + move.w ccr,d1 + btst #15,d0 // byt negativ? + beq set_cc_w2\@ + bset #3,d1 // make negativ +set_cc_w2\@: + move.b d1,ccr_off(a7) + .endm; + +get_pc: .macro + lea.l (a0),a1 + .endm; + +//-------------------------------------------------------------------- +ii_lset:.macro offs + lea table+\offs*4,a0 + move.l #ii_\offs,(a0) + .endm; +ii_lset_dx:.macro // 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 + ii_lset_dxg \1,\2 + ii_lset_dxu \1,\2 + .endm; +ii_lset_dxg:.macro // gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 + lea table+0x\10\2*4,a0 + move.l #ii_0x\10\2,(a0) + lea 0x800(a0),a0 // 4 * 0x200 + move.l #ii_0x\12\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\14\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\16\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\18\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1a\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1c\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1e\2,(a0) + .endm; +ii_lset_dxu:.macro // ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40 + lea table+0x\11\2*4,a0 + move.l #ii_0x\11\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\13\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\15\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\17\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\19\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1b\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1d\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1f\2,(a0) + .endm; + diff --git a/BaS_GNU/sources/ii_move.h b/BaS_GNU/sources/ii_move.h new file mode 100644 index 0000000..4fb5832 --- /dev/null +++ b/BaS_GNU/sources/ii_move.h @@ -0,0 +1,1270 @@ +//------------------------------------------------------------------- +// move +//------------------------------------------------------------------- +.extern ewf + +.text +ii_move_lset:.macro +//------------------------------------------------------------------------- +// 0x1000 move.b +//------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 11,e +// move.x d16(ax),xxx.l + ii_lset_opeau 13,e +// move.x d16(pc),xxx.w + ii_lset 0x11fa +// move.x d16(pc),xxx.l + ii_lset 0x13fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 1,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 1,79 +// move.x #xx,d16(ax) + ii_lset_dxu 1,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x11f8 +// move.x xxx.l,xxx.w + ii_lset 0x11f9 +// move.x xxx.w,xxx.l + ii_lset 0x13f8 +// move.x xxx.l,xxx.l + ii_lset 0x13f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x11fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x13fc +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 11,8 + ii_lset_opeag 13,8 + ii_lset_opeag 15,8 + ii_lset_opeag 17,8 + ii_lset_opeag 19,8 + ii_lset_opeag 1b,8 + ii_lset_opeag 1d,8 + ii_lset_opeag 1f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 11,9 + ii_lset_opea 13,9 + ii_lset_opea 15,9 + ii_lset_opea 17,9 + ii_lset_opea 19,9 + ii_lset_opea 1b,9 + ii_lset_opea 1d,9 + ii_lset_opea 1f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 11,a + ii_lset_opeag 13,a + ii_lset_opeag 15,a + ii_lset_opeag 17,a + ii_lset_opeag 19,a + ii_lset_opeag 1b,a + ii_lset_opeag 1d,a + ii_lset_opeag 1f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) + ii_lset_opeag 17,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 17,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 17,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 10,3 + ii_lset_opeag 12,3 + ii_lset_opeag 14,3 + ii_lset_opeag 16,3 + ii_lset_opeag 18,3 + ii_lset_opeag 1a,3 + ii_lset_opeag 1c,3 + ii_lset_opeag 1e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 10,7 + ii_lset_opeag 12,7 + ii_lset_opeag 14,7 + ii_lset_opeag 16,7 + ii_lset_opeag 18,7 + ii_lset_opeag 1a,7 + ii_lset_opeag 1c,7 + ii_lset_opeag 1e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 10,b + ii_lset_opeag 12,b + ii_lset_opeag 14,b + ii_lset_opeag 16,b + ii_lset_opeag 18,b + ii_lset_opeag 1a,b + ii_lset_opeag 1c,b + ii_lset_opeag 1e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 10,f + ii_lset_opeag 12,f + ii_lset_opeag 14,f + ii_lset_opeag 16,f + ii_lset_opeag 18,f + ii_lset_opeag 1a,f + ii_lset_opeag 1c,f + ii_lset_opeag 1e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 11,3 + ii_lset_opeag 13,3 + ii_lset_opeag 15,3 + ii_lset_opeag 17,3 + ii_lset_opeag 19,3 + ii_lset_opeag 1b,3 + ii_lset_opeag 1d,3 + ii_lset_opeag 1f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 1,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 1,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 1,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 1,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 1,3b +//------------------------------------------------------------------------- +// 0x2000 move.l +//------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 21,e +// move.x d16(ax),xxx.l + ii_lset_opeau 23,e +// move.x d16(pc),xxx.w + ii_lset 0x21fa +// move.x d16(pc),xxx.l + ii_lset 0x23fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 2,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 2,79 +// move.x #xx,d16(ax) + ii_lset_dxu 2,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x21f8 +// move.x xxx.l,xxx.w + ii_lset 0x21f9 +// move.x xxx.w,xxx.l + ii_lset 0x23f8 +// move.x xxx.l,xxx.l + ii_lset 0x23f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x21fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x23fc +// move.x ea,d8(ax,dy) ------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 21,8 + ii_lset_opeag 23,8 + ii_lset_opeag 25,8 + ii_lset_opeag 27,8 + ii_lset_opeag 29,8 + ii_lset_opeag 2b,8 + ii_lset_opeag 2d,8 + ii_lset_opeag 2f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 21,9 + ii_lset_opea 23,9 + ii_lset_opea 25,9 + ii_lset_opea 27,9 + ii_lset_opea 29,9 + ii_lset_opea 2b,9 + ii_lset_opea 2d,9 + ii_lset_opea 2f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 21,a + ii_lset_opeag 23,a + ii_lset_opeag 25,a + ii_lset_opeag 27,a + ii_lset_opeag 29,a + ii_lset_opeag 2b,a + ii_lset_opeag 2d,a + ii_lset_opeag 2f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) +// move.x ax,d8(pc,dy) + ii_lset_opea 27,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 27,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 27,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 20,3 + ii_lset_opeag 22,3 + ii_lset_opeag 24,3 + ii_lset_opeag 26,3 + ii_lset_opeag 28,3 + ii_lset_opeag 2a,3 + ii_lset_opeag 2c,3 + ii_lset_opeag 2e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 20,7 + ii_lset_opeag 22,7 + ii_lset_opeag 24,7 + ii_lset_opeag 26,7 + ii_lset_opeag 28,7 + ii_lset_opeag 2a,7 + ii_lset_opeag 2c,7 + ii_lset_opeag 2e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 20,b + ii_lset_opeag 22,b + ii_lset_opeag 24,b + ii_lset_opeag 26,b + ii_lset_opeag 28,b + ii_lset_opeag 2a,b + ii_lset_opeag 2c,b + ii_lset_opeag 2e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 20,f + ii_lset_opeag 22,f + ii_lset_opeag 24,f + ii_lset_opeag 26,f + ii_lset_opeag 28,f + ii_lset_opeag 2a,f + ii_lset_opeag 2c,f + ii_lset_opeag 2e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 21,3 + ii_lset_opeag 23,3 + ii_lset_opeag 25,3 + ii_lset_opeag 27,3 + ii_lset_opeag 29,3 + ii_lset_opeag 2b,3 + ii_lset_opeag 2d,3 + ii_lset_opeag 2f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 2,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 2,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 2,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 2,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 2,3b +//------------------------------------------------------------------------- +// 0x3000 move.w +///------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 31,e +// move.x d16(ax),xxx.l + ii_lset_opeau 33,e +// move.x d16(pc),xxx.w + ii_lset 0x31fa +// move.x d16(pc),xxx.l + ii_lset 0x33fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 3,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 3,79 +// move.x #xx,d16(ax) + ii_lset_dxu 3,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x31f8 +// move.x xxx.l,xxx.w + ii_lset 0x31f9 +// move.x xxx.w,xxx.l + ii_lset 0x33f8 +// move.x xxx.l,xxx.l + ii_lset 0x33f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x31fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x33fc +// move.x ea,d8(ax,dy) ------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 31,8 + ii_lset_opeag 33,8 + ii_lset_opeag 35,8 + ii_lset_opeag 37,8 + ii_lset_opeag 39,8 + ii_lset_opeag 3b,8 + ii_lset_opeag 3d,8 + ii_lset_opeag 3f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 31,9 + ii_lset_opea 33,9 + ii_lset_opea 35,9 + ii_lset_opea 37,9 + ii_lset_opea 39,9 + ii_lset_opea 3b,9 + ii_lset_opea 3d,9 + ii_lset_opea 3f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 31,a + ii_lset_opeag 33,a + ii_lset_opeag 35,a + ii_lset_opeag 37,a + ii_lset_opeag 39,a + ii_lset_opeag 3b,a + ii_lset_opeag 3d,a + ii_lset_opeag 3f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) +// move.x ax,d8(pc,dy) + ii_lset_opea 37,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 37,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 37,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 30,3 + ii_lset_opeag 32,3 + ii_lset_opeag 34,3 + ii_lset_opeag 36,3 + ii_lset_opeag 38,3 + ii_lset_opeag 3a,3 + ii_lset_opeag 3c,3 + ii_lset_opeag 3e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 30,7 + ii_lset_opeag 32,7 + ii_lset_opeag 34,7 + ii_lset_opeag 36,7 + ii_lset_opeag 38,7 + ii_lset_opeag 3a,7 + ii_lset_opeag 3c,7 + ii_lset_opeag 3e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 30,b + ii_lset_opeag 32,b + ii_lset_opeag 34,b + ii_lset_opeag 36,b + ii_lset_opeag 38,b + ii_lset_opeag 3a,b + ii_lset_opeag 3c,b + ii_lset_opeag 3e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 30,f + ii_lset_opeag 32,f + ii_lset_opeag 34,f + ii_lset_opeag 36,f + ii_lset_opeag 38,f + ii_lset_opeag 3a,f + ii_lset_opeag 3c,f + ii_lset_opeag 3e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 31,3 + ii_lset_opeag 33,3 + ii_lset_opeag 35,3 + ii_lset_opeag 37,3 + ii_lset_opeag 39,3 + ii_lset_opeag 3b,3 + ii_lset_opeag 3d,3 + ii_lset_opeag 3f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 3,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 3,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 3,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 3,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 3,3b +.endm +//--------------------------------------------------------------------------------------------- +// function +//--------------------------------------------------------------------------------------------- +ii_move_op:.macro +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_move_d16ax_xxx 1e8,a0_off(a7),w + ii_move_d16ax_xxx 1e9,a1_off(a7),w + ii_move_d16ax_xxx 1ea,a2,w + ii_move_d16ax_xxx 1eb,a3,w + ii_move_d16ax_xxx 1ec,a4,w + ii_move_d16ax_xxx 1ed,a5,w + ii_move_d16ax_xxx 1ee,a6,w + ii_move_d16ax_xxx 1ef,usp,w +// move.x d16(ax),xxx.l + ii_move_d16ax_xxx 3e8,a0_off(a7),l + ii_move_d16ax_xxx 3e9,a1_off(a7),l + ii_move_d16ax_xxx 3ea,a2,l + ii_move_d16ax_xxx 3eb,a3,l + ii_move_d16ax_xxx 3ec,a4,l + ii_move_d16ax_xxx 3ed,a5,l + ii_move_d16ax_xxx 3ee,a6,l + ii_move_d16ax_xxx 3ef,usp,l +// move.x d16(pc),xxx.w + ii_move_d16ax_xxx 1fa,a0,w +// move.x d16(pc),xxx.l + ii_move_d16ax_xxx 3fa,a0,l +// move.x xxx.w,d16(ax) +// move.x xxx.l,d16(ax) +// move.x #xx,d16(ax) + ii_move_xxx_d16ax 1,a0_off(a7) + ii_move_xxx_d16ax 3,a1_off(a7) + ii_move_xxx_d16ax 5,a2 + ii_move_xxx_d16ax 7,a3 + ii_move_xxx_d16ax 9,a4 + ii_move_xxx_d16ax b,a5 + ii_move_xxx_d16ax d,a6 + ii_move_xxx_d16ax f,usp +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_move_xxx_xxx b,w,w,11f8 + ii_move_xxx_xxx l,w,w,21f8 + ii_move_xxx_xxx w,w,w,31f8 +// move.x xxx.l,xxx.w + ii_move_xxx_xxx b,l,w,11f9 + ii_move_xxx_xxx l,l,w,21f9 + ii_move_xxx_xxx w,l,w,31f9 +// move.x xxx.w,xxx.l + ii_move_xxx_xxx b,w,l,13f8 + ii_move_xxx_xxx l,w,l,23f8 + ii_move_xxx_xxx w,w,l,33f8 +// move.x xxx.l,xxx.l + ii_move_xxx_xxx b,l,l,13f9 + ii_move_xxx_xxx l,l,l,23f9 + ii_move_xxx_xxx w,l,l,33f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_move_im_xxx b,w,11fc + ii_move_im_xxx l,w,21fc + ii_move_im_xxx w,w,31fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_move_im_xxx b,l,13fc + ii_move_im_xxx l,l,23fc + ii_move_im_xxx w,l,33fc +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(ax/pc,dy) + ii_move_dxxia d0_off(a7),80,id,d,c0 + ii_move_dxxia d1_off(a7),81,id,d,c1 + ii_move_dxxia d2,82,d,d,c2 + ii_move_dxxia d3,83,d,d,c3 + ii_move_dxxia d4,84,d,d,c4 + ii_move_dxxia d5,85,d,d,c5 + ii_move_dxxia d6,86,d,d,c6 + ii_move_dxxia d7,87,d,d,c7 +// move.x ax,d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),88,id,d,c8 + ii_move_dxxia a1_off(a7),89,id,d,c9 + ii_move_dxxia a2,8a,d,da,ca + ii_move_dxxia a3,8b,d,da,cb + ii_move_dxxia a4,8c,d,da,cc + ii_move_dxxia a5,8d,d,da,cd + ii_move_dxxia a6,8e,d,da,ce + ii_move_dxxia a7,8f,a7,da,cf +// move.x (ax),d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),90,ia,d,d0 + ii_move_dxxia a1_off(a7),91,ia,d,d1 + ii_move_dxxia (a2),92,d,d,d2 + ii_move_dxxia (a3),93,d,d,d3 + ii_move_dxxia (a4),94,d,d,d4 + ii_move_dxxia (a5),95,d,d,d5 + ii_move_dxxia (a6),96,d,d,d6 + ii_move_dxxia (a7),97,a7,d,d7 +// move.x (ax)+,d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),98,iap,d,d8 + ii_move_dxxia a1_off(a7),99,iap,d,d9 + ii_move_dxxia (a2)+,9a,d,d,da + ii_move_dxxia (a3)+,9b,d,d,db + ii_move_dxxia (a4)+,9c,d,d,dc + ii_move_dxxia (a5)+,9d,d,d,dd + ii_move_dxxia (a6)+,9e,d,d,de + ii_move_dxxia (a7)+,9f,a7,d,df +// move.x -(ax),d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),a0,iam,d,e0 + ii_move_dxxia a1_off(a7),a1,iam,d,e1 + ii_move_dxxia -(a2),a2,d,d,e2 + ii_move_dxxia -(a3),a3,d,d,e3 + ii_move_dxxia -(a4),a4,d,d,e4 + ii_move_dxxia -(a5),a5,d,d,e5 + ii_move_dxxia -(a6),a6,d,d,e6 + ii_move_dxxia -(a7),a7,a7,d,e7 +//--------------------------------------------------------------------- +// move.x d8(ax/pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax/pc,dy),dz + ii_move_d8_dest d0,id,03,dx + ii_move_d8_dest d1,id,23,dx + ii_move_d8_dest d2,d,43,dx + ii_move_d8_dest d3,d,63,dx + ii_move_d8_dest d4,d,83,dx + ii_move_d8_dest d5,d,a3,dx + ii_move_d8_dest d6,d,c3,dx + ii_move_d8_dest d7,d,e3,dx +// move.x d8(ax/pc,dy),az + ii_move_d8_dest a0,id,07,ax + ii_move_d8_dest a1,id,27,ax + ii_move_d8_dest a2,d,47,ax + ii_move_d8_dest a3,d,67,ax + ii_move_d8_dest a4,d,87,ax + ii_move_d8_dest a5,d,a7,ax + ii_move_d8_dest a6,d,c7,ax + ii_move_d8_dest usp,id,e7,ax +// move.x d8(ax/pc,dy),(az) + ii_move_d8_dest a0_off(a7),id,0b,ia + ii_move_d8_dest a1_off(a7),id,2b,ia + ii_move_d8_dest (a2),d,4b,ia + ii_move_d8_dest (a3),d,6b,ia + ii_move_d8_dest (a4),d,8b,ia + ii_move_d8_dest (a5),d,ab,ia + ii_move_d8_dest (a6),d,cb,ia + ii_move_d8_dest usp,id,eb,ia +// move.x d8(ax/pc,dy),(az)+ + ii_move_d8_dest a0_off(a7),id,0f,iap + ii_move_d8_dest a1_off(a7),id,2f,iap + ii_move_d8_dest (a2)+,d,4f,iap + ii_move_d8_dest (a3)+,d,6f,iap + ii_move_d8_dest (a4)+,d,8f,iap + ii_move_d8_dest (a5)+,d,af,iap + ii_move_d8_dest (a6)+,d,cf,iap + ii_move_d8_dest usp,id,ef,iap +// move.x d8(ax/pc,dy),-(az) + ii_move_d8_dest a0_off(a7),id,13,iam + ii_move_d8_dest a1_off(a7),id,33,iam + ii_move_d8_dest -(a2),d,53,iam + ii_move_d8_dest -(a3),d,73,iam + ii_move_d8_dest -(a4),d,93,iam + ii_move_d8_dest -(a5),d,b3,iam + ii_move_d8_dest -(a6),d,d3,iam + ii_move_d8_dest usp,id,f3,iam +.endm //end function +//==================================================================== +// subs ---------------------------------------------------------- +//==================================================================== +// move.x d16(ax),xxx.w/l 1=code 2=adress register 3=dest adr size +ii_move_d16ax_xxx:.macro +ii_0x1\1: //byt: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.b (a1),d0 + move.\3 (a0)+,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x2\1: //long: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.l (a1),d0 + move.\3 (a0)+,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x3\1: //word: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.w (a1),d0 + move.\3 (a0)+,a1 + move.w d0,(a1) + set_cc0 + ii_end +.endm +//---------------------------------------- +// move.x xxx.w,d16(ax) +// move.x xxx.l,d16(ax) +// move.x #xx,d16(ax) +ii_move_xxx_d16ax:.macro //1=code 2=adress register +ii_0x1\178: //byt xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.b (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x1\179: //byt xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.b (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x1\17c: //byt #x +#ifdef halten_move + halt +#endif + mvs.b (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x2\178: //long xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.l (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x2\179: //long xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.l (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x2\17c: //long #x +#ifdef halten_move + halt +#endif + move.l (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end + ii_end +ii_0x3\178: //word xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.w (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +ii_0x3\179: //word xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.w (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +ii_0x3\17c: //word #x +#ifdef halten_move + halt +#endif + move.w (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +.endm +// move.x xxx,xxx +ii_move_xxx_xxx:.macro //1=size 2=size source adr 3=size dest adr 4=code +ii_0x\4: +#ifdef halten_move + halt +#endif + move.\2 (a0)+,a1 + move.\1 (a1),d0 + move.\3 (a0)+,d1 + move.\1 d0,(a1) + set_cc0 + ii_end +.endm +// move.x im,xxx +ii_move_im_xxx:.macro //1=size 2=size dest adr 3=code +ii_0x\3: +#ifdef halten_move + halt +#endif +.ifc 1,b + move.w (a0)+,d0 +.else + move.\1 (a0)+,d0 +.endif + move.\2 (a0)+,a1 + move.\1 d0,(a1) + set_cc0 + ii_end +.endm +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// ea=dx,ax,(ax),(ax)+,-(ax) +//--------------------------------------------------------------------- +ii_move_dxxia:.macro //1=source 2=code 1.stelle 3=code 2 letzte Stellen 4=art 5=code d8(pc,dy) +.ifc \3,id + ii_move_dxxi b,\1+3,1,\2,\3,\5 + ii_move_dxxi w,\1+2,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 +.else + .ifc \4,da + ii_move_dxxi w,\1,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 + .else + ii_move_dxxi b,\1,1,\2,\3,\5 + ii_move_dxxi w,\1,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 + .endif +.endif +.endm + +ii_move_dxxi:.macro +ii_0x\31\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + move_end \1,\2,\5 +ii_0x\33\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + move_end \1,\2,\5 +ii_0x\35\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a2,a1 + move_end \1,\2,\5 +ii_0x\37\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a3,a1 + move_end \1,\2,\5 +ii_0x\39\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a4,a1 + move_end \1,\2,\5 +ii_0x\3b\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a5,a1 + move_end \1,\2,\5 +ii_0x\3d\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a6,a1 + move_end \1,\2,\5 +ii_0x\3f\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l usp,a1 + move_end \1,\2,\5 +ii_0x\37\6: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a0,a1 + move_end \1,\2,\5 +.endm +//------------------------------------ +move_end:.macro + jsr ewf +.ifc 3,a7 + move.l a7,d1 // a7 sichern + move.l usp,a7 // a7 holen +.endif +.ifc 3,ia + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 (a2),(a1) + move.l d1,a2 // a2 zurück +.else + .ifc 3,iap + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 (a2)+,(a1) + .else + .ifc 3,iam + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 -(a2),(a1) + .else + move.\1 \2,(a1) + .endif + .endif +.endif +.ifc 3,a7 + movea.l a7,usp // a7 zurück + movea.l d1,a7 // a7 setzen +.endif + set_cc0 +.ifc 3,iap + move.l d1,a2 // a2 zurück +.endif +.ifc 3,iam + move.l d1,a2 // a2 zurück +.endif + ii_end +.endm +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) +//--------------------------------------------------------------------- + +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea --------------------------------------------- +//--------------------------------------------------------------------- +ii_move_d8_dest:.macro //1=dest 2=art 3=code 2.+3.stelle 4=art adresse +//byt +ii_0x1\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + moveb_a1_src\4 \1,\2 +ii_0x1\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + moveb_a1_src\4 \1,\2 +ii_0x1\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +//long +ii_0x2\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + movel_a1_src\4 \1,\2 +ii_0x2\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + movel_a1_src\4 \1,\2 +ii_0x2\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + movel_a1_src\4 \1,\2 +ii_0x2\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + movel_a1_src\4 \1,\2 +ii_0x2\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + movel_a1_src\4 \1,\2 +ii_0x2\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + movel_a1_src\4 \1,\2 +ii_0x2\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + movel_a1_src\4 \1,\2 +ii_0x2\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + movel_a1_src\4 \1,\2 +ii_0x2\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +//word +ii_0x3\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + movew_a1_src\4 \1,\2 +ii_0x3\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + movew_a1_src\4 \1,\2 +ii_0x3\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + movew_a1_src\4 \1,\2 +ii_0x3\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + movew_a1_src\4 \1,\2 +ii_0x3\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + movew_a1_src\4 \1,\2 +ii_0x3\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + movew_a1_src\4 \1,\2 +ii_0x3\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + movew_a1_src\4 \1,\2 +ii_0x3\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + movew_a1_src\4 \1,\2 +ii_0x3\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +.endm +//--------------------------------------------------------------------- +//dx +moveb_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.b (a1),\1_off+3(a7) +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.l (a1),\1_off(a7) +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.w (a1),\1_off+2(a7) +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// ax +moveb_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.w (a1),a1 + move.l a1,usp + .else + move.w (a1),\1_off+2(a7) + .endif +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.l (a1),a1 + move.l a1,usp + .else + move.l (a1),\1_off(a7) + .endif +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.w (a1),a1 + move.l a1,usp + .else + move.w (a1),\1_off+2(a7) + .endif +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// (ax) +moveb_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,(a1) +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,(a1) +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,(a1) +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// (ax)+ +moveb_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,(a1)+ + move.l a1,\1 +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,(a1)+ + move.l a1,\1 +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,(a1)+ + move.l a1,\1 +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// -(ax) +moveb_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,-(a1) + move.l a1,\1 +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,-(a1) + move.l a1,\1 +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,-(a1) + move.l a1,\1 +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm + +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea +//--------------------------------------------------------------------- + + + +// move.w dx,(a0,dx.w*SF) + ii_lset 0x3180 + ii_lset 0x3181 + ii_lset 0x3182 + ii_lset 0x3183 + ii_lset 0x3184 + ii_lset 0x3185 + ii_lset 0x3186 + ii_lset 0x3187 + +//-------------------------------------------------------------------- +// // move.w dx,d(ay,dz.w*sf) +//-------------------------------------------------------------------- +movew_ewfw:.macro off1, off2 + move.l \off2,a1 + jsr ewf + move.w \off1,(a1) + set_cc0 + ii_end + .endm +ii_0x3180: + movew_ewfw d0_off+2(a7),a0_off(a7) +ii_0x3181: + movew_ewfw d0_off+2(a7),a0_off(a7) +ii_0x3182: + movew_ewfw d2,a0_off(a7) +ii_0x3183: + movew_ewfw d3,a0_off(a7) +ii_0x3184: + movew_ewfw d4,a0_off(a7) +ii_0x3185: + movew_ewfw d5,a0_off(a7) +ii_0x3186: + movew_ewfw d6,a0_off(a7) +ii_0x3187: + movew_ewfw d7,a0_off(a7) diff --git a/BaS_GNU/sources/ii_movem.h b/BaS_GNU/sources/ii_movem.h new file mode 100644 index 0000000..5e8a470 --- /dev/null +++ b/BaS_GNU/sources/ii_movem.h @@ -0,0 +1,374 @@ +//***********************************************************************************/ +// movem +//***********************************************************************************/ +ii_movem_lset: .macro +// movem.l rx,xxx.L + ii_lset 0x48f9 +// movem.l xxx.L,rx + ii_lset 0x4cf9 +// movem.w rx,xxx.L + ii_lset 0x48b9 +// movem.w xxx.L,rx + ii_lset 0x4cb9 +// movem.l rx,-(ax) + ii_lset 0x48e0 + ii_lset 0x48e1 + ii_lset 0x48e2 + ii_lset 0x48e3 + ii_lset 0x48e4 + ii_lset 0x48e5 + ii_lset 0x48e6 + ii_lset 0x48e7 +// movem.l (ax)+,rx + ii_lset 0x4cd8 + ii_lset 0x4cd9 + ii_lset 0x4cda + ii_lset 0x4cdb + ii_lset 0x4cdc + ii_lset 0x4cdd + ii_lset 0x4cde + ii_lset 0x4cdf +.endm +//***********************************************************************************/ +ii_movem_func: .macro +//------------------------------------------------------------------- +// movem.l +//-------------------------------------------------------------------- +// movem.l (ax)+,reg +//-------------------------------------------------------------------- + .long 0 +az_reg_table: + .byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70 + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0 + .byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0 +//------------------------------------------------------------------------------- +ii_0x48e0: // movem.l reglist,-(a0) + mvm_mem_macro 0x48d0,a0_off(a7),2 +ii_0x48e1: // movem.l reglist,-(a1) + mvm_mem_macro 0x48d1,a1_off(a7),2 +ii_0x48e2: // movem.l reglist,-(a2) + mvm_mem_macro 0x48d2,a2,2 +ii_0x48e3: // movem.l reglist,-(a3) + mvm_mem_macro 0x48d3,a3,2 +ii_0x48e4: // movem.l reglist,-(a4) + mvm_mem_macro 0x48d4,a4,2 +ii_0x48e5: // movem.l reglist,-(a5) + mvm_mem_macro 0x48d5,a5,2 +ii_0x48e6: // movem.l reglist,-(a6) + mvm_mem_macro 0x48d6,a6,2 +ii_0x48e7: // movem.l reglist,-(a7) + mvm_mem_macro 0x48d7,usp,2 +//------------------------------------------------------------------------------- +ii_0x4cd8: // movem.l (a0)+,reglist + mvm_reg_macro 0x4cd0,0x41e8,2 +ii_0x4cd9: // movem.l (a1)+,reglist + mvm_reg_macro 0x4cd1,0x43e9,2 +ii_0x4cda: // movem.l (a2)+,reglist + mvm_reg_macro 0x4cd2,0x45ea,2 +ii_0x4cdb: // movem.l (a3)+,reglist + mvm_reg_macro 0x4cd3,0x47eb,2 +ii_0x4cdc: // movem.l (a4)+,reglist + mvm_reg_macro 0x4cd4,0x49ec,2 +ii_0x4cdd: // movem.l (a5)+,reglist + mvm_reg_macro 0x4cd5,0x4bed,2 +ii_0x4cde: // movem.l (a6)+,reglist + mvm_reg_macro 0x4cd6,0x4dee,2 +ii_0x4cdf: // movem.l (a7)+,reglist + mvm_reg_macro 0x4cd7,0x4fef,2 +//---------------------------------------------------------------------------- +ii_0x48f9: // movem.l reg,xxx.L +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro l +//--------------------------------------------------------------------------------------------- +ii_0x4cf9: // movem.l xxx.L,reg +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro l +//---------------------------------------------------------------------------- +ii_0x48b9: // movem.w reg,xxx.L +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro w +//--------------------------------------------------------------------------------------------- +ii_0x4cb9: // movem.w xxx.L,reg +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro w +.endm +//============================================================== +mvm_mem_macro:.macro +#ifdef halten_movem + halt +#endif + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lsl.l #\3,d1 // * anzahl byts pro wert + move.l \2,a1 + sub.l d1,a1 // ax-anzahl byts + move.l a1,\2 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x reg_list,-(a7) + move.w (a0)+,(a1)+ // register list + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte +.endm +//--------------------------------------------------------------------------------- +mvm_reg_macro:.macro +#ifdef halten_movem + halt +#endif + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x (ax),reg_list + move.w (a0)+,(a1)+ // register list + move.w #\2,(a1)+ // lea 0(ax),ax + lsl.l #\3,d1 // * anzahl byts pro wert + move.w d1,(a1)+ // offset von lea + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte +.endm +//--------------------------------------------------------------------------------- +movemrm_macro:.macro // in d0 register liste, in a1 zieladresse +#ifdef halten_movem + halt +#endif + tst.b d0 // datenregister zu verschieben? + bne mrm_dx\@ // ja-> + lsr.l #8,d0 // sonst zu addressregister + jmp mmrm_nd7\@ // -> +mrm_dx\@: + lsr.l #1,d0 + bcc mmrm_nd0\@ +.ifc 1,l + move.l d0_off(a7),(a1)+ +.else + move.w d0_off+2(a7),(a1)+ +.endif +mmrm_nd0\@: + lsr.l #1,d0 + bcc mmrm_nd1\@ +.ifc 1,l + move.l d1_off(a7),(a1)+ +.else + move.w d1_off+2(a7),(a1)+ +.endif +mmrm_nd1\@: + lsr.l #1,d0 + bcc mmrm_nd2\@ + move.\1 d2,(a1)+ +mmrm_nd2\@: + lsr.l #1,d0 + bcc mmrm_nd3\@ + move.\1 d3,(a1)+ +mmrm_nd3\@: + lsr.l #1,d0 + bcc mmrm_nd4\@ + move.\1 d4,(a1)+ +mmrm_nd4\@: + lsr.l #1,d0 + bcc mmrm_nd5\@ + move.\1 d5,(a1)+ +mmrm_nd5\@: + lsr.l #1,d0 + bcc mmrm_nd6\@ + move.l d6,(a1)+ +mmrm_nd6\@: + lsr.l #1,d0 + bcc mmrm_nd7\@ + move.\1 d7,(a1)+ +mmrm_nd7\@: + tst.b d0 // addressregister zu verschieben? + beq mmrm_na7\@ + lsr.l #1,d0 + bcc mmrm_na0\@ +.ifc 1,l + move.l a0_off(a7),(a1)+ +.else + move.w a0_off+2(a7),(a1)+ +.endif +mmrm_na0\@: + lsr.l #1,d0 + bcc mmrm_na1\@ +.ifc 1,l + move.l a1_off(a7),(a1)+ +.else + move.w a1_off+2(a7),(a1)+ +.endif +mmrm_na1\@: + lsr.l #1,d0 + bcc mmrm_na2\@ + move.\1 a2,(a1)+ +mmrm_na2\@: + lsr.l #1,d0 + bcc mmrm_na3\@ + move.\1 a3,(a1)+ +mmrm_na3\@: + lsr.l #1,d0 + bcc mmrm_na4\@ + move.\1 a4,(a1)+ +mmrm_na4\@: + lsr.l #1,d0 + bcc mmrm_na5\@ + move.\1 a5,(a1)+ +mmrm_na5\@: + lsr.l #1,d0 + bcc mmrm_na6\@ + move.\1 a6,(a1)+ +mmrm_na6\@: + lsr.l #1,d0 + bcc mmrm_na7\@ + move.l a0,d1 // sichern + move.l usp,a0 // ist ja usp + move.\1 a0,(a1)+ // nach a0 + move.l d1,a0 // pc zurück +mmrm_na7\@: + ii_end + .endm +//--------------------------------------------------------------------------------------------- +movemmr_macro:.macro // in d0 register liste, in a1 source adr +#ifdef halten_movem + halt +#endif + tst.b d0 // datenregister zu verschieben? + bne mmr_dx\@ // ja-> + lsr.l #8,d0 // sonst zu addressregister + bra mmmr_nd7\@ // -> +mmr_dx\@: + lsr.l #1,d0 + bcc mmmr_nd0\@ +.ifc 1,l + move.l (a1)+,d0_off(a7) +.else + move.w (a1)+,d0_off+2(a7) +.endif +mmmr_nd0\@: + lsr.l #1,d0 + bcc mmmr_nd1\@ +.ifc 1,l + move.l (a1)+,d1_off(a7) +.else + move.w (a1)+,d1_off+2(a7) +.endif +mmmr_nd1\@: + lsr.l #1,d0 + bcc mmmr_nd2\@ + move.\1 (a1)+,d2 +mmmr_nd2\@: + lsr.l #1,d0 + bcc mmmr_nd3\@ + move.\1 (a1)+,d3 +mmmr_nd3\@: + lsr.l #1,d0 + bcc mmmr_nd4\@ + move.\1 (a1)+,d4 +mmmr_nd4\@: + lsr.l #1,d0 + bcc mmmr_nd5\@ + move.\1 (a1)+,d5 +mmmr_nd5\@: + lsr.l #1,d0 + bcc mmmr_nd6\@ + move.\1 (a1)+,d6 +mmmr_nd6\@: + lsr.l #1,d0 + bcc mmmr_nd7\@ + move.\1 (a1)+,d7 +mmmr_nd7\@: + tst.b d0 // addressregister zu verschieben? + beq mmmr_na7\@ // nein-> + lsr.l #1,d0 + bcc mmmr_na0\@ +.ifc 1,l + move.l (a1)+,a0_off(a7) +.else + move.w (a1)+,a0_off+2(a7) +.endif +mmmr_na0\@: + lsr.l #1,d0 + bcc mmmr_na1\@ +.ifc 1,l + move.l (a1)+,a1_off(a7) +.else + move.w (a1)+,a1_off+2(a7) +.endif +mmmr_na1\@: + lsr.l #1,d0 + bcc mmmr_na2\@ + move.\1 (a1)+,a2 +mmmr_na2\@: + lsr.l #1,d0 + bcc mmmr_na3\@ + move.\1 (a1)+,a3 +mmmr_na3\@: + lsr.l #1,d0 + bcc mmmr_na4\@ + move.\1 (a1)+,a4 +mmmr_na4\@: + lsr.l #1,d0 + bcc mmmr_na5\@ + move.\1 (a1)+,a5 +mmmr_na5\@: + lsr.l #1,d0 + bcc mmmr_na6\@ + move.\1 (a1)+,a6 +mmmr_na6\@: + lsr.l #1,d0 + bcc mmmr_na7\@ + move.\1 (a1)+,a1 // nach a0 + move.l a1,usp // war ja usp +mmmr_na7\@: + ii_end + .endm diff --git a/BaS_GNU/sources/ii_movep.h b/BaS_GNU/sources/ii_movep.h new file mode 100644 index 0000000..830fdf7 --- /dev/null +++ b/BaS_GNU/sources/ii_movep.h @@ -0,0 +1,179 @@ +//-------------------------------------------------------------------- +// movep +//-------------------------------------------------------------------- +.text +ii_movep_lset:.macro + ii_lset_opeau 01,0 //movep.w d(a0-7),d0 + ii_lset_opeau 03,0 //movep.w d(a0-7),d1 + ii_lset_opeau 05,0 //movep.w d(a0-7),d2 + ii_lset_opeau 07,0 //movep.w d(a0-7),d3 + ii_lset_opeau 09,0 //movep.w d(a0-7),d4 + ii_lset_opeau 0b,0 //movep.w d(a0-7),d5 + ii_lset_opeau 0d,0 //movep.w d(a0-7),d6 + ii_lset_opeau 0f,0 //movep.w d(a0-7),d7 + + ii_lset_opeau 01,4 //movep.w d0,d(a0-7) + ii_lset_opeau 03,4 //movep.w d1,d(a0-7) + ii_lset_opeau 05,4 //movep.w d2,d(a0-7) + ii_lset_opeau 07,4 //movep.w d3,d(a0-7) + ii_lset_opeau 09,4 //movep.w d4,d(a0-7) + ii_lset_opeau 0b,4 //movep.w d5,d(a0-7) + ii_lset_opeau 0d,4 //movep.w d6,d(a0-7) + ii_lset_opeau 0f,4 //movep.w d7,d(a0-7) + + ii_lset_opeau 01,8 //movep.l d(a0-7),d0 + ii_lset_opeau 03,8 //movep.l d(a0-7),d1 + ii_lset_opeau 05,8 //movep.l d(a0-7),d2 + ii_lset_opeau 07,8 //movep.l d(a0-7),d3 + ii_lset_opeau 09,8 //movep.l d(a0-7),d4 + ii_lset_opeau 0b,8 //movep.l d(a0-7),d5 + ii_lset_opeau 0d,8 //movep.l d(a0-7),d6 + ii_lset_opeau 0f,8 //movep.l d(a0-7),d7 + + ii_lset_opeau 01,c //movep.l d0,d(a0-7) + ii_lset_opeau 03,c //movep.l d1,d(a0-7) + ii_lset_opeau 05,c //movep.l d2,d(a0-7) + ii_lset_opeau 07,c //movep.l d3,d(a0-7) + ii_lset_opeau 09,c //movep.l d4,d(a0-7) + ii_lset_opeau 0b,c //movep.l d5,d(a0-7) + ii_lset_opeau 0d,c //movep.l d6,d(a0-7) + ii_lset_opeau 0f,c //movep.l d7,d(a0-7) +.endm +//--------------------------------------------------------------------------------------------- +ii_movep_func:.macro +//movep.w d(a0-7),d0-7 + ii_movep 010,d0_off(a7),wad + ii_movep 030,d1_off(a7),wad + ii_movep 050,d2,wad + ii_movep 070,d3,wad + ii_movep 090,d4,wad + ii_movep 0b0,d5,wad + ii_movep 0d0,d6,wad + ii_movep 0f0,d7,wad +//movep.w d0-7,d(a0-7) + ii_movep 014,d0_off(a7),wda + ii_movep 034,d1_off(a7),wda + ii_movep 054,d2,wda + ii_movep 074,d3,wda + ii_movep 094,d4,wda + ii_movep 0b4,d5,wda + ii_movep 0d4,d6,wda + ii_movep 0f4,d7,wda +//movep.l d(a0-7),d0-7 + ii_movep 018,d0_off(a7),lad + ii_movep 038,d1_off(a7),lad + ii_movep 058,d2,lad + ii_movep 078,d3,lad + ii_movep 098,d4,lad + ii_movep 0b8,d5,lad + ii_movep 0d8,d6,lad + ii_movep 0f8,d7,lad +//movep.l d0-7,d(a0-7) + ii_movep 01c,d0_off(a7),lda + ii_movep 03c,d1_off(a7),lda + ii_movep 05c,d2,lda + ii_movep 07c,d3,lda + ii_movep 09c,d4,lda + ii_movep 0bc,d5,lda + ii_movep 0dc,d6,lda + ii_movep 0fc,d7,lda +.endm +//--------------------------------------------------------------------------------------------- +ii_movep:.macro //1=code ziffer 1-3 2=register 3=art +ii_0x\18: +#ifdef halten_movep + halt +#endif + move.l a0_off(a7),a1 + ii_movep\3_up1 \2 +ii_0x\19: +#ifdef halten_movep + halt +#endif + move.l a1_off(a7),a1 + ii_movep\3_up1 \2 +ii_0x\1a: +#ifdef halten_movep + halt +#endif + move.l a2,a1 + ii_movep\3_up1 \2 +ii_0x\1b: +#ifdef halten_movep + halt +#endif + move.l a3,a1 + ii_movep\3_up1 \2 +ii_0x\1c: +#ifdef halten_movep + halt +#endif + move.l a4,a1 + ii_movep\3_up1 \2 +ii_0x\1d: +#ifdef halten_movep + halt +#endif + move.l a5,a1 + ii_movep\3_up1 \2 +ii_0x\1e: +#ifdef halten_movep + halt +#endif + move.l a6,a1 + ii_movep\3_up1 \2 +ii_0x\1f: +#ifdef halten_movep + halt +#endif + move.l usp,a1 + ii_movep\3_up1 \2 +.endm + +ii_movepwad_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.b (a1),d0 + lsl.l #8,d0 + move.b 2(a1,d1.l),d0 + move.w d0,\1 + ii_end +.endm + +ii_movepwda_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.w \1,d0 + move.b d0,2(a1) + lsr.l #8,d0 + move.b d0,(a1) + ii_end +.endm + +ii_moveplad_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.b (a1),d0 + lsl.l #8,d0 + move.b 2(a1),d0 + lsl.l #8,d0 + move.b 4(a1),d0 + lsl.l #8,d0 + move.b 6(a1),d0 + move.l d0,\1 + ii_end +.endm + +ii_moveplda_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.l \1,d0 + move.b d0,6(a1) + lsr.l #8,d0 + move.b d0,4(a1) + lsr.l #8,d0 + move.b d0,2(a1) + lsr.l #8,d0 + move.b d0,(a1) + ii_end +.endm diff --git a/BaS_GNU/sources/ii_op.h b/BaS_GNU/sources/ii_op.h new file mode 100644 index 0000000..a3fc0cf --- /dev/null +++ b/BaS_GNU/sources/ii_op.h @@ -0,0 +1,661 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_lset_op:.macro +//byt + ii_lset_opea \1,0 // dx,ax + ii_lset_opea \1,1 // (ax), (ax)+ + ii_lset_opea \1,2 // -(ax),d16(ax) + ii_lset_opeag \1,3 // d8(ax,dy) + lea table+0x\1\238*4,a0 + move.l #ii_0x\138,(a0)+ // xxx.w + move.l #ii_0x\139,(a0)+ // xxx.l +//word + ii_lset_opea \1,4 // dx,ax + ii_lset_opea \1,5 // (ax), (ax)+ + ii_lset_opea \1,6 // -(ax),d16(ax) + ii_lset_opeag \1,7 // d8(ax,dy) + lea table+0x\178*4,a0 + move.l #ii_0x\178,(a0)+ // xxx.w + move.l #ii_0x\179,(a0)+ // xxx.l +//long + ii_lset_opea \1,8 // dx,ax + ii_lset_opea \1,9 // (ax), (ax)+ + ii_lset_opea \1,a // -(ax),d16(ax) + ii_lset_opeag \1,b // d8(ax,dy) + lea table+0x\1b8*4,a0 + move.l #ii_0x\1b8,(a0)+ // xxx.w + move.l #ii_0x\1b9,(a0)+ // xxx.l + .endm + +ii_lset_opeag:.macro // 0x1120-0x1127 + lea table+0x\1\20*4,a0 + move.l #ii_0x\1\20,(a0)+ + move.l #ii_0x\1\21,(a0)+ + move.l #ii_0x\1\22,(a0)+ + move.l #ii_0x\1\23,(a0)+ + move.l #ii_0x\1\24,(a0)+ + move.l #ii_0x\1\25,(a0)+ + move.l #ii_0x\1\26,(a0)+ + move.l #ii_0x\1\27,(a0)+ + .endm; + +ii_lset_opeau:.macro // 0x1128-0x112f + lea table+0x\1\28*4,a0 + move.l #ii_0x\1\28,(a0)+ + move.l #ii_0x\1\29,(a0)+ + move.l #ii_0x\1\2a,(a0)+ + move.l #ii_0x\1\2b,(a0)+ + move.l #ii_0x\1\2c,(a0)+ + move.l #ii_0x\1\2d,(a0)+ + move.l #ii_0x\1\2e,(a0)+ + move.l #ii_0x\1\2f,(a0)+ + .endm; + +ii_lset_opea:.macro + ii_lset_opeag \1,\2 + ii_lset_opeau \1,\2 + .endm +/******************************************************/ +ii_op:.macro // 1=code 2=operation 3 = normal oder immediat/quick +// byt + opdx \1,\2,b,0,\3 // dx,ax + opia \1,\2,b,1,\3 // (ax),(ax)+ + opdia \1,\2,b,2,\3 // -(ax),d16(ax) + opd8a \1,\2,b,3,\3 // d8(ax),xxx +// word + opdx \1,\2,w,4,\3 // dx,ax + opia \1,\2,w,5,\3 // (ax),(ax)+ + opdia \1,\2,w,6,\3 // -(ax),d16(ax) + opd8a \1,\2,w,7,\3 // d8(ax),xxx +// long + opdx \1,\2,l,8,\3 // dx,ax + opia \1,\2,l,9,\3 // (ax),(ax)+ + opdia \1,\2,l,a,\3 // -(ax),d16(ax) + opd8a \1,\2,l,b,\3 // d8(ax),xxx + .endm +/******************************************************/ +// byt word long +/******************************************************/ +opdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + .ifc \3,b + op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 + .else + op\5smd \2,d0_off(a7),d0_off(a7),\3 + .endif + .endif +ii_0x\1\41: + .ifc \3,b + op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 + .else + op\5smd \2,d1_off(a7),d1_off(a7),\3 + .endif +.endif +ii_0x\1\42: + op\5smd \2,d2,d2,\3 +ii_0x\1\43: + op\5smd \2,d3,d3,\3 +ii_0x\1\44: + op\5smd \2,d4,d4,\3 +ii_0x\1\45: + op\5smd \2,d5,d5,\3 +ii_0x\1\46: + op\5smd \2,d6,d6,\3 +ii_0x\1\47: + op\5smd \2,d7,d7,\3 +//ax +ii_0x\1\48: + opa\5smd \2,a0_off(a7),a0_off(a7),\3 +ii_0x\1\49: + opa\5smd \2,a1_off(a7),a1_off(a7),\3 +ii_0x\1\4a: + opa\5smd \2,a2,a2,\3 +ii_0x\1\4b: + opa\5smd \2,a3,a3,\3 +ii_0x\1\4c: + opa\5smd \2,a4,a4,\3 +ii_0x\1\4d: + opa\5smd \2,a5,a5,\3 +ii_0x\1\4e: + opa\5smd \2,a6,a6,\3 +ii_0x\1\4f: + opa\5smd \2,usp,usp,\3 +.endm; +//----------------------------------------------- +opia: .macro // (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +//(ax) +ii_0x\1\40: + op\5sia \2,a0_off(a7),(a1),(a1),\3 +ii_0x\1\41: + op\5sia \2,a1_off(a7),(a1),(a1),\3 +ii_0x\1\42: + op\5smd \2,(a2),(a2),\3 +ii_0x\1\43: + op\5smd \2,(a3),(a3),\3 +ii_0x\1\44: + op\5smd \2,(a4),(a4),\3 +ii_0x\1\45: + op\5smd \2,(a5),(a5),\3 +ii_0x\1\46: + op\5smd \2,(a6),(a6),\3 +ii_0x\1\47: + op\5sia \2,usp,(a1),(a1),\3 +//(ax)+ +ii_0x\1\48: + op\5sia \2,a0_off(a7),(a1),(a1)+,\3 +ii_0x\1\49: + op\5sia \2,a1_off(a7),(a1),(a1)+,\3 +ii_0x\1\4a: + op\5smd \2,(a2),(a2)+,\3 +ii_0x\1\4b: + op\5smd \2,(a3),(a3)+,\3 +ii_0x\1\4c: + op\5smd \2,(a4),(a4)+,\3 +ii_0x\1\4d: + op\5smd \2,(a5),(a5)+,\3 +ii_0x\1\4e: + op\5smd \2,(a6),(a6)+,\3 +ii_0x\1\4f: + op\5sia \2,usp,(a1),(a1)+,\3 +.endm; +//----------------------------------------------- +opdia: .macro // -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + op\5sia \2,a0_off(a7),-(a1),(a1),\3 +ii_0x\1\41: + op\5sia \2,a1_off(a7),-(a1),(a1),\3 +ii_0x\1\42: + op\5smd \2,-(a2),(a2),\3 +ii_0x\1\43: + op\5smd \2,-(a3),(a3),\3 +ii_0x\1\44: + op\5smd \2,-(a4),(a4),\3 +ii_0x\1\45: + op\5smd \2,-(a5),(a5),\3 +ii_0x\1\46: + op\5smd \2,-(a6),(a6),\3 +ii_0x\1\47: + op\5sia \2,usp,-(a1),(a1),\3 + +ii_0x\1\48: + op\5sd16a \2,a0_off(a7),\3 +ii_0x\1\49: + op\5sd16a \2,a1_off(a7),\3 +ii_0x\1\4a: + op\5sd16a \2,a2,\3 +ii_0x\1\4b: + op\5sd16a \2,a3,\3 +ii_0x\1\4c: + op\5sd16a \2,a4,\3 +ii_0x\1\4d: + op\5sd16a \2,a5,\3 +ii_0x\1\4e: + op\5sd16a \2,a6,\3 +ii_0x\1\4f: + op\5sd16a \2,usp,\3 +.endm; +//----------------------------------------------- +opd8a: .macro // d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + op\5sd8a \2,a0_off(a7),\3 +ii_0x\1\41: + op\5sd8a \2,a1_off(a7),\3 +ii_0x\1\42: + op\5sd8a \2,a2,\3 +ii_0x\1\43: + op\5sd8a \2,a3,\3 +ii_0x\1\44: + op\5sd8a \2,a4,\3 +ii_0x\1\45: + op\5sd8a \2,a5,\3 +ii_0x\1\46: + op\5sd8a \2,a6,\3 +ii_0x\1\47: + op\5sd8a \2,usp,\3 + +ii_0x\1\48: + op\5sxx \2,\3,w +ii_0x\1\49: + op\5sxx \2,\3,l +.endm; +//----------------------------------------------- +opnsmd:.macro // direct dx: 1=operation 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opansmd:.macro // direct ax: 1=operation 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d1 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end +.endm; + +opnsia:.macro // indirect: 1=operation 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opnsd16a:.macro // indirect: 1=operation 2=adress register 3=size +#ifdef halten_op + halt +#endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opnsd8a:.macro // indirect: 1=operation 2=adress register 3=size +#ifdef halten_op + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opnsxx:.macro // indirect: 1=operation 2=size 3=size adresse +#ifdef halten_op + halt +#endif + +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif + move.\3 (a0)+,a1 + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; +//*******************************************************************************3 +opismd:.macro // immediate dx: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\4 d1,\3 +.endif + ii_end +.endm; + +opaismd:.macro // immediate ax: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d0,d1 +.ifnc \1,cmp.l +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif +.endif + ii_end +.endm; + +opisia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + +.ifc \5,l + move.l (a0)+,d0 +.else + .ifc \5,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\5 d1,\4 +.endif + ii_end +.endm; + +opisd16a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + +.ifc \3,l + move.l (a0)+,d0 +.else + .ifc \3,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\3 d1,(a1) +.endif + ii_end + .endm; + +opisd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + +.ifc \3,l + move.l (a0)+,d0 +.else + .ifc \3,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\3 d1,(a1) +.endif + ii_end + .endm; + +opisxx:.macro // immediate: 1=opieration 2=size 3=size adresse +.ifc \2,l + move.l (a0)+,d0 +.else + .ifc \2,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\2 d1,(a1) +.endif + ii_end + .endm; +//*******************************************************************************3 +opqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opaqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 ,d1 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end + .endm; + +opqsia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opqsd16a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opqsd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opqsxx:.macro // quick: 1=opieration 2=size 3=size adresse +#ifdef halten_op + halt +#endif + + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; diff --git a/BaS_GNU/sources/ii_opc.h b/BaS_GNU/sources/ii_opc.h new file mode 100644 index 0000000..8b887ce --- /dev/null +++ b/BaS_GNU/sources/ii_opc.h @@ -0,0 +1,263 @@ +/*****************************************************************************************/ +// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax +// zusammen mit op.h +/*****************************************************************************************/ +ii_lset_opc:.macro + ii_lset_opeag \1,c // dx,ax + ii_lset_opea \1,d // (ax), (ax)+ + ii_lset_opea \1,e // -(ax),d16(ax) + ii_lset_opeag \1,f // d8(ax,dy) + lea table+0x\1b8*4,a0 + move.l #ii_0x\1b8,(a0)+ // xxx.w + move.l #ii_0x\1b9,(a0)+ // xxx.l + .endm + +/******************************************************/ +ii_opc:.macro // 1=code 2=operation 3 = normal oder immediat + opcdx \1,\2,l,c,\3 // dx,ax + opia \1,\2,l,d,\3 // (ax),(ax)+ + opdia \1,\2,l,e,\3 // -(ax),d16(ax) + opd8a \1,\2,l,f,\3 // d8(ax),xxx + .endm +//*******************************************************************************3 +/******************************************************/ +// byt word long +/******************************************************/ +opcdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: +#ifdef halten_opc + halt +#endif + .ifc \3,b + op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 + .else + op\5smd \2,d0_off(a7),d0_off(a7),\3 + .endif + .endif +ii_0x\1\41: + .ifc \3,b + op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 + .else + op\5smd \2,d1_off(a7),d1_off(a7),\3 + .endif +.endif +ii_0x\1\42: + op\5smd \2,d2,d2,\3 +ii_0x\1\43: + op\5smd \2,d3,d3,\3 +ii_0x\1\44: + op\5smd \2,d4,d4,\3 +ii_0x\1\45: + op\5smd \2,d5,d5,\3 +ii_0x\1\46: + op\5smd \2,d6,d6,\3 +ii_0x\1\47: + op\5smd \2,d7,d7,\3 +.endm +//----------------------------------------------------- +opcsmd:.macro // dx: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opacsmd:.macro // ax: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d1 + set_cc0 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end + .endm; + +opcsia:.macro // (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opcsd16a:.macro // d16(ax): 1=opieration 2=adress register 3=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opcsd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opcsxx:.macro // indirect: 1=opieration 2=size 3=size adresse +#ifdef halten_opc + halt +#endif + +.ifc \2,l + move.l (a0)+,d0 +.else + .ifc \2,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; From 5c362a08d2390efb034a17ed1b97ca075ad1fe86 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 08:54:21 +0000 Subject: [PATCH 044/276] replaced by the same file ".S" (instead of ".s") --- BaS_GNU/sources/supervisor.s | 585 ----------------------------------- 1 file changed, 585 deletions(-) delete mode 100644 BaS_GNU/sources/supervisor.s diff --git a/BaS_GNU/sources/supervisor.s b/BaS_GNU/sources/supervisor.s deleted file mode 100644 index 29cd97f..0000000 --- a/BaS_GNU/sources/supervisor.s +++ /dev/null @@ -1,585 +0,0 @@ -/********************************************************/ -/* user/supervisor handler -/********************************************************/ - -.include "startcf.h" - -.extern _rt_cacr; -.extern _rt_mod; -.extern _rt_ssp; -.extern _rt_usp; -.extern ___MMUBAR - -/* Register read/write macros */ -#define MCF_MMU_MMUCR ___MMUBAR -#define MCF_MMU_MMUOR ___MMUBAR+0x04 -#define MCF_MMU_MMUSR ___MMUBAR+0x08 -#define MCF_MMU_MMUAR ___MMUBAR+0x10 -#define MCF_MMU_MMUTR ___MMUBAR+0x14 -#define MCF_MMU_MMUDR ___MMUBAR+0x18 - -.public _privileg_violation -.public cpusha - -.text -_privileg_violation: - move.w #0x2700,sr - lea -12(a7),a7 - movem.l d0/a0/a5,(a7) -#ifndef cf_stack - lea 0x52f0,a0 - move.l #0x20,(a0) // set auf 68030 -#endif - lea _rt_mod,a0 // zugriff setzen - tst.b (a0) // vom rt_supervisormodus? - bne pv_work // ja-> -// tatsächlich privileg violation - mov3q.l #-1,(a0) // sr_mod setzen - move.l usp,a5 // usp holen - move.l a5,8(a0) // sichern - move.l 4(a0),a5 // rt_ssp holen -#ifdef cf_stack - move.l 16(a7),-(a5) // pc verschieben - move.l 12(a7),-(a5) // sr verschieben - bset #5,2(a5) // auf super setzen -#else - move.w 12(a7),-(a5) // vector nr. - move.l 16(a7),-(a5) // pc verschieben - move.w 14(a7),-(a5) // sr verschieben - bset #5,(a5) // auf super -#endif - move.l a5,usp - move.l 12(a0),a5 // rt_vbr - lea 0x18(a5),a5 // vector - move.l (a5),16(a7) // vector privileg violation - movem.l (a7),d0/a0/a5 // register zurück - lea 12(a7),a7 - rte -// privileg violation -pv_work: - move.l 16(a7),a5 // fault pc - move.b (a5),d0 // fault code - cmp.b #0x4e,d0 // 1.byt 0x4e - beq pv_4e // ja-> - cmp.b #0x46,d0 // 1.byt 0x46 - beq pv_46 // ja-> - cmp.b #0x40,d0 // 1.byt 0x40 - beq pv_40 // ja-> - cmp.b #0xf4,d0 // 0xf4? - beq pv_f4 - cmp.b #0xf3,d0 // 0xf3? - beq pv_f3 -// hierher sollt man nicht kommen - nop - halt - nop -// code 0x4exx ******************************************** -pv_4e: - move.b 1(a5),d0 - cmp.b #0x73,d0 //rte? - beq pv_rte //ja-> - cmp.b #0x72,d0 //stop? - beq pv_stop //ja-> - cmp.b #0x7B,d0 //movec? - beq pv_movec //ja-> -// move usp - btst #3,d0 // to or from - bne pv_usp_to_ax // usp -> ax -// move ax->usp - cmp.b #0x60,d0 //movec? - beq pv_a0_usp //ja-> - cmp.b #0x61,d0 //movec? - beq pv_a1_usp //ja-> - cmp.b #0x62,d0 //movec? - beq pv_a2_usp //ja-> - cmp.b #0x63,d0 //movec? - beq pv_a3_usp //ja-> - cmp.b #0x64,d0 //movec? - beq pv_a4_usp //ja-> - cmp.b #0x65,d0 //movec? - beq pv_a5_usp //ja-> - cmp.b #0x66,d0 //movec? - beq pv_a6_usp //ja-> - halt - bra pv_a7_usp //ja-> -// move usp->ax -pv_usp_to_ax: - move.l 8(a0),a5 //rt_usp holen - cmp.b #0x68,d0 //movec? - beq pv_usp_a0 //ja-> - cmp.b #0x69,d0 //movec? - beq pv_usp_a1 //ja-> - cmp.b #0x6a,d0 //movec? - beq pv_usp_a2 //ja-> - cmp.b #0x6b,d0 //movec? - beq pv_usp_a3 //ja-> - cmp.b #0x6c,d0 //movec? - beq pv_usp_a4 //ja-> - cmp.b #0x6d,d0 //movec? - beq pv_usp_a5 //ja-> - cmp.b #0x6e,d0 //movec? - beq pv_usp_a6 //ja-> -// usp->a7 - move.l a5,4(a0) // rt usp -> rt ssp - move.l a5,usp // und setzen - bra pv_usp_ax -// a0->usp -pv_a0_usp: move.l 4(a7),a5 - bra pv_ax_usp -// a1->usp -pv_a1_usp: move.l a1,a5 - bra pv_ax_usp -// a2->usp -pv_a2_usp: move.l a2,a5 - bra pv_ax_usp -// a3->usp -pv_a3_usp: move.l a3,a5 - bra pv_ax_usp -// a4->usp -pv_a4_usp: move.l a4,a5 - bra pv_ax_usp -// a5->usp -pv_a5_usp: move.l 8(a7),a5 - bra pv_ax_usp -// a6->usp -pv_a6_usp: move.l a6,a5 - bra pv_ax_usp -// a7->usp -pv_a7_usp: move.l 4(a0),a5 // rt_ssp -> a5 -pv_ax_usp: - move.l a5,8(a0) // usp -> rt_usp - addq.l #2,16(a7) // next - movem.l (a7),d0/a0/a5 // register zurück - lea 12(a7),a7 - rte -// usp->a0 -pv_usp_a0: - move.l a5,4(a7) - bra pv_usp_ax -pv_usp_a1: - move.l a5,a1 - bra pv_usp_ax -pv_usp_a2: - move.l a5,a2 - bra pv_usp_ax -pv_usp_a3: - move.l a5,a3 - bra pv_usp_ax -pv_usp_a4: - move.l a5,a4 - bra pv_usp_ax -pv_usp_a5: - move.l a5,8(a7) - bra pv_usp_ax -pv_usp_a6: - move.l a5,a6 -pv_usp_ax: - addq.l #2,16(a7) // next - movem.l (a7),d0/a0/a5 // register zurück - lea 12(a7),a7 - rte -// rte -pv_rte: - move.l usp,a5 -#ifdef cf_stack - move.l (a5)+,12(a7) // sr verschieben - move.l (a5)+,16(a7) // pc verschieben -#else - move.w (a5)+,14(a7) // sr verschieben - move.l (a5)+,16(a7) // pc verschieben - move.w (a5)+,12(a7) // vector -#endif - bclr #5,14(a7) // war es von super? - bne pv_rte_sup // ja-> - clr.l (a0) // rt_mod auf user - move.l a5,4(a0) // rt_ssp sichern - move.l 8(a0),a5 // rt_usp holen -pv_rte_sup: - move.l a5,usp // usp setzen - movem.l (a7),d0/a0/a5 // register zurück - lea 12(a7),a7 - rte -// stop -pv_stop: - move.b 2(a5),d0 // sr wert - and.l #0x0700,d0 // int mask - cmp.w #0x700,d0 - beq stop7 - cmp.w #0x600,d0 - beq stop6 - cmp.w #0x500,d0 - beq stop5 - cmp.w #0x400,d0 - beq stop4 - cmp.w #0x300,d0 - beq stop3 - cmp.w #0x200,d0 - beq stop2 - cmp.w #0x100,d0 - beq stop1 - stop #0x2000 - bra stop_weiter -stop1: - stop #0x2100 - bra stop_weiter -stop2: - stop #0x2200 - bra stop_weiter -stop3: - stop #0x2300 - bra stop_weiter -stop4: - stop #0x2400 - bra stop_weiter -stop5: - stop #0x2500 - bra stop_weiter -stop6: - stop #0x2600 - bra stop_weiter -stop7: - stop #0x2700 -stop_weiter: - addq.l #4,16(a7) // next - movem.l (a7),d0/a0/a5 // register zurück - lea 12(a7),a7 - rte -// movec ??????? -pv_movec: - move.w 2(a5),d0 // 2.word holen - and.l #0xf000,d0 - btst #15,d0 // addressregister? - bne pv_movec_ax // ja-> - tst.w d0 // d0? - bne pvm_d1 // nein-> - move.l (a7),-(a7) // d0 holen und sichern - bra pvm_me -pvm_d1: - cmp.w #0x1000,d0 // d1? - bne pvm_d2 // nein-> - move.l d1,-(a7) // d1 holen und sichern - bra pvm_me // fertig machen -pvm_d2: - cmp.w #0x2000,d0 // d1? - bne pvm_d3 // nein-> - move.l d2,-(a7) // d2 holen und sichern - bra pvm_me // fertig machen -pvm_d3: - cmp.w #0x3000,d0 // d1? - bne pvm_d4 // nein-> - move.l d3,-(a7) // d3 holen und sichern - bra pvm_me // fertig machen -pvm_d4: - cmp.w #0x4000,d0 // d1? - bne pvm_d5 // nein-> - move.l d4,-(a7) // d4 holen und sichern - bra pvm_me // fertig machen -pvm_d5: - cmp.w #0x5000,d0 // d1? - bne pvm_d6 // nein-> - move.l d5,-(a7) // d5 holen und sichern - bra pvm_me // fertig machen -pvm_d6: - cmp.w #0x6000,d0 // d1? - bne pvm_d7 // nein-> - move.l d6,-(a7) // d6 holen und sichern - bra pvm_me // fertig machen -pvm_d7: - move.l d7,-(a7) // d7 holen und sichern - bra pvm_me // fertig machen -pv_movec_ax: - cmp.w #0x8000,d0 // a0? - bne pvm_a1 // nein-> - move.l 4(a7),-(a7) // a0 holen und sichern - bra pvm_me // fertig machen -pvm_a1: - cmp.w #0x9000,d0 // a0? - bne pvm_a2 // nein-> - move.l a1,-(a7) // a1 holen und sichern - bra pvm_me // fertig machen -pvm_a2: - cmp.w #0xa000,d0 // a0? - bne pvm_a3 // nein-> - move.l a2,-(a7) // a2 holen und sichern - bra pvm_me // fertig machen -pvm_a3: - cmp.w #0xb000,d0 // a0? - bne pvm_a4 // nein-> - move.l a3,-(a7) // a3 holen und sichern - bra pvm_me // fertig machen -pvm_a4: - cmp.w #0xc000,d0 // a0? - bne pvm_a5 // nein-> - move.l a4,-(a7) // a4 holen und sichern - bra pvm_me // fertig machen -pvm_a5: - cmp.w #0xd000,d0 // a0? - bne pvm_a6 // nein-> - move.l 8(a7),-(a7) // a5 holen und sichern - bra pvm_me // fertig machen -pvm_a6: - cmp.w #0xe000,d0 // a0? - bne pvm_a7 // nein-> - move.l a6,-(a7) // a6 holen und sichern - bra pvm_me // fertig machen -pvm_a7: - move.l 4(a7),-(a7) // a7 holen und sichern -pvm_me: - move.w 2(a5),d0 // 2.word holen - andi.l #0xf,d0 // nur letzte 4 bits - move.l (a7)+,8(a0,d0*4) // start bei +8, *4 weil long - jsr cpusha // gesammten cache flushen - rte -// code 0x46xx ***************************************** -pv_46: - move.b 1(a5),d0 - cmp.b #0xfc,d0 //#d16->sr - beq im_sr //ja-> -//move dx->sr (sr und rt_mod ist supervisor sonst wäre es privileg violation - cmp.b #0xc0,d0 //d0->sr? - bne d1_sr //nein-> - move.w 2(a7),d0 //hier ist d0 gesichert - bra d0_sr -d1_sr: - cmp.b #0xc1,d0 //d1->sr? - bne d2_sr //nein-> - move.w d1,d0 - bra d0_sr -d2_sr: - cmp.b #0xc2,d0 //d2->sr? - bne d3_sr - move.w d2,d0 - bra d0_sr -d3_sr: - cmp.b #0xc3,d0 //d3->sr? - bne d4_sr - move.w d3,d0 - bra d0_sr -d4_sr: - cmp.b #0xc4,d0 //d4->sr? - bne d5_sr - move.w d4,d0 - bra d0_sr -d5_sr: - cmp.b #0xc5,d0 //d5->sr? - bne d6_sr - move.w d5,d0 - bra d0_sr -d6_sr: - cmp.b #0xc6,d0 //d6->sr? - bne d7_sr - move.w d6,d0 - bra d0_sr -d7_sr: - move.w d7,d0 // sonst d7->sr -d0_sr: - addq.l #2,16(a7) // next - bra pv_set_sr_end // fertig machen -// move #xxxx,sr -im_sr: - addq.l #4,16(a7) // next - move.w 2(a5),d0 // data -pv_set_sr_end: - bclr #13,d0 // war super? - bne pv_sre2 // ja -> - clr.l (a0) - move.l usp,a5 // usp - move.l a5,4(a0) // rt_ssp speichern - move.l 8(a0),a5 // rt_usp holen - move.l a5,usp // setzen -pv_sre2: - move.w d0,14(a7) // sr setzen - movem.l (a7),d0/a0/a5 // register zurück - lea 12(a7),a7 - rte -// code 0x40xx ***************************************** -pv_40: - move.b 1(a5),d0 // 2.byt - cmp.b #0xe7,d0 - beq pv_strldsr -// move sr->dx - move.l 12(a7),a5 // sr holen - tst.b (a0) // super? - beq pv_40_user // nein? - lea 0x2000(a5),a5 // super zuaddieren -pv_40_user: - cmp.b #0xc0,d0 - bne nsr_d1 - move.w a5,2(a7) - bra sr_dx_end -nsr_d1: - cmp.b #0xc1,d0 - bne nsr_d2 - move.w a5,d1 - bra sr_dx_end -nsr_d2: - cmp.b #0xc2,d0 - bne nsr_d3 - move.w a5,d2 - bra sr_dx_end -nsr_d3: - cmp.b #0xc3,d0 - bne nsr_d4 - move.w a5,d3 - bra sr_dx_end -nsr_d4: - cmp.b #0xc4,d0 - bne nsr_d5 - move.w a5,d4 - bra sr_dx_end -nsr_d5: - cmp.b #0xc5,d0 - bne nsr_d6 - move.w a5,d5 - bra sr_dx_end -nsr_d6: - cmp.b #0xc6,d0 - bne nsr_d7 - move.w a5,d6 - bra sr_dx_end -nsr_d7: - move.w a5,d7 - halt -sr_dx_end: - addq.l #2,16(a7) // next - movem.l (a7),d0/a0/a5 // register zurück - lea 12(a7),a7 - rte -// strldsr -pv_strldsr: - nop - halt - nop -// code 0xf4xx *********************************** -pv_f4: - addq.l #2,16(a7) // next instr - move.b 1(a5),d0 // 2.byt - bsr pv_ax_a0 // richtiges register - move.b 1(a5),d0 // 2.byt - cmp.b #0x30,d0 // >0xf430 - blo pv_intouch -// cpushl - cpushl bc,(a0) - movem.l (a7),d0/a0/a5 - lea 12(a7),a7 - rte -pv_intouch: - intouch (a0) - movem.l (a7),d0/a0/a5 - lea 12(a7),a7 - rte -// subroutine register ax->a0 -pv_ax_a0: - and.l #0x7,d0 // nur register nummer - subq.l #1,d0 - bmi pv_a0_a0 - subq.l #1,d0 - bmi pv_a1_a0 - subq.l #1,d0 - bmi pv_a2_a0 - subq.l #1,d0 - bmi pv_a3_a0 - subq.l #1,d0 - bmi pv_a4_a0 - subq.l #1,d0 - bmi pv_a5_a0 - subq.l #1,d0 - bmi pv_a6_a0 - move.l a7,a0 - rts -pv_a0_a0: - move.l 8(a7),a0 - rts -pv_a1_a0: - move.l a1,a0 - rts -pv_a2_a0: - move.l a2,a0 - rts -pv_a3_a0: - move.l a3,a0 - rts -pv_a4_a0: - move.l a4,a0 - rts -pv_a5_a0: - move.l 12(a7),a0 - rts -pv_a6_a0: - move.l a6,a0 - rts -// code 0xf4xx *********************************** -pv_f3: - addq.l #2,16(a7) // next instr - move.b 1(a5),d0 // 2. byt - cmp.b #0x40,d0 - bgt pv_frestore -//fsave (ax) oder d16(ax) - jsr pv_ax_a0 // richtiges register holen - move.b 1(a5),d0 - cmp.b #0x20,d0 -// +d16 - blt pv_f3_ax - addq.l #2,16(a7) // next instr - clr.l d0 - move.w 2(a0),d0 // d16 - add.l d0,a0 -pv_f3_ax: - fsave (a0) - movem.l (a7),d0/a0/a5 - lea 12(a7),a7 - rte -pv_frestore: - cmp.b #0x7a,d0 - beq pv_f_d16pc -// frestore (ax) oder d16(ax) - jsr pv_ax_a0 // richtiges register holen - move.b 1(a5),d0 - cmp.b #0x60,d0 - blt pv_frestore_ax -pv_fend: - addq.l #2,16(a7) // next instr - clr.l d0 - move.w 2(a0),d0 // d16 - add.l d0,a0 -pv_frestore_ax: - frestore (a0) - movem.l (a7),d0/a0/a5 - lea 12(a7),a7 - rte -// frestore d16(pc) -pv_f_d16pc: - move.l 16(a7),a0 // pc holen - bra pv_fend -//***************************************************** -cpusha: - lea -16(a7),a7 - movem.l d0-d2/a0,(a7) // register sichern - move sr,d2 - nop - move #0x2700,sr // no interrupts - - clr.l d0 - clr.l d1 - move.l d0,a0 -cfa_setloop: - cpushl bc,(a0) // flush - lea 0x10(a0),a0 // index+1 - addq.l #1,d1 // index+1 - cmpi.w #512,d1 // alle sets? - bne cfa_setloop // nein-> - clr.l d1 - addq.l #1,d0 - move.l d0,a0 - cmpi.w #4,d0 // all ways? - bne cfa_setloop // nein-> - nop - move.l _rt_cacr,d0 // holen - movec d0,cacr // setzen - move.w d2,sr // alte interrupt maske - movem.l (a7),d0-d2/a0 // register zurück - lea 16(a7),a7 - - rts -//*******************************************************33 - From bf5cda3c287e3aa44af9a6ea38ad827285f9d8ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 17:04:34 +0000 Subject: [PATCH 045/276] --- BaS_GNU/sources/ewf.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/BaS_GNU/sources/ewf.S b/BaS_GNU/sources/ewf.S index 5a4363b..7f5a644 100644 --- a/BaS_GNU/sources/ewf.S +++ b/BaS_GNU/sources/ewf.S @@ -2,7 +2,7 @@ // extension word format: a0 zeigt auf code, in a1 ist ay, d0/d1 wird zerstört //------------------------------------------------------------------------------ -#include "ii_macro.h" +.include "ii_macro.h" .global ewf //----------------------------------------------------------- @@ -14,8 +14,8 @@ ewferr: //----------------------------------------------------------- ewf: mvz.b (a0)+,d1 // 1. byt ewf - mvs.w ewf_table-.-2(pc,d1*2),d1 - jmp ewf_table-.-2(pc,d1) + mvs.w ewf_table-*-2(pc,d1*2),d1 + jmp ewf_table-*-2(pc,d1) ewf_table: .short ewf_00-ewf_table,ewf_01-ewf_table,ewf_02-ewf_table,ewf_03-ewf_table .short ewf_04-ewf_table,ewf_05-ewf_table,ewf_06-ewf_table,ewf_07-ewf_table @@ -1311,8 +1311,8 @@ ewf_ff: //-------------------------------------------------------------------- ewf_full: mvz.b (a0)+,d1 - mvs.w ewff_table-.-2(pc,d1*2),d1 - jmp ewff_table-.-2(pc,d1) + mvs.w ewff_table-*-2(pc,d1*2),d1 + jmp ewff_table-*-2(pc,d1) ewff_table: .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //00 .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table @@ -1561,5 +1561,5 @@ ewff_lln: add.l d0,a1 add.l d0,a1 rts - +/**************************************************************************************************************** From a9ae4dc25ce494df7bc2a7c7d9234d4efb5341dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 17:16:08 +0000 Subject: [PATCH 046/276] wrong includefile syntax corrected --- BaS_GNU/sources/ewf.S | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/BaS_GNU/sources/ewf.S b/BaS_GNU/sources/ewf.S index 7f5a644..6046a63 100644 --- a/BaS_GNU/sources/ewf.S +++ b/BaS_GNU/sources/ewf.S @@ -2,7 +2,7 @@ // extension word format: a0 zeigt auf code, in a1 ist ay, d0/d1 wird zerstört //------------------------------------------------------------------------------ -.include "ii_macro.h" +#include "ii_macro.h" .global ewf //----------------------------------------------------------- @@ -14,8 +14,8 @@ ewferr: //----------------------------------------------------------- ewf: mvz.b (a0)+,d1 // 1. byt ewf - mvs.w ewf_table-*-2(pc,d1*2),d1 - jmp ewf_table-*-2(pc,d1) + mvs.w ewf_table-.-2(pc,d1*2),d1 + jmp ewf_table-.-2(pc,d1) ewf_table: .short ewf_00-ewf_table,ewf_01-ewf_table,ewf_02-ewf_table,ewf_03-ewf_table .short ewf_04-ewf_table,ewf_05-ewf_table,ewf_06-ewf_table,ewf_07-ewf_table @@ -1311,8 +1311,8 @@ ewf_ff: //-------------------------------------------------------------------- ewf_full: mvz.b (a0)+,d1 - mvs.w ewff_table-*-2(pc,d1*2),d1 - jmp ewff_table-*-2(pc,d1) + mvs.w ewff_table-.-2(pc,d1*2),d1 + jmp ewff_table-.-2(pc,d1) ewff_table: .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //00 .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table @@ -1561,5 +1561,3 @@ ewff_lln: add.l d0,a1 add.l d0,a1 rts -/**************************************************************************************************************** - From 0cf76ab2caecd9961a94822a57ddcdbbeebfc331 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 17:16:43 +0000 Subject: [PATCH 047/276] --- BaS_GNU/.project | 4 - BaS_GNU/sources/ewf.s | 1565 ----------------------------------------- 2 files changed, 1569 deletions(-) delete mode 100644 BaS_GNU/sources/ewf.s diff --git a/BaS_GNU/.project b/BaS_GNU/.project index e715825..95d4b1c 100644 --- a/BaS_GNU/.project +++ b/BaS_GNU/.project @@ -29,10 +29,6 @@ org.eclipse.cdt.make.core.buildCommand make - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/BaS_GNU} - org.eclipse.cdt.make.core.cleanBuildTarget clean diff --git a/BaS_GNU/sources/ewf.s b/BaS_GNU/sources/ewf.s deleted file mode 100644 index 7f5a644..0000000 --- a/BaS_GNU/sources/ewf.s +++ /dev/null @@ -1,1565 +0,0 @@ -/*************************************************************************************************/ -// extension word format: a0 zeigt auf code, in a1 ist ay, d0/d1 wird zerstört -//------------------------------------------------------------------------------ - -.include "ii_macro.h" - -.global ewf -//----------------------------------------------------------- -.text -ewferr: - nop - halt - nop -//----------------------------------------------------------- -ewf: - mvz.b (a0)+,d1 // 1. byt ewf - mvs.w ewf_table-*-2(pc,d1*2),d1 - jmp ewf_table-*-2(pc,d1) -ewf_table: - .short ewf_00-ewf_table,ewf_01-ewf_table,ewf_02-ewf_table,ewf_03-ewf_table - .short ewf_04-ewf_table,ewf_05-ewf_table,ewf_06-ewf_table,ewf_07-ewf_table - .short ewferr-ewf_table,ewf_09-ewf_table,ewferr-ewf_table,ewf_0b-ewf_table - .short ewferr-ewf_table,ewf_0d-ewf_table,ewferr-ewf_table,ewf_0f-ewf_table - .short ewf_10-ewf_table,ewf_11-ewf_table,ewf_12-ewf_table,ewf_13-ewf_table - .short ewf_14-ewf_table,ewf_15-ewf_table,ewf_16-ewf_table,ewf_17-ewf_table - .short ewferr-ewf_table,ewf_19-ewf_table,ewferr-ewf_table,ewf_1b-ewf_table - .short ewferr-ewf_table,ewf_1d-ewf_table,ewferr-ewf_table,ewf_1f-ewf_table - .short ewf_20-ewf_table,ewf_21-ewf_table,ewf_22-ewf_table,ewf_23-ewf_table - .short ewf_24-ewf_table,ewf_25-ewf_table,ewf_26-ewf_table,ewf_27-ewf_table - .short ewferr-ewf_table,ewf_29-ewf_table,ewferr-ewf_table,ewf_2b-ewf_table - .short ewferr-ewf_table,ewf_2d-ewf_table,ewferr-ewf_table,ewf_2f-ewf_table - .short ewf_30-ewf_table,ewf_31-ewf_table,ewf_32-ewf_table,ewf_33-ewf_table - .short ewf_34-ewf_table,ewf_35-ewf_table,ewf_36-ewf_table,ewf_37-ewf_table - .short ewferr-ewf_table,ewf_39-ewf_table,ewferr-ewf_table,ewf_3b-ewf_table - .short ewferr-ewf_table,ewf_3d-ewf_table,ewferr-ewf_table,ewf_3f-ewf_table - .short ewf_40-ewf_table,ewf_41-ewf_table,ewf_42-ewf_table,ewf_43-ewf_table - .short ewf_44-ewf_table,ewf_45-ewf_table,ewf_46-ewf_table,ewf_47-ewf_table - .short ewferr-ewf_table,ewf_49-ewf_table,ewferr-ewf_table,ewf_4b-ewf_table - .short ewferr-ewf_table,ewf_4d-ewf_table,ewferr-ewf_table,ewf_4f-ewf_table - .short ewf_50-ewf_table,ewf_51-ewf_table,ewf_52-ewf_table,ewf_53-ewf_table - .short ewf_54-ewf_table,ewf_55-ewf_table,ewf_56-ewf_table,ewf_57-ewf_table - .short ewferr-ewf_table,ewf_59-ewf_table,ewferr-ewf_table,ewf_5b-ewf_table - .short ewferr-ewf_table,ewf_5d-ewf_table,ewferr-ewf_table,ewf_5f-ewf_table - .short ewf_60-ewf_table,ewf_61-ewf_table,ewf_62-ewf_table,ewf_63-ewf_table - .short ewf_64-ewf_table,ewf_65-ewf_table,ewf_66-ewf_table,ewf_67-ewf_table - .short ewferr-ewf_table,ewf_69-ewf_table,ewferr-ewf_table,ewf_6b-ewf_table - .short ewferr-ewf_table,ewf_6d-ewf_table,ewferr-ewf_table,ewf_6f-ewf_table - .short ewf_70-ewf_table,ewf_71-ewf_table,ewf_72-ewf_table,ewf_73-ewf_table - .short ewf_74-ewf_table,ewf_75-ewf_table,ewf_76-ewf_table,ewf_77-ewf_table - .short ewferr-ewf_table,ewf_79-ewf_table,ewferr-ewf_table,ewf_7b-ewf_table - .short ewferr-ewf_table,ewf_7d-ewf_table,ewferr-ewf_table,ewf_7f-ewf_table - .short ewf_80-ewf_table,ewf_81-ewf_table,ewf_82-ewf_table,ewf_83-ewf_table - .short ewf_84-ewf_table,ewf_85-ewf_table,ewf_86-ewf_table,ewf_87-ewf_table - .short ewferr-ewf_table,ewf_89-ewf_table,ewferr-ewf_table,ewf_8b-ewf_table - .short ewferr-ewf_table,ewf_8d-ewf_table,ewferr-ewf_table,ewf_8f-ewf_table - .short ewf_90-ewf_table,ewf_91-ewf_table,ewf_92-ewf_table,ewf_93-ewf_table - .short ewf_94-ewf_table,ewf_95-ewf_table,ewf_96-ewf_table,ewf_97-ewf_table - .short ewferr-ewf_table,ewf_99-ewf_table,ewferr-ewf_table,ewf_9b-ewf_table - .short ewferr-ewf_table,ewf_9d-ewf_table,ewferr-ewf_table,ewf_9f-ewf_table - .short ewf_a0-ewf_table,ewf_a1-ewf_table,ewf_a2-ewf_table,ewf_a3-ewf_table - .short ewf_a4-ewf_table,ewf_a5-ewf_table,ewf_a6-ewf_table,ewf_a7-ewf_table - .short ewferr-ewf_table,ewf_a9-ewf_table,ewferr-ewf_table,ewf_ab-ewf_table - .short ewferr-ewf_table,ewf_ad-ewf_table,ewferr-ewf_table,ewf_af-ewf_table - .short ewf_b0-ewf_table,ewf_b1-ewf_table,ewf_b2-ewf_table,ewf_b3-ewf_table - .short ewf_b4-ewf_table,ewf_b5-ewf_table,ewf_b6-ewf_table,ewf_b7-ewf_table - .short ewferr-ewf_table,ewf_b9-ewf_table,ewferr-ewf_table,ewf_bb-ewf_table - .short ewferr-ewf_table,ewf_bd-ewf_table,ewferr-ewf_table,ewf_bf-ewf_table - .short ewf_c0-ewf_table,ewf_c1-ewf_table,ewf_c2-ewf_table,ewf_c3-ewf_table - .short ewf_c4-ewf_table,ewf_c5-ewf_table,ewf_c6-ewf_table,ewf_c7-ewf_table - .short ewferr-ewf_table,ewf_c9-ewf_table,ewferr-ewf_table,ewf_cb-ewf_table - .short ewferr-ewf_table,ewf_cd-ewf_table,ewferr-ewf_table,ewf_cf-ewf_table - .short ewf_d0-ewf_table,ewf_d1-ewf_table,ewf_d2-ewf_table,ewf_d3-ewf_table - .short ewf_d4-ewf_table,ewf_d5-ewf_table,ewf_d6-ewf_table,ewf_d7-ewf_table - .short ewferr-ewf_table,ewf_d9-ewf_table,ewferr-ewf_table,ewf_db-ewf_table - .short ewferr-ewf_table,ewf_dd-ewf_table,ewferr-ewf_table,ewf_df-ewf_table - .short ewf_e0-ewf_table,ewf_e1-ewf_table,ewf_e2-ewf_table,ewf_e3-ewf_table - .short ewf_e4-ewf_table,ewf_e5-ewf_table,ewf_e6-ewf_table,ewf_e7-ewf_table - .short ewferr-ewf_table,ewf_e9-ewf_table,ewferr-ewf_table,ewf_eb-ewf_table - .short ewferr-ewf_table,ewf_ed-ewf_table,ewferr-ewf_table,ewf_ef-ewf_table - .short ewf_f0-ewf_table,ewf_f1-ewf_table,ewf_f2-ewf_table,ewf_f3-ewf_table - .short ewf_f4-ewf_table,ewf_f5-ewf_table,ewf_f6-ewf_table,ewf_f7-ewf_table - .short ewferr-ewf_table,ewf_f9-ewf_table,ewferr-ewf_table,ewf_fb-ewf_table - .short ewferr-ewf_table,ewf_fd-ewf_table,ewferr-ewf_table,ewf_ff-ewf_table -//d0.w * 1 -ewf_00: - mvs.b (a0)+,d1 - mvs.w d0_off+6(a7),d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_01: - mvs.w d0_off+6(a7),d0 - bra ewf_full -//d0.w * 2 -ewf_02: - mvs.b (a0)+,d1 - mvs.w d0_off+6(a7),d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_03: - mvs.w d0_off+6(a7),d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d0.w * 4 -ewf_04: - mvs.b (a0)+,d1 - mvs.w d0_off+6(a7),d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_05: - mvs.w d0_off+6(a7),d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d0.w * 8 -ewf_06: - mvs.b (a0)+,d1 - mvs.w d0_off+6(a7),d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_07: - mvs.w d0_off+6(a7),d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d0.l * 1 -ewf_09: - move.l d0_off+4(a7),d0 - bra ewf_full -//d0.l * 2 -ewf_0b: - move.l d0_off+4(a7),d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d0.l * 4 -ewf_0d: - move.l d0_off+4(a7),d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d0.l * 8 -ewf_0f: - move.l d0_off+4(a7),d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d1.w * 1 -ewf_10: - mvs.b (a0)+,d1 - mvs.w d1_off+6(a7),d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_11: - mvs.w d1_off+6(a7),d0 - bra ewf_full -//d1.w * 2 -ewf_12: - mvs.b (a0)+,d1 - mvs.w d1_off+6(a7),d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_13: - mvs.w d1_off+6(a7),d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d1.w * 4 -ewf_14: - mvs.b (a0)+,d1 - mvs.w d1_off+6(a7),d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_15: - mvs.w d1_off+6(a7),d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d1.w * 8 -ewf_16: - mvs.b (a0)+,d1 - mvs.w d1_off+6(a7),d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_17: - mvs.w d1_off+6(a7),d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d1.l * 1 -ewf_19: - move.l d1_off+4(a7),d0 - bra ewf_full -//d1.l * 2 -ewf_1b: - move.l d1_off+4(a7),d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d1.l * 4 -ewf_1d: - move.l d1_off+4(a7),d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d1.l * 8 -ewf_1f: - move.l d1_off+4(a7),d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d2.w * 1 -ewf_20: - mvs.b (a0)+,d1 - mvs.w d2,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_21: - mvs.w d2,d0 - bra ewf_full -//d2.w * 2 -ewf_22: - mvs.b (a0)+,d1 - mvs.w d2,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_23: - mvs.w d2,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d2.w * 4 -ewf_24: - mvs.b (a0)+,d1 - mvs.w d2,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_25: - mvs.w d2,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d2.w * 8 -ewf_26: - mvs.b (a0)+,d1 - mvs.w d2,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_27: - mvs.w d2,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d2.l * 1 -ewf_29: - move.l d2,d0 - bra ewf_full -//d2.l * 2 -ewf_2b: - move.l d2,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d2.l * 4 -ewf_2d: - move.l d2,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d2.l * 8 -ewf_2f: - move.l d2,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d3.w * 1 -ewf_30: - mvs.b (a0)+,d1 - mvs.w d3,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_31: - mvs.w d3,d0 - bra ewf_full -//d3.w * 2 -ewf_32: - mvs.b (a0)+,d1 - mvs.w d3,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_33: - mvs.w d3,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d3.w * 4 -ewf_34: - mvs.b (a0)+,d1 - mvs.w d3,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_35: - mvs.w d3,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d3.w * 8 -ewf_36: - mvs.b (a0)+,d1 - mvs.w d3,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_37: - mvs.w d3,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d3.l * 1 -ewf_39: - move.l d3,d0 - bra ewf_full -//d3.l * 3 -ewf_3b: - move.l d3,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d3.l * 4 -ewf_3d: - move.l d3,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d3.l * 8 -ewf_3f: - move.l d3,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d4.w * 1 -ewf_40: - mvs.b (a0)+,d1 - mvs.w d4,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_41: - mvs.w d4,d0 - bra ewf_full -//d4.w * 2 -ewf_42: - mvs.b (a0)+,d1 - mvs.w d4,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_43: - mvs.w d4,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d4.w * 4 -ewf_44: - mvs.b (a0)+,d1 - mvs.w d4,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_45: - mvs.w d4,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d4.w * 8 -ewf_46: - mvs.b (a0)+,d1 - mvs.w d4,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_47: - mvs.w d4,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d4.l * 1 -ewf_49: - move.l d4,d0 - bra ewf_full -//d4.l * 4 -ewf_4b: - move.l d4,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d4.l * 4 -ewf_4d: - move.l d4,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d4.l * 8 -ewf_4f: - move.l d4,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d5.w * 1 -ewf_50: - mvs.b (a0)+,d1 - mvs.w d5,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_51: - mvs.w d5,d0 - bra ewf_full -//d5.w * 2 -ewf_52: - mvs.b (a0)+,d1 - mvs.w d5,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_53: - mvs.w d5,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d5.w * 4 -ewf_54: - mvs.b (a0)+,d1 - mvs.w d5,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_55: - mvs.w d5,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d5.w * 8 -ewf_56: - mvs.b (a0)+,d1 - mvs.w d5,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_57: - mvs.w d5,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d5.l * 1 -ewf_59: - move.l d5,d0 - bra ewf_full -//d5.l * 5 -ewf_5b: - move.l d5,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d5.l * 4 -ewf_5d: - move.l d5,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d5.l * 8 -ewf_5f: - move.l d5,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d6.w * 1 -ewf_60: - mvs.b (a0)+,d1 - mvs.w d6,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_61: - mvs.w d6,d0 - bra ewf_full -//d6.w * 2 -ewf_62: - mvs.b (a0)+,d1 - mvs.w d6,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_63: - mvs.w d6,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d6.w * 4 -ewf_64: - mvs.b (a0)+,d1 - mvs.w d6,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_65: - mvs.w d6,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d6.w * 8 -ewf_66: - mvs.b (a0)+,d1 - mvs.w d6,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_67: - mvs.w d6,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d6.l * 1 -ewf_69: - move.l d6,d0 - bra ewf_full -//d6.l * 6 -ewf_6b: - move.l d6,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d6.l * 4 -ewf_6d: - move.l d6,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d6.l * 8 -ewf_6f: - move.l d6,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d7.w * 1 -ewf_70: - mvs.b (a0)+,d1 - mvs.w d7,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_71: - mvs.w d7,d0 - bra ewf_full -//d7.w * 2 -ewf_72: - mvs.b (a0)+,d1 - mvs.w d7,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_73: - mvs.w d7,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d7.w * 4 -ewf_74: - mvs.b (a0)+,d1 - mvs.w d7,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_75: - mvs.w d7,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d7.w * 8 -ewf_76: - mvs.b (a0)+,d1 - mvs.w d7,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_77: - mvs.w d7,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//d7.l * 1 -ewf_79: - move.l d7,d0 - bra ewf_full -//d7.l * 7 -ewf_7b: - move.l d7,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//d7.l * 4 -ewf_7d: - move.l d7,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//d7.l * 8 -ewf_7f: - move.l d7,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a0.w * 1 -ewf_80: - mvs.b (a0)+,d1 - mvs.w a0_off+6(a7),d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_81: - mvs.w a0_off+6(a7),d0 - bra ewf_full -//a0.w * 2 -ewf_82: - mvs.b (a0)+,d1 - mvs.w a0_off+6(a7),d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_83: - mvs.w a0_off+6(a7),d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a0.w * 4 -ewf_84: - mvs.b (a0)+,d1 - mvs.w a0_off+6(a7),d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_85: - mvs.w a0_off+6(a7),d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a0.w * 8 -ewf_86: - mvs.b (a0)+,d1 - mvs.w a0_off+6(a7),d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_87: - mvs.w a0_off+6(a7),d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a0.l * 1 -ewf_89: - move.l a0_off+4(a7),d0 - bra ewf_full -//a0.l * 2 -ewf_8b: - move.l a0_off+4(a7),d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a0.l * 4 -ewf_8d: - move.l a0_off+4(a7),d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a0.l * 8 -ewf_8f: - move.l a0_off+4(a7),d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a1.w * 1 -ewf_90: - mvs.b (a0)+,d1 - mvs.w a1_off+6(a7),d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_91: - mvs.w a1_off+6(a7),d0 - bra ewf_full -//a1.w * 2 -ewf_92: - mvs.b (a0)+,d1 - mvs.w a1_off+6(a7),d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_93: - mvs.w a1_off+6(a7),d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a1.w * 4 -ewf_94: - mvs.b (a0)+,d1 - mvs.w a1_off+6(a7),d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_95: - mvs.w a1_off+6(a7),d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a1.w * 8 -ewf_96: - mvs.b (a0)+,d1 - mvs.w a1_off+6(a7),d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_97: - mvs.w a1_off+6(a7),d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a1.l * 1 -ewf_99: - move.l a1_off+4(a7),d0 - bra ewf_full -//a1.l * 2 -ewf_9b: - move.l a1_off+4(a7),d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a1.l * 4 -ewf_9d: - move.l a1_off+4(a7),d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a1.l * 8 -ewf_9f: - move.l a1_off+4(a7),d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a2.w * 1 -ewf_a0: - mvs.b (a0)+,d1 - mvs.w a2,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_a1: - mvs.w a2,d0 - bra ewf_full -//a2.w * 2 -ewf_a2: - mvs.b (a0)+,d1 - mvs.w a2,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_a3: - mvs.w a2,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a2.w * 4 -ewf_a4: - mvs.b (a0)+,d1 - mvs.w a2,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_a5: - mvs.w a2,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a2.w * 8 -ewf_a6: - mvs.b (a0)+,d1 - mvs.w a2,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_a7: - mvs.w a2,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a2.l * 1 -ewf_a9: - move.l a2,d0 - bra ewf_full -//a2.l * 2 -ewf_ab: - move.l a2,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a2.l * 4 -ewf_ad: - move.l a2,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a2.l * 8 -ewf_af: - move.l a2,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a3.w * 1 -ewf_b0: - mvs.b (a0)+,d1 - mvs.w a3,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_b1: - mvs.w a3,d0 - bra ewf_full -//a3.w * 2 -ewf_b2: - mvs.b (a0)+,d1 - mvs.w a3,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_b3: - mvs.w a3,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a3.w * 4 -ewf_b4: - mvs.b (a0)+,d1 - mvs.w a3,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_b5: - mvs.w a3,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a3.w * 8 -ewf_b6: - mvs.b (a0)+,d1 - mvs.w a3,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_b7: - mvs.w a3,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a3.l * 1 -ewf_b9: - move.l a3,d0 - bra ewf_full -//a3.l * 3 -ewf_bb: - move.l a3,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a3.l * 4 -ewf_bd: - move.l a3,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a3.l * 8 -ewf_bf: - move.l a3,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a4.w * 1 -ewf_c0: - mvs.b (a0)+,d1 - mvs.w a4,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_c1: - mvs.w a4,d0 - bra ewf_full -//a4.w * 2 -ewf_c2: - mvs.b (a0)+,d1 - mvs.w a4,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_c3: - mvs.w a4,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a4.w * 4 -ewf_c4: - mvs.b (a0)+,d1 - mvs.w a4,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_c5: - mvs.w a4,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a4.w * 8 -ewf_c6: - mvs.b (a0)+,d1 - mvs.w a4,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_c7: - mvs.w a4,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a4.l * 1 -ewf_c9: - move.l a4,d0 - bra ewf_full -//a4.l * 4 -ewf_cb: - move.l a4,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a4.l * 4 -ewf_cd: - move.l a4,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a4.l * 8 -ewf_cf: - move.l a4,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a5.w * 1 -ewf_d0: - mvs.b (a0)+,d1 - mvs.w a5,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_d1: - mvs.w a5,d0 - bra ewf_full -//a5.w * 2 -ewf_d2: - mvs.b (a0)+,d1 - mvs.w a5,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_d3: - mvs.w a5,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a5.w * 4 -ewf_d4: - mvs.b (a0)+,d1 - mvs.w a5,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_d5: - mvs.w a5,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a5.w * 8 -ewf_d6: - mvs.b (a0)+,d1 - mvs.w a5,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_d7: - mvs.w a5,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a5.l * 1 -ewf_d9: - move.l a5,d0 - bra ewf_full -//a5.l * 5 -ewf_db: - move.l a5,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a5.l * 4 -ewf_dd: - move.l a5,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a5.l * 8 -ewf_df: - move.l a5,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a6.w * 1 -ewf_e0: - mvs.b (a0)+,d1 - mvs.w a6,d0 - add.l d0,a1 - add.l d1,a1 - rts -ewf_e1: - mvs.w a6,d0 - bra ewf_full -//a6.w * 2 -ewf_e2: - mvs.b (a0)+,d1 - mvs.w a6,d0 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_e3: - mvs.w a6,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a6.w * 4 -ewf_e4: - mvs.b (a0)+,d1 - mvs.w a6,d0 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_e5: - mvs.w a6,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a6.w * 8 -ewf_e6: - mvs.b (a0)+,d1 - mvs.w a6,d0 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_e7: - mvs.w a6,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//a6.l * 1 -ewf_e9: - move.l a6,d0 - bra ewf_full -//a6.l * 6 -ewf_eb: - move.l a6,d0 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//a6.l * 4 -ewf_ed: - move.l a6,d0 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//a6.l * 8 -ewf_ef: - move.l a6,d0 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//usp.w * 1 -ewf_f0: - mvs.b (a0)+,d1 - move.l a1,-(a7) - move.l usp,a1 - add.l (a7)+,a1 - add.l d1,a1 - rts -ewf_f1: - move.l a1,-(a7) - move.l usp,a1 - mvs.w a1,d0 - move.l (a7)+,a1 - bra ewf_full -//usp.w * 2 -ewf_f2: - mvs.b (a0)+,d1 - move.l usp,a1 - mvs.w a1,d0 - move.l (a7)+,a1 - lea 0(a1,d0*2),a1 - add.l d1,a1 - rts -ewf_f3: - move.l usp,a1 - move.l a1,-(a7) - move.l usp,a1 - add.l (a7)+,a1 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//usp.w * 4 -ewf_f4: - mvs.b (a0)+,d1 - move.l a1,-(a7) - move.l usp,a1 - add.l (a7)+,a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_f5: - move.l a1,-(a7) - move.l usp,a1 - add.l (a7)+,a1 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//usp.w * 8 -ewf_f6: - mvs.b (a0)+,d1 - move.l a1,-(a7) - move.l usp,a1 - add.l (a7)+,a1 - lea 0(a1,d0*4),a1 - lea 0(a1,d0*4),a1 - add.l d1,a1 - rts -ewf_f7: - move.l a1,-(a7) - move.l usp,a1 - add.l (a7)+,a1 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//usp.l * 1 -ewf_f9: - move.l a1,-(a7) - move.l usp,a1 - add.l (a7)+,a1 - bra ewf_full -//usp.l * 7 -ewf_fb: - move.l a1,-(a7) - move.l usp,a1 - add.l (a7)+,a1 - move.w ccr,d1 - asl.l #1,d0 - move.w d1,ccr - bra ewf_full -//usp.l * 4 -ewf_fd: - move.l a1,-(a7) - move.l usp,a1 - add.l (a7)+,a1 - move.w ccr,d1 - asl.l #2,d0 - move.w d1,ccr - bra ewf_full -//usp.l * 8 -ewf_ff: - move.l a1,-(a7) - move.l usp,a1 - add.l (a7)+,a1 - move.w ccr,d1 - asl.l #3,d0 - move.w d1,ccr - bra ewf_full -//----------------------------------------------------------------------------------- -// extension full format rest von ewf -//-------------------------------------------------------------------- -ewf_full: - mvz.b (a0)+,d1 - mvs.w ewff_table-*-2(pc,d1*2),d1 - jmp ewff_table-*-2(pc,d1) -ewff_table: - .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //00 - .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //10 - .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_bsw-ewff_table,ewff_w0v-ewff_table,ewff_wwv-ewff_table,ewff_wlv-ewff_table //20 - .short ewff_end-ewff_table,ewff_w0n-ewff_table,ewff_wwn-ewff_table,ewff_wln-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_bsl-ewff_table,ewff_l0v-ewff_table,ewff_lwv-ewff_table,ewff_llv-ewff_table //30 - .short ewff_end-ewff_table,ewff_l0n-ewff_table,ewff_lwn-ewff_table,ewff_lln-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //40 - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //50 - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_bsw-ewff_table,ewff_wi0-ewff_table,ewff_wiw-ewff_table,ewff_wil-ewff_table //60 - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_bsl-ewff_table,ewff_li0-ewff_table,ewff_liw-ewff_table,ewff_lil-ewff_table //70 - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //80 - .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //90 - .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //a0 - .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //b0 - .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //c0 - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //d0 - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //e0 - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //f0 - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table - .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table -ewff_end: - rts -ewff_bsw: - mvs.w (a0)+,d1 - add.l d1,a1 - add.l d0,a1 - rts -ewff_bsl: - move.l (a0)+,d1 - add.l d1,a1 - add.l d0,a1 - rts -ewff_i0v: - add.l d0,a1 - move.l (a1),a1 - rts -ewff_iwv: - add.l d0,a1 - move.l (a1),a1 - mvs.w (a0)+,d0 - add.l d0,a1 - rts -ewff_ilv: - add.l d0,a1 - move.l (a1),a1 - move.l (a0)+,d0 - add.l d0,a1 - rts -ewff_i0n: - move.l (a1),a1 - add.l d0,a1 - rts -ewff_iwn: - move.l (a1),a1 - add.l d0,a1 - mvs.w (a0)+,d0 - add.l d0,a1 - rts -ewff_iln: - move.l (a1),a1 - add.l d0,a1 - move.l (a0)+,d0 - add.l d0,a1 - rts -ewff_mi0: - add.l d0,a1 - rts -ewff_miw: - mvs.w (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - rts -ewff_mil: - move.l (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - rts -ewff_wi0: - mvs.w (a0)+,d1 - add.l d1,a1 - add.l d0,a1 - rts -ewff_wiw: - mvs.w (a0)+,d1 - add.l d1,a1 - mvs.w (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - rts -ewff_wil: - mvs.w (a0)+,d1 - add.l d1,a1 - move.l (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - rts -ewff_li0: - move.l (a0)+,d1 - add.l d1,a1 - add.l d0,a1 - rts -ewff_liw: - move.l (a0)+,d1 - add.l d1,a1 - mvs.w (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - rts -ewff_lil: - move.l (a0)+,d1 - add.l d1,a1 - move.l (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - rts -ewff_w0v: - mvs.w (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - move.l (a1),a1 - rts -ewff_wwv: - mvs.w (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - move.l (a1),a1 - mvs.w (a0)+,d0 - add.l d0,a1 - rts -ewff_wlv: - mvs.w (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - move.l (a1),a1 - move.l (a0)+,d0 - add.l d0,a1 - rts -ewff_l0v: - move.l (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - move.l (a1),a1 - rts -ewff_lwv: - move.l (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - move.l (a1),a1 - mvs.w (a0)+,d0 - add.l d0,a1 - rts -ewff_llv: - move.l (a0)+,d1 - add.l d0,a1 - add.l d1,a1 - move.l (a1),a1 - move.l (a0)+,d0 - add.l d0,a1 - rts -ewff_w0n: - mvs.w (a0)+,d1 - add.l d1,a1 - move.l (a1),a1 - add.l d0,a1 - rts -ewff_wwn: - mvs.w (a0)+,d1 - add.l d1,a1 - move.l (a1),a1 - mvs.w (a0)+,d0 - add.l d0,a1 - add.l d0,a1 - rts -ewff_wln: - mvs.w (a0)+,d1 - add.l d1,a1 - move.l (a1),a1 - move.l (a0)+,d0 - add.l d0,a1 - add.l d0,a1 - rts -ewff_l0n: - move.l (a0)+,d1 - add.l d1,a1 - move.l (a1),a1 - add.l d0,a1 - rts -ewff_lwn: - move.l (a0)+,d1 - add.l d1,a1 - move.l (a1),a1 - mvs.w (a0)+,d0 - add.l d0,a1 - add.l d0,a1 - rts -ewff_lln: - move.l (a0)+,d1 - add.l d1,a1 - move.l (a1),a1 - move.l (a0)+,d0 - add.l d0,a1 - add.l d0,a1 - rts -/**************************************************************************************************************** - From 895a465cfcfa255e343d54a50a1fef7ca8a16c59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 17:38:37 +0000 Subject: [PATCH 048/276] complete --- BaS_GNU/sources/startcf.c | 98 +++++++++++---------------------------- 1 file changed, 28 insertions(+), 70 deletions(-) diff --git a/BaS_GNU/sources/startcf.c b/BaS_GNU/sources/startcf.c index 9376197..916295c 100644 --- a/BaS_GNU/sources/startcf.c +++ b/BaS_GNU/sources/startcf.c @@ -1,77 +1,35 @@ -/* - * CF_Startup.c - Default init/startup/termination routines for - * Embedded Metrowerks C++ - * - * Copyright � 1993-1998 Metrowerks, Inc. All Rights Reserved. - * Copyright � 2005 Freescale semiConductor Inc. All Rights Reserved. - * - * - * THEORY OF OPERATION - * - * This version of thestartup code is intended for linker relocated - * executables. The startup code will assign the stack pointer to - * __SP_INIT, assign the address of the data relative base address - * to a5, initialize the .bss/.sbss sections to zero, call any - * static C++ initializers and then call main. Upon returning from - * main it will call C++ destructors and call exit to terminate. - */ - #include -/* imported data */ - -extern uint32_t _SP_INIT, _SDA_BASE; -extern uint32_t _START_BSS, _END_BSS; -extern uint32_t _START_SBSS, _END_SBSS; -extern uint32_t __DATA_RAM, __DATA_ROM, __DATA_END; -extern uint32_t __Bas_base; - -extern uint32_t __SUP_SP,__BOOT_FLASH; -extern uint32_t rt_mbar; - -/* imported routines */ - -extern int BaS(int, char **); - -/* exported routines */ -extern void __initialize_hardware(void); -extern void init_slt(void); - - void _startup(void) { -#ifdef _NOT_USED_ asm("\n\t" - "bra warmstart\n\t" - "jmp __BOOT_FLASH + 8 // ist zugleich reset vector\n\t" - "/* disable interrupts */\n\t" + "bra warmstart\n\t" + "jmp __BOOT_FLASH + 8 | ist zugleich reset vector\n\t" + "| disable interrupts\n\t" "warmstart:\n\t" - "// disable interrupts\n\t" - "move.w #0x2700,sr\n\t" - "// Initialize MBAR\n\t" - "MOVE.L #__MBAR,D0\n\t" - "MOVEC D0,MBAR\n\t" - "MOVE.L D0,rt_mbar\n\t" -"// mmu off\n\t" - "move.l #__MMUBAR+1,d0\n\t" - movec d0,MMUBAR //mmubar setzen - clr.l d0 - move.l d0,MCF_MMU_MMUCR // mmu off - /* Initialize RAMBARs: locate SRAM and validate it */ \ - move.l #__RAMBAR0 + 0x7,d0 // supervisor only - movec d0,RAMBAR0 - move.l #__RAMBAR1 + 0x1,d0 // on for all - movec d0,RAMBAR1 - -// STACKPOINTER AUF ENDE SRAM1 - lea __SUP_SP,a7 - -// instruction cache on - move.l #0x000C8100,d0 - movec d0,cacr - nop -// initialize any hardware specific issues - bra __initialize_hardware -"); -#endif /* _NOT_USED_ */ + "| disable interrupts\n\t" + "move.w #0x2700,sr\n\t" + "|// Initialize MBAR\n\t" + "MOVE.L #__MBAR,D0\n\t" + "MOVEC D0,MBAR\n\t" + "MOVE.L D0,rt_mbar\n\t" + "| mmu off\n\t" + "move.l #__MMUBAR+1,d0\n\t" + "movec d0,MMUBAR | mmubar setzen\n\t" + "clr.l d0\n\t" + "move.l d0,MCF_MMU_MMUCR\n\t | mmu off" + "|/* Initialize RAMBARs: locate SRAM and validate it */\n\t" + "move.l #__RAMBAR0 + 0x7,d0\n\t | supervisor only" + "movec d0,RAMBAR0\n\t" + "move.l #__RAMBAR1 + 0x1,d0\n\t""" + "movec d0,RAMBAR1\n\t" + "| STACKPOINTER AUF ENDE SRAM1\n\t" + "lea __SUP_SP,a7\n\t" + "| instruction cache on\n\t" + "move.l #0x000C8100,d0\n\t" + "movec d0,cacr\n\t" + "nop\n\t" + "| initialize any hardware specific issues\n\t" + "bra __initialize_hardware\n\t" +); } From f50654d54e563d1194c07e072fcbdac1588a8144 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 17:42:09 +0000 Subject: [PATCH 049/276] still a few functions left to fix --- BaS_GNU/sources/sysinit.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 10ae0e2..16522df 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -296,7 +296,7 @@ void wait_pll(void) { do { wait1ms(); - } while (! * (uint16_t *) 0xf0000800); + } while (! * (volatile uint16_t *) 0xf0000800); } void init_pll(void) @@ -807,19 +807,19 @@ asm( "lea copy_start,A0\n\t" "lea BaS,A1\n\t" "sub.l A0,A1\n\t" - "move.l #__Bas_base,A2\n\t" - "move.l A2,A3\n\t" + "move.l #__Bas_base,A2\n\t" + "move.l A2,A3\n\t" "add.l A1,A3\n\t" "lea copy_end,A4\n\t" -"BaS_copy_loop: /* copy 16 bytes per turn */\n\t" - "move.l (A0)+,(A2)+\n\t" - "move.l (A0)+,(A2)+\n\t" - "move.l (A0)+,(A2)+\n\t" - "move.l (A0)+,(A2)+\n\t" +"BaS_copy_loop: /* copy 16 bytes per turn */\n\t" + "move.l (A0)+,(A2)+\n\t" + "move.l (A0)+,(A2)+\n\t" + "move.l (A0)+,(A2)+\n\t" + "move.l (A0)+,(A2)+\n\t" "cmp.l A4,A0\n\t" "blt BaS_copy_loop\n\t" "\n\t" - "intouch A3\n\t" /* we'd better update caches to contain the data we just copied */ + "intouch A3\n\t" /* FIXME: we'd better update caches to contain the data we just copied */ "jmp (A3)\n\t" "copy_start:\n\t" "nop\n\t" From 7405be55096319573bd68efdaba192e1508a2538 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 19:19:42 +0000 Subject: [PATCH 050/276] more initialization done --- BaS_GNU/sources/sysinit.c | 98 +++++++++++++++++++++------------------ 1 file changed, 52 insertions(+), 46 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 16522df..6a202fd 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -299,63 +299,69 @@ void wait_pll(void) } while (! * (volatile uint16_t *) 0xf0000800); } +static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600; void init_pll(void) { + * (volatile uint16_t *) (pll_base + 0x48) = 0x27; /* loopfilter r */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */ + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */ + wait_pll(); + * (volatile uint8_t *) 0xf0000800 = 0; /* set */ + + MCF_PSC0_PSCTB_8BIT = 'SET!'; + MCF_PSC0_PSCTB_8BIT = 0x0a0d; } -#ifdef _NOT_USED_ -// init pll - MCF_PSC0_PSCTB_8BIT = 'PLL '; asm { - lea 0xf0000600, a0 lea 0xf0000800, a1 bsr wait_pll move.w -#27,0x48(a0) // loopfilter r - bsr wait_pll move.w -#1,0x08(a0) // charge pump I - bsr wait_pll move.w -#12,0x0(a0) // N counter high = 12 - bsr wait_pll move.w -#12,0x40(a0) // N counter low = 12 - bsr wait_pll move.w -#1,0x114(a0) // ck1 bypass - bsr wait_pll move.w -#1,0x118(a0) // ck2 bypass - bsr wait_pll move.w -#1,0x11c(a0) // ck3 bypass - bsr wait_pll move.w -#1,0x10(a0) // ck0 high = 1 - bsr wait_pll move.w -#1,0x50(a0) // ck0 low = 1 - bsr wait_pll move.w -#1,0x144(a0) // M odd division - bsr wait_pll move.w -#1,0x44(a0) // M low = 1 - bsr wait_pll move.w -#145,0x04(a0) // M high = 145 = 146MHz - bsr wait_pll clr.b(a1) // set - } - MCF_PSC0_PSCTB_8BIT = 'SET!'; MCF_PSC0_PSCTB_8BIT = 0x0a0d;} /* * INIT VIDEO DDR RAM */ -void init_video_ddr(void) { - asm { +#define NOP() asm("nop\n\t") -// init video ram - moveq.l #0xB,d0 - move.w d0, 0xF0000400 //set cke=1, cs=1 config=1 - nop lea __VRAM, a0 //zeiger auf video ram - nop move.l #0x00050400,(a0) //IPALL - nop move.l #0x00072000,(a0) //load EMR pll on - nop move.l #0x00070122,(a0) //load MR: reset pll, cl=2 BURST=4lw - nop move.l #0x00050400,(a0) //IPALL - nop move.l #0x00060000,(a0) //auto refresh - nop move.l #0x00060000,(a0) //auto refresh - nop move.l #0000070022,(a0) //load MR dll on - nop move.l #0x01070002,d0 // fifo on, refresh on, ddrcs und cke on, video dac on, - move.l d0, 0xf0000400} - } +void init_video_ddr(void) { + * (uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */ + NOP(); + _VRAM = 0x00050400; /* IPALL */ + NOP(); + _VRAM = 0x00072000; /* load EMR pll on */ + NOP(); + _VRAM = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */ + NOP(); + _VRAM = 0x00050400; /* IPALL */ + NOP(); + _VRAM = 0x00060000; /* auto refresh */ + NOP(); + _VRAM = 0x00060000; /* auto refresh */ + NOP(); + _VRAM = 0000070022; /* load MR dll on */ + NOP(); + * (uint32_t *) 0xf0000400 = 0x01070002; +} + + +#ifdef _NOT_USED_ /********************************************************************/ /* video mit auflösung 1280x1000 137MHz /* From 03b4c4715dc0a8501c67c9e27089a7b2acd82db1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 19:27:52 +0000 Subject: [PATCH 051/276] --- BaS_GNU/sources/sysinit.c | 59 +++++++++++++++------------------------ 1 file changed, 22 insertions(+), 37 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 6a202fd..062f069 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -404,48 +404,33 @@ flo6: bgt loop5 // screen setzen //horizontal 1280 - lea 0xffff8282, a0 move.w -#1800,(a0)+ - move.w -#1380,(a0)+ - move.w -#99,(a0)+ - move.w -#100,(a0)+ - move.w -#1379,(a0)+ - move.w -#1500,(a0) + lea 0xffff8282, a0 + move.w #1800,(a0)+ + move.w #1380,(a0)+ + move.w #99,(a0)+ + move.w #100,(a0)+ + move.w #1379,(a0)+ + move.w #1500,(a0) //vertical 1024 - lea 0xffff82a2, a0 move.w -#1150,(a0)+ - move.w -#1074,(a0)+ - move.w -#49,(a0)+ - move.w -#50,(a0)+ - move.w -#1073,(a0)+ - move.w -#1100,(a0)+ + lea 0xffff82a2, a0 + move.w #1150,(a0)+ + move.w #1074,(a0)+ + move.w #49,(a0)+ + move.w #50,(a0)+ + move.w #1073,(a0)+ + move.w #1100,(a0)+ // acp video on - move.l -#0x01070207,d0 + move.l #0x01070207,d0 move.l d0, 0xf0000400 // clut setzen - lea 0xf0000000, a0 move.l -#0xffffffff,(a0)+ - move.l -#0xff,(a0)+ - move.l -#0xff00,(a0)+ - move.l -#0xff0000,(a0) + lea 0xf0000000, a0 + move.l #0xffffffff,(a0)+ + move.l #0xff,(a0)+ + move.l #0xff00,(a0)+ + move.l #0xff0000,(a0) // halt - } - - } + } +} #endif From fd26b3cd3fe52e92ff0351962e1cd277f779587d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 21:14:57 +0000 Subject: [PATCH 052/276] started link script rewrite - needed lots of symbol changes because leading underscores in symbol names --- BaS_GNU/Makefile | 3 + BaS_GNU/bas.hex.map | 238 +++++++++++++++++++++++++++++++++++ BaS_GNU/flash.lk | 86 +++++++++++++ BaS_GNU/sources/exceptions.S | 60 ++++----- BaS_GNU/sources/startcf.c | 17 +-- BaS_GNU/sources/supervisor.S | 12 +- BaS_GNU/sources/sysinit.c | 2 +- 7 files changed, 373 insertions(+), 45 deletions(-) create mode 100644 BaS_GNU/bas.hex.map create mode 100644 BaS_GNU/flash.lk diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index bc350cc..210d499 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -43,7 +43,10 @@ OBJS=$(COBJS) $(AOBJS) all: $(EXEC) +SADDR=0xe0000000 + $(EXEC): $(OBJS) + $(LD) --oformat srec -Map $@.map --cref -T flash.lk -s -o $@ $(OBJS) echo "generating executable" clean: diff --git a/BaS_GNU/bas.hex.map b/BaS_GNU/bas.hex.map new file mode 100644 index 0000000..aff34d8 --- /dev/null +++ b/BaS_GNU/bas.hex.map @@ -0,0 +1,238 @@ + +Memory Configuration + +Name Origin Length Attributes +code 0xe0000000 0x00200000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + + 0x1fe00000 __Bas_base = 0x1fe00000 + 0xe0000000 ___BOOT_FLASH = 0xe0000000 + 0x00800000 ___BOOT_FLASH_SIZE = 0x800000 + 0x00000000 ___SDRAM = 0x0 + 0x20000000 ___SDRAM_SIZE = 0x20000000 + 0x60000000 ___VRAM = 0x60000000 + 0xff000000 ___MBAR = 0xff000000 + 0xff040000 ___MMUBAR = 0xff040000 + 0xff100000 ___RAMBAR0 = 0xff100000 + 0x00001000 ___RAMBAR0_SIZE = 0x1000 + 0xff100ffc ___SUP_SP = ((___RAMBAR0 + ___RAMBAR0_SIZE) - 0x4) + 0xff101000 ___RAMBAR1 = 0xff101000 + 0x00001000 ___RAMBAR1_SIZE = 0x1000 + 0xff100800 _rt_mod = (___RAMBAR0 + 0x800) + 0xff100804 _rt_ssp = (___RAMBAR0 + 0x804) + 0xff100808 _rt_usp = (___RAMBAR0 + 0x808) + 0xff10080c _rt_vbr = (___RAMBAR0 + 0x80c) + 0xff100810 _rt_cacr = (___RAMBAR0 + 0x810) + 0xff100814 _rt_asid = (___RAMBAR0 + 0x814) + 0xff100818 _rt_acr0 = (___RAMBAR0 + 0x818) + 0xff10081c _rt_acr1 = (___RAMBAR0 + 0x81c) + 0xff100820 _rt_acr2 = (___RAMBAR0 + 0x820) + 0xff100824 _rt_acr3 = (___RAMBAR0 + 0x824) + 0xff100828 _rt_mmubar = (___RAMBAR0 + 0x828) + 0xff10082c _rt_sr = (___RAMBAR0 + 0x82c) + 0xff100830 _d0_save = (___RAMBAR0 + 0x830) + 0xff100834 _a7_save = (___RAMBAR0 + 0x834) + 0xff100838 _video_tlb = (___RAMBAR0 + 0x838) + 0xff10083c _video_sbt = (___RAMBAR0 + 0x83c) + 0xff100844 _rt_mbar = (___RAMBAR0 + 0x844) + 0xff010000 __SYS_SRAM = 0xff010000 + 0x00008000 __SYS_SRAM_SIZE = 0x8000 + +.code + +.text 0xe0000000 0x30a0 + objs/startcf.o(.text) + .text 0xe0000000 0x58 objs/startcf.o + 0xe0000000 __startup + objs/sysinit.o(.text) + .text 0xe0000058 0xc4c objs/sysinit.o + 0xe0000058 _init_slt + 0xe000007e _init_gpio + 0xe00000d2 _init_serial + 0xe0000202 _init_ddram + 0xe00002e8 _init_fbcs + 0xe00003aa _init_fpga + 0xe00004bc _wait_pll + 0xe00004d2 _init_pll + 0xe0000570 _init_video_ddr + 0xe0000598 _init_PCI + 0xe0000642 _test_upd720101 + 0xe00006ac _vdi_on + 0xe0000a18 _init_ac97 + 0xe0000c1a ___initialize_hardware + objs/BaS.o(.text) + .text 0xe0000ca4 0x290 objs/BaS.o + 0xe0000ca4 _wait_10ms + 0xe0000cbc _wait_1ms + 0xe0000cd4 _wait_100us + 0xe0000cec _wait_50us + 0xe0000d04 _wait_10us + 0xe0000d1c _wait_1us + 0xe0000d34 _BaS + objs/sd_card.o(.text) + .text 0xe0000f34 0x88 objs/sd_card.o + 0xe0000f34 _sd_com + 0xe0000f5c _sd_get_status + 0xe0000f78 _sd_rcv_info + 0xe0000fb8 _sd_card_idle + objs/mmu.o(.text) + .text 0xe0000fbc 0x1b0 objs/mmu.o + 0xe0000fbc _mmu_init + 0xe0001130 _mmutr_miss + objs/exceptions.o(.text) + .text 0xe000116c 0x9b4 objs/exceptions.o + 0xe000116c _vec_init + objs/supervisor.o(.text) + .text 0xe0001b20 0x5cc objs/supervisor.o + 0xe0001b20 _privileg_violation + 0xe000209e cpusha + objs/ewf.o(.text) + .text 0xe00020ec 0xe40 objs/ewf.o + 0xe00020f2 ewf + objs/illegal_instruction.o(.text) + .text 0xe0002f2c 0x170 objs/illegal_instruction.o + 0xe0003098 _illegal_instruction + 0xe0003098 _illegal_table_make + objs/last.o(.text) + .text 0xe000309c 0x4 objs/last.o + 0xe000309c copy_end + 0xe000309c _copy_end +LOAD objs/startcf.o +LOAD objs/sysinit.o +LOAD objs/BaS.o +LOAD objs/sd_card.o +LOAD objs/last.o +LOAD objs/mmu.o +LOAD objs/exceptions.o +LOAD objs/supervisor.o +LOAD objs/ewf.o +LOAD objs/illegal_instruction.o +OUTPUT(bas.hex srec) + +.data 0x00000000 0x0 + .data 0x00000000 0x0 objs/startcf.o + .data 0x00000000 0x0 objs/sysinit.o + .data 0x00000000 0x0 objs/BaS.o + .data 0x00000000 0x0 objs/sd_card.o + .data 0x00000000 0x0 objs/mmu.o + .data 0x00000000 0x0 objs/exceptions.o + .data 0x00000000 0x0 objs/supervisor.o + .data 0x00000000 0x0 objs/ewf.o + .data 0x00000000 0x0 objs/illegal_instruction.o + .data 0x00000000 0x0 objs/last.o + +.bss 0x00000000 0x0 + .bss 0x00000000 0x0 objs/startcf.o + .bss 0x00000000 0x0 objs/sysinit.o + .bss 0x00000000 0x0 objs/BaS.o + .bss 0x00000000 0x0 objs/sd_card.o + .bss 0x00000000 0x0 objs/mmu.o + .bss 0x00000000 0x0 objs/exceptions.o + .bss 0x00000000 0x0 objs/supervisor.o + .bss 0x00000000 0x0 objs/ewf.o + .bss 0x00000000 0x0 objs/illegal_instruction.o + .bss 0x00000000 0x0 objs/last.o + +Cross Reference Table + +Symbol File +BaS objs/sysinit.o +MCF_MMU_MMUCR objs/startcf.o +_BaS objs/BaS.o +_MCF_PCICR1_CACHELINESIZE objs/sysinit.o +_MCF_PCICR2_MINGNT objs/sysinit.o +__Bas_base objs/sysinit.o +__MBAR objs/exceptions.o +__MMUBAR objs/exceptions.o +__VRAM objs/sysinit.o +___BOOT_FLASH objs/exceptions.o + objs/startcf.o +___Bas_base objs/exceptions.o + objs/BaS.o +___MBAR objs/exceptions.o + objs/sd_card.o + objs/BaS.o + objs/sysinit.o + objs/startcf.o +___MMUBAR objs/mmu.o + objs/BaS.o + objs/startcf.o +___RAMBAR0 objs/exceptions.o + objs/startcf.o +___RAMBAR1 objs/startcf.o +___SUP_SP objs/exceptions.o + objs/startcf.o +___initialize_hardware objs/sysinit.o +__startup objs/startcf.o +_copy_end objs/last.o +_copy_firetos objs/BaS.o +_illegal_instruction objs/illegal_instruction.o + objs/exceptions.o +_illegal_table_make objs/illegal_instruction.o + objs/BaS.o +_init_PCI objs/sysinit.o +_init_ac97 objs/sysinit.o +_init_ddram objs/sysinit.o +_init_fbcs objs/sysinit.o +_init_fpga objs/sysinit.o +_init_gpio objs/sysinit.o +_init_pll objs/sysinit.o +_init_serial objs/sysinit.o +_init_slt objs/sysinit.o +_init_video_ddr objs/sysinit.o +_initialize_hardware objs/startcf.o +_mmu_init objs/mmu.o + objs/BaS.o +_mmutr_miss objs/mmu.o + objs/exceptions.o +_privileg_violation objs/supervisor.o + objs/exceptions.o +_rt_acr0 objs/mmu.o +_rt_acr1 objs/mmu.o +_rt_acr2 objs/mmu.o +_rt_acr3 objs/mmu.o +_rt_asid objs/mmu.o +_rt_cacr objs/supervisor.o + objs/mmu.o +_rt_mbar objs/startcf.o +_rt_mmubar objs/mmu.o +_rt_mod objs/supervisor.o + objs/exceptions.o +_rt_ssp objs/exceptions.o +_rt_usp objs/exceptions.o +_rt_vbr objs/exceptions.o +_sd_card_idle objs/sd_card.o + objs/BaS.o +_sd_card_init objs/BaS.o +_sd_com objs/sd_card.o +_sd_get_status objs/sd_card.o +_sd_rcv_info objs/sd_card.o +_test_upd720101 objs/sysinit.o +_vdi_on objs/sysinit.o +_vec_init objs/exceptions.o + objs/BaS.o +_video_sbt objs/exceptions.o + objs/mmu.o +_video_tlb objs/exceptions.o + objs/mmu.o +_wait1ms objs/sysinit.o +_wait_100us objs/BaS.o +_wait_10ms objs/BaS.o +_wait_10us objs/BaS.o + objs/sysinit.o +_wait_1ms objs/BaS.o +_wait_1us objs/BaS.o +_wait_50us objs/BaS.o + objs/sysinit.o +_wait_pll objs/sysinit.o +_warte10us objs/sysinit.o +copy_end objs/last.o + objs/sysinit.o +cpusha objs/supervisor.o + objs/exceptions.o + objs/mmu.o +ewf objs/ewf.o + objs/illegal_instruction.o +rt_cacr objs/sysinit.o diff --git a/BaS_GNU/flash.lk b/BaS_GNU/flash.lk new file mode 100644 index 0000000..5938ddf --- /dev/null +++ b/BaS_GNU/flash.lk @@ -0,0 +1,86 @@ +MEMORY { + code (RX) : ORIGIN = 0xE0000000, LENGTH = 0x00200000 +} + +SECTIONS { + __Bas_base = 0x1FE00000; + + /* Board Memory map definitions from linker command files: + * __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE + * linker symbols must be defined in the linker command file. + */ + + /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */ + ___BOOT_FLASH = ABSOLUTE(0xE0000000); + ___BOOT_FLASH_SIZE = ABSOLUTE(0x00800000); + /* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */ + ___SDRAM = ABSOLUTE(0x00000000); + ___SDRAM_SIZE = ABSOLUTE(0x20000000); + + /* VIDEO RAM BASIS */ + ___VRAM = ABSOLUTE(0x60000000); + + /* + * MCF5475 Derivative Memory map definitions from linker command files: + * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE + * linker symbols must be defined in the linker command file. + */ + + /* Memory mapped registers */ + ___MBAR = ABSOLUTE(0xFF000000); + ___MMUBAR = ABSOLUTE(0xFF040000); + + /* + * 4KB on-chip Core SRAM0: -> exception table and exception stack + */ + ___RAMBAR0 = ABSOLUTE(0xFF100000); + ___RAMBAR0_SIZE = ABSOLUTE(0x00001000); + + ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4; + + /* 4KB on-chip Core SRAM1: -> modified code */ + ___RAMBAR1 = ABSOLUTE(0xFF101000); + ___RAMBAR1_SIZE = ABSOLUTE(0x00001000); + + /* Systemveriablem:****************************************** */ + /* RAMBAR0 0 bis 0x7FF -> exception vectoren */ + _rt_mod = ___RAMBAR0 + 0x800; + _rt_ssp = ___RAMBAR0 + 0x804; + _rt_usp = ___RAMBAR0 + 0x808; + _rt_vbr = ___RAMBAR0 + 0x80C; /* (8)01 */ + _rt_cacr = ___RAMBAR0 + 0x810; /* 002 */ + _rt_asid = ___RAMBAR0 + 0x814; /* 003 */ + _rt_acr0 = ___RAMBAR0 + 0x818; /* 004 */ + _rt_acr1 = ___RAMBAR0 + 0x81c; /* 005 */ + _rt_acr2 = ___RAMBAR0 + 0x820; /* 006 */ + _rt_acr3 = ___RAMBAR0 + 0x824; /* 007 */ + _rt_mmubar = ___RAMBAR0 + 0x828; /* 008 */ + _rt_sr = ___RAMBAR0 + 0x82c; + _d0_save = ___RAMBAR0 + 0x830; + _a7_save = ___RAMBAR0 + 0x834; + _video_tlb = ___RAMBAR0 + 0x838; + _video_sbt = ___RAMBAR0 + 0x83C; + _rt_mbar = ___RAMBAR0 + 0x844; /* (c)0f */ + +/**********************************************************/ + +/* 32KB on-chip System SRAM */ + __SYS_SRAM = 0xFF010000; + __SYS_SRAM_SIZE = 0x00008000; + + .code : {} > code + + .text : + { + objs/startcf.o(.text) + objs/sysinit.o(.text) + objs/BaS.o(.text) + objs/sd_card.o(.text) + objs/mmu.o(.text) + objs/exceptions.o(.text) + objs/supervisor.o(.text) + objs/ewf.o(.text) + objs/illegal_instruction.o(.text) + objs/last.o(.text) + } > code +} \ No newline at end of file diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S index 9c2120a..0997fd2 100644 --- a/BaS_GNU/sources/exceptions.S +++ b/BaS_GNU/sources/exceptions.S @@ -4,10 +4,10 @@ #include "startcf.h" -.extern ___Bas_base -.extern ___SUP_SP -.extern ___BOOT_FLASH -.extern ___RAMBAR0 +.extern __Bas_base +.extern __SUP_SP +.extern __BOOT_FLASH +.extern __RAMBAR0 .extern _rt_cacr .extern _rt_mod .extern _rt_ssp @@ -16,44 +16,44 @@ .extern _illegal_instruction .extern _privileg_violation .extern _mmutr_miss -.extern ___MBAR -.extern ___MMUBAR +.extern __MBAR +.extern __MMUBAR .extern _video_tlb .extern _video_sbt .extern cpusha /* Register read/write macros */ -#define MCF_MMU_MMUCR ___MMUBAR -#define MCF_MMU_MMUOR ___MMUBAR+0x04 -#define MCF_MMU_MMUSR ___MMUBAR+0x08 -#define MCF_MMU_MMUAR ___MMUBAR+0x10 -#define MCF_MMU_MMUTR ___MMUBAR+0x14 -#define MCF_MMU_MMUDR ___MMUBAR+0x18 +#define MCF_MMU_MMUCR __MMUBAR +#define MCF_MMU_MMUOR __MMUBAR+0x04 +#define MCF_MMU_MMUSR __MMUBAR+0x08 +#define MCF_MMU_MMUAR __MMUBAR+0x10 +#define MCF_MMU_MMUTR __MMUBAR+0x14 +#define MCF_MMU_MMUDR __MMUBAR+0x18 -#define MCF_EPORT_EPPAR ___MBAR+0xF00 -#define MCF_EPORT_EPDDR ___MBAR+0xF04 -#define MCF_EPORT_EPIER ___MBAR+0xF05 -#define MCF_EPORT_EPDR ___MBAR+0xF08 -#define MCF_EPORT_EPPDR ___MBAR+0xF09 -#define MCF_EPORT_EPFR ___MBAR+0xF0C +#define MCF_EPORT_EPPAR __MBAR+0xF00 +#define MCF_EPORT_EPDDR __MBAR+0xF04 +#define MCF_EPORT_EPIER __MBAR+0xF05 +#define MCF_EPORT_EPDR __MBAR+0xF08 +#define MCF_EPORT_EPPDR __MBAR+0xF09 +#define MCF_EPORT_EPFR __MBAR+0xF0C -#define MCF_GPIO_PODR_FEC1L ___MBAR+0xA07 +#define MCF_GPIO_PODR_FEC1L __MBAR+0xA07 -#define MCF_PSC0_PSCTB_8BIT ___MBAR+0x860C +#define MCF_PSC0_PSCTB_8BIT __MBAR+0x860C -#define MCF_PSC3_PSCRB_8BIT ___MBAR+0x890C -#define MCF_PSC3_PSCTB_8BIT ___MBAR+0x890C +#define MCF_PSC3_PSCRB_8BIT __MBAR+0x890C +#define MCF_PSC3_PSCTB_8BIT __MBAR+0x890C .global _vec_init //mmu --------------------------------------------------- /* Register read/write macros */ -#define MCF_MMU_MMUCR ___MMUBAR -#define MCF_MMU_MMUOR ___MMUBAR+0x04 -#define MCF_MMU_MMUSR ___MMUBAR+0x08 -#define MCF_MMU_MMUAR ___MMUBAR+0x10 -#define MCF_MMU_MMUTR ___MMUBAR+0x14 -#define MCF_MMU_MMUDR ___MMUBAR+0x18 +#define MCF_MMU_MMUCR __MMUBAR +#define MCF_MMU_MMUOR __MMUBAR+0x04 +#define MCF_MMU_MMUSR __MMUBAR+0x08 +#define MCF_MMU_MMUAR __MMUBAR+0x10 +#define MCF_MMU_MMUTR __MMUBAR+0x14 +#define MCF_MMU_MMUDR __MMUBAR+0x18 /* Bit definitions and macros for MCF_MMU_MMUCR */ @@ -111,7 +111,7 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_GPT0_GMS ___MBAR+0x800 +#define MCF_GPT0_GMS __MBAR+0x800 /********************************************************************* * @@ -119,7 +119,7 @@ * *********************************************************************/ -#define MCF_SLT0_SCNT ___MBAR+0x908 +#define MCF_SLT0_SCNT __MBAR+0x908 /**********************************************************/ // macros diff --git a/BaS_GNU/sources/startcf.c b/BaS_GNU/sources/startcf.c index 916295c..1fef820 100644 --- a/BaS_GNU/sources/startcf.c +++ b/BaS_GNU/sources/startcf.c @@ -3,33 +3,34 @@ void _startup(void) { asm("\n\t" + ".extern _initialize_hardware\n\t" "bra warmstart\n\t" - "jmp __BOOT_FLASH + 8 | ist zugleich reset vector\n\t" + "jmp ___BOOT_FLASH + 8 | ist zugleich reset vector\n\t" "| disable interrupts\n\t" "warmstart:\n\t" "| disable interrupts\n\t" "move.w #0x2700,sr\n\t" "|// Initialize MBAR\n\t" - "MOVE.L #__MBAR,D0\n\t" + "MOVE.L #___MBAR,D0\n\t" "MOVEC D0,MBAR\n\t" - "MOVE.L D0,rt_mbar\n\t" + "MOVE.L D0,_rt_mbar\n\t" "| mmu off\n\t" - "move.l #__MMUBAR+1,d0\n\t" + "move.l #___MMUBAR+1,d0\n\t" "movec d0,MMUBAR | mmubar setzen\n\t" "clr.l d0\n\t" "move.l d0,MCF_MMU_MMUCR\n\t | mmu off" "|/* Initialize RAMBARs: locate SRAM and validate it */\n\t" - "move.l #__RAMBAR0 + 0x7,d0\n\t | supervisor only" + "move.l #___RAMBAR0 + 0x7,d0\n\t | supervisor only" "movec d0,RAMBAR0\n\t" - "move.l #__RAMBAR1 + 0x1,d0\n\t""" + "move.l #___RAMBAR1 + 0x1,d0\n\t""" "movec d0,RAMBAR1\n\t" "| STACKPOINTER AUF ENDE SRAM1\n\t" - "lea __SUP_SP,a7\n\t" + "lea ___SUP_SP,a7\n\t" "| instruction cache on\n\t" "move.l #0x000C8100,d0\n\t" "movec d0,cacr\n\t" "nop\n\t" "| initialize any hardware specific issues\n\t" - "bra __initialize_hardware\n\t" + "bra _initialize_hardware\n\t" ); } diff --git a/BaS_GNU/sources/supervisor.S b/BaS_GNU/sources/supervisor.S index c9520c9..5e20f85 100644 --- a/BaS_GNU/sources/supervisor.S +++ b/BaS_GNU/sources/supervisor.S @@ -11,12 +11,12 @@ .extern ___MMUBAR /* Register read/write macros */ -#define MCF_MMU_MMUCR ___MMUBAR -#define MCF_MMU_MMUOR ___MMUBAR+0x04 -#define MCF_MMU_MMUSR ___MMUBAR+0x08 -#define MCF_MMU_MMUAR ___MMUBAR+0x10 -#define MCF_MMU_MMUTR ___MMUBAR+0x14 -#define MCF_MMU_MMUDR ___MMUBAR+0x18 +#define MCF_MMU_MMUCR __MMUBAR +#define MCF_MMU_MMUOR __MMUBAR+0x04 +#define MCF_MMU_MMUSR __MMUBAR+0x08 +#define MCF_MMU_MMUAR __MMUBAR+0x10 +#define MCF_MMU_MMUTR __MMUBAR+0x14 +#define MCF_MMU_MMUDR __MMUBAR+0x18 .global _privileg_violation .global cpusha diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 062f069..c5020d2 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -14,7 +14,7 @@ static const uint8_t *FPGA_FLASH_DATA = (uint8_t *) 0xe0700000L; static const uint8_t *FPGA_FLASH_DATA_END = (uint8_t *) 0xe0800000L; -extern unsigned long _VRAM; +extern unsigned long __VRAM; extern unsigned long _Bas_base; extern unsigned long BaS; extern unsigned long _BOOT_FLASH[]; From 61bf238d205ceb0e296ae2db1de833cdc2fe56ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 21:22:40 +0000 Subject: [PATCH 053/276] less undefined symbol references --- BaS_GNU/bas.hex.map | 10 +++++----- BaS_GNU/flash.lk | 4 ++-- BaS_GNU/lcf/FLASH.lcf | 2 +- BaS_GNU/sources/exceptions.S | 2 +- BaS_GNU/sources/sysinit.c | 4 ++-- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/BaS_GNU/bas.hex.map b/BaS_GNU/bas.hex.map index aff34d8..a1d8cc8 100644 --- a/BaS_GNU/bas.hex.map +++ b/BaS_GNU/bas.hex.map @@ -7,12 +7,12 @@ code 0xe0000000 0x00200000 xr Linker script and memory map - 0x1fe00000 __Bas_base = 0x1fe00000 + 0x1fe00000 _Bas_base = 0x1fe00000 0xe0000000 ___BOOT_FLASH = 0xe0000000 0x00800000 ___BOOT_FLASH_SIZE = 0x800000 0x00000000 ___SDRAM = 0x0 0x20000000 ___SDRAM_SIZE = 0x20000000 - 0x60000000 ___VRAM = 0x60000000 + 0x60000000 __VRAM = 0x60000000 0xff000000 ___MBAR = 0xff000000 0xff040000 ___MMUBAR = 0xff040000 0xff100000 ___RAMBAR0 = 0xff100000 @@ -141,16 +141,16 @@ Symbol File BaS objs/sysinit.o MCF_MMU_MMUCR objs/startcf.o _BaS objs/BaS.o +_Bas_base objs/exceptions.o + objs/sysinit.o _MCF_PCICR1_CACHELINESIZE objs/sysinit.o _MCF_PCICR2_MINGNT objs/sysinit.o -__Bas_base objs/sysinit.o __MBAR objs/exceptions.o __MMUBAR objs/exceptions.o __VRAM objs/sysinit.o ___BOOT_FLASH objs/exceptions.o objs/startcf.o -___Bas_base objs/exceptions.o - objs/BaS.o +___Bas_base objs/BaS.o ___MBAR objs/exceptions.o objs/sd_card.o objs/BaS.o diff --git a/BaS_GNU/flash.lk b/BaS_GNU/flash.lk index 5938ddf..ca45959 100644 --- a/BaS_GNU/flash.lk +++ b/BaS_GNU/flash.lk @@ -3,7 +3,7 @@ MEMORY { } SECTIONS { - __Bas_base = 0x1FE00000; + _Bas_base = 0x1FE00000; /* Board Memory map definitions from linker command files: * __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE @@ -18,7 +18,7 @@ SECTIONS { ___SDRAM_SIZE = ABSOLUTE(0x20000000); /* VIDEO RAM BASIS */ - ___VRAM = ABSOLUTE(0x60000000); + __VRAM = ABSOLUTE(0x60000000); /* * MCF5475 Derivative Memory map definitions from linker command files: diff --git a/BaS_GNU/lcf/FLASH.lcf b/BaS_GNU/lcf/FLASH.lcf index 0315e2f..970ad7a 100644 --- a/BaS_GNU/lcf/FLASH.lcf +++ b/BaS_GNU/lcf/FLASH.lcf @@ -25,7 +25,7 @@ SECTIONS { ___SDRAM_SIZE = 0x20000000; #VIDEO RAM BASIS - ___VRAM = 0x60000000; + __VRAM = 0x60000000; # MCF5475 Derivative Memory map definitions from linker command files: # __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S index 0997fd2..6dc2797 100644 --- a/BaS_GNU/sources/exceptions.S +++ b/BaS_GNU/sources/exceptions.S @@ -386,7 +386,7 @@ access_mmu: btst #1,d0 bne bus_error move.l MCF_MMU_MMUAR,d0 - cmp.l #___Bas_base,d0 // max User RAM Bereich + cmp.l #_Bas_base,d0 // max User RAM Bereich bge bus_error // grösser -> bus error bra _mmutr_miss bus_error: diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index c5020d2..c44e4b8 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -14,7 +14,7 @@ static const uint8_t *FPGA_FLASH_DATA = (uint8_t *) 0xe0700000L; static const uint8_t *FPGA_FLASH_DATA_END = (uint8_t *) 0xe0800000L; -extern unsigned long __VRAM; +extern unsigned long _VRAM; extern unsigned long _Bas_base; extern unsigned long BaS; extern unsigned long _BOOT_FLASH[]; @@ -798,7 +798,7 @@ asm( "lea copy_start,A0\n\t" "lea BaS,A1\n\t" "sub.l A0,A1\n\t" - "move.l #__Bas_base,A2\n\t" + "move.l #_Bas_base,A2\n\t" "move.l A2,A3\n\t" "add.l A1,A3\n\t" "lea copy_end,A4\n\t" From 601fb73564df91f9213675efb1d703a8b88165d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 21:24:50 +0000 Subject: [PATCH 054/276] even less undefied symbol references --- BaS_GNU/bas.hex.map | 238 -------------------------------------------- 1 file changed, 238 deletions(-) delete mode 100644 BaS_GNU/bas.hex.map diff --git a/BaS_GNU/bas.hex.map b/BaS_GNU/bas.hex.map deleted file mode 100644 index a1d8cc8..0000000 --- a/BaS_GNU/bas.hex.map +++ /dev/null @@ -1,238 +0,0 @@ - -Memory Configuration - -Name Origin Length Attributes -code 0xe0000000 0x00200000 xr -*default* 0x00000000 0xffffffff - -Linker script and memory map - - 0x1fe00000 _Bas_base = 0x1fe00000 - 0xe0000000 ___BOOT_FLASH = 0xe0000000 - 0x00800000 ___BOOT_FLASH_SIZE = 0x800000 - 0x00000000 ___SDRAM = 0x0 - 0x20000000 ___SDRAM_SIZE = 0x20000000 - 0x60000000 __VRAM = 0x60000000 - 0xff000000 ___MBAR = 0xff000000 - 0xff040000 ___MMUBAR = 0xff040000 - 0xff100000 ___RAMBAR0 = 0xff100000 - 0x00001000 ___RAMBAR0_SIZE = 0x1000 - 0xff100ffc ___SUP_SP = ((___RAMBAR0 + ___RAMBAR0_SIZE) - 0x4) - 0xff101000 ___RAMBAR1 = 0xff101000 - 0x00001000 ___RAMBAR1_SIZE = 0x1000 - 0xff100800 _rt_mod = (___RAMBAR0 + 0x800) - 0xff100804 _rt_ssp = (___RAMBAR0 + 0x804) - 0xff100808 _rt_usp = (___RAMBAR0 + 0x808) - 0xff10080c _rt_vbr = (___RAMBAR0 + 0x80c) - 0xff100810 _rt_cacr = (___RAMBAR0 + 0x810) - 0xff100814 _rt_asid = (___RAMBAR0 + 0x814) - 0xff100818 _rt_acr0 = (___RAMBAR0 + 0x818) - 0xff10081c _rt_acr1 = (___RAMBAR0 + 0x81c) - 0xff100820 _rt_acr2 = (___RAMBAR0 + 0x820) - 0xff100824 _rt_acr3 = (___RAMBAR0 + 0x824) - 0xff100828 _rt_mmubar = (___RAMBAR0 + 0x828) - 0xff10082c _rt_sr = (___RAMBAR0 + 0x82c) - 0xff100830 _d0_save = (___RAMBAR0 + 0x830) - 0xff100834 _a7_save = (___RAMBAR0 + 0x834) - 0xff100838 _video_tlb = (___RAMBAR0 + 0x838) - 0xff10083c _video_sbt = (___RAMBAR0 + 0x83c) - 0xff100844 _rt_mbar = (___RAMBAR0 + 0x844) - 0xff010000 __SYS_SRAM = 0xff010000 - 0x00008000 __SYS_SRAM_SIZE = 0x8000 - -.code - -.text 0xe0000000 0x30a0 - objs/startcf.o(.text) - .text 0xe0000000 0x58 objs/startcf.o - 0xe0000000 __startup - objs/sysinit.o(.text) - .text 0xe0000058 0xc4c objs/sysinit.o - 0xe0000058 _init_slt - 0xe000007e _init_gpio - 0xe00000d2 _init_serial - 0xe0000202 _init_ddram - 0xe00002e8 _init_fbcs - 0xe00003aa _init_fpga - 0xe00004bc _wait_pll - 0xe00004d2 _init_pll - 0xe0000570 _init_video_ddr - 0xe0000598 _init_PCI - 0xe0000642 _test_upd720101 - 0xe00006ac _vdi_on - 0xe0000a18 _init_ac97 - 0xe0000c1a ___initialize_hardware - objs/BaS.o(.text) - .text 0xe0000ca4 0x290 objs/BaS.o - 0xe0000ca4 _wait_10ms - 0xe0000cbc _wait_1ms - 0xe0000cd4 _wait_100us - 0xe0000cec _wait_50us - 0xe0000d04 _wait_10us - 0xe0000d1c _wait_1us - 0xe0000d34 _BaS - objs/sd_card.o(.text) - .text 0xe0000f34 0x88 objs/sd_card.o - 0xe0000f34 _sd_com - 0xe0000f5c _sd_get_status - 0xe0000f78 _sd_rcv_info - 0xe0000fb8 _sd_card_idle - objs/mmu.o(.text) - .text 0xe0000fbc 0x1b0 objs/mmu.o - 0xe0000fbc _mmu_init - 0xe0001130 _mmutr_miss - objs/exceptions.o(.text) - .text 0xe000116c 0x9b4 objs/exceptions.o - 0xe000116c _vec_init - objs/supervisor.o(.text) - .text 0xe0001b20 0x5cc objs/supervisor.o - 0xe0001b20 _privileg_violation - 0xe000209e cpusha - objs/ewf.o(.text) - .text 0xe00020ec 0xe40 objs/ewf.o - 0xe00020f2 ewf - objs/illegal_instruction.o(.text) - .text 0xe0002f2c 0x170 objs/illegal_instruction.o - 0xe0003098 _illegal_instruction - 0xe0003098 _illegal_table_make - objs/last.o(.text) - .text 0xe000309c 0x4 objs/last.o - 0xe000309c copy_end - 0xe000309c _copy_end -LOAD objs/startcf.o -LOAD objs/sysinit.o -LOAD objs/BaS.o -LOAD objs/sd_card.o -LOAD objs/last.o -LOAD objs/mmu.o -LOAD objs/exceptions.o -LOAD objs/supervisor.o -LOAD objs/ewf.o -LOAD objs/illegal_instruction.o -OUTPUT(bas.hex srec) - -.data 0x00000000 0x0 - .data 0x00000000 0x0 objs/startcf.o - .data 0x00000000 0x0 objs/sysinit.o - .data 0x00000000 0x0 objs/BaS.o - .data 0x00000000 0x0 objs/sd_card.o - .data 0x00000000 0x0 objs/mmu.o - .data 0x00000000 0x0 objs/exceptions.o - .data 0x00000000 0x0 objs/supervisor.o - .data 0x00000000 0x0 objs/ewf.o - .data 0x00000000 0x0 objs/illegal_instruction.o - .data 0x00000000 0x0 objs/last.o - -.bss 0x00000000 0x0 - .bss 0x00000000 0x0 objs/startcf.o - .bss 0x00000000 0x0 objs/sysinit.o - .bss 0x00000000 0x0 objs/BaS.o - .bss 0x00000000 0x0 objs/sd_card.o - .bss 0x00000000 0x0 objs/mmu.o - .bss 0x00000000 0x0 objs/exceptions.o - .bss 0x00000000 0x0 objs/supervisor.o - .bss 0x00000000 0x0 objs/ewf.o - .bss 0x00000000 0x0 objs/illegal_instruction.o - .bss 0x00000000 0x0 objs/last.o - -Cross Reference Table - -Symbol File -BaS objs/sysinit.o -MCF_MMU_MMUCR objs/startcf.o -_BaS objs/BaS.o -_Bas_base objs/exceptions.o - objs/sysinit.o -_MCF_PCICR1_CACHELINESIZE objs/sysinit.o -_MCF_PCICR2_MINGNT objs/sysinit.o -__MBAR objs/exceptions.o -__MMUBAR objs/exceptions.o -__VRAM objs/sysinit.o -___BOOT_FLASH objs/exceptions.o - objs/startcf.o -___Bas_base objs/BaS.o -___MBAR objs/exceptions.o - objs/sd_card.o - objs/BaS.o - objs/sysinit.o - objs/startcf.o -___MMUBAR objs/mmu.o - objs/BaS.o - objs/startcf.o -___RAMBAR0 objs/exceptions.o - objs/startcf.o -___RAMBAR1 objs/startcf.o -___SUP_SP objs/exceptions.o - objs/startcf.o -___initialize_hardware objs/sysinit.o -__startup objs/startcf.o -_copy_end objs/last.o -_copy_firetos objs/BaS.o -_illegal_instruction objs/illegal_instruction.o - objs/exceptions.o -_illegal_table_make objs/illegal_instruction.o - objs/BaS.o -_init_PCI objs/sysinit.o -_init_ac97 objs/sysinit.o -_init_ddram objs/sysinit.o -_init_fbcs objs/sysinit.o -_init_fpga objs/sysinit.o -_init_gpio objs/sysinit.o -_init_pll objs/sysinit.o -_init_serial objs/sysinit.o -_init_slt objs/sysinit.o -_init_video_ddr objs/sysinit.o -_initialize_hardware objs/startcf.o -_mmu_init objs/mmu.o - objs/BaS.o -_mmutr_miss objs/mmu.o - objs/exceptions.o -_privileg_violation objs/supervisor.o - objs/exceptions.o -_rt_acr0 objs/mmu.o -_rt_acr1 objs/mmu.o -_rt_acr2 objs/mmu.o -_rt_acr3 objs/mmu.o -_rt_asid objs/mmu.o -_rt_cacr objs/supervisor.o - objs/mmu.o -_rt_mbar objs/startcf.o -_rt_mmubar objs/mmu.o -_rt_mod objs/supervisor.o - objs/exceptions.o -_rt_ssp objs/exceptions.o -_rt_usp objs/exceptions.o -_rt_vbr objs/exceptions.o -_sd_card_idle objs/sd_card.o - objs/BaS.o -_sd_card_init objs/BaS.o -_sd_com objs/sd_card.o -_sd_get_status objs/sd_card.o -_sd_rcv_info objs/sd_card.o -_test_upd720101 objs/sysinit.o -_vdi_on objs/sysinit.o -_vec_init objs/exceptions.o - objs/BaS.o -_video_sbt objs/exceptions.o - objs/mmu.o -_video_tlb objs/exceptions.o - objs/mmu.o -_wait1ms objs/sysinit.o -_wait_100us objs/BaS.o -_wait_10ms objs/BaS.o -_wait_10us objs/BaS.o - objs/sysinit.o -_wait_1ms objs/BaS.o -_wait_1us objs/BaS.o -_wait_50us objs/BaS.o - objs/sysinit.o -_wait_pll objs/sysinit.o -_warte10us objs/sysinit.o -copy_end objs/last.o - objs/sysinit.o -cpusha objs/supervisor.o - objs/exceptions.o - objs/mmu.o -ewf objs/ewf.o - objs/illegal_instruction.o -rt_cacr objs/sysinit.o From e4671bd6decdafebb874abbe2e2edfab0501458c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 21:39:10 +0000 Subject: [PATCH 055/276] --- BaS_GNU/flash.lk | 52 ++++++++++++++++++------------------ BaS_GNU/sources/exceptions.S | 8 +++--- BaS_GNU/sources/sysinit.c | 2 +- 3 files changed, 31 insertions(+), 31 deletions(-) diff --git a/BaS_GNU/flash.lk b/BaS_GNU/flash.lk index ca45959..27b4b52 100644 --- a/BaS_GNU/flash.lk +++ b/BaS_GNU/flash.lk @@ -27,46 +27,46 @@ SECTIONS { */ /* Memory mapped registers */ - ___MBAR = ABSOLUTE(0xFF000000); - ___MMUBAR = ABSOLUTE(0xFF040000); + __MBAR = ABSOLUTE(0xFF000000); + __MMUBAR = ABSOLUTE(0xFF040000); /* * 4KB on-chip Core SRAM0: -> exception table and exception stack */ - ___RAMBAR0 = ABSOLUTE(0xFF100000); - ___RAMBAR0_SIZE = ABSOLUTE(0x00001000); + __RAMBAR0 = ABSOLUTE(0xFF100000); + __RAMBAR0_SIZE = ABSOLUTE(0x00001000); - ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4; + __SUP_SP = ABSOLUTE(__RAMBAR0 + __RAMBAR0_SIZE - 4); /* 4KB on-chip Core SRAM1: -> modified code */ - ___RAMBAR1 = ABSOLUTE(0xFF101000); - ___RAMBAR1_SIZE = ABSOLUTE(0x00001000); + __RAMBAR1 = ABSOLUTE(0xFF101000); + __RAMBAR1_SIZE = ABSOLUTE(0x00001000); /* Systemveriablem:****************************************** */ /* RAMBAR0 0 bis 0x7FF -> exception vectoren */ - _rt_mod = ___RAMBAR0 + 0x800; - _rt_ssp = ___RAMBAR0 + 0x804; - _rt_usp = ___RAMBAR0 + 0x808; - _rt_vbr = ___RAMBAR0 + 0x80C; /* (8)01 */ - _rt_cacr = ___RAMBAR0 + 0x810; /* 002 */ - _rt_asid = ___RAMBAR0 + 0x814; /* 003 */ - _rt_acr0 = ___RAMBAR0 + 0x818; /* 004 */ - _rt_acr1 = ___RAMBAR0 + 0x81c; /* 005 */ - _rt_acr2 = ___RAMBAR0 + 0x820; /* 006 */ - _rt_acr3 = ___RAMBAR0 + 0x824; /* 007 */ - _rt_mmubar = ___RAMBAR0 + 0x828; /* 008 */ - _rt_sr = ___RAMBAR0 + 0x82c; - _d0_save = ___RAMBAR0 + 0x830; - _a7_save = ___RAMBAR0 + 0x834; - _video_tlb = ___RAMBAR0 + 0x838; - _video_sbt = ___RAMBAR0 + 0x83C; - _rt_mbar = ___RAMBAR0 + 0x844; /* (c)0f */ + _rt_mod = __RAMBAR0 + 0x800; + _rt_ssp = __RAMBAR0 + 0x804; + _rt_usp = __RAMBAR0 + 0x808; + _rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */ + _rt_cacr = __RAMBAR0 + 0x810; /* 002 */ + _rt_asid = __RAMBAR0 + 0x814; /* 003 */ + _rt_acr0 = __RAMBAR0 + 0x818; /* 004 */ + _rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */ + _rt_acr2 = __RAMBAR0 + 0x820; /* 006 */ + _rt_acr3 = __RAMBAR0 + 0x824; /* 007 */ + _rt_mmubar = __RAMBAR0 + 0x828; /* 008 */ + _rt_sr = __RAMBAR0 + 0x82c; + _d0_save = __RAMBAR0 + 0x830; + _a7_save = __RAMBAR0 + 0x834; + _video_tlb = __RAMBAR0 + 0x838; + _video_sbt = __RAMBAR0 + 0x83C; + _rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */ /**********************************************************/ /* 32KB on-chip System SRAM */ - __SYS_SRAM = 0xFF010000; - __SYS_SRAM_SIZE = 0x00008000; + __SYS_SRAM = ABSOLUTE(0xFF010000); + __SYS_SRAM_SIZE = ABSOLUTE(0x00008000); .code : {} > code diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S index 6dc2797..d49ca70 100644 --- a/BaS_GNU/sources/exceptions.S +++ b/BaS_GNU/sources/exceptions.S @@ -208,7 +208,7 @@ _vec_init: clr.l _rt_ssp clr.l _rt_usp clr.l _rt_vbr - move.l #___RAMBAR0,d0 // sind in rambar0 + move.l #__RAMBAR0,d0 // sind in rambar0 movec d0,VBR move.l d0,a0 move.l a0,a2 @@ -220,7 +220,7 @@ init_vec_loop: subq.l #1,d0 bne init_vec_loop - move.l #___SUP_SP,(a0) + move.l #__SUP_SP,(a0) lea reset_vector(pc),a1 move.l a1,0x04(a0) lea acess(pc),a1 @@ -366,7 +366,7 @@ reset_vector: move.l #0x31415926,d0 cmp.l 0x426,d0 // reset vector gültg? beq std_exc_vec // ja-> - jmp ___BOOT_FLASH // sonst kaltstart + jmp __BOOT_FLASH // sonst kaltstart acess: move.w #0x2700,sr // disable interrupt move.l d0,-(sp) // ++ vr @@ -679,7 +679,7 @@ irq7: lea -12(sp),sp movem.l d0/a0,(sp) - move.l ___RAMBAR0+0x008,a0 // Real Access Error handler + move.l __RAMBAR0+0x008,a0 // Real Access Error handler move.l a0,8(sp) // This will be the return address for rts move.w 12(sp),d0 // Format/Vector word diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index c44e4b8..2130a49 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -768,7 +768,7 @@ void __initialize_hardware(void) { _init_hardware: asm( "move.l #0x000C8120,D0\n\t" - "move.l D0,rt_cacr\n\t" + "move.l D0,_rt_cacr\n\t" "movec D0,CACR\n\t" "nop\n\t" ); From 4a3d01c13a97c3e1ad9e3265eda22d3dcd22243f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 13 Oct 2012 21:40:28 +0000 Subject: [PATCH 056/276] --- BaS_GNU/firebeeV1.mcp | Bin 110530 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100644 BaS_GNU/firebeeV1.mcp diff --git a/BaS_GNU/firebeeV1.mcp b/BaS_GNU/firebeeV1.mcp deleted file mode 100644 index af6610311b9139379d75980a8eb8c2741bdacbf3..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 110530 zcmeHwd6*m3mG5oS0%L5_VGCe2kqwx|wlKyf#@N{1YPH>_7t!6um^8?0sk&RXHniAn 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v9qVcruQLBn9WB Date: Sun, 14 Oct 2012 05:34:33 +0000 Subject: [PATCH 057/276] more fiddling with leading underscore in symbols --- BaS_GNU/flash.lk | 2 +- BaS_GNU/include/MCF5475.h | 24 +- BaS_GNU/include/MCF5475_CLOCK.h | 2 +- BaS_GNU/include/MCF5475_CTM.h | 20 +- BaS_GNU/include/MCF5475_DMA.h | 126 ++++---- BaS_GNU/include/MCF5475_DSPI.h | 50 +-- BaS_GNU/include/MCF5475_EPORT.h | 12 +- BaS_GNU/include/MCF5475_FBCS.h | 42 +-- BaS_GNU/include/MCF5475_FEC.h | 540 +++++++++++++++---------------- BaS_GNU/include/MCF5475_GPIO.h | 104 +++--- BaS_GNU/include/MCF5475_GPT.h | 40 +-- BaS_GNU/include/MCF5475_I2C.h | 12 +- BaS_GNU/include/MCF5475_INTC.h | 162 +++++----- BaS_GNU/include/MCF5475_MMU.h | 12 +- BaS_GNU/include/MCF5475_PAD.h | 24 +- BaS_GNU/include/MCF5475_PCI.h | 94 +++--- BaS_GNU/include/MCF5475_PCIARB.h | 4 +- BaS_GNU/include/MCF5475_PSC.h | 438 ++++++++++++------------- BaS_GNU/include/MCF5475_SDRAMC.h | 20 +- BaS_GNU/include/MCF5475_SEC.h | 96 +++--- BaS_GNU/include/MCF5475_SIU.h | 8 +- BaS_GNU/include/MCF5475_SLT.h | 24 +- BaS_GNU/sources/BaS.c | 4 +- BaS_GNU/sources/startcf.c | 12 +- BaS_GNU/sources/startcf.h | 4 +- BaS_GNU/sources/sysinit.c | 2 +- 26 files changed, 939 insertions(+), 939 deletions(-) diff --git a/BaS_GNU/flash.lk b/BaS_GNU/flash.lk index 27b4b52..29dfa72 100644 --- a/BaS_GNU/flash.lk +++ b/BaS_GNU/flash.lk @@ -3,7 +3,7 @@ MEMORY { } SECTIONS { - _Bas_base = 0x1FE00000; + ___Bas_base = ABSOLUTE(0x1FE00000); /* Board Memory map definitions from linker command files: * __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE diff --git a/BaS_GNU/include/MCF5475.h b/BaS_GNU/include/MCF5475.h index e64b900..fa08e81 100644 --- a/BaS_GNU/include/MCF5475.h +++ b/BaS_GNU/include/MCF5475.h @@ -23,19 +23,19 @@ * linker symbols must be defined in the linker command file. */ -extern uint8_t __MBAR[]; -extern uint8_t __MMUBAR[]; -extern uint8_t __RAMBAR0[]; -extern uint8_t __RAMBAR0_SIZE[]; -extern uint8_t __RAMBAR1[]; -extern uint8_t __RAMBAR1_SIZE[]; +extern uint8_t _MBAR[]; +extern uint8_t _MMUBAR[]; +extern uint8_t _RAMBAR0[]; +extern uint8_t _RAMBAR0_SIZE[]; +extern uint8_t _RAMBAR1[]; +extern uint8_t _RAMBAR1_SIZE[]; -#define MBAR_ADDRESS (uint32_t)__MBAR -#define MMUBAR_ADDRESS (uint32_t)__MMUBAR -#define RAMBAR0_ADDRESS (uint32_t)__RAMBAR0 -#define RAMBAR0_SIZE (uint32_t)__RAMBAR0_SIZE -#define RAMBAR1_ADDRESS (uint32_t)__RAMBAR1 -#define RAMBAR1_SIZE (uint32_t)__RAMBAR1_SIZE +#define MBAR_ADDRESS (uint32_t)_MBAR +#define MMUBAR_ADDRESS (uint32_t)_MMUBAR +#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0 +#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE +#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1 +#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE #include "MCF5475_SIU.h" diff --git a/BaS_GNU/include/MCF5475_CLOCK.h b/BaS_GNU/include/MCF5475_CLOCK.h index d56c057..4603098 100644 --- a/BaS_GNU/include/MCF5475_CLOCK.h +++ b/BaS_GNU/include/MCF5475_CLOCK.h @@ -24,7 +24,7 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&__MBAR[0x300])) +#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300])) /* Bit definitions and macros for MCF_CLOCK_SPCR */ diff --git a/BaS_GNU/include/MCF5475_CTM.h b/BaS_GNU/include/MCF5475_CTM.h index b2d8776..5ba86e4 100644 --- a/BaS_GNU/include/MCF5475_CTM.h +++ b/BaS_GNU/include/MCF5475_CTM.h @@ -24,16 +24,16 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&__MBAR[0x7F00])) -#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&__MBAR[0x7F04])) -#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&__MBAR[0x7F08])) -#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&__MBAR[0x7F0C])) -#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&__MBAR[0x7F10])) -#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&__MBAR[0x7F14])) -#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&__MBAR[0x7F18])) -#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&__MBAR[0x7F1C])) -#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&__MBAR[0x7F00 + ((x)*0x4)])) -#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&__MBAR[0x7F10 + ((x-4)*0x4)])) +#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00])) +#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04])) +#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08])) +#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C])) +#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10])) +#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14])) +#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18])) +#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C])) +#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)])) +#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)])) /* Bit definitions and macros for MCF_CTM_CTCRF */ diff --git a/BaS_GNU/include/MCF5475_DMA.h b/BaS_GNU/include/MCF5475_DMA.h index 9d84060..3334cca 100644 --- a/BaS_GNU/include/MCF5475_DMA.h +++ b/BaS_GNU/include/MCF5475_DMA.h @@ -24,69 +24,69 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&__MBAR[0x8000])) -#define MCF_DMA_CP (*(volatile uint32_t*)(&__MBAR[0x8004])) -#define MCF_DMA_EP (*(volatile uint32_t*)(&__MBAR[0x8008])) -#define MCF_DMA_VP (*(volatile uint32_t*)(&__MBAR[0x800C])) -#define MCF_DMA_PTD (*(volatile uint32_t*)(&__MBAR[0x8010])) -#define MCF_DMA_DIPR (*(volatile uint32_t*)(&__MBAR[0x8014])) -#define MCF_DMA_DIMR (*(volatile uint32_t*)(&__MBAR[0x8018])) -#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&__MBAR[0x801C])) -#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&__MBAR[0x801E])) -#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&__MBAR[0x8020])) -#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&__MBAR[0x8022])) -#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&__MBAR[0x8024])) -#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&__MBAR[0x8026])) -#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&__MBAR[0x8028])) -#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&__MBAR[0x802A])) -#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&__MBAR[0x802C])) -#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&__MBAR[0x802E])) -#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&__MBAR[0x8030])) -#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&__MBAR[0x8032])) -#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&__MBAR[0x8034])) -#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&__MBAR[0x8036])) -#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&__MBAR[0x8038])) -#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&__MBAR[0x803A])) -#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&__MBAR[0x803C])) -#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&__MBAR[0x803D])) -#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&__MBAR[0x803E])) -#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&__MBAR[0x803F])) -#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&__MBAR[0x8040])) -#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&__MBAR[0x8041])) -#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&__MBAR[0x8042])) -#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&__MBAR[0x8043])) -#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&__MBAR[0x8044])) -#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&__MBAR[0x8045])) -#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&__MBAR[0x8046])) -#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&__MBAR[0x8047])) -#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&__MBAR[0x8048])) -#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&__MBAR[0x8049])) -#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&__MBAR[0x804A])) -#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&__MBAR[0x804B])) -#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&__MBAR[0x804C])) -#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&__MBAR[0x804D])) -#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&__MBAR[0x804E])) -#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&__MBAR[0x804F])) -#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&__MBAR[0x8050])) -#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&__MBAR[0x8051])) -#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&__MBAR[0x8052])) -#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&__MBAR[0x8053])) -#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&__MBAR[0x8054])) -#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&__MBAR[0x8055])) -#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&__MBAR[0x8056])) -#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&__MBAR[0x8057])) -#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&__MBAR[0x8058])) -#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&__MBAR[0x8059])) -#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&__MBAR[0x805A])) -#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&__MBAR[0x805B])) -#define MCF_DMA_IMCR (*(volatile uint32_t*)(&__MBAR[0x805C])) -#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&__MBAR[0x8060])) -#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&__MBAR[0x8064])) -#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&__MBAR[0x8070])) -#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&__MBAR[0x8074])) -#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&__MBAR[0x8078])) -#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&__MBAR[0x801C + ((x)*0x2)])) -#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&__MBAR[0x803C + ((x)*0x1)])) +#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000])) +#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004])) +#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008])) +#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C])) +#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010])) +#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014])) +#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018])) +#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C])) +#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E])) +#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020])) +#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022])) +#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024])) +#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026])) +#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028])) +#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A])) +#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C])) +#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E])) +#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030])) +#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032])) +#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034])) +#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036])) +#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038])) +#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A])) +#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C])) +#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D])) +#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E])) +#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F])) +#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040])) +#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041])) +#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042])) +#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043])) +#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044])) +#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045])) +#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046])) +#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047])) +#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048])) +#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049])) +#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A])) +#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B])) +#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C])) +#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D])) +#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E])) +#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F])) +#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050])) +#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051])) +#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052])) +#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053])) +#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054])) +#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055])) +#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056])) +#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057])) +#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058])) +#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059])) +#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A])) +#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B])) +#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C])) +#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060])) +#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064])) +#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070])) +#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074])) +#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078])) +#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)])) +#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)])) /* Bit definitions and macros for MCF_DMA_TASKBAR */ diff --git a/BaS_GNU/include/MCF5475_DSPI.h b/BaS_GNU/include/MCF5475_DSPI.h index d969e8f..76cac28 100644 --- a/BaS_GNU/include/MCF5475_DSPI.h +++ b/BaS_GNU/include/MCF5475_DSPI.h @@ -24,31 +24,31 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&__MBAR[0x8A00])) -#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&__MBAR[0x8A08])) -#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&__MBAR[0x8A0C])) -#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&__MBAR[0x8A10])) -#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&__MBAR[0x8A14])) -#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&__MBAR[0x8A18])) -#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&__MBAR[0x8A1C])) -#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&__MBAR[0x8A20])) -#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&__MBAR[0x8A24])) -#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&__MBAR[0x8A28])) -#define MCF_DSPI_DSR (*(volatile uint32_t*)(&__MBAR[0x8A2C])) -#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&__MBAR[0x8A30])) -#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&__MBAR[0x8A34])) -#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&__MBAR[0x8A38])) -#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&__MBAR[0x8A3C])) -#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&__MBAR[0x8A40])) -#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&__MBAR[0x8A44])) -#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&__MBAR[0x8A48])) -#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&__MBAR[0x8A7C])) -#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&__MBAR[0x8A80])) -#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&__MBAR[0x8A84])) -#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&__MBAR[0x8A88])) -#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&__MBAR[0x8A0C + ((x)*0x4)])) -#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8A3C + ((x)*0x4)])) -#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8A7C + ((x)*0x4)])) +#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00])) +#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08])) +#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C])) +#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10])) +#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14])) +#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18])) +#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C])) +#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20])) +#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24])) +#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28])) +#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C])) +#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30])) +#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34])) +#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38])) +#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C])) +#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40])) +#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44])) +#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48])) +#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C])) +#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80])) +#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84])) +#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88])) +#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)])) +#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)])) +#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)])) /* Bit definitions and macros for MCF_DSPI_DMCR */ diff --git a/BaS_GNU/include/MCF5475_EPORT.h b/BaS_GNU/include/MCF5475_EPORT.h index 37d9bf8..6506196 100644 --- a/BaS_GNU/include/MCF5475_EPORT.h +++ b/BaS_GNU/include/MCF5475_EPORT.h @@ -24,12 +24,12 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&__MBAR[0xF00])) -#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&__MBAR[0xF04])) -#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&__MBAR[0xF05])) -#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&__MBAR[0xF08])) -#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&__MBAR[0xF09])) -#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&__MBAR[0xF0C])) +#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00])) +#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04])) +#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05])) +#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08])) +#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09])) +#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C])) diff --git a/BaS_GNU/include/MCF5475_FBCS.h b/BaS_GNU/include/MCF5475_FBCS.h index 938a5f0..37daf00 100644 --- a/BaS_GNU/include/MCF5475_FBCS.h +++ b/BaS_GNU/include/MCF5475_FBCS.h @@ -24,33 +24,33 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&__MBAR[0x500])) -#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&__MBAR[0x504])) -#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&__MBAR[0x508])) +#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500])) +#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504])) +#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508])) -#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&__MBAR[0x50C])) -#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&__MBAR[0x510])) -#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&__MBAR[0x514])) +#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C])) +#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510])) +#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514])) -#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&__MBAR[0x518])) -#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&__MBAR[0x51C])) -#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&__MBAR[0x520])) +#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518])) +#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C])) +#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520])) -#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&__MBAR[0x524])) -#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&__MBAR[0x528])) -#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&__MBAR[0x52C])) +#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524])) +#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528])) +#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C])) -#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&__MBAR[0x530])) -#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&__MBAR[0x534])) -#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&__MBAR[0x538])) +#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530])) +#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534])) +#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538])) -#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&__MBAR[0x53C])) -#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&__MBAR[0x540])) -#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&__MBAR[0x544])) +#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C])) +#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540])) +#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544])) -#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&__MBAR[0x500 + ((x)*0xC)])) -#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&__MBAR[0x504 + ((x)*0xC)])) -#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&__MBAR[0x508 + ((x)*0xC)])) +#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)])) +#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)])) +#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)])) /* Bit definitions and macros for MCF_FBCS_CSAR */ diff --git a/BaS_GNU/include/MCF5475_FEC.h b/BaS_GNU/include/MCF5475_FEC.h index dc998ff..fdd9403 100644 --- a/BaS_GNU/include/MCF5475_FEC.h +++ b/BaS_GNU/include/MCF5475_FEC.h @@ -24,278 +24,278 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_FEC0_EIR (*(volatile uint32_t*)(&__MBAR[0x9004])) -#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&__MBAR[0x9008])) -#define MCF_FEC0_ECR (*(volatile uint32_t*)(&__MBAR[0x9024])) -#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&__MBAR[0x9040])) -#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&__MBAR[0x9044])) -#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&__MBAR[0x9064])) -#define MCF_FEC0_RCR (*(volatile uint32_t*)(&__MBAR[0x9084])) -#define MCF_FEC0_RHR (*(volatile uint32_t*)(&__MBAR[0x9088])) -#define MCF_FEC0_TCR (*(volatile uint32_t*)(&__MBAR[0x90C4])) -#define MCF_FEC0_PALR (*(volatile uint32_t*)(&__MBAR[0x90E4])) -#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&__MBAR[0x90E8])) -#define MCF_FEC0_OPD (*(volatile uint32_t*)(&__MBAR[0x90EC])) -#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&__MBAR[0x9118])) -#define MCF_FEC0_IALR (*(volatile uint32_t*)(&__MBAR[0x911C])) -#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&__MBAR[0x9120])) -#define MCF_FEC0_GALR (*(volatile uint32_t*)(&__MBAR[0x9124])) -#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&__MBAR[0x9144])) -#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&__MBAR[0x9184])) -#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&__MBAR[0x9188])) -#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&__MBAR[0x918C])) -#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&__MBAR[0x9190])) -#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&__MBAR[0x9194])) -#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&__MBAR[0x9198])) -#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&__MBAR[0x919C])) -#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&__MBAR[0x91A0])) -#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&__MBAR[0x91A4])) -#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&__MBAR[0x91A8])) -#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&__MBAR[0x91AC])) -#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&__MBAR[0x91B0])) -#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&__MBAR[0x91B4])) -#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&__MBAR[0x91B8])) -#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&__MBAR[0x91BC])) -#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&__MBAR[0x91C0])) -#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&__MBAR[0x91C4])) -#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&__MBAR[0x91C8])) -#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9200])) -#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9204])) -#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9208])) -#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x920C])) -#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9210])) -#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9214])) -#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9218])) -#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&__MBAR[0x921C])) -#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&__MBAR[0x9220])) -#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&__MBAR[0x9224])) -#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&__MBAR[0x9228])) -#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x922C])) -#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x9230])) -#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x9234])) -#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x9238])) -#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x923C])) -#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x9240])) -#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&__MBAR[0x9244])) -#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9248])) -#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x924C])) -#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&__MBAR[0x9250])) -#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&__MBAR[0x9254])) -#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&__MBAR[0x9258])) -#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&__MBAR[0x925C])) -#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&__MBAR[0x9260])) -#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&__MBAR[0x9264])) -#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&__MBAR[0x9268])) -#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&__MBAR[0x926C])) -#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&__MBAR[0x9270])) -#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x9274])) -#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&__MBAR[0x9280])) -#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9284])) -#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9288])) -#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x928C])) -#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9290])) -#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9294])) -#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9298])) -#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&__MBAR[0x929C])) -#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&__MBAR[0x92A0])) -#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&__MBAR[0x92A4])) -#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&__MBAR[0x92A8])) -#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x92AC])) -#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x92B0])) -#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x92B4])) -#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x92B8])) -#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x92BC])) -#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x92C0])) -#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&__MBAR[0x92C4])) -#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&__MBAR[0x92C8])) -#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x92CC])) -#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&__MBAR[0x92D0])) -#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&__MBAR[0x92D4])) -#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&__MBAR[0x92D8])) -#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&__MBAR[0x92DC])) -#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x92E0])) +#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004])) +#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008])) +#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024])) +#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040])) +#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044])) +#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064])) +#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084])) +#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088])) +#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4])) +#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4])) +#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8])) +#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC])) +#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118])) +#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C])) +#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120])) +#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124])) +#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144])) +#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184])) +#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188])) +#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C])) +#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190])) +#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194])) +#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198])) +#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C])) +#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0])) +#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4])) +#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8])) +#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC])) +#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0])) +#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4])) +#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8])) +#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC])) +#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0])) +#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4])) +#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8])) +#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200])) +#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204])) +#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208])) +#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C])) +#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210])) +#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214])) +#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218])) +#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C])) +#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220])) +#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224])) +#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228])) +#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C])) +#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230])) +#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234])) +#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238])) +#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C])) +#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240])) +#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244])) +#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248])) +#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C])) +#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250])) +#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254])) +#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258])) +#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C])) +#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260])) +#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264])) +#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268])) +#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C])) +#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270])) +#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274])) +#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280])) +#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284])) +#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288])) +#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C])) +#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290])) +#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294])) +#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298])) +#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C])) +#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0])) +#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4])) +#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8])) +#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC])) +#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0])) +#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4])) +#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8])) +#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC])) +#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0])) +#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4])) +#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8])) +#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC])) +#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0])) +#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4])) +#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8])) +#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC])) +#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0])) -#define MCF_FEC1_EIR (*(volatile uint32_t*)(&__MBAR[0x9804])) -#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&__MBAR[0x9808])) -#define MCF_FEC1_ECR (*(volatile uint32_t*)(&__MBAR[0x9824])) -#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&__MBAR[0x9840])) -#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&__MBAR[0x9844])) -#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&__MBAR[0x9864])) -#define MCF_FEC1_RCR (*(volatile uint32_t*)(&__MBAR[0x9884])) -#define MCF_FEC1_RHR (*(volatile uint32_t*)(&__MBAR[0x9888])) -#define MCF_FEC1_TCR (*(volatile uint32_t*)(&__MBAR[0x98C4])) -#define MCF_FEC1_PALR (*(volatile uint32_t*)(&__MBAR[0x98E4])) -#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&__MBAR[0x98E8])) -#define MCF_FEC1_OPD (*(volatile uint32_t*)(&__MBAR[0x98EC])) -#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&__MBAR[0x9918])) -#define MCF_FEC1_IALR (*(volatile uint32_t*)(&__MBAR[0x991C])) -#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&__MBAR[0x9920])) -#define MCF_FEC1_GALR (*(volatile uint32_t*)(&__MBAR[0x9924])) -#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&__MBAR[0x9944])) -#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&__MBAR[0x9984])) -#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&__MBAR[0x9988])) -#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&__MBAR[0x998C])) -#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&__MBAR[0x9990])) -#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&__MBAR[0x9994])) -#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&__MBAR[0x9998])) -#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&__MBAR[0x999C])) -#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&__MBAR[0x99A0])) -#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&__MBAR[0x99A4])) -#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&__MBAR[0x99A8])) -#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&__MBAR[0x99AC])) -#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&__MBAR[0x99B0])) -#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&__MBAR[0x99B4])) -#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&__MBAR[0x99B8])) -#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&__MBAR[0x99BC])) -#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&__MBAR[0x99C0])) -#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&__MBAR[0x99C4])) -#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&__MBAR[0x99C8])) -#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9A00])) -#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9A04])) -#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A08])) -#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A0C])) -#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9A10])) -#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A14])) -#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A18])) -#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&__MBAR[0x9A1C])) -#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&__MBAR[0x9A20])) -#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&__MBAR[0x9A24])) -#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&__MBAR[0x9A28])) -#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x9A2C])) -#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x9A30])) -#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x9A34])) -#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x9A38])) -#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x9A3C])) -#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x9A40])) -#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&__MBAR[0x9A44])) -#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&__MBAR[0x9A48])) -#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x9A4C])) -#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&__MBAR[0x9A50])) -#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&__MBAR[0x9A54])) -#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&__MBAR[0x9A58])) -#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&__MBAR[0x9A5C])) -#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&__MBAR[0x9A60])) -#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&__MBAR[0x9A64])) -#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&__MBAR[0x9A68])) -#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&__MBAR[0x9A6C])) -#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&__MBAR[0x9A70])) -#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x9A74])) -#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&__MBAR[0x9A80])) -#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&__MBAR[0x9A84])) -#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A88])) -#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&__MBAR[0x9A8C])) -#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9A90])) -#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A94])) -#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&__MBAR[0x9A98])) -#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&__MBAR[0x9A9C])) -#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&__MBAR[0x9AA0])) -#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&__MBAR[0x9AA4])) -#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&__MBAR[0x9AA8])) -#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&__MBAR[0x9AAC])) -#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&__MBAR[0x9AB0])) -#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&__MBAR[0x9AB4])) -#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&__MBAR[0x9AB8])) -#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&__MBAR[0x9ABC])) -#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&__MBAR[0x9AC0])) -#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&__MBAR[0x9AC4])) -#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&__MBAR[0x9AC8])) -#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&__MBAR[0x9ACC])) -#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&__MBAR[0x9AD0])) -#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&__MBAR[0x9AD4])) -#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&__MBAR[0x9AD8])) -#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&__MBAR[0x9ADC])) -#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&__MBAR[0x9AE0])) +#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804])) +#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808])) +#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824])) +#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840])) +#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844])) +#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864])) +#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884])) +#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888])) +#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4])) +#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4])) +#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8])) +#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC])) +#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918])) +#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C])) +#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920])) +#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924])) +#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944])) +#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984])) +#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988])) +#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C])) +#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990])) +#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994])) +#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998])) +#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C])) +#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0])) +#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4])) +#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8])) +#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC])) +#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0])) +#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4])) +#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8])) +#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC])) +#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0])) +#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4])) +#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8])) +#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00])) +#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04])) +#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08])) +#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C])) +#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10])) +#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14])) +#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18])) +#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C])) +#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20])) +#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24])) +#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28])) +#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C])) +#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30])) +#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34])) +#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38])) +#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C])) +#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40])) +#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44])) +#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48])) +#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C])) +#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50])) +#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54])) +#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58])) +#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C])) +#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60])) +#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64])) +#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68])) +#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C])) +#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70])) +#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74])) +#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80])) +#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84])) +#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88])) +#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C])) +#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90])) +#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94])) +#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98])) +#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C])) +#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0])) +#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4])) +#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8])) +#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC])) +#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0])) +#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4])) +#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8])) +#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC])) +#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0])) +#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4])) +#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8])) +#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC])) +#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0])) +#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4])) +#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8])) +#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC])) +#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0])) -#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&__MBAR[0x9004 + ((x)*0x800)])) -#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&__MBAR[0x9008 + ((x)*0x800)])) -#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&__MBAR[0x9024 + ((x)*0x800)])) -#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&__MBAR[0x9040 + ((x)*0x800)])) -#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&__MBAR[0x9044 + ((x)*0x800)])) -#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&__MBAR[0x9064 + ((x)*0x800)])) -#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&__MBAR[0x9084 + ((x)*0x800)])) -#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&__MBAR[0x9088 + ((x)*0x800)])) -#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&__MBAR[0x90C4 + ((x)*0x800)])) -#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&__MBAR[0x90E4 + ((x)*0x800)])) -#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&__MBAR[0x90E8 + ((x)*0x800)])) -#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&__MBAR[0x90EC + ((x)*0x800)])) -#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&__MBAR[0x9118 + ((x)*0x800)])) -#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&__MBAR[0x911C + ((x)*0x800)])) -#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&__MBAR[0x9120 + ((x)*0x800)])) -#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&__MBAR[0x9124 + ((x)*0x800)])) -#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&__MBAR[0x9144 + ((x)*0x800)])) -#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&__MBAR[0x9184 + ((x)*0x800)])) -#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&__MBAR[0x9188 + ((x)*0x800)])) -#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&__MBAR[0x918C + ((x)*0x800)])) -#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&__MBAR[0x9190 + ((x)*0x800)])) -#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&__MBAR[0x9194 + ((x)*0x800)])) -#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&__MBAR[0x9198 + ((x)*0x800)])) -#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&__MBAR[0x919C + ((x)*0x800)])) -#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&__MBAR[0x91A0 + ((x)*0x800)])) -#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&__MBAR[0x91A4 + ((x)*0x800)])) -#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&__MBAR[0x91A8 + ((x)*0x800)])) -#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&__MBAR[0x91AC + ((x)*0x800)])) -#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&__MBAR[0x91B0 + ((x)*0x800)])) -#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&__MBAR[0x91B4 + ((x)*0x800)])) -#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&__MBAR[0x91B8 + ((x)*0x800)])) -#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&__MBAR[0x91BC + ((x)*0x800)])) -#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&__MBAR[0x91C0 + ((x)*0x800)])) -#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&__MBAR[0x91C4 + ((x)*0x800)])) -#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&__MBAR[0x91C8 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x9200 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&__MBAR[0x9204 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x9208 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x920C + ((x)*0x800)])) -#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&__MBAR[0x9210 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9214 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9218 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&__MBAR[0x921C + ((x)*0x800)])) -#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&__MBAR[0x9220 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&__MBAR[0x9224 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&__MBAR[0x9228 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&__MBAR[0x922C + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&__MBAR[0x9230 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&__MBAR[0x9234 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&__MBAR[0x9238 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&__MBAR[0x923C + ((x)*0x800)])) -#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&__MBAR[0x9240 + ((x)*0x800)])) -#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&__MBAR[0x9244 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x9248 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&__MBAR[0x924C + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&__MBAR[0x9250 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&__MBAR[0x9254 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&__MBAR[0x9258 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&__MBAR[0x925C + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&__MBAR[0x9260 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&__MBAR[0x9264 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&__MBAR[0x9268 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&__MBAR[0x926C + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&__MBAR[0x9270 + ((x)*0x800)])) -#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&__MBAR[0x9274 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x9280 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&__MBAR[0x9284 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x9288 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&__MBAR[0x928C + ((x)*0x800)])) -#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&__MBAR[0x9290 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9294 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&__MBAR[0x9298 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&__MBAR[0x929C + ((x)*0x800)])) -#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&__MBAR[0x92A0 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&__MBAR[0x92A4 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&__MBAR[0x92A8 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&__MBAR[0x92AC + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&__MBAR[0x92B0 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&__MBAR[0x92B4 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&__MBAR[0x92B8 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&__MBAR[0x92BC + ((x)*0x800)])) -#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&__MBAR[0x92C0 + ((x)*0x800)])) -#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&__MBAR[0x92C4 + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&__MBAR[0x92C8 + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&__MBAR[0x92CC + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&__MBAR[0x92D0 + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&__MBAR[0x92D4 + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&__MBAR[0x92D8 + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&__MBAR[0x92DC + ((x)*0x800)])) -#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&__MBAR[0x92E0 + ((x)*0x800)])) +#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)])) +#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)])) +#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)])) +#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)])) +#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)])) +#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)])) +#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)])) +#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)])) +#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)])) +#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)])) +#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)])) +#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)])) +#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)])) +#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)])) +#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)])) +#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)])) +#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)])) +#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)])) +#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)])) +#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)])) +#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)])) +#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)])) +#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)])) +#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)])) +#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)])) +#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)])) +#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)])) +#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)])) +#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)])) +#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)])) +#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)])) +#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)])) +#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)])) +#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)])) +#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)])) /* Bit definitions and macros for MCF_FEC_EIR */ diff --git a/BaS_GNU/include/MCF5475_GPIO.h b/BaS_GNU/include/MCF5475_GPIO.h index fba9b56..5dd2583 100644 --- a/BaS_GNU/include/MCF5475_GPIO.h +++ b/BaS_GNU/include/MCF5475_GPIO.h @@ -24,70 +24,70 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA00])) -#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA10])) -#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA20])) -#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&__MBAR[0xA30])) +#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00])) +#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10])) +#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20])) +#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30])) -#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA01])) -#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA11])) -#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA21])) -#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA31])) +#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01])) +#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11])) +#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21])) +#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31])) -#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&__MBAR[0xA02])) -#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&__MBAR[0xA12])) -#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&__MBAR[0xA22])) -#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&__MBAR[0xA32])) +#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02])) +#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12])) +#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22])) +#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32])) -#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA04])) -#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA14])) -#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA24])) -#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&__MBAR[0xA34])) +#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04])) +#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14])) +#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24])) +#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34])) -#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA05])) -#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA15])) -#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA25])) -#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&__MBAR[0xA35])) +#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05])) +#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15])) +#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25])) +#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35])) -#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA06])) -#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA16])) -#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA26])) -#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&__MBAR[0xA36])) +#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06])) +#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16])) +#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26])) +#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36])) -#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA07])) -#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA17])) -#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA27])) -#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&__MBAR[0xA37])) +#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07])) +#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17])) +#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27])) +#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37])) -#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA08])) -#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA18])) -#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA28])) -#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&__MBAR[0xA38])) +#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08])) +#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18])) +#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28])) +#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38])) -#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA09])) -#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA19])) -#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA29])) -#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&__MBAR[0xA39])) +#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09])) +#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19])) +#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29])) +#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39])) -#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA0A])) -#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA1A])) -#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA2A])) -#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&__MBAR[0xA3A])) +#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A])) +#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A])) +#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A])) +#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A])) -#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA0C])) -#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA1C])) -#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA2C])) -#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&__MBAR[0xA3C])) +#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C])) +#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C])) +#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C])) +#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C])) -#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA0D])) -#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA1D])) -#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA2D])) -#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&__MBAR[0xA3D])) +#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D])) +#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D])) +#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D])) +#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D])) -#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA0E])) -#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA1E])) -#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA2E])) -#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&__MBAR[0xA3E])) +#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E])) +#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E])) +#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E])) +#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E])) diff --git a/BaS_GNU/include/MCF5475_GPT.h b/BaS_GNU/include/MCF5475_GPT.h index caf2d5b..f9fbc98 100644 --- a/BaS_GNU/include/MCF5475_GPT.h +++ b/BaS_GNU/include/MCF5475_GPT.h @@ -24,30 +24,30 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_GPT0_GMS (*(volatile uint32_t*)(&__MBAR[0x800])) -#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&__MBAR[0x804])) -#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&__MBAR[0x808])) -#define MCF_GPT0_GSR (*(volatile uint32_t*)(&__MBAR[0x80C])) +#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800])) +#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804])) +#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808])) +#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C])) -#define MCF_GPT1_GMS (*(volatile uint32_t*)(&__MBAR[0x810])) -#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&__MBAR[0x814])) -#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&__MBAR[0x818])) -#define MCF_GPT1_GSR (*(volatile uint32_t*)(&__MBAR[0x81C])) +#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810])) +#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814])) +#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818])) +#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C])) -#define MCF_GPT2_GMS (*(volatile uint32_t*)(&__MBAR[0x820])) -#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&__MBAR[0x824])) -#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&__MBAR[0x828])) -#define MCF_GPT2_GSR (*(volatile uint32_t*)(&__MBAR[0x82C])) +#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820])) +#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824])) +#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828])) +#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C])) -#define MCF_GPT3_GMS (*(volatile uint32_t*)(&__MBAR[0x830])) -#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&__MBAR[0x834])) -#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&__MBAR[0x838])) -#define MCF_GPT3_GSR (*(volatile uint32_t*)(&__MBAR[0x83C])) +#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830])) +#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834])) +#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838])) +#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C])) -#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&__MBAR[0x800 + ((x)*0x10)])) -#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&__MBAR[0x804 + ((x)*0x10)])) -#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&__MBAR[0x808 + ((x)*0x10)])) -#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&__MBAR[0x80C + ((x)*0x10)])) +#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)])) +#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)])) +#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)])) +#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)])) /* Bit definitions and macros for MCF_GPT_GMS */ diff --git a/BaS_GNU/include/MCF5475_I2C.h b/BaS_GNU/include/MCF5475_I2C.h index 70a77e9..1e8a85b 100644 --- a/BaS_GNU/include/MCF5475_I2C.h +++ b/BaS_GNU/include/MCF5475_I2C.h @@ -24,12 +24,12 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&__MBAR[0x8F00])) -#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&__MBAR[0x8F04])) -#define MCF_I2C_I2CR (*(volatile uint8_t *)(&__MBAR[0x8F08])) -#define MCF_I2C_I2SR (*(volatile uint8_t *)(&__MBAR[0x8F0C])) -#define MCF_I2C_I2DR (*(volatile uint8_t *)(&__MBAR[0x8F10])) -#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&__MBAR[0x8F20])) +#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&_MBAR[0x8F00])) +#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&_MBAR[0x8F04])) +#define MCF_I2C_I2CR (*(volatile uint8_t *)(&_MBAR[0x8F08])) +#define MCF_I2C_I2SR (*(volatile uint8_t *)(&_MBAR[0x8F0C])) +#define MCF_I2C_I2DR (*(volatile uint8_t *)(&_MBAR[0x8F10])) +#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&_MBAR[0x8F20])) diff --git a/BaS_GNU/include/MCF5475_INTC.h b/BaS_GNU/include/MCF5475_INTC.h index c9bd59e..61265ed 100644 --- a/BaS_GNU/include/MCF5475_INTC.h +++ b/BaS_GNU/include/MCF5475_INTC.h @@ -24,87 +24,87 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_INTC_IPRH (*(volatile uint32_t*)(&__MBAR[0x700])) -#define MCF_INTC_IPRL (*(volatile uint32_t*)(&__MBAR[0x704])) -#define MCF_INTC_IMRH (*(volatile uint32_t*)(&__MBAR[0x708])) -#define MCF_INTC_IMRL (*(volatile uint32_t*)(&__MBAR[0x70C])) -#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&__MBAR[0x710])) -#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&__MBAR[0x714])) -#define MCF_INTC_IRLR (*(volatile uint8_t *)(&__MBAR[0x718])) -#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&__MBAR[0x719])) -#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&__MBAR[0x741])) -#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&__MBAR[0x742])) -#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&__MBAR[0x743])) -#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&__MBAR[0x744])) -#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&__MBAR[0x745])) -#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&__MBAR[0x746])) -#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&__MBAR[0x747])) -#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&__MBAR[0x748])) -#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&__MBAR[0x749])) -#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&__MBAR[0x74A])) -#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&__MBAR[0x74B])) -#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&__MBAR[0x74C])) -#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&__MBAR[0x74D])) -#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&__MBAR[0x74E])) -#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&__MBAR[0x74F])) -#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&__MBAR[0x750])) -#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&__MBAR[0x751])) -#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&__MBAR[0x752])) -#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&__MBAR[0x753])) -#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&__MBAR[0x754])) -#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&__MBAR[0x755])) -#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&__MBAR[0x756])) -#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&__MBAR[0x757])) -#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&__MBAR[0x758])) -#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&__MBAR[0x759])) -#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&__MBAR[0x75A])) -#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&__MBAR[0x75B])) -#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&__MBAR[0x75C])) -#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&__MBAR[0x75D])) -#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&__MBAR[0x75E])) -#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&__MBAR[0x75F])) -#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&__MBAR[0x760])) -#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&__MBAR[0x761])) -#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&__MBAR[0x762])) -#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&__MBAR[0x763])) -#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&__MBAR[0x764])) -#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&__MBAR[0x765])) -#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&__MBAR[0x766])) -#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&__MBAR[0x767])) -#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&__MBAR[0x768])) -#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&__MBAR[0x769])) -#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&__MBAR[0x76A])) -#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&__MBAR[0x76B])) -#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&__MBAR[0x76C])) -#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&__MBAR[0x76D])) -#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&__MBAR[0x76E])) -#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&__MBAR[0x76F])) -#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&__MBAR[0x770])) -#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&__MBAR[0x771])) -#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&__MBAR[0x772])) -#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&__MBAR[0x773])) -#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&__MBAR[0x774])) -#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&__MBAR[0x775])) -#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&__MBAR[0x776])) -#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&__MBAR[0x777])) -#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&__MBAR[0x778])) -#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&__MBAR[0x779])) -#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&__MBAR[0x77A])) -#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&__MBAR[0x77B])) -#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&__MBAR[0x77C])) -#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&__MBAR[0x77D])) -#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&__MBAR[0x77E])) -#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&__MBAR[0x77F])) -#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&__MBAR[0x7E0])) -#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&__MBAR[0x7E4])) -#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&__MBAR[0x7E8])) -#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&__MBAR[0x7EC])) -#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&__MBAR[0x7F0])) -#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&__MBAR[0x7F4])) -#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&__MBAR[0x7F8])) -#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&__MBAR[0x7FC])) -#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&__MBAR[0x741 + ((x-1)*0x1)])) -#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&__MBAR[0x7E4 + ((x-1)*0x4)])) +#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700])) +#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704])) +#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708])) +#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C])) +#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710])) +#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714])) +#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718])) +#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719])) +#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741])) +#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742])) +#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743])) +#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744])) +#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745])) +#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746])) +#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747])) +#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748])) +#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749])) +#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A])) +#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B])) +#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C])) +#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D])) +#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E])) +#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F])) +#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750])) +#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751])) +#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752])) +#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753])) +#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754])) +#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755])) +#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756])) +#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757])) +#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758])) +#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759])) +#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A])) +#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B])) +#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C])) +#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D])) +#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E])) +#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F])) +#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760])) +#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761])) +#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762])) +#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763])) +#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764])) +#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765])) +#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766])) +#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767])) +#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768])) +#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769])) +#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A])) +#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B])) +#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C])) +#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D])) +#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E])) +#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F])) +#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770])) +#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771])) +#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772])) +#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773])) +#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774])) +#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775])) +#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776])) +#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777])) +#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778])) +#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779])) +#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A])) +#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B])) +#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C])) +#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D])) +#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E])) +#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F])) +#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0])) +#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4])) +#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8])) +#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC])) +#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0])) +#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4])) +#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8])) +#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC])) +#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)])) +#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)])) diff --git a/BaS_GNU/include/MCF5475_MMU.h b/BaS_GNU/include/MCF5475_MMU.h index a93397a..a865fd8 100644 --- a/BaS_GNU/include/MCF5475_MMU.h +++ b/BaS_GNU/include/MCF5475_MMU.h @@ -24,12 +24,12 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_MMU_MMUCR (*(volatile uint32_t*)(&__MMUBAR[0])) -#define MCF_MMU_MMUOR (*(volatile uint32_t*)(&__MMUBAR[0x4])) -#define MCF_MMU_MMUSR (*(volatile uint32_t*)(&__MMUBAR[0x8])) -#define MCF_MMU_MMUAR (*(volatile uint32_t*)(&__MMUBAR[0x10])) -#define MCF_MMU_MMUTR (*(volatile uint32_t*)(&__MMUBAR[0x14])) -#define MCF_MMU_MMUDR (*(volatile uint32_t*)(&__MMUBAR[0x18])) +#define MCF_MMU_MMUCR (*(volatile uint32_t*)(&_MMUBAR[0])) +#define MCF_MMU_MMUOR (*(volatile uint32_t*)(&_MMUBAR[0x4])) +#define MCF_MMU_MMUSR (*(volatile uint32_t*)(&_MMUBAR[0x8])) +#define MCF_MMU_MMUAR (*(volatile uint32_t*)(&_MMUBAR[0x10])) +#define MCF_MMU_MMUTR (*(volatile uint32_t*)(&_MMUBAR[0x14])) +#define MCF_MMU_MMUDR (*(volatile uint32_t*)(&_MMUBAR[0x18])) /* Bit definitions and macros for MCF_MMU_MMUCR */ diff --git a/BaS_GNU/include/MCF5475_PAD.h b/BaS_GNU/include/MCF5475_PAD.h index e2db4be..1d87e2e 100644 --- a/BaS_GNU/include/MCF5475_PAD.h +++ b/BaS_GNU/include/MCF5475_PAD.h @@ -24,18 +24,18 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&__MBAR[0xA40])) -#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&__MBAR[0xA42])) -#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&__MBAR[0xA43])) -#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&__MBAR[0xA44])) -#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&__MBAR[0xA48])) -#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&__MBAR[0xA4A])) -#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&__MBAR[0xA4C])) -#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&__MBAR[0xA4D])) -#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&__MBAR[0xA4E])) -#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&__MBAR[0xA4F])) -#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&__MBAR[0xA50])) -#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&__MBAR[0xA52])) +#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&_MBAR[0xA40])) +#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA42])) +#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&_MBAR[0xA43])) +#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&_MBAR[0xA44])) +#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&_MBAR[0xA48])) +#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&_MBAR[0xA4A])) +#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&_MBAR[0xA4C])) +#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&_MBAR[0xA4D])) +#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&_MBAR[0xA4E])) +#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&_MBAR[0xA4F])) +#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&_MBAR[0xA50])) +#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&_MBAR[0xA52])) /* Bit definitions and macros for MCF_PAD_PAR_FBCTL */ diff --git a/BaS_GNU/include/MCF5475_PCI.h b/BaS_GNU/include/MCF5475_PCI.h index b89c24d..3eb3341 100644 --- a/BaS_GNU/include/MCF5475_PCI.h +++ b/BaS_GNU/include/MCF5475_PCI.h @@ -24,53 +24,53 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&__MBAR[0xB00])) -#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&__MBAR[0xB04])) -#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&__MBAR[0xB08])) -#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&__MBAR[0xB0C])) -#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&__MBAR[0xB10])) -#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&__MBAR[0xB14])) -#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&__MBAR[0xB28])) -#define MCF_PCI_PCISID (*(volatile uint32_t*)(&__MBAR[0xB2C])) -#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&__MBAR[0xB3C])) -#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&__MBAR[0xB60])) -#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&__MBAR[0xB64])) -#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&__MBAR[0xB68])) -#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&__MBAR[0xB6C])) -#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&__MBAR[0xB70])) -#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&__MBAR[0xB74])) -#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&__MBAR[0xB78])) -#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&__MBAR[0xB80])) -#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&__MBAR[0xB84])) -#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&__MBAR[0xB88])) -#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&__MBAR[0xBF8])) -#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&__MBAR[0x8400])) -#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&__MBAR[0x8404])) -#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&__MBAR[0x8408])) -#define MCF_PCI_PCITER (*(volatile uint32_t*)(&__MBAR[0x840C])) -#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&__MBAR[0x8410])) -#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&__MBAR[0x8414])) -#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&__MBAR[0x8418])) -#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&__MBAR[0x841C])) -#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&__MBAR[0x8440])) -#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&__MBAR[0x8444])) -#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&__MBAR[0x8448])) -#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&__MBAR[0x844C])) -#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&__MBAR[0x8450])) -#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&__MBAR[0x8454])) -#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&__MBAR[0x8480])) -#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&__MBAR[0x8484])) -#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&__MBAR[0x8488])) -#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&__MBAR[0x848C])) -#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&__MBAR[0x8490])) -#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&__MBAR[0x8498])) -#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&__MBAR[0x849C])) -#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&__MBAR[0x84C0])) -#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&__MBAR[0x84C4])) -#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&__MBAR[0x84C8])) -#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&__MBAR[0x84CC])) -#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&__MBAR[0x84D0])) -#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&__MBAR[0x84D4])) +#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&_MBAR[0xB00])) +#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&_MBAR[0xB04])) +#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&_MBAR[0xB08])) +#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&_MBAR[0xB0C])) +#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&_MBAR[0xB10])) +#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&_MBAR[0xB14])) +#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&_MBAR[0xB28])) +#define MCF_PCI_PCISID (*(volatile uint32_t*)(&_MBAR[0xB2C])) +#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&_MBAR[0xB3C])) +#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&_MBAR[0xB60])) +#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&_MBAR[0xB64])) +#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&_MBAR[0xB68])) +#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&_MBAR[0xB6C])) +#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&_MBAR[0xB70])) +#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&_MBAR[0xB74])) +#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&_MBAR[0xB78])) +#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&_MBAR[0xB80])) +#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&_MBAR[0xB84])) +#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&_MBAR[0xB88])) +#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&_MBAR[0xBF8])) +#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&_MBAR[0x8400])) +#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&_MBAR[0x8404])) +#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&_MBAR[0x8408])) +#define MCF_PCI_PCITER (*(volatile uint32_t*)(&_MBAR[0x840C])) +#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&_MBAR[0x8410])) +#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&_MBAR[0x8414])) +#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&_MBAR[0x8418])) +#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&_MBAR[0x841C])) +#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&_MBAR[0x8440])) +#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&_MBAR[0x8444])) +#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&_MBAR[0x8448])) +#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&_MBAR[0x844C])) +#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&_MBAR[0x8450])) +#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&_MBAR[0x8454])) +#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&_MBAR[0x8480])) +#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&_MBAR[0x8484])) +#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&_MBAR[0x8488])) +#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&_MBAR[0x848C])) +#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&_MBAR[0x8490])) +#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&_MBAR[0x8498])) +#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&_MBAR[0x849C])) +#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&_MBAR[0x84C0])) +#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&_MBAR[0x84C4])) +#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&_MBAR[0x84C8])) +#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&_MBAR[0x84CC])) +#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&_MBAR[0x84D0])) +#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&_MBAR[0x84D4])) /* Bit definitions and macros for MCF_PCI_PCIIDR */ diff --git a/BaS_GNU/include/MCF5475_PCIARB.h b/BaS_GNU/include/MCF5475_PCIARB.h index 5fa1b18..9e8c05b 100644 --- a/BaS_GNU/include/MCF5475_PCIARB.h +++ b/BaS_GNU/include/MCF5475_PCIARB.h @@ -24,8 +24,8 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&__MBAR[0xC00])) -#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&__MBAR[0xC04])) +#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&_MBAR[0xC00])) +#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&_MBAR[0xC04])) /* Bit definitions and macros for MCF_PCIARB_PACR */ diff --git a/BaS_GNU/include/MCF5475_PSC.h b/BaS_GNU/include/MCF5475_PSC.h index 8f51214..ffa9f3e 100644 --- a/BaS_GNU/include/MCF5475_PSC.h +++ b/BaS_GNU/include/MCF5475_PSC.h @@ -24,229 +24,229 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8600])) -#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8600])) -#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8604])) -#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8604])) -#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8608])) -#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x860C])) -#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8610])) -#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8610])) -#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8614])) -#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8614])) -#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8618])) -#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x861C])) -#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8634])) -#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8638])) -#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x863C])) -#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8640])) -#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8644])) -#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8648])) -#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x864C])) -#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8650])) -#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8654])) -#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8658])) -#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x865C])) -#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8660])) -#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8664])) -#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8668])) -#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x866E])) -#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8672])) -#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8676])) -#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x867A])) -#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x867E])) -#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8680])) -#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8684])) -#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8688])) -#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x868E])) -#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8692])) -#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8696])) -#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x869A])) -#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x869E])) +#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8608])) +#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8618])) +#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x861C])) +#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8634])) +#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8638])) +#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x863C])) +#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8640])) +#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8644])) +#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8648])) +#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x864C])) +#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8650])) +#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8654])) +#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8658])) +#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x865C])) +#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8660])) +#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8664])) +#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8668])) +#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x866E])) +#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8672])) +#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8676])) +#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x867A])) +#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x867E])) +#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8680])) +#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8684])) +#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8688])) +#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x868E])) +#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8692])) +#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8696])) +#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x869A])) +#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x869E])) -#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8700])) -#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8700])) -#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8704])) -#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8704])) -#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8708])) -#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x870C])) -#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8710])) -#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8710])) -#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8714])) -#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8714])) -#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8718])) -#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x871C])) -#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8734])) -#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8738])) -#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x873C])) -#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8740])) -#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8744])) -#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8748])) -#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x874C])) -#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8750])) -#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8754])) -#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8758])) -#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x875C])) -#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8760])) -#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8764])) -#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8768])) -#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x876E])) -#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8772])) -#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8776])) -#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x877A])) -#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x877E])) -#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8780])) -#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8784])) -#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8788])) -#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x878E])) -#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8792])) -#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8796])) -#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x879A])) -#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x879E])) +#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8708])) +#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8718])) +#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x871C])) +#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8734])) +#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8738])) +#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x873C])) +#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8740])) +#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8744])) +#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8748])) +#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x874C])) +#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8750])) +#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8754])) +#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8758])) +#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x875C])) +#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8760])) +#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8764])) +#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8768])) +#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x876E])) +#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8772])) +#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8776])) +#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x877A])) +#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x877E])) +#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8780])) +#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8784])) +#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8788])) +#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x878E])) +#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8792])) +#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8796])) +#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x879A])) +#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x879E])) -#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8800])) -#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8800])) -#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8804])) -#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8804])) -#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8808])) -#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x880C])) -#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8810])) -#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8810])) -#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8814])) -#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8814])) -#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8818])) -#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x881C])) -#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8834])) -#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8838])) -#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x883C])) -#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8840])) -#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8844])) -#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8848])) -#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x884C])) -#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8850])) -#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8854])) -#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8858])) -#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x885C])) -#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8860])) -#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8864])) -#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8868])) -#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x886E])) -#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8872])) -#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8876])) -#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x887A])) -#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x887E])) -#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8880])) -#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8884])) -#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8888])) -#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x888E])) -#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8892])) -#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8896])) -#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x889A])) -#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x889E])) +#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8808])) +#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8818])) +#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x881C])) +#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8834])) +#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8838])) +#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x883C])) +#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8840])) +#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8844])) +#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8848])) +#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x884C])) +#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8850])) +#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8854])) +#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8858])) +#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x885C])) +#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8860])) +#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8864])) +#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8868])) +#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x886E])) +#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8872])) +#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8876])) +#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x887A])) +#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x887E])) +#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8880])) +#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8884])) +#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8888])) +#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x888E])) +#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8892])) +#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8896])) +#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x889A])) +#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x889E])) -#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&__MBAR[0x8900])) -#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&__MBAR[0x8900])) -#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&__MBAR[0x8904])) -#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&__MBAR[0x8904])) -#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&__MBAR[0x8908])) -#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&__MBAR[0x890C])) -#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&__MBAR[0x8910])) -#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&__MBAR[0x8910])) -#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&__MBAR[0x8914])) -#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&__MBAR[0x8914])) -#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&__MBAR[0x8918])) -#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&__MBAR[0x891C])) -#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&__MBAR[0x8934])) -#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&__MBAR[0x8938])) -#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&__MBAR[0x893C])) -#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&__MBAR[0x8940])) -#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&__MBAR[0x8944])) -#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&__MBAR[0x8948])) -#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&__MBAR[0x894C])) -#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&__MBAR[0x8950])) -#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&__MBAR[0x8954])) -#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&__MBAR[0x8958])) -#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&__MBAR[0x895C])) -#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&__MBAR[0x8960])) -#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&__MBAR[0x8964])) -#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&__MBAR[0x8968])) -#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&__MBAR[0x896E])) -#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&__MBAR[0x8972])) -#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&__MBAR[0x8976])) -#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&__MBAR[0x897A])) -#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&__MBAR[0x897E])) -#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&__MBAR[0x8980])) -#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&__MBAR[0x8984])) -#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&__MBAR[0x8988])) -#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&__MBAR[0x898E])) -#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&__MBAR[0x8992])) -#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&__MBAR[0x8996])) -#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&__MBAR[0x899A])) -#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&__MBAR[0x899E])) +#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8908])) +#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8918])) +#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x891C])) +#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8934])) +#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8938])) +#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x893C])) +#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8940])) +#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8944])) +#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8948])) +#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x894C])) +#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8950])) +#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8954])) +#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8958])) +#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x895C])) +#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8960])) +#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8964])) +#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8968])) +#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x896E])) +#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8972])) +#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8976])) +#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x897A])) +#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x897E])) +#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8980])) +#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8984])) +#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8988])) +#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x898E])) +#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8992])) +#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8996])) +#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x899A])) +#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x899E])) -#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&__MBAR[0x8600 + ((x)*0x100)])) -#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&__MBAR[0x8604 + ((x)*0x100)])) -#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&__MBAR[0x8604 + ((x)*0x100)])) -#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&__MBAR[0x8608 + ((x)*0x100)])) -#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&__MBAR[0x860C + ((x)*0x100)])) -#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&__MBAR[0x8610 + ((x)*0x100)])) -#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&__MBAR[0x8610 + ((x)*0x100)])) -#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&__MBAR[0x8614 + ((x)*0x100)])) -#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&__MBAR[0x8614 + ((x)*0x100)])) -#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&__MBAR[0x8618 + ((x)*0x100)])) -#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&__MBAR[0x861C + ((x)*0x100)])) -#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&__MBAR[0x8634 + ((x)*0x100)])) -#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&__MBAR[0x8638 + ((x)*0x100)])) -#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&__MBAR[0x863C + ((x)*0x100)])) -#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&__MBAR[0x8640 + ((x)*0x100)])) -#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&__MBAR[0x8644 + ((x)*0x100)])) -#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&__MBAR[0x8648 + ((x)*0x100)])) -#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&__MBAR[0x864C + ((x)*0x100)])) -#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&__MBAR[0x8650 + ((x)*0x100)])) -#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&__MBAR[0x8654 + ((x)*0x100)])) -#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&__MBAR[0x8658 + ((x)*0x100)])) -#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&__MBAR[0x865C + ((x)*0x100)])) -#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8660 + ((x)*0x100)])) -#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&__MBAR[0x8664 + ((x)*0x100)])) -#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&__MBAR[0x8668 + ((x)*0x100)])) -#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&__MBAR[0x866E + ((x)*0x100)])) -#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&__MBAR[0x8672 + ((x)*0x100)])) -#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&__MBAR[0x8676 + ((x)*0x100)])) -#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&__MBAR[0x867A + ((x)*0x100)])) -#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&__MBAR[0x867E + ((x)*0x100)])) -#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&__MBAR[0x8680 + ((x)*0x100)])) -#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&__MBAR[0x8684 + ((x)*0x100)])) -#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&__MBAR[0x8688 + ((x)*0x100)])) -#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&__MBAR[0x868E + ((x)*0x100)])) -#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&__MBAR[0x8692 + ((x)*0x100)])) -#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&__MBAR[0x8696 + ((x)*0x100)])) -#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&__MBAR[0x869A + ((x)*0x100)])) -#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&__MBAR[0x869E + ((x)*0x100)])) +#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)])) +#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)])) +#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)])) +#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)])) +#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)])) +#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)])) +#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)])) +#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)])) +#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)])) +#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)])) +#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)])) +#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)])) +#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)])) +#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)])) +#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)])) +#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)])) +#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)])) +#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)])) +#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)])) +#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)])) +#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)])) +#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)])) +#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)])) +#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)])) +#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)])) /* Bit definitions and macros for MCF_PSC_PSCMR */ #define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0) diff --git a/BaS_GNU/include/MCF5475_SDRAMC.h b/BaS_GNU/include/MCF5475_SDRAMC.h index d3d5f46..6cdbd68 100644 --- a/BaS_GNU/include/MCF5475_SDRAMC.h +++ b/BaS_GNU/include/MCF5475_SDRAMC.h @@ -24,16 +24,16 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&__MBAR[0x4])) -#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&__MBAR[0x20])) -#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&__MBAR[0x24])) -#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&__MBAR[0x28])) -#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&__MBAR[0x2C])) -#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&__MBAR[0x100])) -#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&__MBAR[0x104])) -#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&__MBAR[0x108])) -#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&__MBAR[0x10C])) -#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&__MBAR[0x20 + ((x)*0x4)])) +#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&_MBAR[0x4])) +#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&_MBAR[0x20])) +#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&_MBAR[0x24])) +#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&_MBAR[0x28])) +#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&_MBAR[0x2C])) +#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&_MBAR[0x100])) +#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&_MBAR[0x104])) +#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&_MBAR[0x108])) +#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&_MBAR[0x10C])) +#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)])) /* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ diff --git a/BaS_GNU/include/MCF5475_SEC.h b/BaS_GNU/include/MCF5475_SEC.h index 64e9b97..8deff0b 100644 --- a/BaS_GNU/include/MCF5475_SEC.h +++ b/BaS_GNU/include/MCF5475_SEC.h @@ -24,54 +24,54 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&__MBAR[0x21000])) -#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&__MBAR[0x21004])) -#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&__MBAR[0x21008])) -#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&__MBAR[0x2100C])) -#define MCF_SEC_SISRH (*(volatile uint32_t*)(&__MBAR[0x21010])) -#define MCF_SEC_SISRL (*(volatile uint32_t*)(&__MBAR[0x21014])) -#define MCF_SEC_SICRH (*(volatile uint32_t*)(&__MBAR[0x21018])) -#define MCF_SEC_SICRL (*(volatile uint32_t*)(&__MBAR[0x2101C])) -#define MCF_SEC_SIDR (*(volatile uint32_t*)(&__MBAR[0x21020])) -#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&__MBAR[0x21028])) -#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&__MBAR[0x2102C])) -#define MCF_SEC_SMCR (*(volatile uint32_t*)(&__MBAR[0x21030])) -#define MCF_SEC_MEAR (*(volatile uint32_t*)(&__MBAR[0x21038])) -#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&__MBAR[0x2200C])) -#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&__MBAR[0x22010])) -#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&__MBAR[0x22014])) -#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&__MBAR[0x22044])) -#define MCF_SEC_FR0 (*(volatile uint32_t*)(&__MBAR[0x2204C])) -#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&__MBAR[0x2300C])) -#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&__MBAR[0x23010])) -#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&__MBAR[0x23014])) -#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&__MBAR[0x23044])) -#define MCF_SEC_FR1 (*(volatile uint32_t*)(&__MBAR[0x2304C])) -#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&__MBAR[0x28018])) -#define MCF_SEC_AFSR (*(volatile uint32_t*)(&__MBAR[0x28028])) -#define MCF_SEC_AFISR (*(volatile uint32_t*)(&__MBAR[0x28030])) -#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&__MBAR[0x28038])) -#define MCF_SEC_DRCR (*(volatile uint32_t*)(&__MBAR[0x2A018])) -#define MCF_SEC_DSR (*(volatile uint32_t*)(&__MBAR[0x2A028])) -#define MCF_SEC_DISR (*(volatile uint32_t*)(&__MBAR[0x2A030])) -#define MCF_SEC_DIMR (*(volatile uint32_t*)(&__MBAR[0x2A038])) -#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&__MBAR[0x2C018])) -#define MCF_SEC_MDSR (*(volatile uint32_t*)(&__MBAR[0x2C028])) -#define MCF_SEC_MDISR (*(volatile uint32_t*)(&__MBAR[0x2C030])) -#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&__MBAR[0x2C038])) -#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&__MBAR[0x2E018])) -#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&__MBAR[0x2E028])) -#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&__MBAR[0x2E030])) -#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&__MBAR[0x2E038])) -#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&__MBAR[0x32018])) -#define MCF_SEC_AESSR (*(volatile uint32_t*)(&__MBAR[0x32028])) -#define MCF_SEC_AESISR (*(volatile uint32_t*)(&__MBAR[0x32030])) -#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&__MBAR[0x32038])) -#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&__MBAR[0x2200C + ((x)*0x1000)])) -#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&__MBAR[0x22010 + ((x)*0x1000)])) -#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&__MBAR[0x22014 + ((x)*0x1000)])) -#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&__MBAR[0x22044 + ((x)*0x1000)])) -#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&__MBAR[0x2204C + ((x)*0x1000)])) +#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&_MBAR[0x21000])) +#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&_MBAR[0x21004])) +#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&_MBAR[0x21008])) +#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&_MBAR[0x2100C])) +#define MCF_SEC_SISRH (*(volatile uint32_t*)(&_MBAR[0x21010])) +#define MCF_SEC_SISRL (*(volatile uint32_t*)(&_MBAR[0x21014])) +#define MCF_SEC_SICRH (*(volatile uint32_t*)(&_MBAR[0x21018])) +#define MCF_SEC_SICRL (*(volatile uint32_t*)(&_MBAR[0x2101C])) +#define MCF_SEC_SIDR (*(volatile uint32_t*)(&_MBAR[0x21020])) +#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&_MBAR[0x21028])) +#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&_MBAR[0x2102C])) +#define MCF_SEC_SMCR (*(volatile uint32_t*)(&_MBAR[0x21030])) +#define MCF_SEC_MEAR (*(volatile uint32_t*)(&_MBAR[0x21038])) +#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&_MBAR[0x2200C])) +#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&_MBAR[0x22010])) +#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&_MBAR[0x22014])) +#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&_MBAR[0x22044])) +#define MCF_SEC_FR0 (*(volatile uint32_t*)(&_MBAR[0x2204C])) +#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&_MBAR[0x2300C])) +#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&_MBAR[0x23010])) +#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&_MBAR[0x23014])) +#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&_MBAR[0x23044])) +#define MCF_SEC_FR1 (*(volatile uint32_t*)(&_MBAR[0x2304C])) +#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&_MBAR[0x28018])) +#define MCF_SEC_AFSR (*(volatile uint32_t*)(&_MBAR[0x28028])) +#define MCF_SEC_AFISR (*(volatile uint32_t*)(&_MBAR[0x28030])) +#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&_MBAR[0x28038])) +#define MCF_SEC_DRCR (*(volatile uint32_t*)(&_MBAR[0x2A018])) +#define MCF_SEC_DSR (*(volatile uint32_t*)(&_MBAR[0x2A028])) +#define MCF_SEC_DISR (*(volatile uint32_t*)(&_MBAR[0x2A030])) +#define MCF_SEC_DIMR (*(volatile uint32_t*)(&_MBAR[0x2A038])) +#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&_MBAR[0x2C018])) +#define MCF_SEC_MDSR (*(volatile uint32_t*)(&_MBAR[0x2C028])) +#define MCF_SEC_MDISR (*(volatile uint32_t*)(&_MBAR[0x2C030])) +#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&_MBAR[0x2C038])) +#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&_MBAR[0x2E018])) +#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&_MBAR[0x2E028])) +#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&_MBAR[0x2E030])) +#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&_MBAR[0x2E038])) +#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&_MBAR[0x32018])) +#define MCF_SEC_AESSR (*(volatile uint32_t*)(&_MBAR[0x32028])) +#define MCF_SEC_AESISR (*(volatile uint32_t*)(&_MBAR[0x32030])) +#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&_MBAR[0x32038])) +#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)])) +#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)])) +#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)])) +#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)])) +#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)])) /* Bit definitions and macros for MCF_SEC_EUACRH */ diff --git a/BaS_GNU/include/MCF5475_SIU.h b/BaS_GNU/include/MCF5475_SIU.h index f8d900f..4dda666 100644 --- a/BaS_GNU/include/MCF5475_SIU.h +++ b/BaS_GNU/include/MCF5475_SIU.h @@ -24,10 +24,10 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_SIU_SBCR (*(volatile uint32_t*)(&__MBAR[0x10])) -#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&__MBAR[0x38])) -#define MCF_SIU_RSR (*(volatile uint32_t*)(&__MBAR[0x44])) -#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&__MBAR[0x50])) +#define MCF_SIU_SBCR (*(volatile uint32_t*)(&_MBAR[0x10])) +#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&_MBAR[0x38])) +#define MCF_SIU_RSR (*(volatile uint32_t*)(&_MBAR[0x44])) +#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&_MBAR[0x50])) /* Bit definitions and macros for MCF_SIU_SBCR */ diff --git a/BaS_GNU/include/MCF5475_SLT.h b/BaS_GNU/include/MCF5475_SLT.h index 7a3c52e..f66fdc9 100644 --- a/BaS_GNU/include/MCF5475_SLT.h +++ b/BaS_GNU/include/MCF5475_SLT.h @@ -24,20 +24,20 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&__MBAR[0x900])) -#define MCF_SLT0_SCR (*(volatile uint32_t*)(&__MBAR[0x904])) -#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&__MBAR[0x908])) -#define MCF_SLT0_SSR (*(volatile uint32_t*)(&__MBAR[0x90C])) +#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&_MBAR[0x900])) +#define MCF_SLT0_SCR (*(volatile uint32_t*)(&_MBAR[0x904])) +#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&_MBAR[0x908])) +#define MCF_SLT0_SSR (*(volatile uint32_t*)(&_MBAR[0x90C])) -#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&__MBAR[0x910])) -#define MCF_SLT1_SCR (*(volatile uint32_t*)(&__MBAR[0x914])) -#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&__MBAR[0x918])) -#define MCF_SLT1_SSR (*(volatile uint32_t*)(&__MBAR[0x91C])) +#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&_MBAR[0x910])) +#define MCF_SLT1_SCR (*(volatile uint32_t*)(&_MBAR[0x914])) +#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&_MBAR[0x918])) +#define MCF_SLT1_SSR (*(volatile uint32_t*)(&_MBAR[0x91C])) -#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&__MBAR[0x900 + ((x)*0x10)])) -#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&__MBAR[0x904 + ((x)*0x10)])) -#define MCF_SLT_SCNT(x) (*(volatile uint32_t*)(&__MBAR[0x908 + ((x)*0x10)])) -#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&__MBAR[0x90C + ((x)*0x10)])) +#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)])) +#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)])) +#define MCF_SLT_SCNT(x) (*(volatile uint32_t*)(&_MBAR[0x908 + ((x)*0x10)])) +#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)])) /* Bit definitions and macros for MCF_SLT_STCNT */ diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index d60feb0..3836263 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -8,7 +8,7 @@ #include "MCF5475_SLT.h" #include "startcf.h" -extern unsigned long __Bas_base[]; +extern unsigned long _Bas_base[]; /* imported routines */ extern int mmu_init(); @@ -203,7 +203,7 @@ void BaS(void) /* TT-RAM */ - * (uint32_t *) 0x5a4 = (uint32_t *) __Bas_base; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a4 = (uint32_t *) _Bas_base; /* ramtop TOS system variable */ * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ /* init ACIA */ diff --git a/BaS_GNU/sources/startcf.c b/BaS_GNU/sources/startcf.c index 1fef820..f271686 100644 --- a/BaS_GNU/sources/startcf.c +++ b/BaS_GNU/sources/startcf.c @@ -11,26 +11,26 @@ void _startup(void) "| disable interrupts\n\t" "move.w #0x2700,sr\n\t" "|// Initialize MBAR\n\t" - "MOVE.L #___MBAR,D0\n\t" + "MOVE.L #__MBAR,D0\n\t" "MOVEC D0,MBAR\n\t" "MOVE.L D0,_rt_mbar\n\t" "| mmu off\n\t" - "move.l #___MMUBAR+1,d0\n\t" + "move.l #__MMUBAR+1,d0\n\t" "movec d0,MMUBAR | mmubar setzen\n\t" "clr.l d0\n\t" "move.l d0,MCF_MMU_MMUCR\n\t | mmu off" "|/* Initialize RAMBARs: locate SRAM and validate it */\n\t" - "move.l #___RAMBAR0 + 0x7,d0\n\t | supervisor only" + "move.l #__RAMBAR0 + 0x7,d0\n\t | supervisor only" "movec d0,RAMBAR0\n\t" - "move.l #___RAMBAR1 + 0x1,d0\n\t""" + "move.l #__RAMBAR1 + 0x1,d0\n\t""" "movec d0,RAMBAR1\n\t" "| STACKPOINTER AUF ENDE SRAM1\n\t" - "lea ___SUP_SP,a7\n\t" + "lea __SUP_SP,a7\n\t" "| instruction cache on\n\t" "move.l #0x000C8100,d0\n\t" "movec d0,cacr\n\t" "nop\n\t" "| initialize any hardware specific issues\n\t" "bra _initialize_hardware\n\t" -); + ); } diff --git a/BaS_GNU/sources/startcf.h b/BaS_GNU/sources/startcf.h index 0fe3808..ad9e185 100644 --- a/BaS_GNU/sources/startcf.h +++ b/BaS_GNU/sources/startcf.h @@ -40,8 +40,8 @@ #define halten_movep #define halten_ewf -#define DIP_SWITCH (*(volatile uint8_t *)(&__MBAR[0xA2C])) -#define DIP_SWITCHa ___MBAR + 0xA2C +#define DIP_SWITCH (*(volatile uint8_t *)(&_MBAR[0xA2C])) +#define DIP_SWITCHa __MBAR + 0xA2C #define sca_page_ID 6 diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 2130a49..1537248 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -231,7 +231,7 @@ void init_fpga(void) while (!MCF_GPIO_PPDSDR_FEC1L & (1 << 0)) { - warte10us(); + wait10us(); } /* From a608d1a748e163f13d4d5daf5ac6ac5f0bb3e9bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 06:05:51 +0000 Subject: [PATCH 058/276] fixed lots of external references --- BaS_GNU/sources/sysinit.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 1537248..afa1d53 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -231,7 +231,7 @@ void init_fpga(void) while (!MCF_GPIO_PPDSDR_FEC1L & (1 << 0)) { - wait10us(); + wait_10us(); } /* @@ -295,7 +295,7 @@ void init_fpga(void) void wait_pll(void) { do { - wait1ms(); + wait_1ms(); } while (! * (volatile uint16_t *) 0xf0000800); } @@ -451,8 +451,8 @@ void init_PCI(void) { + MCF_PCIARB_PACR_EXTMINTEN(0x1F); // Setup burst parameters - MCF_PCI_PCICR1 = MCF_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32); - MCF_PCI_PCICR2 = MCF_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16); + MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32); + MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16); // Turn on error signaling MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_TAE * MCF_PCI_PCIICR_REE + 32; @@ -764,8 +764,7 @@ ac97_end: MCF_PSC0_PSCTB_8BIT = ' OK!'; MCF_PSC0_PSCTB_8BIT = 0x0a0d; } -void __initialize_hardware(void) { -_init_hardware: +void initialize_hardware(void) { asm( "move.l #0x000C8120,D0\n\t" "move.l D0,_rt_cacr\n\t" @@ -796,7 +795,7 @@ asm( asm volatile( "lea copy_start,A0\n\t" - "lea BaS,A1\n\t" + "lea _BaS,A1\n\t" "sub.l A0,A1\n\t" "move.l #_Bas_base,A2\n\t" "move.l A2,A3\n\t" From e0d904f5bd90f028d81774fc9687485a19081731 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 06:09:09 +0000 Subject: [PATCH 059/276] fixed external reference to _BaS_base --- BaS_GNU/sources/BaS.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 3836263..6208025 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -8,7 +8,7 @@ #include "MCF5475_SLT.h" #include "startcf.h" -extern unsigned long _Bas_base[]; +extern unsigned long Bas_base[]; /* imported routines */ extern int mmu_init(); @@ -203,7 +203,7 @@ void BaS(void) /* TT-RAM */ - * (uint32_t *) 0x5a4 = (uint32_t *) _Bas_base; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a4 = (uint32_t *) Bas_base; /* ramtop TOS system variable */ * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ /* init ACIA */ From 1bfe6b97bd231afc7c382223179f0439bfcdf7e0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 06:16:18 +0000 Subject: [PATCH 060/276] provided empty sd_card_init() function to make the linker happy --- BaS_GNU/sources/sd_card.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/BaS_GNU/sources/sd_card.c b/BaS_GNU/sources/sd_card.c index b3c9453..7295ec2 100644 --- a/BaS_GNU/sources/sd_card.c +++ b/BaS_GNU/sources/sd_card.c @@ -2,8 +2,8 @@ * sd card */ -#include #include +#include #define dspi_dtar0 0x0c #define dspi_dsr 0x2c @@ -83,13 +83,13 @@ void sd_card_idle(void) #endif } -#ifdef _NOT_USED_ + int sd_card_init(void) { long az_sectors; - +#ifdef _NOT_USED_ asm { lea MCF_PSC0_PSCTB_8BIT,a1 @@ -424,8 +424,11 @@ sd_c_not: return -2; sd_c_error: return -1; + +#endif /* _NOT_USED_ */ } +#ifdef _NOT_USED_ void sd_rcv_sector(void) // 1 sector daten holen ---------------------------- { if (sd_get_status() == 0xfe) From 54aa93185a7cf747aeb3d8f0ad3b757ff60aacf9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 06:28:06 +0000 Subject: [PATCH 061/276] fixed a few compiler warnings --- BaS_GNU/sources/BaS.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 6208025..77f12ff 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -8,7 +8,7 @@ #include "MCF5475_SLT.h" #include "startcf.h" -extern unsigned long Bas_base[]; +extern uint32_t Bas_base[]; /* imported routines */ extern int mmu_init(); @@ -78,7 +78,7 @@ void BaS(void) if (DIP_SWITCH & (1 << 6)) { - copy_firetos(); + goto copy_firetos; } MCF_PSC3_PSCTB_8BIT = 'ACPF'; @@ -104,6 +104,7 @@ void BaS(void) } else { +copy_firetos: /* copy FireTOS */ src = (uint8_t *) 0xe0400000L; while (src < (uint8_t *) 0xe0500000L) @@ -185,7 +186,7 @@ void BaS(void) /* * memory setup */ - for (adr = 0x400L; adr < 0x800L; adr += 32) { + for (adr = (uint32_t *) 0x400L; adr < (uint32_t *) 0x800L; adr += 32) { *adr = 0x0L; *adr = 0x0L; *adr = 0x0L; @@ -203,7 +204,7 @@ void BaS(void) /* TT-RAM */ - * (uint32_t *) 0x5a4 = (uint32_t *) Bas_base; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a4 = (uint32_t) Bas_base; /* ramtop TOS system variable */ * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ /* init ACIA */ From ed90e0b985152b00991d9274c4eb6a95b8a37077 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 06:30:46 +0000 Subject: [PATCH 062/276] fixed undefined external references --- BaS_GNU/sources/mmu.S | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/BaS_GNU/sources/mmu.S b/BaS_GNU/sources/mmu.S index 9c668f7..a95b47f 100644 --- a/BaS_GNU/sources/mmu.S +++ b/BaS_GNU/sources/mmu.S @@ -18,12 +18,12 @@ .extern _video_sbt /* Register read/write macros */ -#define MCF_MMU_MMUCR ___MMUBAR -#define MCF_MMU_MMUOR ___MMUBAR+0x04 -#define MCF_MMU_MMUSR ___MMUBAR+0x08 -#define MCF_MMU_MMUAR ___MMUBAR+0x10 -#define MCF_MMU_MMUTR ___MMUBAR+0x14 -#define MCF_MMU_MMUDR ___MMUBAR+0x18 +#define MCF_MMU_MMUCR __MMUBAR +#define MCF_MMU_MMUOR __MMUBAR+0x04 +#define MCF_MMU_MMUSR __MMUBAR+0x08 +#define MCF_MMU_MMUAR __MMUBAR+0x10 +#define MCF_MMU_MMUTR __MMUBAR+0x14 +#define MCF_MMU_MMUDR __MMUBAR+0x18 /* Bit definitions and macros for MCF_MMU_MMUCR */ @@ -102,7 +102,7 @@ _mmu_init: movec d0,ACR3 move.l d0,_rt_acr3 // sichern - move.l #___MMUBAR+1,d0 + move.l #__MMUBAR+1,d0 movec d0,MMUBAR //mmubar setzen move.l d0,_rt_mmubar // sichern @@ -134,7 +134,7 @@ _mmu_init: move.l #0x2000,d0 move.l d0,_video_tlb // setze page als video page - clr.l _video_sbt // zeit löschen + clr.l _video_sbt // zeit l�schen //------------------------------------------------------------------------------------- // 00e0'0000 locked move.l #0x00e00000|std_mmutr,d0 From 4d2caeca377fda115a3c6f63c69c8beb79f680f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 06:34:11 +0000 Subject: [PATCH 063/276] fixed linker control file --- BaS_GNU/flash.lk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/flash.lk b/BaS_GNU/flash.lk index 29dfa72..d474d16 100644 --- a/BaS_GNU/flash.lk +++ b/BaS_GNU/flash.lk @@ -3,7 +3,7 @@ MEMORY { } SECTIONS { - ___Bas_base = ABSOLUTE(0x1FE00000); + _Bas_base = ABSOLUTE(0x1FE00000); /* Board Memory map definitions from linker command files: * __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE From 1555f31976a12a2eb5692702bf81bf64117a5078 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 06:45:34 +0000 Subject: [PATCH 064/276] fixed CFLAGS according to Vincent's suggestions --- BaS_GNU/Makefile | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 210d499..01e2deb 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -9,17 +9,27 @@ # the m68k-elf version which also allows to use gdb together with bdm tools for debugging # +# This Makefile is meant for cross compiling the BaS with Vincent Riviere's cross compilers. +# If you want to compile native on an Atari (you will need at least GCC 4.6.3), set +# TCPREFIX to be empty. TCPREFIX=m68k-atari-mint- CC=$(TCPREFIX)gcc LD=$(TCPREFIX)ld INCLUDE=-Iinclude -CFLAGS=-mcfv4e -Wno-multichar -Os -Wa,-mcpu=547x -fomit-frame-pointer -#CFLAGS=-mcfv4e -Wno-multichar -S -O3 -fomit-frame-pointer +CFLAGS=-mcpu=5475 -Wno-multichar -Os -fomit-frame-pointer + SRCDIR=sources OBJDIR=objs +MAPFILE=bas.map + +# Linker control files. flash.lk is meant for BaS in flash, ram.lk (not written yet) for +# debugging in RAM. +LDCFILE=flash.lk +# LDCFILE=ram.lk + EXEC=bas.hex CSRCS= \ @@ -43,14 +53,11 @@ OBJS=$(COBJS) $(AOBJS) all: $(EXEC) -SADDR=0xe0000000 - $(EXEC): $(OBJS) - $(LD) --oformat srec -Map $@.map --cref -T flash.lk -s -o $@ $(OBJS) - echo "generating executable" + $(LD) --oformat srec -Map $(MAPFILE) --cref -T flash.lk -s -o $@ $(OBJS) clean: - rm $(EXEC) $(OBJS) + @ rm -f $(EXEC) $(OBJS) $(MAPFILE) $(OBJDIR)/%.o:$(SRCDIR)/%.c $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ From be10263f800fb9f17105febcf62ab29258c0822c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 06:47:13 +0000 Subject: [PATCH 065/276] cleanup of startup() --- BaS_GNU/sources/startcf.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/BaS_GNU/sources/startcf.c b/BaS_GNU/sources/startcf.c index f271686..7285e5e 100644 --- a/BaS_GNU/sources/startcf.c +++ b/BaS_GNU/sources/startcf.c @@ -1,6 +1,6 @@ #include -void _startup(void) +void startup(void) { asm("\n\t" ".extern _initialize_hardware\n\t" @@ -10,15 +10,20 @@ void _startup(void) "warmstart:\n\t" "| disable interrupts\n\t" "move.w #0x2700,sr\n\t" - "|// Initialize MBAR\n\t" - "MOVE.L #__MBAR,D0\n\t" - "MOVEC D0,MBAR\n\t" - "MOVE.L D0,_rt_mbar\n\t" - "| mmu off\n\t" - "move.l #__MMUBAR+1,d0\n\t" - "movec d0,MMUBAR | mmubar setzen\n\t" - "clr.l d0\n\t" - "move.l d0,MCF_MMU_MMUCR\n\t | mmu off" + ); + + /* Initialize MBAR */ + asm("MOVE.L #__MBAR,D0\n\t"); + asm("MOVEC D0,MBAR\n\t"); + asm("MOVE.L D0,_rt_mbar\n\t"); + + /* mmu off */ + asm("move.l #__MMUBAR+1,d0\n\t"); + asm("movec d0,MMUBAR"); /* set mmubar */ + + * (volatile uint32_t *) MCF_MMU_MMUCR = 0L; /* MMU off */ + + asm( "|/* Initialize RAMBARs: locate SRAM and validate it */\n\t" "move.l #__RAMBAR0 + 0x7,d0\n\t | supervisor only" "movec d0,RAMBAR0\n\t" From fca9811ebb8a6ee19cdaec31f4d4b97f20c48323 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 06:49:11 +0000 Subject: [PATCH 066/276] fixed reference to __BOOT_FLASH --- BaS_GNU/sources/exceptions.S | 58 ++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S index d49ca70..a8ab724 100644 --- a/BaS_GNU/sources/exceptions.S +++ b/BaS_GNU/sources/exceptions.S @@ -140,7 +140,7 @@ btst #7,d0 bne irq_protect // ja-> // ------------------------------------------- - movem.l (a7),d0/a5 // register zurück + movem.l (a7),d0/a5 // register zur�ck addq.l #8,a7 move.l \vector,-(a7) move #0x2200,sr @@ -178,7 +178,7 @@ irq_end: adda.l _rt_vbr,a5 move.l (a5),12(a7) // vectoradresse eintragen move.b #\int_mask,10(a7) // intmaske setzen - movem.l (a7),d0/a5 // register zurück + movem.l (a7),d0/a5 // register zur�ck addq.l #8,a7 rte // und weg .endm @@ -216,7 +216,7 @@ init_vec: move.l #256,d0 lea std_exc_vec(pc),a1 // standard vector init_vec_loop: - move.l a1,(a2)+ // mal standard vector für alle setzen + move.l a1,(a2)+ // mal standard vector f�r alle setzen subq.l #1,d0 bne init_vec_loop @@ -305,12 +305,12 @@ std_exc_vec: add.l _rt_vbr,d0 // + basis move.l d0,a5 move.l (a5),d0 - move.l 4(a7),a5 // a5 zurück + move.l 4(a7),a5 // a5 zur�ck move.l d0,4(a7) move.w 10(a7),d0 bset #13,d0 // super move.w d0,sr // orginal sr wert in super setzen - move.l (a7)+,d0 // d0 zurück + move.l (a7)+,d0 // d0 zur�ck rts stv_protect: move.l usp,a5 // usp holen @@ -335,7 +335,7 @@ stv_protect: add.l _rt_vbr,d0 // + basis move.l d0,a5 move.l (a5),12(a7) // hier geht's weiter - movem.l (a7),d0/a5 // register zurück + movem.l (a7),d0/a5 // register zur�ck addq.l #8,a7 rte // und weg sev_sup: @@ -357,16 +357,16 @@ sev_sup: add.l _rt_vbr,d0 // + basis move.l d0,a5 move.l (a5),12(a7) // hier geht's weiter - movem.l (a7),d0/a5 // register zurück + movem.l (a7),d0/a5 // register zur�ck addq.l #8,a7 rte // und weg //******************************************* reset_vector: move.w #0x2700,sr // disable interrupt move.l #0x31415926,d0 - cmp.l 0x426,d0 // reset vector gültg? + cmp.l 0x426,d0 // reset vector g�ltg? beq std_exc_vec // ja-> - jmp __BOOT_FLASH // sonst kaltstart + jmp ___BOOT_FLASH // sonst kaltstart acess: move.w #0x2700,sr // disable interrupt move.l d0,-(sp) // ++ vr @@ -387,7 +387,7 @@ access_mmu: bne bus_error move.l MCF_MMU_MMUAR,d0 cmp.l #_Bas_base,d0 // max User RAM Bereich - bge bus_error // grösser -> bus error + bge bus_error // gr�sser -> bus error bra _mmutr_miss bus_error: move.l (sp)+,d0 @@ -464,7 +464,7 @@ irq6: // mfp // test auf timeout screen adr change ------------------------------------------------------- move.l _video_sbt,d0 beq irq6_non_sca // wenn 0 nichts zu tun - sub.l #0x70000000,d0 // 14 sec abzählen + sub.l #0x70000000,d0 // 14 sec abz�hlen lea MCF_SLT0_SCNT,a5 cmp.l (a5),d0 // aktuelle zeit weg ble irq6_non_sca // noch nicht abgelaufen @@ -484,13 +484,13 @@ irq6: // mfp swap d4 move.l d4,MCF_MMU_MMUAR mvz.w #0x10e,d4 - move.l d4,MCF_MMU_MMUOR // einträge holen aus mmu + move.l d4,MCF_MMU_MMUOR // eintr�ge holen aus mmu nop move.l MCF_MMU_MMUTR,d4 // ID holen lsr.l #2,d4 // bit 9 bis 2 cmp.w #sca_page_ID,d4 // ist screen change ID? bne irq6_sca_pn // nein -> page keine screen area next -// eintrag ändern +// eintrag �ndern add.l #std_mmutr,d0 move.l d3,d1 // page 0? beq irq6_sca_pn0 // ja -> @@ -524,9 +524,9 @@ irq6_sca_pn: move.l #0x2000,d0 move.l d0,_video_tlb // anfangszustand wieder herstellen - clr.l _video_sbt // zeit löschen + clr.l _video_sbt // zeit l�schen - movem.l (a7),d0-d4/a0-a1 // register zurück + movem.l (a7),d0-d4/a0-a1 // register zur�ck lea 28(a7),a7 irq6_non_sca: // test auf acsi dma ----------------------------------------------------------------- @@ -563,9 +563,9 @@ irq6_2: move.l 0xF0020000,a5 // vector holen add.l _rt_vbr,a5 // basis move.l (a5),d0 // vector holen - move.l 4(a7),a5 // a5 zurück + move.l 4(a7),a5 // a5 zur�ck move.l d0,4(a7) // vector eintragen - move.l (a7)+,d0 // d0 zurück + move.l (a7)+,d0 // d0 zur�ck move #0x2600,sr rts irq6_3: @@ -587,7 +587,7 @@ irq6_3: move.l 0xF0020000,a5 // vector holen: intack routine add.l _rt_vbr,a5 // virtuelle VBR des Systems move.l (a5),12(a7) // hier gehts weiter - movem.l (a7),d0/a5 // register zurück + movem.l (a7),d0/a5 // register zur�ck addq.l #8,a7 move.b #6,2(a7) // intmaske setzen rte // und weg @@ -606,7 +606,7 @@ sev_sup6: move.l 0xF0020000,a5 // vector holen: intack routine add.l _rt_vbr,a5 // virtuelle VBR des Systems move.l (a5),12(a7) // hier gehts weiter - movem.l (a7),d0/a5 // register zurück + movem.l (a7),d0/a5 // register zur�ck rts blinker:.long 0 /**************************************************/ @@ -657,8 +657,8 @@ acsi_dma_wl: sub.l #16,d0 // byt counter -16 bpl acsi_dma_wl acsi_dma_fertig: - move.l a1,-12(a5) // adresse zurück - move.l d0,-8(a5) // byt counter zurück + move.l a1,-12(a5) // adresse zur�ck + move.l d0,-8(a5) // byt counter zur�ck acsi_dma_end: tst.b -4(a5) // dma req? bmi acsi_dma_start // ja-> @@ -731,7 +731,7 @@ loop_sr2: cmp.b d1,d2 bne loop_sr2 psc3_fertig: - movem.l (a7),d0-d2/a0/a3 // register zurück + movem.l (a7),d0-d2/a0/a3 // register zur�ck lea 20(a7),a7 RTE /**************************************************/ @@ -742,7 +742,7 @@ timer0: // halt lea -28(a7),a7 movem.l d0-d4/a0-a1,(a7) - mvz.b 0xffff8201,d0 // löschen und high byt + mvz.b 0xffff8201,d0 // l�schen und high byt cmp.w #2,d0 blt video_chg_end cmp.w #0xd0,d0 // normale addresse @@ -762,7 +762,7 @@ video_chg_1page: move.l d0,d2 lsr.l d4,d2 // neue page move.l _video_tlb,d4 - bset.l d2,d4 // setzen als geändert + bset.l d2,d4 // setzen als ge�ndert bne video_chg_2page // schon gesetzt gewesen? ja->weg move.l d4,_video_tlb bsr cpusha // cache leeren @@ -784,7 +784,7 @@ video_copy_data_loop: // eintrag suchen move.l d0,MCF_MMU_MMUAR // addresse move.l #0x106,d4 - move.l d4,MCF_MMU_MMUOR // suchen -> schlägt neuen vor wenn keiner + move.l d4,MCF_MMU_MMUOR // suchen -> schl�gt neuen vor wenn keiner nop move.l MCF_MMU_MMUOR,d4 clr.w d4 @@ -806,17 +806,17 @@ video_chg_2page: mvz.w 0xffff82a8,d1 // zeilenstart sub.l d1,d2 // differenz = anzahl zeilen mulu d2,d4 // maximal 480 zeilen - add.l d4,d0 // video grösse + add.l d4,d0 // video gr�sse cmp.l #0xe00000,d0 // maximale addresse - bge video_chg_end // wenn gleich oder grösser -> fertig + bge video_chg_end // wenn gleich oder gr�sser -> fertig moveq #20,d4 move.l d0,d2 lsr.l d4,d2 // neue page move.l _video_tlb,d4 - bset.l d2,d4 // setzen als geändert + bset.l d2,d4 // setzen als ge�ndert beq video_copy_data // nein nochmal video_chg_end: -// int pending löschen +// int pending l�schen lea MCF_GPT0_GMS,a0 bclr.b #0,3(a0) nop From 0b3a146609b2233557c9e6df903910c343d0a60f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 07:01:07 +0000 Subject: [PATCH 067/276] fixed "clean" target to really clean added a "depend" target --- BaS_GNU/Makefile | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 01e2deb..089a5d5 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -57,10 +57,16 @@ $(EXEC): $(OBJS) $(LD) --oformat srec -Map $(MAPFILE) --cref -T flash.lk -s -o $@ $(OBJS) clean: - @ rm -f $(EXEC) $(OBJS) $(MAPFILE) + @ rm -f $(EXEC) $(OBJS) $(MAPFILE) depend $(OBJDIR)/%.o:$(SRCDIR)/%.c $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ $(OBJDIR)/%.o:$(SRCDIR)/%.S $(CC) -c $(CFLAGS) -Wa,--bitwise-or $(INCLUDE) $< -o $@ + +depend: $(ASRCS) $(CSRCS) + $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) > depend + +include depend + \ No newline at end of file From a79a3c494c4bb31a5c4ef8bda03b9dc7cbb8bc14 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 07:04:04 +0000 Subject: [PATCH 068/276] (Nearly) clean build. Still one warning (possible integer overflow) left - need to look into it --- BaS_GNU/.cproject | 63 +++++++++++++++++++++++++++++++---------------- 1 file changed, 42 insertions(+), 21 deletions(-) diff --git a/BaS_GNU/.cproject b/BaS_GNU/.cproject index 91dd41f..32cb7e0 100644 --- a/BaS_GNU/.cproject +++ b/BaS_GNU/.cproject @@ -13,29 +13,32 @@ + + + - + @@ -58,6 +61,9 @@ + + + @@ -100,18 +106,6 @@ - - - - make - - all - true - true - true - - - @@ -139,4 +133,31 @@ + + + + make + all + true + true + true + + + make + + clean + true + true + true + + + make + + depend + true + true + true + + + From 92388fda3821e4f2b10be809ea30c1c6fc15bede Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 08:12:45 +0000 Subject: [PATCH 069/276] eclipse --- BaS_GNU/.cproject | 43 ++++--------------------------------------- 1 file changed, 4 insertions(+), 39 deletions(-) diff --git a/BaS_GNU/.cproject b/BaS_GNU/.cproject index 32cb7e0..c52737e 100644 --- a/BaS_GNU/.cproject +++ b/BaS_GNU/.cproject @@ -13,34 +13,17 @@ - - - + @@ -69,29 +52,11 @@ - + From 6d99e90df754eddbe8217c26dc2d9d9e4e60e295 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 08:35:41 +0000 Subject: [PATCH 070/276] still had the wrong CPU in the Makefile. Not its "-mcpu=5474" as suggested. --- BaS_GNU/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 089a5d5..cf9bdb7 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -18,7 +18,7 @@ CC=$(TCPREFIX)gcc LD=$(TCPREFIX)ld INCLUDE=-Iinclude -CFLAGS=-mcpu=5475 -Wno-multichar -Os -fomit-frame-pointer +CFLAGS=-mcpu=5474 -Wno-multichar -Os -fomit-frame-pointer SRCDIR=sources OBJDIR=objs From 67477861dc9df9133caf81cc6db759774087f7a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 14 Oct 2012 09:24:25 +0000 Subject: [PATCH 071/276] Made compiler more picky by adding -Wall to CFLAGS. This showed up more warnings where some are already fixed. --- BaS_GNU/.cproject | 8 +++----- BaS_GNU/.project | 14 +++---------- BaS_GNU/Makefile | 2 +- BaS_GNU/flash.lk | 16 +++------------ BaS_GNU/sources/BaS.c | 7 ++++--- BaS_GNU/sources/exceptions.S | 38 +++++++++++++++++++----------------- BaS_GNU/sources/mmu.S | 12 ++++++------ BaS_GNU/sources/sd_card.c | 7 ++++--- BaS_GNU/sources/supervisor.S | 26 ++++++++++++------------ BaS_GNU/sources/sysinit.c | 10 ++++++---- 10 files changed, 63 insertions(+), 77 deletions(-) diff --git a/BaS_GNU/.cproject b/BaS_GNU/.cproject index c52737e..95711f6 100644 --- a/BaS_GNU/.cproject +++ b/BaS_GNU/.cproject @@ -39,14 +39,9 @@ - - - - - @@ -57,6 +52,9 @@ From 428d38f7da30da70a5cbeb48cc44ff9c41e32201 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 16 Oct 2012 17:33:55 +0000 Subject: [PATCH 112/276] --- BaS_GNU/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 1d02320..94ceb42 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -49,6 +49,7 @@ ASRCS= \ STRT_SRC = startcf.S STRT_OBJ = $(OBJDIR)/startcf.o + COBJS=$(patsubst $(SRCDIR)/%.o,$(OBJDIR)/%.o,$(patsubst %.c,%.o,$(CSRCS))) AOBJS=$(patsubst $(SRCDIR)/%.o,$(OBJDIR)/%.o,$(patsubst %.S,%.o,$(ASRCS))) From 9c146c2bde016c796bf718da2d573466d5991f51 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 16 Oct 2012 17:51:37 +0000 Subject: [PATCH 113/276] added function to clear cache --- BaS_GNU/sources/cache.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/sources/cache.c b/BaS_GNU/sources/cache.c index b74bae9..4953be7 100644 --- a/BaS_GNU/sources/cache.c +++ b/BaS_GNU/sources/cache.c @@ -6,7 +6,7 @@ void flushDataCacheRegion(void *adr, uint32_t length) { - asm volatile + __asm__ ( " move.l %0,d0 | start address\n\t" " move.l d0,a1\n\t" @@ -34,7 +34,7 @@ void flushDataCacheRegion(void *adr, uint32_t length) void flushInstructionCacheRegion(void *adr, uint32_t length) { - asm volatile + __asm__ ( " move.l %0,d0 | start address\n\t" " move.l d0,a1\n\t" @@ -59,3 +59,35 @@ void flushInstructionCacheRegion(void *adr, uint32_t length) /* clobber */: "d0", "d1", "a0", "a1" ); } + +void clear_caches(void) +{ + __asm__ ( + "cpusha:\n\t" + " move sr,d2\n\t" + " move.l d2,-(sp)\n\t" + " move #0x2700,sr | no interrupts\n\t" + " clr.l d0\n\t" + " clr.l d1\n\t" + " move.l d0,a0\n\t" + "cfa_setloop:\n\t" + " cpushl bc,(a0) | flush\n\t" + " lea 0x10(a0),a0 | index+1\n\t" + " addq.l #1,d1 | index+1\n\t" + " cmpi.w #512,d1 | alle sets?\n\t" + " bne cfa_setloop | nein->\n\t" + " clr.l d1\n\t" + " addq.l #1,d0\n\t" + " move.l d0,a0\n\t" + " cmpi.w #4,d0 | all ways?\n\t" + " bne cfa_setloop | nein->\n\t" + " nop\n\t" + " move.l _rt_cacr,d0 | holen\n\t" + " movec d0,cacr | setzen\n\t" + " move.l (sp)+,d2\n\t" + " move.w d2,sr | alte interrupt maske\n\t" + /* input */ : + /* output */ : + /* clobber */ : "d0", "d1", "d2", "a0" + ); +} From 27cb784c072a88dd53a8b128c9911d3f475aa5ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 16 Oct 2012 17:55:57 +0000 Subject: [PATCH 114/276] added function to clear all cache lines (from illegal_instruction.S) --- BaS_GNU/sources/cache.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/BaS_GNU/sources/cache.c b/BaS_GNU/sources/cache.c index 4953be7..5ebd2ea 100644 --- a/BaS_GNU/sources/cache.c +++ b/BaS_GNU/sources/cache.c @@ -74,18 +74,18 @@ void clear_caches(void) " cpushl bc,(a0) | flush\n\t" " lea 0x10(a0),a0 | index+1\n\t" " addq.l #1,d1 | index+1\n\t" - " cmpi.w #512,d1 | alle sets?\n\t" - " bne cfa_setloop | nein->\n\t" + " cmpi.w #512,d1 | all sets?\n\t" + " bne cfa_setloop | no->\n\t" " clr.l d1\n\t" " addq.l #1,d0\n\t" " move.l d0,a0\n\t" " cmpi.w #4,d0 | all ways?\n\t" - " bne cfa_setloop | nein->\n\t" + " bne cfa_setloop | no->\n\t" " nop\n\t" - " move.l _rt_cacr,d0 | holen\n\t" - " movec d0,cacr | setzen\n\t" + " move.l _rt_cacr,d0 | get cacr shadow register\n\t" + " movec d0,cacr | set old value\n\t" " move.l (sp)+,d2\n\t" - " move.w d2,sr | alte interrupt maske\n\t" + " move.w d2,sr | restore previous interrupt mask\n\t" /* input */ : /* output */ : /* clobber */ : "d0", "d1", "d2", "a0" From 504dcc2c85a527e5a9a03197cd3e829c29e668f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Tue, 16 Oct 2012 19:18:38 +0000 Subject: [PATCH 115/276] Fixed FPGA initialization bit ordering. --- BaS_GNU/sources/init_fpga.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/sources/init_fpga.c b/BaS_GNU/sources/init_fpga.c index c863776..066e1e5 100644 --- a/BaS_GNU/sources/init_fpga.c +++ b/BaS_GNU/sources/init_fpga.c @@ -61,10 +61,10 @@ void init_fpga(void) do { uint8_t value = *fpga_data++; - for (i = 0; i < 8; i++) + for (i = 0; i < 8; i++, value >>= 1) { - if ((value << i) & 0b10000000) + if (value & 1) { /* bit set -> toggle DATA0 to high */ MCF_GPIO_PODR_FEC1L |= FPGA_DATA0; From 858154a5f0ceecf77f1c38f9a72a2492a874d086 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 16 Oct 2012 19:51:22 +0000 Subject: [PATCH 116/276] --- BaS_GNU/sources/sysinit.c | 41 ++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 54880dd..a7d6d7e 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -240,8 +240,8 @@ void init_pll(void) wait_pll(); * (volatile uint8_t *) 0xf0000800 = 0; /* set */ - MCF_PSC0_PSCTB_8BIT = 'SET!'; - MCF_PSC0_PSCTB_8BIT = 0x0a0d; + uart_out_word('SET!'); + uart_out_word(0x0a0d); } @@ -355,7 +355,7 @@ flo6: * INIT PCI */ void init_PCI(void) { - MCF_PSC0_PSCTB_8BIT = 'PCI '; + uart_out_word('PCI '); MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI + MCF_PCIARB_PACR_EXTMPRI(0x1F) @@ -386,8 +386,8 @@ void init_PCI(void) { /* reset PCI devices */ MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR; - MCF_PSC0_PSCTB_8BIT = 'OK! '; - MCF_PSC0_PSCTB_8BIT = 0x0d0a; + uart_out_word('OK! '); + uart_out_word(0x0d0a); } @@ -397,7 +397,7 @@ void init_PCI(void) { void test_upd720101(void) { - MCF_PSC0_PSCTB_8BIT = 'NEC '; + uart_out_word('NEC '); /* select UPD720101 AD17 */ MCF_PCI_PCICAR = MCF_PCI_PCICAR_E + @@ -422,25 +422,25 @@ void test_upd720101(void) MCF_PCI_PCICAR_FUNCNUM(0) + MCF_PCI_PCICAR_DWORD(57); } - MCF_PSC0_PSCTB_8BIT = 'OK! '; - MCF_PSC0_PSCTB_8BIT = 0x0d0a; + uart_out_word('OK! '); + uart_out_word(0x0d0a); } /* * TFP410 (DVI) on */ -void vdi_on(void) { +void dvi_on(void) { uint8_t RBYT; uint8_t DBYT; /* FIXME: produces a warning about being unused when it is in fact (for a dummy read) */ - int versuche; + int tries; - MCF_PSC0_PSCTB_8BIT = 'DVI '; + uart_out_word('DVI '); MCF_I2C_I2FDR = 0x3c; // 100kHz standard - versuche = 0; + tries = 0; loop_i2c: - if (versuche++ > 10) + if (tries++ > 10) goto next; MCF_I2C_I2ICR = 0x0; @@ -569,10 +569,10 @@ loop_i2c: goto loop_i2c; goto dvi_ok; next: - MCF_PSC0_PSCTB_8BIT = 'NOT '; + uart_out_word('NOT '); dvi_ok: - MCF_PSC0_PSCTB_8BIT = 'OK! '; - MCF_PSC0_PSCTB_8BIT = 0x0a0d; + uart_out_word('OK! '); + uart_out_word(0x0a0d); MCF_I2C_I2CR = 0x0; // i2c off } @@ -588,7 +588,7 @@ void init_ac97(void) { int vb; int vc; - MCF_PSC0_PSCTB_8BIT = 'AC97'; + uart_out_word('AC97'); MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS // PSC2=TX,RX BCLK,CTS->AC'97 | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK | MCF_PAD_PAR_PSC2_PAR_TXD2 @@ -638,7 +638,7 @@ void init_ac97(void) { goto livo;} } } - MCF_PSC0_PSCTB_8BIT = ' NOT'; + uart_out_word(' NOT'); livo: // AUX VOLUME ->-0dB MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME @@ -669,7 +669,8 @@ livo: } MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data - MCF_PSC0_PSCTB_8BIT = ' OK!'; MCF_PSC0_PSCTB_8BIT = 0x0a0d; + uart_out_word(' OK!'); + uart_out_word(0x0a0d); } void initialize_hardware(void) { @@ -699,7 +700,7 @@ void initialize_hardware(void) { init_fpga(); init_video_ddr(); - vdi_on(); + dvi_on(); /* do not initialize ports if DIP switch 5 = on */ if (DIP_SWITCH & (1 << 6)) { From 2d5a8fc5beeb0dd733b7468b6e2644deb67ec75d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 17 Oct 2012 05:29:25 +0000 Subject: [PATCH 117/276] added missing call to init_pll() --- BaS_GNU/sources/sysinit.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index a7d6d7e..5895879 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -214,6 +214,8 @@ static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600; void init_pll(void) { + uart_out_word('PLL '); + * (volatile uint16_t *) (pll_base + 0x48) = 0x27; /* loopfilter r */ wait_pll(); * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ @@ -255,20 +257,28 @@ void init_pll(void) void init_video_ddr(void) { * (uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */ NOP(); + _VRAM = 0x00050400; /* IPALL */ NOP(); + _VRAM = 0x00072000; /* load EMR pll on */ NOP(); + _VRAM = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */ NOP(); + _VRAM = 0x00050400; /* IPALL */ NOP(); + _VRAM = 0x00060000; /* auto refresh */ NOP(); + _VRAM = 0x00060000; /* auto refresh */ NOP(); + _VRAM = 0000070022; /* load MR dll on */ NOP(); + * (uint32_t *) 0xf0000400 = 0x01070002; } @@ -699,6 +709,7 @@ void initialize_hardware(void) { init_PCI(); init_fpga(); + init_pll(); init_video_ddr(); dvi_on(); From 967e705d0295f54215e34e3b5504704538bc6d94 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 17 Oct 2012 20:31:30 +0000 Subject: [PATCH 118/276] modified _VRAM storage class to volatile --- BaS_GNU/sources/sysinit.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 5895879..bd0166d 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -12,7 +12,7 @@ #include "cache.h" #include "sysinit.h" -extern unsigned long _VRAM; +extern volatile long _VRAM; extern unsigned long BaS; extern int copy_end(); @@ -218,29 +218,29 @@ void init_pll(void) * (volatile uint16_t *) (pll_base + 0x48) = 0x27; /* loopfilter r */ wait_pll(); - * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ + * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ wait_pll(); - * (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */ + * (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */ wait_pll(); - * (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */ + * (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */ wait_pll(); - * (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */ + * (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */ wait_pll(); - * (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */ + * (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */ wait_pll(); - * (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */ + * (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */ wait_pll(); - * (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */ + * (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */ wait_pll(); - * (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */ + * (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */ wait_pll(); - * (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */ + * (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */ wait_pll(); - * (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */ + * (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */ wait_pll(); * (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */ wait_pll(); - * (volatile uint8_t *) 0xf0000800 = 0; /* set */ + * (volatile uint8_t *) 0xf0000800 = 0; /* set */ uart_out_word('SET!'); uart_out_word(0x0a0d); @@ -255,7 +255,7 @@ void init_pll(void) #define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") void init_video_ddr(void) { - * (uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */ + * (volatile uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */ NOP(); _VRAM = 0x00050400; /* IPALL */ From cdd7a0c623ae4595b5c3567adffce4f7343efc37 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 18 Oct 2012 11:42:16 +0000 Subject: [PATCH 119/276] rearranged linker script to relocate BaS code to target RAM address --- BaS_GNU/flash.lk | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/BaS_GNU/flash.lk b/BaS_GNU/flash.lk index 9763ae3..bbbdbcd 100644 --- a/BaS_GNU/flash.lk +++ b/BaS_GNU/flash.lk @@ -1,6 +1,6 @@ -ENTRY(_startup); MEMORY { - code (RX) : ORIGIN = 0xE0000000, LENGTH = 0x00200000 + flash (RX) : ORIGIN = 0xE0000000, LENGTH = 0xFFFFFFFF + ram (WX) : ORIGIN = 0x1FE00000, LENGTH = 0x00100000 /* target to copy BaS to */ } SECTIONS { @@ -33,8 +33,9 @@ SECTIONS { __RAMBAR1 = ABSOLUTE(0xFF101000); __RAMBAR1_SIZE = ABSOLUTE(0x00001000); - /* Systemveriablem:****************************************** */ - /* RAMBAR0 0 bis 0x7FF -> exception vectoren */ + /* system variables */ + + /* RAMBAR0 0 to 0x7FF -> exception vectors */ _rt_mod = __RAMBAR0 + 0x800; _rt_ssp = __RAMBAR0 + 0x804; _rt_usp = __RAMBAR0 + 0x808; @@ -53,20 +54,19 @@ SECTIONS { _video_sbt = __RAMBAR0 + 0x83C; _rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */ -/**********************************************************/ - -/* 32KB on-chip System SRAM */ + /* 32KB on-chip System SRAM */ __SYS_SRAM = ABSOLUTE(0xFF010000); __SYS_SRAM_SIZE = ABSOLUTE(0x00008000); - .code : {} > code - + .code ___BOOT_FLASH : + { + objs/startcf.o + } > flash + .text : { - objs/startcf.o(.text) objs/sysinit.o(.text) objs/init_fpga.o(.text) - objs/BaS.o(.text) objs/sd_card.o(.text) objs/cache.o(.text) objs/mmu.o(.text) @@ -74,6 +74,12 @@ SECTIONS { objs/supervisor.o(.text) objs/ewf.o(.text) objs/illegal_instruction.o(.text) - objs/last.o(.text) - } > code + _bas = .; + } > flash + + .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) + { + objs/BaS.o(.text) + _bas_length = . - _BaS; + } > ram } \ No newline at end of file From e76ed0b5d929154f297fe5cca04c6d421d980940 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 18 Oct 2012 11:44:00 +0000 Subject: [PATCH 120/276] modified to work with multi-section linker script --- BaS_GNU/sources/sysinit.c | 147 +++++++++++++++----------------------- 1 file changed, 58 insertions(+), 89 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index bd0166d..02501ba 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -13,12 +13,51 @@ #include "sysinit.h" extern volatile long _VRAM; -extern unsigned long BaS; -extern int copy_end(); -extern void wait_1ms(); -extern void wait_50us(); +/* + * warte_routinen + */ +void wait_10ms(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 1320000; + while (MCF_SLT_SCNT(0) > target); +} + +void wait_1ms(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 132000; + + while (MCF_SLT_SCNT(0) > target); +} + +void wait_100us(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 13200; + + while (MCF_SLT_SCNT(0) > target); +} + +void wait_50us(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 6600; + + while (MCF_SLT_SCNT(0) > target); +} + +void wait_10us(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 1320; + + while (MCF_SLT_SCNT(0) > target); +} + +void wait_1us(void) +{ + register uint32_t target = MCF_SLT_SCNT(0) - 132; + + while (MCF_SLT_SCNT(0) > target); +} /* * init SLICE TIMER 0 @@ -283,79 +322,6 @@ void init_video_ddr(void) { } -#ifdef _NOT_USED_ - -/* - * video mit auflösung 1280x1000 137MHz - */ - -void video_1280_1024(void) { - extern int wait_pll; - - asm { - // SPEICHER FÃœLLEM - //testmuster 1 - lea __VRAM, a2 - lea __VRAM + 0x600000,a3 - clr.l d0 - move.l #0x1000102,d1 - loop5: - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - move.l d0, (a2) + - add.l d1, d0 -flo6: - cmp.l a2, a3 - bgt loop5 -// screen setzen -//horizontal 1280 - lea 0xffff8282, a0 - move.w #1800,(a0)+ - move.w #1380,(a0)+ - move.w #99,(a0)+ - move.w #100,(a0)+ - move.w #1379,(a0)+ - move.w #1500,(a0) -//vertical 1024 - lea 0xffff82a2, a0 - move.w #1150,(a0)+ - move.w #1074,(a0)+ - move.w #49,(a0)+ - move.w #50,(a0)+ - move.w #1073,(a0)+ - move.w #1100,(a0)+ -// acp video on - move.l #0x01070207,d0 - move.l d0, 0xf0000400 -// clut setzen - lea 0xf0000000, a0 - move.l #0xffffffff,(a0)+ - move.l #0xff,(a0)+ - move.l #0xff00,(a0)+ - move.l #0xff0000,(a0) -// halt - } -} - -#endif - #define PCI_MEMORY_OFFSET (0x80000000) #define PCI_MEMORY_SIZE (0x40000000) #define PCI_IO_OFFSET (0xD0000000) @@ -684,11 +650,15 @@ livo: } void initialize_hardware(void) { - extern uint8_t *copy_start; - extern uint8_t *Bas_base; + extern uint8_t *Bas_base; /* target address to copy bas to (from linker script) */ + extern uint8_t *bas; /* source address to copy bas from (from linker script) FIXME: beware of possible alignment */ + extern uint32_t bas_length;/* length of BaS code to copy (from linker script) */ + extern void *BaS; /* BaS routine to jump to after copy */ + + int i; uint32_t *src; uint32_t *dst; - uint32_t jmp; + uint8_t *jmp; __asm__ __volatile__( "move.l #0x000C8120,D0\n\t" @@ -721,24 +691,23 @@ void initialize_hardware(void) { } /* copy the BaS code contained in flash to its final location */ - src = ©_start; - dst = &Bas_base; - jmp = (uint8_t *) &BaS - (uint32_t) ©_start + (uint32_t) &Bas_base; - do { + src = (uint32_t *)&bas; + dst = (uint32_t *)&Bas_base; + jmp = (uint8_t *)&BaS; + for (i = 0; i < (int) &bas_length; i+= 4) + { *src++ = *dst++; *src++ = *dst++; *src++ = *dst++; *src++ = *dst++; - } while (src < (uint8_t *) ©_end); + } - flushDataCacheRegion(&Bas_base, (uint8_t *) ©_end - copy_start); - flushInstructionCacheRegion(&Bas_base, (uint8_t *) ©_end - copy_start); + flushDataCacheRegion(&Bas_base, (int) &bas_length); + flushInstructionCacheRegion(&Bas_base, (int) &bas_length); __asm__ __volatile__( - " .global _copy_start | \n\t" " move.l %0,a3 | calculated start address\n\t" " jmp (a3) | go! \n\t" - "_copy_start: | \n\t" /* output */ : /* input */ : "g" (jmp) /* clobber */: "a3", "memory" From f43d30b44cb92a8fb8f8ff7ab8b4f023cebbb66c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 18 Oct 2012 14:00:47 +0000 Subject: [PATCH 121/276] found a line been lost in dvi_on() --- BaS_GNU/sources/sysinit.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 02501ba..b496866 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -244,9 +244,9 @@ void init_fbcs() void wait_pll(void) { + register uint32_t trgt = MCF_SLT0_SCNT - 100000; do { - wait_1ms(); - } while (! * (volatile uint16_t *) 0xf0000800); + } while ((* (volatile uint16_t *) 0xf0000800 > 0) && MCF_SLT0_SCNT > trgt); } static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600; @@ -255,30 +255,44 @@ void init_pll(void) { uart_out_word('PLL '); + wait_pll(); * (volatile uint16_t *) (pll_base + 0x48) = 0x27; /* loopfilter r */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */ + wait_pll(); * (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */ + wait_pll(); + * (volatile uint8_t *) 0xf0000800 = 0; /* set */ uart_out_word('SET!'); @@ -491,6 +505,9 @@ loop_i2c: MCF_I2C_I2SR &= 0xfd; MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); + + MCF_I2C_I2SR &= 0xfd;; MCF_I2C_I2CR = 0x80; // stop DBYT = MCF_I2C_I2DR; // dummy read MCF_I2C_I2SR = 0x0; // clear sr From 899cf936522112d0bd6d18b9396efcb854cd8680 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 18 Oct 2012 14:02:23 +0000 Subject: [PATCH 122/276] modified for relocating multi-section linker script --- BaS_GNU/sources/BaS.c | 48 ++++--------------------------------------- 1 file changed, 4 insertions(+), 44 deletions(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index f2956f6..0dea05c 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -16,51 +16,11 @@ extern int mmu_init(); extern int vec_init(); extern int illegal_table_make(); extern void sd_card_idle(); +extern int sd_card_init(); -/* - * warte_routinen - */ -void wait_10ms(void) -{ - register uint32_t target = MCF_SLT_SCNT(0) - 1320000; - - while (MCF_SLT_SCNT(0) > target); -} - -void wait_1ms(void) -{ - register uint32_t target = MCF_SLT_SCNT(0) - 132000; - - while (MCF_SLT_SCNT(0) > target); -} - -void wait_100us(void) -{ - register uint32_t target = MCF_SLT_SCNT(0) - 13200; - - while (MCF_SLT_SCNT(0) > target); -} - -void wait_50us(void) -{ - register uint32_t target = MCF_SLT_SCNT(0) - 6600; - - while (MCF_SLT_SCNT(0) > target); -} - -void wait_10us(void) -{ - register uint32_t target = MCF_SLT_SCNT(0) - 1320; - - while (MCF_SLT_SCNT(0) > target); -} - -void wait_1us(void) -{ - register uint32_t target = MCF_SLT_SCNT(0) - 132; - - while (MCF_SLT_SCNT(0) > target); -} +/* wait...() routines moved to sysinit.c */ +extern void wait_10ms(); +extern void wait_1ms(); /********************************************************************/ void BaS(void) From 56024823a58ed7f0661924b285f2aea8730e94bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 18 Oct 2012 15:44:29 +0000 Subject: [PATCH 123/276] not neccessary anymore --- BaS_GNU/sources/last.c | 14 -------------- 1 file changed, 14 deletions(-) delete mode 100644 BaS_GNU/sources/last.c diff --git a/BaS_GNU/sources/last.c b/BaS_GNU/sources/last.c deleted file mode 100644 index bc9eca1..0000000 --- a/BaS_GNU/sources/last.c +++ /dev/null @@ -1,14 +0,0 @@ -/* - * last file of the list. In the original sources, this marks the end of the - * copy loop that copies the BaS to its final place. - * - * FIXME: bogus mark of end of code - * - * no need to do it that way - this file will probably vanish and be replaced by - * a matching entry in the linker script. - */ -void copy_end(void) -{ - asm(".globl copy_end\n\t"); - asm("copy_end: nop\n\t"); -} From 4d8beb0d8d5d7181feeda56dc5c25c9c30321226 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 18 Oct 2012 15:48:14 +0000 Subject: [PATCH 124/276] fixed formatting --- BaS_GNU/sources/sysinit.c | 65 ++++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 32 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index b496866..11f141e 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -628,42 +628,43 @@ void init_ac97(void) { /* FIXME: that looks more than suspicious (Fredi?) */ if ((va & 0xE0000fff) == 0xE0000800 & vb == 0x02000000 & vc == 0x00000000) { - goto livo;} + goto livo; } } - uart_out_word(' NOT'); + } + uart_out_word(' NOT'); livo: - // AUX VOLUME ->-0dB - MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME - MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16 - MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME - for (i = 3; i < 13; i++) { - MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 - } + // AUX VOLUME ->-0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16 + MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME + for (i = 3; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } - // line in VOLUME +12dB - MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME - MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 - for (i = 2; i < 13; i++) { - MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 - } - // cd in VOLUME 0dB - MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME - MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 - for (i = 2; i < 13; i++) { - MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 - } - // mono out VOLUME 0dB - MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME - MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 - MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 - for (i = 3; i < 13; i++) { - MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 - } - MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF - MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data - uart_out_word(' OK!'); - uart_out_word(0x0a0d); + // line in VOLUME +12dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 2; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + // cd in VOLUME 0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 2; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + // mono out VOLUME 0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 3; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF + MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data + uart_out_word(' OK!'); + uart_out_word(0x0a0d); } void initialize_hardware(void) { From a81625527a2678c705b84f33dfafa68968ea3f35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 18 Oct 2012 15:49:21 +0000 Subject: [PATCH 125/276] removed last file --- BaS_GNU/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 94ceb42..d1440d9 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -37,8 +37,7 @@ CSRCS= \ $(SRCDIR)/init_fpga.c \ $(SRCDIR)/BaS.c \ $(SRCDIR)/cache.c \ - $(SRCDIR)/sd_card.c \ - $(SRCDIR)/last.c + $(SRCDIR)/sd_card.c ASRCS= \ $(SRCDIR)/mmu.S \ From 2f7d46d1c7a9147bcdd2fb7d5e6ffe310a44ad84 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 18 Oct 2012 15:54:45 +0000 Subject: [PATCH 126/276] added $(STRT_OBJ) to clean target --- BaS_GNU/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index d1440d9..44c5489 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -57,7 +57,7 @@ OBJS=$(COBJS) $(AOBJS) .PHONY all: $(EXEC) .PHONY clean: - @ rm -f $(EXEC) $(OBJS) $(MAPFILE) depend + @ rm -f $(EXEC) $(STRT_OBJ) $(OBJS) $(MAPFILE) depend $(EXEC): $(STRT_OBJ) $(OBJS) $(LDCFILE) $(LD) --oformat srec -Map $(MAPFILE) --cref -T flash.lk -s -o $@ From e9d5031209519dc0a51d6eaa5a77eac100d05b7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 18 Oct 2012 15:56:44 +0000 Subject: [PATCH 127/276] removed CodeWarrior linker scripts --- BaS_GNU/lcf/DDRAM.lcf | 88 ------------------------------------------- BaS_GNU/lcf/FLASH.lcf | 88 ------------------------------------------- 2 files changed, 176 deletions(-) delete mode 100644 BaS_GNU/lcf/DDRAM.lcf delete mode 100644 BaS_GNU/lcf/FLASH.lcf diff --git a/BaS_GNU/lcf/DDRAM.lcf b/BaS_GNU/lcf/DDRAM.lcf deleted file mode 100644 index 795732d..0000000 --- a/BaS_GNU/lcf/DDRAM.lcf +++ /dev/null @@ -1,88 +0,0 @@ -# Sample Linker Command File for CodeWarrior for ColdFire - -KEEP_SECTION {.vectortable} - -# Memory ranges - -MEMORY { - code (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0 -} - -SECTIONS { - -#BaS Basis adresse - ___Bas_base = 0x1FE00000; - -# Board Memory map definitions from linker command files: -# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE -# linker symbols must be defined in the linker command file. - -#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) - ___BOOT_FLASH = 0xE0000000; - ___BOOT_FLASH_SIZE = 0x00800000; -#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes - ___SDRAM = 0x00000000; - ___SDRAM_SIZE = 0x20000000; - -#VIDEO RAM BASIS - ___VRAM = 0x60000000; - -# MCF5475 Derivative Memory map definitions from linker command files: -# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE -# linker symbols must be defined in the linker command file. - -# Memory mapped registers - ___MBAR = 0xFF000000; - ___MMUBAR = 0xFF040000; -# 4KB on-chip Core SRAM0: -> exception table and exception stack - ___RAMBAR0 = 0xFF100000; - ___RAMBAR0_SIZE = 0x00001000; - - ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4; - -# 4KB on-chip Core SRAM1: -> modified code - ___RAMBAR1 = 0xFF101000; - ___RAMBAR1_SIZE = 0x00001000; - -# Systemveriablem:****************************************** -# RAMBAR0 0 bis 0x7FF -> exception vectoren -_rt_mod = ___RAMBAR0 + 0x800; -_rt_ssp = ___RAMBAR0 + 0x804; -_rt_usp = ___RAMBAR0 + 0x808; -_rt_vbr = ___RAMBAR0 + 0x80C; # (8)01 -_rt_cacr = ___RAMBAR0 + 0x810; # 002 -_rt_asid = ___RAMBAR0 + 0x814; # 003 -_rt_acr0 = ___RAMBAR0 + 0x818; # 004 -_rt_acr1 = ___RAMBAR0 + 0x81c; # 005 -_rt_acr2 = ___RAMBAR0 + 0x820; # 006 -_rt_acr3 = ___RAMBAR0 + 0x824; # 007 -_rt_mmubar = ___RAMBAR0 + 0x828; # 008 -_rt_sr = ___RAMBAR0 + 0x82c; -_d0_save = ___RAMBAR0 + 0x830; -_a7_save = ___RAMBAR0 + 0x834; -_video_tlb = ___RAMBAR0 + 0x838; -_video_sbt = ___RAMBAR0 + 0x83C; -_rt_mbar = ___RAMBAR0 + 0x844; # (c)0f -#*********************************************************** - -# 32KB on-chip System SRAM - ___SYS_SRAM = 0xFF010000; - ___SYS_SRAM_SIZE = 0x00008000; - - - .text : - { - startcf.c(.text) - sysinit.c(.text) - BaS.c(.text) - sd_card.c(.text) - mmu.s(.text) - exceptions.s(.text) - supervisor.s(.text) - ewf.s(.text) - illegal_instruction.s(.text) - last.c(.text) - . = ALIGN (0x4); - } > code - -} \ No newline at end of file diff --git a/BaS_GNU/lcf/FLASH.lcf b/BaS_GNU/lcf/FLASH.lcf deleted file mode 100644 index 970ad7a..0000000 --- a/BaS_GNU/lcf/FLASH.lcf +++ /dev/null @@ -1,88 +0,0 @@ -# Sample Linker Command File for CodeWarrior for ColdFire - -KEEP_SECTION {.vectortable} - -# Memory ranges - -MEMORY { - code (RX) : ORIGIN = 0xE0000000, LENGTH = 0x00200000 -} - -SECTIONS { - -#BaS Basis adresse - ___Bas_base = 0x1FE00000; - -# Board Memory map definitions from linker command files: -# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE -# linker symbols must be defined in the linker command file. - -#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) - ___BOOT_FLASH = 0xE0000000; - ___BOOT_FLASH_SIZE = 0x00800000; -#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes - ___SDRAM = 0x00000000; - ___SDRAM_SIZE = 0x20000000; - -#VIDEO RAM BASIS - __VRAM = 0x60000000; - -# MCF5475 Derivative Memory map definitions from linker command files: -# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE -# linker symbols must be defined in the linker command file. - -# Memory mapped registers - ___MBAR = 0xFF000000; - ___MMUBAR = 0xFF040000; -# 4KB on-chip Core SRAM0: -> exception table and exception stack - ___RAMBAR0 = 0xFF100000; - ___RAMBAR0_SIZE = 0x00001000; - - ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4; - -# 4KB on-chip Core SRAM1: -> modified code - ___RAMBAR1 = 0xFF101000; - ___RAMBAR1_SIZE = 0x00001000; - -# Systemveriablem:****************************************** -# RAMBAR0 0 bis 0x7FF -> exception vectoren -_rt_mod = ___RAMBAR0 + 0x800; -_rt_ssp = ___RAMBAR0 + 0x804; -_rt_usp = ___RAMBAR0 + 0x808; -_rt_vbr = ___RAMBAR0 + 0x80C; # (8)01 -_rt_cacr = ___RAMBAR0 + 0x810; # 002 -_rt_asid = ___RAMBAR0 + 0x814; # 003 -_rt_acr0 = ___RAMBAR0 + 0x818; # 004 -_rt_acr1 = ___RAMBAR0 + 0x81c; # 005 -_rt_acr2 = ___RAMBAR0 + 0x820; # 006 -_rt_acr3 = ___RAMBAR0 + 0x824; # 007 -_rt_mmubar = ___RAMBAR0 + 0x828; # 008 -_rt_sr = ___RAMBAR0 + 0x82c; -_d0_save = ___RAMBAR0 + 0x830; -_a7_save = ___RAMBAR0 + 0x834; -_video_tlb = ___RAMBAR0 + 0x838; -_video_sbt = ___RAMBAR0 + 0x83C; -_rt_mbar = ___RAMBAR0 + 0x844; # (c)0f -#*********************************************************** - -# 32KB on-chip System SRAM - ___SYS_SRAM = 0xFF010000; - ___SYS_SRAM_SIZE = 0x00008000; - - .code : {} > code - - .text : - { - startcf.c(.text) - sysinit.c(.text) - BaS.c(.text) - sd_card.c(.text) - mmu.s(.text) - exceptions.s(.text) - supervisor.s(.text) - ewf.s(.text) - illegal_instruction.s(.text) - last.c(.text) - } >> code - -} \ No newline at end of file From 74b2a652e3cf0df0c86c63c9ff832f4115923ee5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 18 Oct 2012 15:58:01 +0000 Subject: [PATCH 128/276] removed CodeWarrior .xml -files --- BaS_GNU/flash_config.xml | 47 --------------------------------- BaS_GNU/hardware_diagnostic.xml | 40 ---------------------------- 2 files changed, 87 deletions(-) delete mode 100644 BaS_GNU/flash_config.xml delete mode 100644 BaS_GNU/hardware_diagnostic.xml diff --git a/BaS_GNU/flash_config.xml b/BaS_GNU/flash_config.xml deleted file mode 100644 index ce2e67e..0000000 --- a/BaS_GNU/flash_config.xml +++ /dev/null @@ -1,47 +0,0 @@ - - - - - true - 5474 - PEMICRO_USB - true - C:\FireBee\codewarrior\firebeeV1\cfg\mem.cfg - 0x00000000 - 0x00006000 - true - false - - - - 0xE0000000 - M29W640DB - 4Mx16x1 - 0xE0000000 - 0xE07FFFFF - - - - true - C:\FireBee\codewarrior\firebeeV1\bin\FLASH.elf.S19 - Auto Detect - false - 0xFF800000 - 0xFFFFFFFF - false - 0xC0200000 - - - - false - - false - - - - FileOnTarg - 0xFF800000 - 0x007FFFFF - - - diff --git a/BaS_GNU/hardware_diagnostic.xml b/BaS_GNU/hardware_diagnostic.xml deleted file mode 100644 index b45676f..0000000 --- a/BaS_GNU/hardware_diagnostic.xml +++ /dev/null @@ -1,40 +0,0 @@ - - - - - true - 5474 - PEMICRO_USB - true - {CodeWarrior}\ColdFire_Support\Initialization_Files\MCF5475.cfg - - - - read - long_word - 0x60001000 - FFFFFFFF - - - - read - long_word - 0x00100000 - 0x67 - 1000 - - - - true - true - true - 0x00DE1000 - 0x00DE11FF - long_word - 1 - false - 0x00000100 - 0x0000FFFF - - - From 6609ee07b066192d3f724621aa29136f31d3972a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 19 Oct 2012 05:57:35 +0000 Subject: [PATCH 129/276] fixed wrong BaS copy length. --- BaS_GNU/sources/sysinit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 11f141e..e1bbff3 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -712,7 +712,7 @@ void initialize_hardware(void) { src = (uint32_t *)&bas; dst = (uint32_t *)&Bas_base; jmp = (uint8_t *)&BaS; - for (i = 0; i < (int) &bas_length; i+= 4) + for (i = 0; i < (int) &bas_length / 16; i+= 4) { *src++ = *dst++; *src++ = *dst++; @@ -729,5 +729,5 @@ void initialize_hardware(void) { /* output */ : /* input */ : "g" (jmp) /* clobber */: "a3", "memory" - ); + ); } From 5eb7a0a3eec34f7ac3600244386d7eca6c220f3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 19 Oct 2012 06:23:44 +0000 Subject: [PATCH 130/276] redefined FLASH_DATA_... constants --- BaS_GNU/sources/sysinit.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/sources/sysinit.h b/BaS_GNU/sources/sysinit.h index f8520bf..ec097a0 100644 --- a/BaS_GNU/sources/sysinit.h +++ b/BaS_GNU/sources/sysinit.h @@ -15,8 +15,8 @@ extern void wait_10us(void); #define uart_out_word(a) MCF_PSC0_PSCTB_8BIT = (a); /* adresses where FPGA data lives in flash */ -static const uint8_t *FPGA_FLASH_DATA = (uint8_t *) 0xe0700000L; -static const uint8_t *FPGA_FLASH_DATA_END = (uint8_t *) 0xe0800000L; +#define FPGA_FLASH_DATA ((uint8_t *) 0xe0700000L) +#define FPGA_FLASH_DATA_END ((uint8_t *) 0xe0800000L) /* function(s) from init_fpga.c */ extern void init_fpga(void); From 0d86b7dccbd767877156ae04eafef8a3206c55eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 19 Oct 2012 06:25:00 +0000 Subject: [PATCH 131/276] removed superflous semicolon --- BaS_GNU/sources/sysinit.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/sources/sysinit.h b/BaS_GNU/sources/sysinit.h index ec097a0..a8df15e 100644 --- a/BaS_GNU/sources/sysinit.h +++ b/BaS_GNU/sources/sysinit.h @@ -12,7 +12,7 @@ extern void wait_10us(void); /* send a 16-bit word out on the serial port */ -#define uart_out_word(a) MCF_PSC0_PSCTB_8BIT = (a); +#define uart_out_word(a) MCF_PSC0_PSCTB_8BIT = (a) /* adresses where FPGA data lives in flash */ #define FPGA_FLASH_DATA ((uint8_t *) 0xe0700000L) From 61550f83e645c3dbfad4c886b25013c90e5f1490 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 19 Oct 2012 08:42:35 +0000 Subject: [PATCH 132/276] simplified and corrected BaS copy --- BaS_GNU/flash.lk | 5 +++-- BaS_GNU/sources/sysinit.c | 22 ++++++++++------------ 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/BaS_GNU/flash.lk b/BaS_GNU/flash.lk index bbbdbcd..708008d 100644 --- a/BaS_GNU/flash.lk +++ b/BaS_GNU/flash.lk @@ -1,5 +1,5 @@ MEMORY { - flash (RX) : ORIGIN = 0xE0000000, LENGTH = 0xFFFFFFFF + flash (RX) : ORIGIN = 0xE0000000, LENGTH = 0x00200000 ram (WX) : ORIGIN = 0x1FE00000, LENGTH = 0x00100000 /* target to copy BaS to */ } @@ -80,6 +80,7 @@ SECTIONS { .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) { objs/BaS.o(.text) - _bas_length = . - _BaS; + _bas_end = ABSOLUTE(.); } > ram + } \ No newline at end of file diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index e1bbff3..c9be904 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -668,15 +668,13 @@ livo: } void initialize_hardware(void) { - extern uint8_t *Bas_base; /* target address to copy bas to (from linker script) */ - extern uint8_t *bas; /* source address to copy bas from (from linker script) FIXME: beware of possible alignment */ - extern uint32_t bas_length;/* length of BaS code to copy (from linker script) */ - extern void *BaS; /* BaS routine to jump to after copy */ + extern uint32_t bas; /* source address to copy bas from (from linker script) FIXME: beware of possible alignment */ + extern uint32_t bas_end; /* end of BaS code to copy (from linker script) */ + extern uint32_t BaS; /* BaS routine to jump to after copy */ - int i; uint32_t *src; uint32_t *dst; - uint8_t *jmp; + uint32_t *jmp; __asm__ __volatile__( "move.l #0x000C8120,D0\n\t" @@ -710,18 +708,18 @@ void initialize_hardware(void) { /* copy the BaS code contained in flash to its final location */ src = (uint32_t *)&bas; - dst = (uint32_t *)&Bas_base; - jmp = (uint8_t *)&BaS; - for (i = 0; i < (int) &bas_length / 16; i+= 4) + dst = jmp = (uint32_t *)&BaS; + + do { *src++ = *dst++; *src++ = *dst++; *src++ = *dst++; *src++ = *dst++; - } + } while (dst < &bas_end); - flushDataCacheRegion(&Bas_base, (int) &bas_length); - flushInstructionCacheRegion(&Bas_base, (int) &bas_length); + flushDataCacheRegion(&BaS, (uint32_t) (&bas_end - &BaS)); + flushInstructionCacheRegion(&BaS, (uint32_t) (&bas_end - &BaS)); __asm__ __volatile__( " move.l %0,a3 | calculated start address\n\t" From a00dc595c97a1978304d5ab01e7a0e4c7b4ec81b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 19 Oct 2012 09:56:45 +0000 Subject: [PATCH 133/276] Modified Makefile and linker script ("make ram") to be able to compile with a ram address as target. Should ease BDM debugging roundtrip because no need to flash after a fresh compile. --- BaS_GNU/Makefile | 22 ++++++++----- BaS_GNU/bas.lk.S | 86 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+), 8 deletions(-) create mode 100644 BaS_GNU/bas.lk.S diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 44c5489..bc9c77a 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -16,6 +16,7 @@ TCPREFIX=m68k-atari-mint- CC=$(TCPREFIX)gcc LD=$(TCPREFIX)ld +CPP=$(TCPREFIX)cpp INCLUDE=-Iinclude CFLAGS=-mcpu=5474 -Wall -Wno-multichar -Os -fomit-frame-pointer @@ -25,10 +26,9 @@ OBJDIR=objs MAPFILE=bas.map -# Linker control files. flash.lk is meant for BaS in flash, ram.lk (not written yet) for -# debugging in RAM. -LDCFILE=flash.lk -# LDCFILE=ram.lk +# Linker control file. +LDCFILE=bas.lk +LDCSRC=bas.lk.S EXEC=bas.s19 @@ -57,11 +57,17 @@ OBJS=$(COBJS) $(AOBJS) .PHONY all: $(EXEC) .PHONY clean: - @ rm -f $(EXEC) $(STRT_OBJ) $(OBJS) $(MAPFILE) depend - -$(EXEC): $(STRT_OBJ) $(OBJS) $(LDCFILE) - $(LD) --oformat srec -Map $(MAPFILE) --cref -T flash.lk -s -o $@ + @ rm -f $(EXEC) $(STRT_OBJ) $(OBJS) $(MAPFILE) $(LDCFILE) depend + +$(EXEC): $(STRT_OBJ) $(OBJS) $(LDCSRC) + $(CPP) -P -DTARGET_ADDRESS=0xe0000000 $(LDCSRC) -o $(LDCFILE) + $(LD) --oformat srec -Map $(MAPFILE) --cref -T $(LDCFILE) -s -o $@ + +ram: $(STRT_OBJ) $(OBJS) $(LDCSRC) + $(CPP) -P -DTARGET_ADDRESS=0x01000000 $(LDCSRC) -o $(LDCFILE) + $(LD) --oformat srec -Map $(MAPFILE) --cref -T $(LDCFILE) -s -o $@.s19 + # compile init_fpga with -mbitfield for testing purposes $(OBJDIR)/init_fpga.o: CFLAGS += -mbitfield diff --git a/BaS_GNU/bas.lk.S b/BaS_GNU/bas.lk.S new file mode 100644 index 0000000..41f4503 --- /dev/null +++ b/BaS_GNU/bas.lk.S @@ -0,0 +1,86 @@ +MEMORY { + flash (RX) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00200000 + ram (WX) : ORIGIN = 0x1FE00000, LENGTH = 0x00100000 /* target to copy BaS to */ +} + +SECTIONS { + _Bas_base = ABSOLUTE(0x1FE00000); + _tos_base = ABSOLUTE(0xe00000); + + /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */ + ___BOOT_FLASH = ABSOLUTE(TARGET_ADDRESS); + ___BOOT_FLASH_SIZE = ABSOLUTE(0x00800000); + /* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */ + ___SDRAM = ABSOLUTE(0x00000000); + ___SDRAM_SIZE = ABSOLUTE(0x20000000); + + /* VIDEO RAM BASIS */ + __VRAM = ABSOLUTE(0x60000000); + + /* Memory mapped registers */ + __MBAR = ABSOLUTE(0xFF000000); + __MMUBAR = ABSOLUTE(0xFF040000); + + /* + * 4KB on-chip Core SRAM0: -> exception table and exception stack + */ + __RAMBAR0 = ABSOLUTE(0xFF100000); + __RAMBAR0_SIZE = ABSOLUTE(0x00001000); + + __SUP_SP = ABSOLUTE(__RAMBAR0 + __RAMBAR0_SIZE - 4); + + /* 4KB on-chip Core SRAM1: -> modified code */ + __RAMBAR1 = ABSOLUTE(0xFF101000); + __RAMBAR1_SIZE = ABSOLUTE(0x00001000); + + /* system variables */ + + /* RAMBAR0 0 to 0x7FF -> exception vectors */ + _rt_mod = __RAMBAR0 + 0x800; + _rt_ssp = __RAMBAR0 + 0x804; + _rt_usp = __RAMBAR0 + 0x808; + _rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */ + _rt_cacr = __RAMBAR0 + 0x810; /* 002 */ + _rt_asid = __RAMBAR0 + 0x814; /* 003 */ + _rt_acr0 = __RAMBAR0 + 0x818; /* 004 */ + _rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */ + _rt_acr2 = __RAMBAR0 + 0x820; /* 006 */ + _rt_acr3 = __RAMBAR0 + 0x824; /* 007 */ + _rt_mmubar = __RAMBAR0 + 0x828; /* 008 */ + _rt_sr = __RAMBAR0 + 0x82c; + _d0_save = __RAMBAR0 + 0x830; + _a7_save = __RAMBAR0 + 0x834; + _video_tlb = __RAMBAR0 + 0x838; + _video_sbt = __RAMBAR0 + 0x83C; + _rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */ + + /* 32KB on-chip System SRAM */ + __SYS_SRAM = ABSOLUTE(0xFF010000); + __SYS_SRAM_SIZE = ABSOLUTE(0x00008000); + + .code ___BOOT_FLASH : + { + objs/startcf.o + } > flash + + .text : + { + objs/sysinit.o(.text) + objs/init_fpga.o(.text) + objs/sd_card.o(.text) + objs/cache.o(.text) + objs/mmu.o(.text) + objs/exceptions.o(.text) + objs/supervisor.o(.text) + objs/ewf.o(.text) + objs/illegal_instruction.o(.text) + _bas = .; + } > flash + + .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) + { + objs/BaS.o(.text) + _bas_end = ABSOLUTE(.); + } > ram + +} \ No newline at end of file From db8c3a3c33f1e91aa6cd8a3909824034e3105e77 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 19 Oct 2012 09:59:44 +0000 Subject: [PATCH 134/276] new Makefile target "ram" moved flash.lk to flash.lk.S. Flash.lk is now an intermediate file --- BaS_GNU/.cproject | 10 +++++- BaS_GNU/flash.lk | 86 ----------------------------------------------- 2 files changed, 9 insertions(+), 87 deletions(-) delete mode 100644 BaS_GNU/flash.lk diff --git a/BaS_GNU/.cproject b/BaS_GNU/.cproject index 9245952..293c3ff 100644 --- a/BaS_GNU/.cproject +++ b/BaS_GNU/.cproject @@ -109,6 +109,7 @@ make + all true true @@ -116,12 +117,19 @@ make - clean true true true + + make + + ram + true + true + true + diff --git a/BaS_GNU/flash.lk b/BaS_GNU/flash.lk deleted file mode 100644 index 708008d..0000000 --- a/BaS_GNU/flash.lk +++ /dev/null @@ -1,86 +0,0 @@ -MEMORY { - flash (RX) : ORIGIN = 0xE0000000, LENGTH = 0x00200000 - ram (WX) : ORIGIN = 0x1FE00000, LENGTH = 0x00100000 /* target to copy BaS to */ -} - -SECTIONS { - _Bas_base = ABSOLUTE(0x1FE00000); - _tos_base = ABSOLUTE(0xe00000); - - /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */ - ___BOOT_FLASH = ABSOLUTE(0xE0000000); - ___BOOT_FLASH_SIZE = ABSOLUTE(0x00800000); - /* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */ - ___SDRAM = ABSOLUTE(0x00000000); - ___SDRAM_SIZE = ABSOLUTE(0x20000000); - - /* VIDEO RAM BASIS */ - __VRAM = ABSOLUTE(0x60000000); - - /* Memory mapped registers */ - __MBAR = ABSOLUTE(0xFF000000); - __MMUBAR = ABSOLUTE(0xFF040000); - - /* - * 4KB on-chip Core SRAM0: -> exception table and exception stack - */ - __RAMBAR0 = ABSOLUTE(0xFF100000); - __RAMBAR0_SIZE = ABSOLUTE(0x00001000); - - __SUP_SP = ABSOLUTE(__RAMBAR0 + __RAMBAR0_SIZE - 4); - - /* 4KB on-chip Core SRAM1: -> modified code */ - __RAMBAR1 = ABSOLUTE(0xFF101000); - __RAMBAR1_SIZE = ABSOLUTE(0x00001000); - - /* system variables */ - - /* RAMBAR0 0 to 0x7FF -> exception vectors */ - _rt_mod = __RAMBAR0 + 0x800; - _rt_ssp = __RAMBAR0 + 0x804; - _rt_usp = __RAMBAR0 + 0x808; - _rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */ - _rt_cacr = __RAMBAR0 + 0x810; /* 002 */ - _rt_asid = __RAMBAR0 + 0x814; /* 003 */ - _rt_acr0 = __RAMBAR0 + 0x818; /* 004 */ - _rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */ - _rt_acr2 = __RAMBAR0 + 0x820; /* 006 */ - _rt_acr3 = __RAMBAR0 + 0x824; /* 007 */ - _rt_mmubar = __RAMBAR0 + 0x828; /* 008 */ - _rt_sr = __RAMBAR0 + 0x82c; - _d0_save = __RAMBAR0 + 0x830; - _a7_save = __RAMBAR0 + 0x834; - _video_tlb = __RAMBAR0 + 0x838; - _video_sbt = __RAMBAR0 + 0x83C; - _rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */ - - /* 32KB on-chip System SRAM */ - __SYS_SRAM = ABSOLUTE(0xFF010000); - __SYS_SRAM_SIZE = ABSOLUTE(0x00008000); - - .code ___BOOT_FLASH : - { - objs/startcf.o - } > flash - - .text : - { - objs/sysinit.o(.text) - objs/init_fpga.o(.text) - objs/sd_card.o(.text) - objs/cache.o(.text) - objs/mmu.o(.text) - objs/exceptions.o(.text) - objs/supervisor.o(.text) - objs/ewf.o(.text) - objs/illegal_instruction.o(.text) - _bas = .; - } > flash - - .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) - { - objs/BaS.o(.text) - _bas_end = ABSOLUTE(.); - } > ram - -} \ No newline at end of file From 17751a3ce8fc376b0f817c1ed6a95ead392801c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 19 Oct 2012 10:57:50 +0000 Subject: [PATCH 135/276] simplified Makefile --- BaS_GNU/Makefile | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index bc9c77a..9d20942 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -30,7 +30,10 @@ MAPFILE=bas.map LDCFILE=bas.lk LDCSRC=bas.lk.S -EXEC=bas.s19 +# this Makefile can create the BaS to flash or an arbitrary ram address (for BDM debugging). See +# below for the definition of TARGET_ADDRESS +FLASH_EXEC=bas.s19 +RAM_EXEC=ram.s19 CSRCS= \ $(SRCDIR)/sysinit.c \ @@ -54,19 +57,17 @@ AOBJS=$(patsubst $(SRCDIR)/%.o,$(OBJDIR)/%.o,$(patsubst %.S,%.o,$(ASRCS))) OBJS=$(COBJS) $(AOBJS) -.PHONY all: $(EXEC) - +.PHONY all: $(FLASH_EXEC) +.PHONY ram: $(RAM_EXEC) .PHONY clean: - @ rm -f $(EXEC) $(STRT_OBJ) $(OBJS) $(MAPFILE) $(LDCFILE) depend + @ rm -f $(FLASH_EXEC) $(RAM_EXEC) $(STRT_OBJ) $(OBJS) $(MAPFILE) $(LDCFILE) depend - -$(EXEC): $(STRT_OBJ) $(OBJS) $(LDCSRC) - $(CPP) -P -DTARGET_ADDRESS=0xe0000000 $(LDCSRC) -o $(LDCFILE) - $(LD) --oformat srec -Map $(MAPFILE) --cref -T $(LDCFILE) -s -o $@ +$(FLASH_EXEC): TARGET_ADDRESS=0xe0000000 +$(RAM_EXEC): TARGET_ADDRESS=0x01000000 -ram: $(STRT_OBJ) $(OBJS) $(LDCSRC) - $(CPP) -P -DTARGET_ADDRESS=0x01000000 $(LDCSRC) -o $(LDCFILE) - $(LD) --oformat srec -Map $(MAPFILE) --cref -T $(LDCFILE) -s -o $@.s19 +$(FLASH_EXEC) $(RAM_EXEC): $(STRT_OBJ) $(OBJS) + $(CPP) -P -DTARGET_ADDRESS=$(TARGET_ADDRESS) $(LDCSRC) -o $(LDCFILE) + $(LD) --oformat srec -Map $(MAPFILE) --cref -T $(LDCFILE) -s -o $@ # compile init_fpga with -mbitfield for testing purposes $(OBJDIR)/init_fpga.o: CFLAGS += -mbitfield From c04b07ce0dbc0852e39226e6554d4c68fc02d4b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 19 Oct 2012 12:14:30 +0000 Subject: [PATCH 136/276] added comments --- BaS_GNU/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 9d20942..5f2d0b0 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -26,7 +26,7 @@ OBJDIR=objs MAPFILE=bas.map -# Linker control file. +# Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC) LDCFILE=bas.lk LDCSRC=bas.lk.S From 881d23ae0df805b451bf71c1ee6a719f55be4453 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 19 Oct 2012 12:46:20 +0000 Subject: [PATCH 137/276] update comments --- BaS_GNU/sources/sysinit.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index c9be904..c82e33c 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -12,10 +12,10 @@ #include "cache.h" #include "sysinit.h" -extern volatile long _VRAM; +extern volatile long _VRAM; /* start address of video ram from linker script */ /* - * warte_routinen + * wait routines */ void wait_10ms(void) { @@ -102,10 +102,9 @@ void init_gpio(void) MCF_GPIO_PDDR_FEC1L = 0b00011110; /* OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA) */ } -/********************************************************************/ -// init serial -/********************************************************************/ - +/* + * init serial + */ void init_serial(void) { /* PSC0: SER1 */ @@ -382,9 +381,8 @@ void init_PCI(void) { /* - * test UPC720101 (USB) + * probe for UPC720101 (USB) */ - void test_upd720101(void) { uart_out_word('NEC '); @@ -672,9 +670,10 @@ void initialize_hardware(void) { extern uint32_t bas_end; /* end of BaS code to copy (from linker script) */ extern uint32_t BaS; /* BaS routine to jump to after copy */ - uint32_t *src; - uint32_t *dst; - uint32_t *jmp; + /* used in copy loop */ + uint32_t *src; /* src address to read from flash */ + uint32_t *dst; /* destination address to copy to */ + uint32_t *jmp; /* address of BaS() routine to jmp at after copy */ __asm__ __volatile__( "move.l #0x000C8120,D0\n\t" @@ -690,7 +689,7 @@ void initialize_hardware(void) { init_fbcs(); init_ddram(); - /* do not initialize ports if DIP switch 5 = on */ + /* do not initialize PCI if DIP switch 5 = on */ if (DIP_SWITCH & (1 << 6)) init_PCI(); @@ -718,6 +717,7 @@ void initialize_hardware(void) { *src++ = *dst++; } while (dst < &bas_end); + /* clear all addresses touched during copy from all cache lines */ flushDataCacheRegion(&BaS, (uint32_t) (&bas_end - &BaS)); flushInstructionCacheRegion(&BaS, (uint32_t) (&bas_end - &BaS)); From 9f4f829838ed78ce1dcfce0485d8250f98358b50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 19 Oct 2012 15:12:11 +0000 Subject: [PATCH 138/276] --- BaS_GNU/sources/exceptions.S | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S index e1331fd..1822c05 100644 --- a/BaS_GNU/sources/exceptions.S +++ b/BaS_GNU/sources/exceptions.S @@ -4,23 +4,23 @@ #include "startcf.h" -.extern __Bas_base -.extern __SUP_SP -.extern __BOOT_FLASH -.extern __RAMBAR0 -.extern _rt_cacr -.extern _rt_mod -.extern _rt_ssp -.extern _rt_usp -.extern _rt_vbr -.extern _illegal_instruction -.extern _privileg_violation -.extern _mmutr_miss -.extern __MBAR -.extern __MMUBAR -.extern _video_tlb -.extern _video_sbt -.extern cpusha + .extern __Bas_base + .extern __SUP_SP + .extern __BOOT_FLASH + .extern __RAMBAR0 + .extern _rt_cacr + .extern _rt_mod + .extern _rt_ssp + .extern _rt_usp + .extern _rt_vbr + .extern _illegal_instruction + .extern _privileg_violation + .extern _mmutr_miss + .extern __MBAR + .extern __MMUBAR + .extern _video_tlb + .extern _video_sbt + .extern cpusha /* Register read/write macros */ #define MCF_MMU_MMUCR __MMUBAR From 14f36c9510976e507ad033a1908cc3e68783381c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Fri, 19 Oct 2012 21:09:56 +0000 Subject: [PATCH 139/276] Added comment about the NVRAM. --- BaS_GNU/sources/BaS.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 0dea05c..ec62973 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -56,7 +56,7 @@ void BaS(void) { for (i = 0; i < 64; i++) { - * (uint8_t *) 0xffff8963 = MCF_PSC3_PSCRB_8BIT; /* TODO: what are we doing here ? */ + * (uint8_t *) 0xffff8963 = MCF_PSC3_PSCRB_8BIT; /* Copy the NVRAM data from the PIC to the FPGA */ } } From ced6b5dc9f3fc442b605aff928d6d49d4ee14e06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Fri, 19 Oct 2012 21:43:11 +0000 Subject: [PATCH 140/276] Fixed inverted BaS source and destination. --- BaS_GNU/sources/sysinit.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index c82e33c..adb6af7 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -711,10 +711,10 @@ void initialize_hardware(void) { do { - *src++ = *dst++; - *src++ = *dst++; - *src++ = *dst++; - *src++ = *dst++; + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; } while (dst < &bas_end); /* clear all addresses touched during copy from all cache lines */ From 74af74a3e974b4a3bf8be1747b9e3fe468b4a428 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 20 Oct 2012 06:40:10 +0000 Subject: [PATCH 141/276] --- BaS_GNU/.project | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/BaS_GNU/.project b/BaS_GNU/.project index 66bab9e..2f0d4f5 100644 --- a/BaS_GNU/.project +++ b/BaS_GNU/.project @@ -25,6 +25,10 @@ org.eclipse.cdt.make.core.buildCommand make + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/BaS_GNU} + org.eclipse.cdt.make.core.contents org.eclipse.cdt.make.core.activeConfigSettings From 03daa59aaa59b2a19db187c9dd84905884a096fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Sat, 20 Oct 2012 14:00:11 +0000 Subject: [PATCH 142/276] Clean up CACR initialization. --- BaS_GNU/sources/cache.c | 3 --- BaS_GNU/sources/mmu.S | 7 ------- BaS_GNU/sources/startcf.S | 10 +++++++--- BaS_GNU/sources/supervisor.S | 3 --- BaS_GNU/sources/sysinit.c | 8 -------- 5 files changed, 7 insertions(+), 24 deletions(-) diff --git a/BaS_GNU/sources/cache.c b/BaS_GNU/sources/cache.c index 5ebd2ea..1cb9f9b 100644 --- a/BaS_GNU/sources/cache.c +++ b/BaS_GNU/sources/cache.c @@ -81,9 +81,6 @@ void clear_caches(void) " move.l d0,a0\n\t" " cmpi.w #4,d0 | all ways?\n\t" " bne cfa_setloop | no->\n\t" - " nop\n\t" - " move.l _rt_cacr,d0 | get cacr shadow register\n\t" - " movec d0,cacr | set old value\n\t" " move.l (sp)+,d2\n\t" " move.w d2,sr | restore previous interrupt mask\n\t" /* input */ : diff --git a/BaS_GNU/sources/mmu.S b/BaS_GNU/sources/mmu.S index d268e70..e1e1b11 100644 --- a/BaS_GNU/sources/mmu.S +++ b/BaS_GNU/sources/mmu.S @@ -82,9 +82,6 @@ _mmu_init: clr.l d0 movec d0,ASID // ASID allways 0 move.l d0,_rt_asid // sichern - movec d0,cacr // cache aus - move.l d0,_rt_cacr // sichern - nop move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff movec d0,ACR0 @@ -171,10 +168,6 @@ _mmu_init: move.l d1,MCF_MMU_MMUDR move.l d3,MCF_MMU_MMUOR // setzen instr */ - move.l #0xa10ca120,d0 - move.l d0,_rt_cacr // sichern - movec d0,cacr - nop rts /* diff --git a/BaS_GNU/sources/startcf.S b/BaS_GNU/sources/startcf.S index 646c693..c0f9fdb 100644 --- a/BaS_GNU/sources/startcf.S +++ b/BaS_GNU/sources/startcf.S @@ -33,10 +33,14 @@ warmstart: /* set stack pointer to end of SRAM1 */ lea __SUP_SP,a7 - /* instruction cache on */ - move.l #0x000C8100,d0 + /* Initialize the processor caches. + * The instruction cache is fully enabled. + * The data cache is enabled, but cache-inhibited by default. + * Later, the MMU will fully activate the data cache for specific areas. + * It is important to enable both caches now, otherwise cpushl would hang. + */ + move.l #0xa50c8120,d0 movec d0,cacr - nop /* initialize any hardware specific issues */ bra _initialize_hardware diff --git a/BaS_GNU/sources/supervisor.S b/BaS_GNU/sources/supervisor.S index b728362..9afa84a 100644 --- a/BaS_GNU/sources/supervisor.S +++ b/BaS_GNU/sources/supervisor.S @@ -573,9 +573,6 @@ cfa_setloop: move.l d0,a0 cmpi.w #4,d0 // all ways? bne cfa_setloop // nein-> - nop - move.l _rt_cacr,d0 // holen - movec d0,cacr // setzen move.w d2,sr // alte interrupt maske movem.l (a7),d0-d2/a0 // register zur�ck lea 16(a7),a7 diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index adb6af7..fb01cb8 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -675,14 +675,6 @@ void initialize_hardware(void) { uint32_t *dst; /* destination address to copy to */ uint32_t *jmp; /* address of BaS() routine to jmp at after copy */ - __asm__ __volatile__( - "move.l #0x000C8120,D0\n\t" - "move.l D0,_rt_cacr\n\t" - "movec D0,CACR\n\t" - "nop\n\t" - : : : "d0", "memory" - ); - init_gpio(); init_serial(); init_slt(); From 5dcb6cf41d4eec99167859340ed3e8823f54abb6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Sat, 20 Oct 2012 14:29:57 +0000 Subject: [PATCH 143/276] Fixed cache management. --- BaS_GNU/sources/BaS.c | 4 ++ BaS_GNU/sources/cache.c | 71 ++---------------------------------- BaS_GNU/sources/cache.h | 3 +- BaS_GNU/sources/supervisor.S | 28 +++----------- BaS_GNU/sources/sysinit.c | 5 +-- 5 files changed, 16 insertions(+), 95 deletions(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index ec62973..158dd14 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -7,6 +7,7 @@ #include "MCF5475.h" #include "MCF5475_SLT.h" #include "startcf.h" +#include "cache.h" extern uint32_t Bas_base[]; extern uint8_t tos_base[]; @@ -77,6 +78,9 @@ void BaS(void) } } + /* we have copied a code area, so flush the caches */ + flush_and_invalidate_caches(); + #ifdef _NOT_USED_ /* * set the NVRAM checksum as invalid diff --git a/BaS_GNU/sources/cache.c b/BaS_GNU/sources/cache.c index 1cb9f9b..940b7e5 100644 --- a/BaS_GNU/sources/cache.c +++ b/BaS_GNU/sources/cache.c @@ -3,70 +3,9 @@ */ #include "cache.h" - -void flushDataCacheRegion(void *adr, uint32_t length) -{ - __asm__ - ( - " move.l %0,d0 | start address\n\t" - " move.l d0,a1\n\t" - " add.l %1,a1 | add length\n\t" - " clr.l d1 | way counter\n\t" - " and.l #0xfffffff0,d0 | align start address\n\t" - ".flush_dregion_way_loop:\n\t" - " move.l d0,a0 | initialize a0\n\t" - " add.l d1,a0 | set way index\n\t" - ".flush_dregion_loop:\n\t" - " cpushl DC,(a0) | flush and invalidate the cache line\n\t" - " add.l #0x10,a0 | increment to next cache line\n\t" - " cmp.l a0,a1 | done with region?\n\t" - " bgt .flush_dregion_loop\n\t" - " addq.l #1,d1 | increment way counter\n\t" - " addq.l #1,a1 | update stop address to reflect new way value\n\t" - " cmp.l #4,d1 | cache way\n\t" - " bne .flush_dregion_way_loop\n\t" - /* output */ : - /* input */ : "g" (adr), - "g" (length) - /* clobber */: "d0", "d1", "a0", "a1" - ); -} - -void flushInstructionCacheRegion(void *adr, uint32_t length) -{ - __asm__ - ( - " move.l %0,d0 | start address\n\t" - " move.l d0,a1\n\t" - " add.l %1,a1 | add length\n\t" - " clr.l d1 | way counter\n\t" - " and.l #0xfffffff0,d0 | align start address\n\t" - ".flush_iregion_way_loop:\n\t" - " move.l d0,a0 | initialize a0\n\t" - " add.l d1,a0 | set way index\n\t" - ".flush_iregion_loop:\n\t" - " cpushl IC,(a0) | flush and invalidate the cache line\n\t" - " add.l #0x10,a0 | increment to next cache line\n\t" - " cmp.l a0,a1 | done with region?\n\t" - " bgt .flush_iregion_loop\n\t" - " addq.l #1,d1 | increment way counter\n\t" - " addq.l #1,a1 | update stop address to reflect new way value\n\t" - " cmp.l #4,d1 | cache way\n\t" - " bne .flush_iregion_way_loop\n\t" - /* output */ : - /* input */ : "g" (adr), - "g" (length) - /* clobber */: "d0", "d1", "a0", "a1" - ); -} - -void clear_caches(void) +void flush_and_invalidate_caches(void) { __asm__ ( - "cpusha:\n\t" - " move sr,d2\n\t" - " move.l d2,-(sp)\n\t" - " move #0x2700,sr | no interrupts\n\t" " clr.l d0\n\t" " clr.l d1\n\t" " move.l d0,a0\n\t" @@ -75,16 +14,14 @@ void clear_caches(void) " lea 0x10(a0),a0 | index+1\n\t" " addq.l #1,d1 | index+1\n\t" " cmpi.w #512,d1 | all sets?\n\t" - " bne cfa_setloop | no->\n\t" + " bne.s cfa_setloop | no->\n\t" " clr.l d1\n\t" " addq.l #1,d0\n\t" " move.l d0,a0\n\t" " cmpi.w #4,d0 | all ways?\n\t" - " bne cfa_setloop | no->\n\t" - " move.l (sp)+,d2\n\t" - " move.w d2,sr | restore previous interrupt mask\n\t" + " bne.s cfa_setloop | no->\n\t" /* input */ : /* output */ : - /* clobber */ : "d0", "d1", "d2", "a0" + /* clobber */ : "d0", "d1", "a0" ); } diff --git a/BaS_GNU/sources/cache.h b/BaS_GNU/sources/cache.h index 8e306d6..a8d788d 100644 --- a/BaS_GNU/sources/cache.h +++ b/BaS_GNU/sources/cache.h @@ -3,7 +3,6 @@ #include -extern void flushDataCacheRegion(void *adr, uint32_t length); -extern void flushInstructionCacheRegion(void *adr, uint32_t length); +extern void flush_and_invalidate_caches(void); #endif /* _CACHE_H_ */ diff --git a/BaS_GNU/sources/supervisor.S b/BaS_GNU/sources/supervisor.S index 9afa84a..7988122 100644 --- a/BaS_GNU/sources/supervisor.S +++ b/BaS_GNU/sources/supervisor.S @@ -9,6 +9,7 @@ .extern _rt_ssp; .extern _rt_usp; .extern ___MMUBAR +.extern _flush_and_invalidate_caches /* Register read/write macros */ #define MCF_MMU_MMUCR __MMUBAR @@ -554,29 +555,10 @@ pv_f_d16pc: //***************************************************** cpusha: lea -16(a7),a7 - movem.l d0-d2/a0,(a7) // register sichern - move sr,d2 - nop - move #0x2700,sr // no interrupts - - clr.l d0 - clr.l d1 - move.l d0,a0 -cfa_setloop: - cpushl bc,(a0) // flush - lea 0x10(a0),a0 // index+1 - addq.l #1,d1 // index+1 - cmpi.w #512,d1 // alle sets? - bne cfa_setloop // nein-> - clr.l d1 - addq.l #1,d0 - move.l d0,a0 - cmpi.w #4,d0 // all ways? - bne cfa_setloop // nein-> - move.w d2,sr // alte interrupt maske - movem.l (a7),d0-d2/a0 // register zur�ck - lea 16(a7),a7 - + movem.l d0-d1/a0-a1,(a7) // backup C trash registers + jsr _flush_and_invalidate_caches + movem.l (a7),d0-d1/a0-a1 // restore C trash registers + lea 16(a7),a7 rts //*******************************************************33 diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index fb01cb8..54665ad 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -709,9 +709,8 @@ void initialize_hardware(void) { *dst++ = *src++; } while (dst < &bas_end); - /* clear all addresses touched during copy from all cache lines */ - flushDataCacheRegion(&BaS, (uint32_t) (&bas_end - &BaS)); - flushInstructionCacheRegion(&BaS, (uint32_t) (&bas_end - &BaS)); + /* we have copied a code area, so flush the caches */ + flush_and_invalidate_caches(); __asm__ __volatile__( " move.l %0,a3 | calculated start address\n\t" From a4d56a849789d56eb9b2db840948fcbf737aef8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Sat, 20 Oct 2012 15:03:23 +0000 Subject: [PATCH 144/276] Removed useless .code section. --- BaS_GNU/bas.lk.S | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/BaS_GNU/bas.lk.S b/BaS_GNU/bas.lk.S index 41f4503..e970f5d 100644 --- a/BaS_GNU/bas.lk.S +++ b/BaS_GNU/bas.lk.S @@ -58,13 +58,9 @@ SECTIONS { __SYS_SRAM = ABSOLUTE(0xFF010000); __SYS_SRAM_SIZE = ABSOLUTE(0x00008000); - .code ___BOOT_FLASH : - { - objs/startcf.o - } > flash - - .text : + .text ___BOOT_FLASH : { + objs/startcf.o(.text) objs/sysinit.o(.text) objs/init_fpga.o(.text) objs/sd_card.o(.text) From f18929b8a55a2a3a34b8385fdddb063fe29e91fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Sat, 20 Oct 2012 15:50:36 +0000 Subject: [PATCH 145/276] Clean up BaS linker script symbols. --- BaS_GNU/bas.lk.S | 6 ++++-- BaS_GNU/sources/sysinit.c | 24 +++++++++++++++++------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/BaS_GNU/bas.lk.S b/BaS_GNU/bas.lk.S index e970f5d..2b7b7f3 100644 --- a/BaS_GNU/bas.lk.S +++ b/BaS_GNU/bas.lk.S @@ -70,7 +70,6 @@ SECTIONS { objs/supervisor.o(.text) objs/ewf.o(.text) objs/illegal_instruction.o(.text) - _bas = .; } > flash .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) @@ -78,5 +77,8 @@ SECTIONS { objs/BaS.o(.text) _bas_end = ABSOLUTE(.); } > ram - + + __BAS_LMA = LOADADDR(.bas); + __BAS_VMA = ADDR(.bas); + __BAS_SIZE = SIZEOF(.bas); } \ No newline at end of file diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 54665ad..28b28ff 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -665,13 +665,21 @@ livo: uart_out_word(0x0a0d); } -void initialize_hardware(void) { - extern uint32_t bas; /* source address to copy bas from (from linker script) FIXME: beware of possible alignment */ - extern uint32_t bas_end; /* end of BaS code to copy (from linker script) */ - extern uint32_t BaS; /* BaS routine to jump to after copy */ +/* Symbols from the linker script */ +extern uint8_t _BAS_LMA[]; +#define BAS_LMA ((uint32_t)_BAS_LMA) /* where the BaS is stored in flash */ + +extern uint8_t _BAS_VMA[]; +#define BAS_VMA ((uint32_t)_BAS_VMA) /* where the BaS is run in RAM */ + +extern uint8_t _BAS_SIZE[]; +#define BAS_SIZE ((uint32_t)_BAS_SIZE) /* size of the BaS, in bytes */ + +void initialize_hardware(void) { /* used in copy loop */ uint32_t *src; /* src address to read from flash */ + uint32_t *end; /* end address to read from flash */ uint32_t *dst; /* destination address to copy to */ uint32_t *jmp; /* address of BaS() routine to jmp at after copy */ @@ -698,16 +706,18 @@ void initialize_hardware(void) { } /* copy the BaS code contained in flash to its final location */ - src = (uint32_t *)&bas; - dst = jmp = (uint32_t *)&BaS; + src = (uint32_t *)BAS_LMA; + end = (uint32_t *)(BAS_LMA + BAS_SIZE); + dst = jmp = (uint32_t *)BAS_VMA; + /* FIXME: beware of possible alignment */ do { *dst++ = *src++; *dst++ = *src++; *dst++ = *src++; *dst++ = *src++; - } while (dst < &bas_end); + } while (src < end); /* we have copied a code area, so flush the caches */ flush_and_invalidate_caches(); From dbae718f3144ee9e6c8ade1926580128fc44aae6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Sat, 20 Oct 2012 15:59:03 +0000 Subject: [PATCH 146/276] Cleaned up jump into the BaS. --- BaS_GNU/sources/sysinit.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 28b28ff..c0241e6 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -722,11 +722,7 @@ void initialize_hardware(void) { /* we have copied a code area, so flush the caches */ flush_and_invalidate_caches(); - __asm__ __volatile__( - " move.l %0,a3 | calculated start address\n\t" - " jmp (a3) | go! \n\t" - /* output */ : - /* input */ : "g" (jmp) - /* clobber */: "a3", "memory" - ); + /* jump into the BaS in RAM */ + extern void BaS(void); + BaS(); } From dd865d4eb2ea345bd4b6b6dd628032c5350452f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 20 Oct 2012 17:10:07 +0000 Subject: [PATCH 147/276] renamed according to Vincent's suggestion --- BaS_GNU/bas.lk.in | 84 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 BaS_GNU/bas.lk.in diff --git a/BaS_GNU/bas.lk.in b/BaS_GNU/bas.lk.in new file mode 100644 index 0000000..2b7b7f3 --- /dev/null +++ b/BaS_GNU/bas.lk.in @@ -0,0 +1,84 @@ +MEMORY { + flash (RX) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00200000 + ram (WX) : ORIGIN = 0x1FE00000, LENGTH = 0x00100000 /* target to copy BaS to */ +} + +SECTIONS { + _Bas_base = ABSOLUTE(0x1FE00000); + _tos_base = ABSOLUTE(0xe00000); + + /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */ + ___BOOT_FLASH = ABSOLUTE(TARGET_ADDRESS); + ___BOOT_FLASH_SIZE = ABSOLUTE(0x00800000); + /* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */ + ___SDRAM = ABSOLUTE(0x00000000); + ___SDRAM_SIZE = ABSOLUTE(0x20000000); + + /* VIDEO RAM BASIS */ + __VRAM = ABSOLUTE(0x60000000); + + /* Memory mapped registers */ + __MBAR = ABSOLUTE(0xFF000000); + __MMUBAR = ABSOLUTE(0xFF040000); + + /* + * 4KB on-chip Core SRAM0: -> exception table and exception stack + */ + __RAMBAR0 = ABSOLUTE(0xFF100000); + __RAMBAR0_SIZE = ABSOLUTE(0x00001000); + + __SUP_SP = ABSOLUTE(__RAMBAR0 + __RAMBAR0_SIZE - 4); + + /* 4KB on-chip Core SRAM1: -> modified code */ + __RAMBAR1 = ABSOLUTE(0xFF101000); + __RAMBAR1_SIZE = ABSOLUTE(0x00001000); + + /* system variables */ + + /* RAMBAR0 0 to 0x7FF -> exception vectors */ + _rt_mod = __RAMBAR0 + 0x800; + _rt_ssp = __RAMBAR0 + 0x804; + _rt_usp = __RAMBAR0 + 0x808; + _rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */ + _rt_cacr = __RAMBAR0 + 0x810; /* 002 */ + _rt_asid = __RAMBAR0 + 0x814; /* 003 */ + _rt_acr0 = __RAMBAR0 + 0x818; /* 004 */ + _rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */ + _rt_acr2 = __RAMBAR0 + 0x820; /* 006 */ + _rt_acr3 = __RAMBAR0 + 0x824; /* 007 */ + _rt_mmubar = __RAMBAR0 + 0x828; /* 008 */ + _rt_sr = __RAMBAR0 + 0x82c; + _d0_save = __RAMBAR0 + 0x830; + _a7_save = __RAMBAR0 + 0x834; + _video_tlb = __RAMBAR0 + 0x838; + _video_sbt = __RAMBAR0 + 0x83C; + _rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */ + + /* 32KB on-chip System SRAM */ + __SYS_SRAM = ABSOLUTE(0xFF010000); + __SYS_SRAM_SIZE = ABSOLUTE(0x00008000); + + .text ___BOOT_FLASH : + { + objs/startcf.o(.text) + objs/sysinit.o(.text) + objs/init_fpga.o(.text) + objs/sd_card.o(.text) + objs/cache.o(.text) + objs/mmu.o(.text) + objs/exceptions.o(.text) + objs/supervisor.o(.text) + objs/ewf.o(.text) + objs/illegal_instruction.o(.text) + } > flash + + .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) + { + objs/BaS.o(.text) + _bas_end = ABSOLUTE(.); + } > ram + + __BAS_LMA = LOADADDR(.bas); + __BAS_VMA = ADDR(.bas); + __BAS_SIZE = SIZEOF(.bas); +} \ No newline at end of file From 0321dd59e96fca32582c3338397d08d4c41a82c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 20 Oct 2012 17:34:12 +0000 Subject: [PATCH 148/276] renamed linker script --- BaS_GNU/Makefile | 2 +- BaS_GNU/bas.lk.S | 84 ------------------------------------------------ 2 files changed, 1 insertion(+), 85 deletions(-) delete mode 100644 BaS_GNU/bas.lk.S diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 5f2d0b0..d790abf 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -28,7 +28,7 @@ MAPFILE=bas.map # Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC) LDCFILE=bas.lk -LDCSRC=bas.lk.S +LDCSRC=bas.lk.in # this Makefile can create the BaS to flash or an arbitrary ram address (for BDM debugging). See # below for the definition of TARGET_ADDRESS diff --git a/BaS_GNU/bas.lk.S b/BaS_GNU/bas.lk.S deleted file mode 100644 index 2b7b7f3..0000000 --- a/BaS_GNU/bas.lk.S +++ /dev/null @@ -1,84 +0,0 @@ -MEMORY { - flash (RX) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00200000 - ram (WX) : ORIGIN = 0x1FE00000, LENGTH = 0x00100000 /* target to copy BaS to */ -} - -SECTIONS { - _Bas_base = ABSOLUTE(0x1FE00000); - _tos_base = ABSOLUTE(0xe00000); - - /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */ - ___BOOT_FLASH = ABSOLUTE(TARGET_ADDRESS); - ___BOOT_FLASH_SIZE = ABSOLUTE(0x00800000); - /* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */ - ___SDRAM = ABSOLUTE(0x00000000); - ___SDRAM_SIZE = ABSOLUTE(0x20000000); - - /* VIDEO RAM BASIS */ - __VRAM = ABSOLUTE(0x60000000); - - /* Memory mapped registers */ - __MBAR = ABSOLUTE(0xFF000000); - __MMUBAR = ABSOLUTE(0xFF040000); - - /* - * 4KB on-chip Core SRAM0: -> exception table and exception stack - */ - __RAMBAR0 = ABSOLUTE(0xFF100000); - __RAMBAR0_SIZE = ABSOLUTE(0x00001000); - - __SUP_SP = ABSOLUTE(__RAMBAR0 + __RAMBAR0_SIZE - 4); - - /* 4KB on-chip Core SRAM1: -> modified code */ - __RAMBAR1 = ABSOLUTE(0xFF101000); - __RAMBAR1_SIZE = ABSOLUTE(0x00001000); - - /* system variables */ - - /* RAMBAR0 0 to 0x7FF -> exception vectors */ - _rt_mod = __RAMBAR0 + 0x800; - _rt_ssp = __RAMBAR0 + 0x804; - _rt_usp = __RAMBAR0 + 0x808; - _rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */ - _rt_cacr = __RAMBAR0 + 0x810; /* 002 */ - _rt_asid = __RAMBAR0 + 0x814; /* 003 */ - _rt_acr0 = __RAMBAR0 + 0x818; /* 004 */ - _rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */ - _rt_acr2 = __RAMBAR0 + 0x820; /* 006 */ - _rt_acr3 = __RAMBAR0 + 0x824; /* 007 */ - _rt_mmubar = __RAMBAR0 + 0x828; /* 008 */ - _rt_sr = __RAMBAR0 + 0x82c; - _d0_save = __RAMBAR0 + 0x830; - _a7_save = __RAMBAR0 + 0x834; - _video_tlb = __RAMBAR0 + 0x838; - _video_sbt = __RAMBAR0 + 0x83C; - _rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */ - - /* 32KB on-chip System SRAM */ - __SYS_SRAM = ABSOLUTE(0xFF010000); - __SYS_SRAM_SIZE = ABSOLUTE(0x00008000); - - .text ___BOOT_FLASH : - { - objs/startcf.o(.text) - objs/sysinit.o(.text) - objs/init_fpga.o(.text) - objs/sd_card.o(.text) - objs/cache.o(.text) - objs/mmu.o(.text) - objs/exceptions.o(.text) - objs/supervisor.o(.text) - objs/ewf.o(.text) - objs/illegal_instruction.o(.text) - } > flash - - .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) - { - objs/BaS.o(.text) - _bas_end = ABSOLUTE(.); - } > ram - - __BAS_LMA = LOADADDR(.bas); - __BAS_VMA = ADDR(.bas); - __BAS_SIZE = SIZEOF(.bas); -} \ No newline at end of file From b5d4501fe55490bd6586fc7c8d530eb5cbd97fb9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 20 Oct 2012 18:05:26 +0000 Subject: [PATCH 149/276] --- BaS_GNU/.project | 4 ---- 1 file changed, 4 deletions(-) diff --git a/BaS_GNU/.project b/BaS_GNU/.project index 2f0d4f5..66bab9e 100644 --- a/BaS_GNU/.project +++ b/BaS_GNU/.project @@ -25,10 +25,6 @@ org.eclipse.cdt.make.core.buildCommand make - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/BaS_GNU} - org.eclipse.cdt.make.core.contents org.eclipse.cdt.make.core.activeConfigSettings From 608a84a353e61b4c723ed6e9c088b8bf01f417fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 21 Oct 2012 05:51:23 +0000 Subject: [PATCH 150/276] --- BaS_GNU/.cproject | 20 ++++++++++---------- BaS_GNU/.project | 4 ++++ 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/BaS_GNU/.cproject b/BaS_GNU/.cproject index 293c3ff..096d23a 100644 --- a/BaS_GNU/.cproject +++ b/BaS_GNU/.cproject @@ -7,7 +7,7 @@ - + @@ -22,7 +22,7 @@ @@ -38,30 +38,30 @@ - + - + - + diff --git a/BaS_GNU/.project b/BaS_GNU/.project index 66bab9e..2f0d4f5 100644 --- a/BaS_GNU/.project +++ b/BaS_GNU/.project @@ -25,6 +25,10 @@ org.eclipse.cdt.make.core.buildCommand make + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc:/BaS_GNU} + org.eclipse.cdt.make.core.contents org.eclipse.cdt.make.core.activeConfigSettings From eaabb211dbd341106de6cfaf8890eb2cbc896595 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 21 Oct 2012 19:12:40 +0000 Subject: [PATCH 151/276] modified Makefile to generate an elf file that bdmctrl understands. added mcf5474.bdm to initialize firebee and flash (doesn't work yet for unknown reason) --- BaS_GNU/Makefile | 2 ++ BaS_GNU/mcf5474.bdm | 41 +++++++++++++++++++++++++++++++++++++++++ BaS_GNU/sources/mmu.S | 4 ++-- 3 files changed, 45 insertions(+), 2 deletions(-) create mode 100755 BaS_GNU/mcf5474.bdm diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index d790abf..12550cd 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -17,6 +17,7 @@ TCPREFIX=m68k-atari-mint- CC=$(TCPREFIX)gcc LD=$(TCPREFIX)ld CPP=$(TCPREFIX)cpp +OBJCOPY=$(TCPREFIX)objcopy INCLUDE=-Iinclude CFLAGS=-mcpu=5474 -Wall -Wno-multichar -Os -fomit-frame-pointer @@ -68,6 +69,7 @@ $(RAM_EXEC): TARGET_ADDRESS=0x01000000 $(FLASH_EXEC) $(RAM_EXEC): $(STRT_OBJ) $(OBJS) $(CPP) -P -DTARGET_ADDRESS=$(TARGET_ADDRESS) $(LDCSRC) -o $(LDCFILE) $(LD) --oformat srec -Map $(MAPFILE) --cref -T $(LDCFILE) -s -o $@ + objcopy -I srec -O elf32-big --alt-machine-code 4 $@ $@.elf # compile init_fpga with -mbitfield for testing purposes $(OBJDIR)/init_fpga.o: CFLAGS += -mbitfield diff --git a/BaS_GNU/mcf5474.bdm b/BaS_GNU/mcf5474.bdm new file mode 100755 index 0000000..ae597c2 --- /dev/null +++ b/BaS_GNU/mcf5474.bdm @@ -0,0 +1,41 @@ +#!/usr/local/bin/bdmctrl +# +# firebee board initialization for bdmctrl +# +open $1 +reset + +# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29 +flash 0xE0000000 flash29 +# do not flash yet. First check if board can be initialized correctly + +# set VBR +write-ctrl 0x0801 0x00000000 + +# Turn on MBAR at 0xFF00_0000 +write-ctrl 0x0C0F 0xFF000000 + +# Turn on RAMBAR0 at address FF10_0000 +write-ctrl 0x0C04 0xFF100035 + +# Turn on RAMBAR1 at address FF10_1000 +write-ctrl 0x0C05 0xFF101035 + +# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +write 0xFF000500 0xE0000000 4 +write 0xFF000508 0x00001180 4 # 16-bit port +write 0xFF000504 0x007F0001 4 + +# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +write 0xFF000004 0x000002AA 4 # SDRAMDS configuration +write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +write 0xFF000108 0x53722938 4 # SDCFG1 +write 0xFF00010C 0x24330000 4 # SDCFG2 + +wait +# load -v ram.s19 # unfortunately, this seems to work only with elf files +load -v bas.s19.elf + diff --git a/BaS_GNU/sources/mmu.S b/BaS_GNU/sources/mmu.S index e1e1b11..2485c92 100644 --- a/BaS_GNU/sources/mmu.S +++ b/BaS_GNU/sources/mmu.S @@ -130,8 +130,8 @@ _mmu_init: move.l d3,MCF_MMU_MMUOR // MMU update instruction move.l #0x2000,d0 - move.l d0,_video_tlb // setze page als video page - clr.l _video_sbt // zeit l�schen + move.l d0,_video_tlb // set page as video page + clr.l _video_sbt // clear time //------------------------------------------------------------------------------------- // 00e0'0000 locked move.l #0x00e00000|std_mmutr,d0 From c415faf0d59b6e69605bd916b4adccf1e4b93923 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 21 Oct 2012 20:26:13 +0000 Subject: [PATCH 152/276] --- BaS_GNU/mcf5474.bdm | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/mcf5474.bdm b/BaS_GNU/mcf5474.bdm index ae597c2..66f0f47 100755 --- a/BaS_GNU/mcf5474.bdm +++ b/BaS_GNU/mcf5474.bdm @@ -37,5 +37,5 @@ write 0xFF00010C 0x24330000 4 # SDCFG2 wait # load -v ram.s19 # unfortunately, this seems to work only with elf files -load -v bas.s19.elf +load -v bas.s19.elf # TODO: bdmctrl tries to flash but doesn't succed. Don't know why yet From e06546aa142c595b78de56d961fb10b0b1784433 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Sun, 21 Oct 2012 20:59:32 +0000 Subject: [PATCH 153/276] Backup CACR into _rt_cacr. --- BaS_GNU/sources/startcf.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/BaS_GNU/sources/startcf.S b/BaS_GNU/sources/startcf.S index c0f9fdb..a6722ca 100644 --- a/BaS_GNU/sources/startcf.S +++ b/BaS_GNU/sources/startcf.S @@ -41,6 +41,8 @@ warmstart: */ move.l #0xa50c8120,d0 movec d0,cacr + andi.l #0xfefbfeff,d0 // Clear invalidate bits + move.l d0,_rt_cacr /* initialize any hardware specific issues */ bra _initialize_hardware From d55945e27ac896213028bd92e6aef0a3021532f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Sun, 21 Oct 2012 21:00:32 +0000 Subject: [PATCH 154/276] Fixed missing backup registers. --- BaS_GNU/sources/exceptions.S | 4 ++++ BaS_GNU/sources/mmu.S | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S index 1822c05..a03698b 100644 --- a/BaS_GNU/sources/exceptions.S +++ b/BaS_GNU/sources/exceptions.S @@ -204,6 +204,8 @@ irq_end: .text _vec_init: + move.l a2,-(sp) // Backup registers + mov3q.l #-1,_rt_mod // rt_mod auf super clr.l _rt_ssp clr.l _rt_usp @@ -286,6 +288,8 @@ no_protect_vectors: //timer 1 vectors lea timer0(pc),a1 move.l a1,0x1f8(a0) + + move.l (sp)+,a2 // Restore registers rts /* * exception vector routines diff --git a/BaS_GNU/sources/mmu.S b/BaS_GNU/sources/mmu.S index 2485c92..7b9d53d 100644 --- a/BaS_GNU/sources/mmu.S +++ b/BaS_GNU/sources/mmu.S @@ -79,6 +79,9 @@ .text _mmu_init: + move.l d3,-(sp) // Backup registers + move.l d2,-(sp) + clr.l d0 movec d0,ASID // ASID allways 0 move.l d0,_rt_asid // sichern @@ -168,6 +171,8 @@ _mmu_init: move.l d1,MCF_MMU_MMUDR move.l d3,MCF_MMU_MMUOR // setzen instr */ + move.l (sp)+,d2 // Restore registers + move.l (sp)+,d3 rts /* From b28027ce5d26a28e2d9d56c66eb005c2f0e635f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Sun, 21 Oct 2012 23:14:09 +0000 Subject: [PATCH 155/276] Fixed FireTOS loader using minimal initialization. --- BaS_GNU/sources/sysinit.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index c0241e6..4d0c849 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -683,6 +683,27 @@ void initialize_hardware(void) { uint32_t *dst; /* destination address to copy to */ uint32_t *jmp; /* address of BaS() routine to jmp at after copy */ + /* Test for FireTOS switch: DIP switch #5 up */ + if (!(DIP_SWITCH & (1 << 6))) { + /* Minimal hardware initialization */ + init_gpio(); + init_fbcs(); + init_ddram(); + init_fpga(); + + /* FireTOS seems to have trouble to initialize the ST-RAM by itself, so... */ + /* Validate ST RAM */ + * (volatile uint32_t *) 0x42e = 0x00e00000; /* phystop TOS system variable */ + * (volatile uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */ + * (volatile uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */ + * (volatile uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */ + + /* Jump into FireTOS */ + typedef void void_func(void); + void_func* FireTOS = (void_func*)0xe0400000; + FireTOS(); + } + init_gpio(); init_serial(); init_slt(); From ea73b75bb778eb71143599c2d80f146c2486b2c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 22 Oct 2012 05:58:26 +0000 Subject: [PATCH 156/276] copy everything except the early initialization routines to RAM --- BaS_GNU/bas.lk.in | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/BaS_GNU/bas.lk.in b/BaS_GNU/bas.lk.in index 2b7b7f3..3fb931b 100644 --- a/BaS_GNU/bas.lk.in +++ b/BaS_GNU/bas.lk.in @@ -62,6 +62,12 @@ SECTIONS { { objs/startcf.o(.text) objs/sysinit.o(.text) + } > flash + + .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) + { + objs/BaS.o(.text) + objs/init_fpga.o(.text) objs/sd_card.o(.text) objs/cache.o(.text) @@ -70,11 +76,7 @@ SECTIONS { objs/supervisor.o(.text) objs/ewf.o(.text) objs/illegal_instruction.o(.text) - } > flash - .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) - { - objs/BaS.o(.text) _bas_end = ABSOLUTE(.); } > ram From 19d5ae9f420a799d92136bd921631c7f4bb77bd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 22 Oct 2012 07:36:41 +0000 Subject: [PATCH 157/276] copy exception handlers to RAM together with BaS() --- BaS_GNU/bas.lk.in | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/bas.lk.in b/BaS_GNU/bas.lk.in index 3fb931b..d96aff5 100644 --- a/BaS_GNU/bas.lk.in +++ b/BaS_GNU/bas.lk.in @@ -62,13 +62,14 @@ SECTIONS { { objs/startcf.o(.text) objs/sysinit.o(.text) + objs/init_fpga.o(.text) + } > flash .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) { objs/BaS.o(.text) - - objs/init_fpga.o(.text) + # put other routines into the same segment (RAM) as BaS.o objs/sd_card.o(.text) objs/cache.o(.text) objs/mmu.o(.text) From b3e8ae8914bdc1dec918e4d8c739444dbf31670c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 22 Oct 2012 07:45:24 +0000 Subject: [PATCH 158/276] leave chaches.o in flash (called from sysinit.o) --- BaS_GNU/bas.lk.in | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/BaS_GNU/bas.lk.in b/BaS_GNU/bas.lk.in index d96aff5..23d3ca4 100644 --- a/BaS_GNU/bas.lk.in +++ b/BaS_GNU/bas.lk.in @@ -63,7 +63,7 @@ SECTIONS { objs/startcf.o(.text) objs/sysinit.o(.text) objs/init_fpga.o(.text) - + objs/cache.o(.text) } > flash .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) @@ -71,7 +71,6 @@ SECTIONS { objs/BaS.o(.text) # put other routines into the same segment (RAM) as BaS.o objs/sd_card.o(.text) - objs/cache.o(.text) objs/mmu.o(.text) objs/exceptions.o(.text) objs/supervisor.o(.text) From 2ae321d69c7163bcb92cc429be176c2ed0a67439 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 22 Oct 2012 11:08:26 +0000 Subject: [PATCH 159/276] moved .data where it belongs (to RAM) --- BaS_GNU/bas.lk.in | 6 ++++-- BaS_GNU/sources/BaS.c | 1 + BaS_GNU/sources/exceptions.S | 7 ++++++- BaS_GNU/sources/sysinit.c | 2 +- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/BaS_GNU/bas.lk.in b/BaS_GNU/bas.lk.in index 23d3ca4..a65cee5 100644 --- a/BaS_GNU/bas.lk.in +++ b/BaS_GNU/bas.lk.in @@ -69,14 +69,16 @@ SECTIONS { .bas _Bas_base : AT (ADDR(.text) + SIZEOF(.text)) { objs/BaS.o(.text) - # put other routines into the same segment (RAM) as BaS.o + /* put other routines into the same segment (RAM) as BaS.o */ objs/sd_card.o(.text) objs/mmu.o(.text) objs/exceptions.o(.text) objs/supervisor.o(.text) objs/ewf.o(.text) objs/illegal_instruction.o(.text) - + + *(.data) + _bas_end = ABSOLUTE(.); } > ram diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 158dd14..cca2d15 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -51,6 +51,7 @@ void BaS(void) MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; MCF_PSC0_PSCTB_8BIT = 0x0d0a; + MCF_PSC3_PSCTB_8BIT = 0x01; /* request RTC data */ if (MCF_PSC3_PSCRB_8BIT == 0x81) diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S index a03698b..1e3ad21 100644 --- a/BaS_GNU/sources/exceptions.S +++ b/BaS_GNU/sources/exceptions.S @@ -551,7 +551,7 @@ non_acsi_dma: irq6_1: lea MCF_GPIO_PODR_FEC1L,a5 bclr.b #4,(a5) // led on - lea blinker(pc),a5 + lea blinker,a5 addq.l #1,(a5) // +1 move.l (a5),d0 and.l #0x80,d0 @@ -612,8 +612,13 @@ sev_sup6: move.l (a5),12(a7) // hier gehts weiter movem.l (a7),d0/a5 // register zur�ck rts + + .data blinker:.long 0 + + .text + /* * pseudo dma */ */ diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 4d0c849..4d2d7c7 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -356,7 +356,7 @@ void init_PCI(void) { MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16); // Turn on error signaling - MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_TAE * MCF_PCI_PCIICR_REE + 32; + MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_REE + 32; MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE; /* Configure Initiator Windows */ From 0b6249a54aa295347ec045e37ae20cf1e676e939 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 11:27:20 +0000 Subject: [PATCH 160/276] Added comment about the entry point. --- BaS_GNU/bas.lk.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/bas.lk.in b/BaS_GNU/bas.lk.in index a65cee5..7c346d0 100644 --- a/BaS_GNU/bas.lk.in +++ b/BaS_GNU/bas.lk.in @@ -60,7 +60,7 @@ SECTIONS { .text ___BOOT_FLASH : { - objs/startcf.o(.text) + objs/startcf.o(.text) /* this one is the entry point so it must be the first */ objs/sysinit.o(.text) objs/init_fpga.o(.text) objs/cache.o(.text) From 4767f608f3ea69342670d27e93e9d4cc69d9771d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 11:28:34 +0000 Subject: [PATCH 161/276] Fixed newline at end of file. --- BaS_GNU/bas.lk.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/bas.lk.in b/BaS_GNU/bas.lk.in index 7c346d0..52e9abc 100644 --- a/BaS_GNU/bas.lk.in +++ b/BaS_GNU/bas.lk.in @@ -85,4 +85,4 @@ SECTIONS { __BAS_LMA = LOADADDR(.bas); __BAS_VMA = ADDR(.bas); __BAS_SIZE = SIZEOF(.bas); -} \ No newline at end of file +} From 1638a640af045af90608e541f65533153dd60ad6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 11:35:55 +0000 Subject: [PATCH 162/276] Compile with -fno-strict-aliasing to avoid potential trouble. --- BaS_GNU/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 12550cd..313b73a 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -20,7 +20,7 @@ CPP=$(TCPREFIX)cpp OBJCOPY=$(TCPREFIX)objcopy INCLUDE=-Iinclude -CFLAGS=-mcpu=5474 -Wall -Wno-multichar -Os -fomit-frame-pointer +CFLAGS=-mcpu=5474 -Wall -Wno-multichar -Os -fomit-frame-pointer -fno-strict-aliasing SRCDIR=sources OBJDIR=objs From 9facc5c777e3805b80276598e84fd3235b4bb182 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 11:39:37 +0000 Subject: [PATCH 163/276] Fixed warning about depend file not found. --- BaS_GNU/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 313b73a..2716241 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -83,5 +83,4 @@ $(OBJDIR)/%.o:$(SRCDIR)/%.S depend: $(ASRCS) $(CSRCS) $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) > depend -include depend - \ No newline at end of file +-include depend From a9dc69bd90936228955b03d04733781f133731cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 11:42:07 +0000 Subject: [PATCH 164/276] Remove bas.s19.elf on make clean. --- BaS_GNU/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 2716241..dd0ce1b 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -61,7 +61,7 @@ OBJS=$(COBJS) $(AOBJS) .PHONY all: $(FLASH_EXEC) .PHONY ram: $(RAM_EXEC) .PHONY clean: - @ rm -f $(FLASH_EXEC) $(RAM_EXEC) $(STRT_OBJ) $(OBJS) $(MAPFILE) $(LDCFILE) depend + @ rm -f $(FLASH_EXEC) $(FLASH_EXEC).elf $(RAM_EXEC) $(STRT_OBJ) $(OBJS) $(MAPFILE) $(LDCFILE) depend $(FLASH_EXEC): TARGET_ADDRESS=0xe0000000 $(RAM_EXEC): TARGET_ADDRESS=0x01000000 From e7cb7a5460491953988a6c588378b3db8721d4a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 11:47:10 +0000 Subject: [PATCH 165/276] Do not generated dependencies for make clean. --- BaS_GNU/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index dd0ce1b..823fea7 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -83,4 +83,6 @@ $(OBJDIR)/%.o:$(SRCDIR)/%.S depend: $(ASRCS) $(CSRCS) $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) > depend +ifneq (clean,$(MAKECMDGOALS)) -include depend +endif From be7610b9f8ebe54f1944e4ff0f3c1f189ef37e6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 22 Oct 2012 15:08:29 +0000 Subject: [PATCH 166/276] delete ram.s19.elf on "make clean" --- BaS_GNU/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 823fea7..59b61b6 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -61,7 +61,8 @@ OBJS=$(COBJS) $(AOBJS) .PHONY all: $(FLASH_EXEC) .PHONY ram: $(RAM_EXEC) .PHONY clean: - @ rm -f $(FLASH_EXEC) $(FLASH_EXEC).elf $(RAM_EXEC) $(STRT_OBJ) $(OBJS) $(MAPFILE) $(LDCFILE) depend + @ rm -f $(FLASH_EXEC) $(FLASH_EXEC).elf $(RAM_EXEC) $(RAM_EXEC).elf $(STRT_OBJ) $(OBJS)\ + $(MAPFILE) $(LDCFILE) depend $(FLASH_EXEC): TARGET_ADDRESS=0xe0000000 $(RAM_EXEC): TARGET_ADDRESS=0x01000000 From 5ba3ec3373805a111c2b677ff7368c896f64e12a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 18:02:36 +0000 Subject: [PATCH 167/276] Fixed nested comments. --- BaS_GNU/sources/exceptions.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/BaS_GNU/sources/exceptions.S b/BaS_GNU/sources/exceptions.S index 1e3ad21..ded9d78 100644 --- a/BaS_GNU/sources/exceptions.S +++ b/BaS_GNU/sources/exceptions.S @@ -620,7 +620,7 @@ blinker:.long 0 .text /* - * pseudo dma */ + * pseudo dma */ acsi_dma: // atari dma move.l a1,-(a7) @@ -683,7 +683,7 @@ acsi_dma_end: move.l (a7)+,a1 rts /* - * irq 7 = pseudo bus error */ + * irq 7 = pseudo bus error */ irq7: lea -12(sp),sp @@ -707,7 +707,7 @@ irq7: rts // Forward to the Access Error handler /* - * psc3 com PIC MCF */ + * psc3 com PIC MCF */ psc3: move.w #0x2700,sr // disable interrupt From 78775ab17f60d0ad687341017f7c5cdbae1d6852 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 18:15:01 +0000 Subject: [PATCH 168/276] Removed old FireTOS code. --- BaS_GNU/sources/BaS.c | 54 +++++++++++++++------------------------ BaS_GNU/sources/sysinit.c | 16 +++--------- 2 files changed, 25 insertions(+), 45 deletions(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index cca2d15..b5d596f 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -39,44 +39,32 @@ void BaS(void) sd_card_idle(); } - /* copy tos */ - if (DIP_SWITCH & (1 << 6)) + /* Initialize the NVRAM */ + MCF_PSC3_PSCTB_8BIT = 'ACPF'; + wait_10ms(); + + MCF_PSC0_PSCTB_8BIT = 'PIC '; + + MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; + MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; + MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; + MCF_PSC0_PSCTB_8BIT = 0x0d0a; + + MCF_PSC3_PSCTB_8BIT = 0x01; /* request RTC data */ + + if (MCF_PSC3_PSCRB_8BIT == 0x81) { - MCF_PSC3_PSCTB_8BIT = 'ACPF'; - wait_10ms(); - - MCF_PSC0_PSCTB_8BIT = 'PIC '; - - MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; - MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; - MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; - MCF_PSC0_PSCTB_8BIT = 0x0d0a; - - MCF_PSC3_PSCTB_8BIT = 0x01; /* request RTC data */ - - if (MCF_PSC3_PSCRB_8BIT == 0x81) + for (i = 0; i < 64; i++) { - for (i = 0; i < 64; i++) - { - * (uint8_t *) 0xffff8963 = MCF_PSC3_PSCRB_8BIT; /* Copy the NVRAM data from the PIC to the FPGA */ - } - } - - /* copy EMUTOS */ - src = (uint8_t *) 0xe0600000L; - while (src < (uint8_t *) 0xe0700000L) - { - *dst++ = *src++; + * (uint8_t *) 0xffff8963 = MCF_PSC3_PSCRB_8BIT; /* Copy the NVRAM data from the PIC to the FPGA */ } } - else + + /* copy EMUTOS */ + src = (uint8_t *) 0xe0600000L; + while (src < (uint8_t *) 0xe0700000L) { - /* copy FireTOS */ - src = (uint8_t *) 0xe0400000L; - while (src < (uint8_t *) 0xe0500000L) - { - *dst++ = *src++; - } + *dst++ = *src++; } /* we have copied a code area, so flush the caches */ diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 4d2d7c7..2ef8a73 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -709,22 +709,14 @@ void initialize_hardware(void) { init_slt(); init_fbcs(); init_ddram(); - - /* do not initialize PCI if DIP switch 5 = on */ - if (DIP_SWITCH & (1 << 6)) - init_PCI(); - + init_PCI(); init_fpga(); init_pll(); init_video_ddr(); dvi_on(); - - /* do not initialize ports if DIP switch 5 = on */ - if (DIP_SWITCH & (1 << 6)) { - test_upd720101(); - /* video_1280_1024(); */ - init_ac97(); - } + test_upd720101(); + //video_1280_1024(); + init_ac97(); /* copy the BaS code contained in flash to its final location */ src = (uint32_t *)BAS_LMA; From b093c040bef9d16de0221def9c2326b05a559a09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 18:17:34 +0000 Subject: [PATCH 169/276] Added comments about pseudo-supervisor mode. --- BaS_GNU/sources/BaS.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index b5d596f..db87f0d 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -165,7 +165,10 @@ void BaS(void) * (uint8_t *) 0xfffffa11 = 0; __asm__ __volatile__("nop \n\t" : : : "memory"); + /* Test for pseudo-supervisor mode: DIP switch #6 down */ if (DIP_SWITCH & (1 << 7)) { + /* In this mode, the OS actually runs in user mode + * and all the supervisor instructions are emulated. */ __asm__ __volatile__("move.w #0x0700,sr \n\t" : : : "memory"); } __asm__ __volatile__("jmp 0xe00030 \n\t" : : : "memory"); From 4835567f2900b038a8663c45ef243b507563318e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 18:38:33 +0000 Subject: [PATCH 170/276] Converted jump to the OS into C. --- BaS_GNU/sources/BaS.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index db87f0d..6f08dea 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -171,5 +171,13 @@ void BaS(void) * and all the supervisor instructions are emulated. */ __asm__ __volatile__("move.w #0x0700,sr \n\t" : : : "memory"); } - __asm__ __volatile__("jmp 0xe00030 \n\t" : : : "memory"); + + /* Jump into the OS */ + typedef void void_func(void); + typedef struct { + void *initial_sp; + void_func *initial_pc; + } ROM_HEADER; + ROM_HEADER* os_header = (ROM_HEADER*)tos_base; + os_header->initial_pc(); } From d27482446663a829b0dd06668adbb1bd776c4cf1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 18:42:42 +0000 Subject: [PATCH 171/276] FireTOS never returns. --- BaS_GNU/sources/sysinit.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 2ef8a73..c917fc0 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -701,7 +701,8 @@ void initialize_hardware(void) { /* Jump into FireTOS */ typedef void void_func(void); void_func* FireTOS = (void_func*)0xe0400000; - FireTOS(); + FireTOS(); // Should never return + return; } init_gpio(); From e352230dc86be22507b2fd09f2a0d547e894310b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 19:01:03 +0000 Subject: [PATCH 172/276] Moved FireTOS and EmuTOS symbols to the linker script. --- BaS_GNU/bas.lk.in | 5 +++++ BaS_GNU/sources/BaS.c | 10 ++++++++-- BaS_GNU/sources/sysinit.c | 5 ++++- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/BaS_GNU/bas.lk.in b/BaS_GNU/bas.lk.in index 52e9abc..6fa0e29 100644 --- a/BaS_GNU/bas.lk.in +++ b/BaS_GNU/bas.lk.in @@ -14,6 +14,11 @@ SECTIONS { ___SDRAM = ABSOLUTE(0x00000000); ___SDRAM_SIZE = ABSOLUTE(0x20000000); + /* Flash components */ + __FIRETOS = ABSOLUTE(0xe0400000); + __EMUTOS = ABSOLUTE(0xe0600000); + __EMUTOS_SIZE = ABSOLUTE(0x00100000); + /* VIDEO RAM BASIS */ __VRAM = ABSOLUTE(0x60000000); diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 6f08dea..7e3ad34 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -23,6 +23,12 @@ extern int sd_card_init(); extern void wait_10ms(); extern void wait_1ms(); +/* Symbols from the linker script */ +extern uint8_t _EMUTOS[]; +#define EMUTOS ((uint32_t)_EMUTOS) /* where EmuTOS is stored in flash */ +extern uint8_t _EMUTOS_SIZE[]; +#define EMUTOS_SIZE ((uint32_t)_EMUTOS_SIZE) /* size of EmuTOS, in bytes */ + /********************************************************************/ void BaS(void) { @@ -61,8 +67,8 @@ void BaS(void) } /* copy EMUTOS */ - src = (uint8_t *) 0xe0600000L; - while (src < (uint8_t *) 0xe0700000L) + src = (uint8_t *)EMUTOS; + while (src < (uint8_t *)(EMUTOS + EMUTOS_SIZE)) { *dst++ = *src++; } diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index c917fc0..a4847e7 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -667,6 +667,9 @@ livo: /* Symbols from the linker script */ +extern uint8_t _FIRETOS[]; +#define FIRETOS ((uint32_t)_FIRETOS) /* where FireTOS is stored in flash */ + extern uint8_t _BAS_LMA[]; #define BAS_LMA ((uint32_t)_BAS_LMA) /* where the BaS is stored in flash */ @@ -700,7 +703,7 @@ void initialize_hardware(void) { /* Jump into FireTOS */ typedef void void_func(void); - void_func* FireTOS = (void_func*)0xe0400000; + void_func* FireTOS = (void_func*)FIRETOS; FireTOS(); // Should never return return; } From ee3421b64ecfad46e36329dbf7a52f5acff73f59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 19:03:20 +0000 Subject: [PATCH 173/276] Removed dead code. --- BaS_GNU/sources/BaS.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 7e3ad34..a7c285a 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -76,17 +76,6 @@ void BaS(void) /* we have copied a code area, so flush the caches */ flush_and_invalidate_caches(); -#ifdef _NOT_USED_ - /* - * set the NVRAM checksum as invalid - */ - // Set the NVRAM checksum as invalid - move.b #63,(a0) - move.b 2(a0),d0 - add #1,d0 - move.b d0,2(a0) -#endif /* NOT_USED */ - mmu_init(); vec_init(); illegal_table_make(); From f6092d4c1afce73ca663fe2f4f7ce3df6785f090 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 19:20:33 +0000 Subject: [PATCH 174/276] Fixed typo in interrupt initialization code. --- BaS_GNU/sources/BaS.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index a7c285a..2c5dc4f 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -94,7 +94,7 @@ void BaS(void) MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */ MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */ MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */ - MCF_INTC_IMRH = 0x9ffffffe; /* psc3 and timer 0 int on */ + MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */ MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */ From 0188f30eafd1e28535f3856fd2df4c20f9412292 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 19:26:47 +0000 Subject: [PATCH 175/276] Fixed lower memory initialization. --- BaS_GNU/sources/BaS.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 2c5dc4f..faba804 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -127,11 +127,11 @@ void BaS(void) /* * memory setup */ - for (adr = (uint32_t *) 0x400L; adr < (uint32_t *) 0x800L; adr += 32) { - *adr = 0x0L; - *adr = 0x0L; - *adr = 0x0L; - *adr = 0x0L; + for (adr = (uint32_t *) 0x400L; adr < (uint32_t *) 0x800L; ) { + *adr++ = 0x0L; + *adr++ = 0x0L; + *adr++ = 0x0L; + *adr++ = 0x0L; } * (uint8_t *) 0xffff8007 = 0x48; /* FIXME: what's that ? */ From 29bddf87bdcb276c253741f9c33a133ef1a8a32b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 19:34:29 +0000 Subject: [PATCH 176/276] Fixed MFP ISR register initialization. --- BaS_GNU/sources/BaS.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index faba804..6f6a39d 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -155,9 +155,9 @@ void BaS(void) __asm__ __volatile__("nop \n\t" : : : "memory"); * (uint8_t *) 0xfffffc00 = 0x96; __asm__ __volatile__("nop \n\t" : : : "memory"); - * (uint8_t *) 0xfffffa0f = 0; + * (uint8_t *) 0xfffffa0f = -1; __asm__ __volatile__("nop \n\t" : : : "memory"); - * (uint8_t *) 0xfffffa11 = 0; + * (uint8_t *) 0xfffffa11 = -1; __asm__ __volatile__("nop \n\t" : : : "memory"); /* Test for pseudo-supervisor mode: DIP switch #6 down */ From 1e18dd8af880ad54bd9cc285ef1a79c7491e5c28 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 22 Oct 2012 19:36:30 +0000 Subject: [PATCH 177/276] ram loading does work correctly now --- BaS_GNU/mcf5474.bdm | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/BaS_GNU/mcf5474.bdm b/BaS_GNU/mcf5474.bdm index 66f0f47..abe3471 100755 --- a/BaS_GNU/mcf5474.bdm +++ b/BaS_GNU/mcf5474.bdm @@ -32,10 +32,20 @@ write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 0 write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) -write 0xFF000108 0x53722938 4 # SDCFG1 -write 0xFF00010C 0x24330000 4 # SDCFG2 +write 0xFF000108 0x73622830 4 # SDCFG1 +write 0xFF00010C 0x46770000 4 # SDCFG2 + +write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +write 0xFF000100 0x40010000 4 # SDMR (write to LEMR) +write 0xFF000100 0x048D0000 4 # SDMR (write to LMR) +write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +write 0xFF000100 0x008D0000 4 # SDMR (write to LMR) +write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh) -wait # load -v ram.s19 # unfortunately, this seems to work only with elf files load -v bas.s19.elf # TODO: bdmctrl tries to flash but doesn't succed. Don't know why yet - +#load -v ram.s19.elf +sleep 60000 +execute 0x1000000 From a2790b1222496c8506b564e4035c134872db8a79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 19:44:57 +0000 Subject: [PATCH 178/276] Fixed wrong MCF_GPT0_GMS initialization. --- BaS_GNU/sources/BaS.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 6f6a39d..d6117d7 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -87,7 +87,7 @@ void BaS(void) MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */ MCF_GPT_GMS_IEN | - MCF_GPT_GMS(1); + MCF_GPT_GMS_TMS(1); MCF_INTC_ICR62 = 0x3f; * (uint8_t *) 0xf0010004 = 0xfe; /* enable int 1-7 */ From 0218fc7462c4baa9ab8dcf9522fe68665e079b85 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 20:24:58 +0000 Subject: [PATCH 179/276] Moved slice timer OK message. --- BaS_GNU/sources/sysinit.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index a4847e7..e7b52f0 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -70,12 +70,11 @@ void wait_1us(void) */ void init_slt(void) { - uart_out_word('SLT '); - uart_out_word('OK! '); - MCF_SLT0_STCNT = 0xffffffff; MCF_SLT0_SCR = 0x05; + uart_out_word('SLT '); + uart_out_word('OK! '); uart_out_word(0x0a0d); } From 60adf2dc6a8533ba9da1238a9e7ce26ad6d089a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 20:52:41 +0000 Subject: [PATCH 180/276] Fixed wait_pll(). --- BaS_GNU/sources/sysinit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index e7b52f0..fb2a2e1 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -244,7 +244,7 @@ void wait_pll(void) { register uint32_t trgt = MCF_SLT0_SCNT - 100000; do { - } while ((* (volatile uint16_t *) 0xf0000800 > 0) && MCF_SLT0_SCNT > trgt); + } while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt); } static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600; From 45cc5f720a33e9c4f07774e271c5a387c70b5d73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 21:09:07 +0000 Subject: [PATCH 181/276] Added comment about init_video_ddr(). --- BaS_GNU/sources/sysinit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index fb2a2e1..386d8bd 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -330,7 +330,7 @@ void init_video_ddr(void) { _VRAM = 0000070022; /* load MR dll on */ NOP(); - * (uint32_t *) 0xf0000400 = 0x01070002; + * (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */ } From 26287ffed27b2c7d8a5889717ef9c1d715b8d077 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 21:09:53 +0000 Subject: [PATCH 182/276] Fixed warning about unused variable. --- BaS_GNU/sources/sysinit.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 386d8bd..4be2d54 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -12,6 +12,8 @@ #include "cache.h" #include "sysinit.h" +#define UNUSED(x) (void)(x) /* Unused variable */ + extern volatile long _VRAM; /* start address of video ram from linker script */ /* @@ -564,6 +566,8 @@ dvi_ok: uart_out_word('OK! '); uart_out_word(0x0a0d); MCF_I2C_I2CR = 0x0; // i2c off + + UNUSED(DBYT); // Avoid warning } From 4e849cd5196c22fff034896b6d9ecde00ad8d42c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Rivi=C3=A8re?= Date: Mon, 22 Oct 2012 22:20:27 +0000 Subject: [PATCH 183/276] Fixed wrong value in init_pll(). --- BaS_GNU/sources/sysinit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 4be2d54..54a03dc 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -256,7 +256,7 @@ void init_pll(void) uart_out_word('PLL '); wait_pll(); - * (volatile uint16_t *) (pll_base + 0x48) = 0x27; /* loopfilter r */ + * (volatile uint16_t *) (pll_base + 0x48) = 27; /* loopfilter r */ wait_pll(); * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ From 57cac31383739698fc9d55982101fd86bafc5be5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 23 Oct 2012 06:12:24 +0000 Subject: [PATCH 184/276] Board initialization file for gdb --- BaS_GNU/5474.gdb | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 BaS_GNU/5474.gdb diff --git a/BaS_GNU/5474.gdb b/BaS_GNU/5474.gdb new file mode 100644 index 0000000..64620a9 --- /dev/null +++ b/BaS_GNU/5474.gdb @@ -0,0 +1,50 @@ +# +# GDB Init script for the Coldfire 5206 processor. +# +# The main purpose of this script is to configure the +# DRAM controller so code can be loaded. +# +# + +define addresses +set $mbar = 0xFF000000 +set $vbr = 0x00000000 +set $rambar0 = 0xFF100000 +set $rambar1 = 0xFF101000 +end + +# +# Setup the DRAM controller. +# + +define setup-dram +# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +set *((long *) 0xFF000500) = 0xE0000000 +set *((long *) 0xFF000508) = 0x00001180 +set *((long *) 0xFF000504) = 0x007F0001 + +# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +# SDRAMDS configuration +set *((long *) 0xFF000004) = 0x000002AA +# SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +set *((long *) 0xFF000020) = 0x0000001A +# SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +set *((long *) 0xFF000024) = 0x0800001A +# SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +set *((long *) 0xFF000028) = 0x1000001A +# SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +set *((long *) 0xFF00002C) = 0x1800001A +# SDCFG1 +set *((long *) 0xFF000108) = 0x53722938 +# SDCFG2 +set *((long *) 0xFF00010C) = 0x24330000 +end + +# +# Wake up the board +# + +define initBoard +addresses +setup-dram +end \ No newline at end of file From 07f414a3c6393b85e6cc01c58f7a7a324a47f79e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 23 Oct 2012 08:10:51 +0000 Subject: [PATCH 185/276] further initialization of SDRAM for gcc --- BaS_GNU/5474.gdb | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/BaS_GNU/5474.gdb b/BaS_GNU/5474.gdb index 64620a9..6ce35e2 100644 --- a/BaS_GNU/5474.gdb +++ b/BaS_GNU/5474.gdb @@ -7,8 +7,8 @@ # define addresses -set $mbar = 0xFF000000 set $vbr = 0x00000000 +set $mbar = 0xFF000000 set $rambar0 = 0xFF100000 set $rambar1 = 0xFF101000 end @@ -19,25 +19,30 @@ end define setup-dram # Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) -set *((long *) 0xFF000500) = 0xE0000000 -set *((long *) 0xFF000508) = 0x00001180 -set *((long *) 0xFF000504) = 0x007F0001 +set *((long *) 0xFF000500) = 0xE0000000 # flash address +set *((long *) 0xFF000508) = 0x00001180 # 16 bit 4ws aa +set *((long *) 0xFF000504) = 0x007F0001 # 8MB on + +# set *((long *) 0xFF00050C) = 0xFFF00000 # ATARI I/O address # SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes -# SDRAMDS configuration -set *((long *) 0xFF000004) = 0x000002AA -# SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) -set *((long *) 0xFF000020) = 0x0000001A -# SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) -set *((long *) 0xFF000024) = 0x0800001A -# SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) -set *((long *) 0xFF000028) = 0x1000001A -# SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) -set *((long *) 0xFF00002C) = 0x1800001A -# SDCFG1 -set *((long *) 0xFF000108) = 0x53722938 -# SDCFG2 -set *((long *) 0xFF00010C) = 0x24330000 +set *((long *) 0xFF000004) = 0x000002AA # SDRAMDS configuration +set *((long *) 0xFF000020) = 0x0000001A # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +set *((long *) 0xFF000024) = 0x0800001A # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +set *((long *) 0xFF000028) = 0x1000001A # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +set *((long *) 0xFF00002C) = 0x1800001A # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +set *((long *) 0xFF000108) = 0x73622830 # SDCFG1 +set *((long *) 0xFF00010C) = 0x46770000 # SDCFG2 + + +set *((long *) 0xFF000104) = 0xE10D0002 # SDCR + IPALL +set *((long *) 0xFF000100) = 0x40010000 # SDMR (write to LEMR) +set *((long *) 0xFF000100) = 0x048D0000 # SDMR (write to LMR) +set *((long *) 0xFF000104) = 0xE10D0002 # SDCR + IPALL +set *((long *) 0xFF000104) = 0xE10D0004 # SDCR + IREF (first refresh) +set *((long *) 0xFF000104) = 0xE10D0004 # SDCR + IREF (first refresh) +set *((long *) 0xFF000100) = 0x008D0000 # SDMR (write to LMR) +set *((long *) 0xFF000104) = 0x710D0F00 # SDCR (lock SDMR and enable refresh) end # From 52d22492fc0591e34bc4d05f5101b0a09f859a59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 23 Oct 2012 10:26:25 +0000 Subject: [PATCH 186/276] latest insights from disassembling the binaries --- BaS_GNU/5474.gdb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/5474.gdb b/BaS_GNU/5474.gdb index 6ce35e2..d47b7c4 100644 --- a/BaS_GNU/5474.gdb +++ b/BaS_GNU/5474.gdb @@ -20,7 +20,7 @@ end define setup-dram # Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) set *((long *) 0xFF000500) = 0xE0000000 # flash address -set *((long *) 0xFF000508) = 0x00001180 # 16 bit 4ws aa +set *((long *) 0xFF000508) = 0x00041180 # 16 bit 4ws aa set *((long *) 0xFF000504) = 0x007F0001 # 8MB on # set *((long *) 0xFF00050C) = 0xFFF00000 # ATARI I/O address From bb662f5dc61b0365f49114095fe9b84de11257a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 23 Oct 2012 10:28:35 +0000 Subject: [PATCH 187/276] added latest insights from disassembling the binary distribution --- BaS_GNU/sources/sysinit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 54a03dc..a58c6ba 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -208,7 +208,7 @@ void init_fbcs() /* Flash */ MCF_FBCS0_CSAR = 0xE0000000; // FLASH ADRESS - MCF_FBCS0_CSCR = 0x00001180; // 16 bit 4ws aa + MCF_FBCS0_CSCR = 0x00041180; // 16 bit 4ws aa MCF_FBCS0_CSMR = 0x007F0001; // 8MB on MCF_FBCS1_CSAR = 0xFFF00000; // ATARI I/O ADRESS From eec89836dd2ee4188bfa6ad22495c20666abf3e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 24 Oct 2012 04:27:11 +0000 Subject: [PATCH 188/276] modified comments --- BaS_GNU/5474.gdb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/5474.gdb b/BaS_GNU/5474.gdb index d47b7c4..9da0756 100644 --- a/BaS_GNU/5474.gdb +++ b/BaS_GNU/5474.gdb @@ -1,5 +1,5 @@ # -# GDB Init script for the Coldfire 5206 processor. +# GDB Init script for the Coldfire 5474 processor (Firebee board). # # The main purpose of this script is to configure the # DRAM controller so code can be loaded. @@ -52,4 +52,6 @@ end define initBoard addresses setup-dram -end \ No newline at end of file +end + +initBoard \ No newline at end of file From f35c849be7267f6e9d52a2093329cc473e7852ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 24 Oct 2012 04:31:20 +0000 Subject: [PATCH 189/276] moved comments from line ends to a single line before since gdb doesnt't seem to like them that way --- BaS_GNU/5474.gdb | 55 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 18 deletions(-) diff --git a/BaS_GNU/5474.gdb b/BaS_GNU/5474.gdb index 9da0756..4d86637 100644 --- a/BaS_GNU/5474.gdb +++ b/BaS_GNU/5474.gdb @@ -19,30 +19,49 @@ end define setup-dram # Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) -set *((long *) 0xFF000500) = 0xE0000000 # flash address -set *((long *) 0xFF000508) = 0x00041180 # 16 bit 4ws aa -set *((long *) 0xFF000504) = 0x007F0001 # 8MB on + +# flash address +set *((long *) 0xFF000500) = 0xE0000000 +# 16 bit 4ws aa +set *((long *) 0xFF000508) = 0x00041180 +# 8MB on +set *((long *) 0xFF000504) = 0x007F0001 # set *((long *) 0xFF00050C) = 0xFFF00000 # ATARI I/O address # SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes -set *((long *) 0xFF000004) = 0x000002AA # SDRAMDS configuration -set *((long *) 0xFF000020) = 0x0000001A # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) -set *((long *) 0xFF000024) = 0x0800001A # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) -set *((long *) 0xFF000028) = 0x1000001A # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) -set *((long *) 0xFF00002C) = 0x1800001A # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) -set *((long *) 0xFF000108) = 0x73622830 # SDCFG1 -set *((long *) 0xFF00010C) = 0x46770000 # SDCFG2 +# SDRAMDS configuration +set *((long *) 0xFF000004) = 0x000002AA +# SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +set *((long *) 0xFF000020) = 0x0000001A +# SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +set *((long *) 0xFF000024) = 0x0800001A +# SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +set *((long *) 0xFF000028) = 0x1000001A +# SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +set *((long *) 0xFF00002C) = 0x1800001A +# SDCFG1 +set *((long *) 0xFF000108) = 0x73622830 +# SDCFG2 +set *((long *) 0xFF00010C) = 0x46770000 -set *((long *) 0xFF000104) = 0xE10D0002 # SDCR + IPALL -set *((long *) 0xFF000100) = 0x40010000 # SDMR (write to LEMR) -set *((long *) 0xFF000100) = 0x048D0000 # SDMR (write to LMR) -set *((long *) 0xFF000104) = 0xE10D0002 # SDCR + IPALL -set *((long *) 0xFF000104) = 0xE10D0004 # SDCR + IREF (first refresh) -set *((long *) 0xFF000104) = 0xE10D0004 # SDCR + IREF (first refresh) -set *((long *) 0xFF000100) = 0x008D0000 # SDMR (write to LMR) -set *((long *) 0xFF000104) = 0x710D0F00 # SDCR (lock SDMR and enable refresh) +# SDCR + IPALL +set *((long *) 0xFF000104) = 0xE10D0002 +# SDMR (write to LEMR) +set *((long *) 0xFF000100) = 0x40010000 +# SDMR (write to LMR) +set *((long *) 0xFF000100) = 0x048D0000 +# SDCR + IPALL +set *((long *) 0xFF000104) = 0xE10D0002 +# SDCR + IREF (first refresh) +set *((long *) 0xFF000104) = 0xE10D0004 +# SDCR + IREF (first refresh) +set *((long *) 0xFF000104) = 0xE10D0004 +# SDMR (write to LMR) +set *((long *) 0xFF000100) = 0x008D0000 +# SDCR (lock SDMR and enable refresh) +set *((long *) 0xFF000104) = 0x710D0F00 end # From 3cc9a1ad0acfd6d30359c0dbc2da9dd8f699f2ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 24 Oct 2012 13:02:07 +0000 Subject: [PATCH 190/276] included original sd_card routines instead of dummys --- BaS_GNU/sources/sd_card.c | 583 +------------------ BaS_GNU/sources/{sd_card.s => sd_card_asm.S} | 73 +-- 2 files changed, 48 insertions(+), 608 deletions(-) rename BaS_GNU/sources/{sd_card.s => sd_card_asm.S} (78%) diff --git a/BaS_GNU/sources/sd_card.c b/BaS_GNU/sources/sd_card.c index f8ba54b..af22cb6 100644 --- a/BaS_GNU/sources/sd_card.c +++ b/BaS_GNU/sources/sd_card.c @@ -5,589 +5,22 @@ #include #include -#define dspi_dtar0 0x0c -#define dspi_dsr 0x2c -#define dspi_dtfr 0x34 -#define dspi_drfr 0x38 -#define time1us 1320 - -uint8_t sd_com(uint32_t cmd) -{ - uint8_t res; - - MCF_DSPI_DTFR = cmd; - while (! (MCF_DSPI_DSR & (1 << 7))); - - res = MCF_DSPI_DRFR; - MCF_DSPI_DSR = -1L; - - return res; -} - -/* - * fetch status from SD controller - */ -uint8_t sd_get_status(void) -{ - uint8_t res; - - while ((res = sd_com(0xff)) == 0xff); - - return res; -} - -void sd_rcv_info(uint8_t *buf, uint32_t size) -{ - uint32_t rcvd = 0; - - while (sd_get_status() != 0xfe); /* loop until data available */ - - do { - *buf++ = sd_com(0x18); - rcvd++; - } while (rcvd <= size); -} - - void sd_card_idle(void) { - -#ifdef _NOT_USED_ - asm - { -// sd idle -// speed =400kHz - move.l #0x082000ff,d4 // tx vorbesetzen - lea MCF_DSPI_DMCR,a0 - move.l #0x38558897,d0 - move.l d0,dspi_dtar0(a0) // 400kHz - - move.b #0xff,d4 - bsr sd_com // clocks - move.b #0x40,d4 // cmd idle - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #0x95,d4 - bsr sd_com - } -#endif + __asm__ __volatile__ ( + ".extern sd_idle\n\t" + "bsr sd_idle\n\t" + /* input */ : + /* output */: + /* clobber */: "a0","a1","a2","a3","a4","a5","a6", + "d0","d1","d2","d3","d4","d5","d6","d7","memory" + ); } int sd_card_init(void) { - return 0; /* for now, just to make the compiler happy */ -#ifdef _NOT_USED_ - long az_sectors; - asm - { - lea MCF_PSC0_PSCTB_8BIT,a1 - move.l #'SD-C',(a1) - move.l #'ard ',(a1) - - move.l buffer,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) - move.l #0x1fffffff,d0 // normal dspi - move.l d0,MCF_PAD_PAR_DSPI - lea MCF_DSPI_DMCR,a0 - move.l #0x802d3c00,(a0) // 8 bit cs off clear fifo - move.l #0x38558897,d0 - move.l d0,dspi_dtar0(a0) // 400kHz - move.l #0x082000ff,d4 // tx vorbesetzen - move.l d4,dspi_dtfr // und setzen - mov3q.l #-1,dspi_dsr(a0) // status register l�schen - - move.l #0xc00d3c00,(a0) // clock on cs ist on - bsr wait_10ms - move.l #0x802d3c00,(a0) // clock off cs off - bsr sd_com - bsr sd_com - bsr sd_com - bsr sd_com - bsr sd_com - bsr sd_com - bsr sd_com - bsr sd_com - bsr sd_com - bsr sd_com - move.l #0x800d3c00,(a0) // cs on - bsr sd_com - bsr sd_com - move.l #0x802d3c00,(a0) // cs off - bsr sd_com - bsr sd_com - bsr wait_10ms - -// sd idle - move.l #100,d6 // 100 versuche - move.l #10,d3 // 10 versuche -sd_idle: - bsr sd_card_idle - - move.l #10,d7 - move.b #0xff,d4 -sd_idle_leeren: - bsr sd_com - cmp.b #0x01,d5 - beq idle_end - subq.l #1,d7 - bne sd_idle_leeren - subq.l #1,d6 - beq sd_not - bra sd_idle -idle_end: - -// cdm 8 -read_ic: - move.b #0xff,d4 // clocks - bsr sd_com - move.b #0x48,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #0x01,d4 - bsr sd_com - move.b #0xaa,d4 - bsr sd_com - move.b #0x87,d4 - bsr sd_com - - bsr sd_get_status - cmp.b #5,d5 - beq sd_v1 - cmp.b #1,d5 - bne read_ic - - bsr sd_com // 4byts zum wegwerfen - bsr sd_com - bsr sd_com - bsr sd_com - cmp.b #0xaa,d5 // pattern zur�ckgekommen? - bne sd_testd3 // nein -> - - move.l #'SDHC',(a1) - move.b #' ',(a1) -sd_v1: - -// cdm 58 -read_ocr: - move.b #0xff,d4 // clocks - bsr sd_com - move.b #0x7a,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #0x00,d4 - bsr sd_com - move.b #0x00,d4 - bsr sd_com - move.b #0x01,d4 - bsr sd_com - - bsr sd_get_status - move.l #'Ver1',d6 - cmp.b #5,d5 - beq read_ocr - cmp.b #1,d5 - bne read_ocr - - bsr sd_com // 4 byts zum wegwerfen - bsr sd_com - bsr sd_com - bsr sd_com - -// acdm 41 - move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen -wait_of_aktiv: - move.b #0xff,d4 // clocks - bsr sd_com - move.b #0x77,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #0x95,d4 - bsr sd_com - - bsr sd_get_status - cmp.b #0x05,d5 - beq wait_of_aktiv - -wait_of_aktiv2: - move.b #0xff,d4 // clocks - bsr sd_com - move.b #0x69,d4 - bsr sd_com - move.b #0x40,d4 - bsr sd_com - move.b #0x00,d4 - bsr sd_com - move.b #0x00,d4 - bsr sd_com - move.b #0x00,d4 - bsr sd_com - move.b #0x95,d4 - bsr sd_com - - bsr sd_get_status - tst.b d5 - beq sd_init_ok - cmp.b #0x05,d5 - beq wait_of_aktiv2 - subq.l #1,d6 - bne wait_of_aktiv -sd_testd3: - subq.l #1,d3 - bne sd_idle - bra sd_error - -sd_init_ok: -// fullspeed - move.l #0x38551120,d0 // 22Mbit/sec - move.l d0,dspi_dtar0(a0) // setzen - -// cdm 10 -read_cid: - move.b #0xff,d4 // clocks - bsr sd_com - move.b #0x4a,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #0x00,d4 - bsr sd_com - move.b #0x00,d4 - bsr sd_com - move.b #0x95,d4 - bsr sd_com - - move.l a5,a2 // adresse setzen - bsr sd_rcv_info - -// name ausgeben - lea 1(a5),a2 - moveq #7,d7 -sd_nam_loop: - move.b (a2)+,(a1) - subq.l #1,d7 - bne sd_nam_loop - move.b #' ',(a1) - -// cdm 9 -read_csd: - move.b #0xff,d4 // clocks - bsr sd_com - move.b #0x49,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #00,d4 - bsr sd_com - move.b #0x00,d4 - bsr sd_com - move.b #0x00,d4 - bsr sd_com - move.b #0x01,d4 - bsr sd_com - - move.l a5,a2 // adresse setzen - bsr sd_rcv_info - - mvz.b (a5),d0 - lsr.l #6,d0 - - bne sd_csd2 // format v2 - move.l 6(a5),d1 - moveq #14,d0 // bit 73..62 c_size - lsr.l d0,d1 // bits extrahieren - and.l #0xfff,d1 // 12 bits - addq.l #1,d1 - mvz.w 9(a5),d0 - lsr.l #7,d0 // bits 49..47 - and.l #0x7,d0 // 3 bits - moveq.l #8,d2 // x256 (dif v1 v2) - sub.l d0,d2 - lsr.l d2,d1 - bra sd_print_size -sd_csd2: - mvz.w 8(a5),d1 - addq.l #1,d1 -sd_print_size: - swap d1 - move.l d1,d3 - lsr.l #6,d3 //x65636 /64 -> anzahl sectors - move.l d3,az_sectors - lsl.l #1,d1 - bcc sd_16G - move.l #'32GB',(a1) - bra sd_ok -sd_16G: - lsl.l #1,d1 - bcc sd_8G - move.l #'16GB',(a1) - bra sd_ok -sd_8G: - lsl.l #1,d1 - bcc sd_4G - move.l #' 8GB',(a1) - bra sd_ok -sd_4G: - lsl.l #1,d1 - bcc sd_2G - move.l #' 4GB',(a1) - bra sd_ok -sd_2G: - lsl.l #1,d1 - bcc sd_1G - move.l #' 2GB',(a1) - bra sd_ok -sd_1G: - lsl.l #1,d1 - bcc sd_512M - move.l #' 1GB',(a1) - bra sd_ok -sd_512M: - lsl.l #1,d1 - bcc sd_256M - move.b #'5',(a1) - move.l #'12MB',(a1) - bra sd_ok -sd_256M: - lsl.l #1,d1 - bcc sd_128M - move.b #'2',(a1) - move.l #'56MB',(a1) - bra sd_ok -sd_128M: - lsl.l #1,d1 - bcc sd_64M - move.b #'1',(a1) - move.l #'28MB',(a1) - bra sd_ok -sd_64M: - lsl.l #1,d1 - bcc sd_32M - move.l #'64MB',(a1) - bra sd_ok -sd_32M: - lsl.l #1,d1 - bcc sd_16M - move.l #'32MB',(a1) - bra sd_ok -sd_16M: - lsl.l #1,d1 - bcc sd_8M - move.l #'16MB',(a1) - bra sd_ok -sd_8M: - move.l #'<9MB',(a1) -sd_ok: - move.l #' OK!',(a1) - move.l #0x0a0d,(a1) - bra sd_c_ok -// subs ende ------------------------------- -sd_error: - move.l #'Erro',(a1) - move.l #'r!',(a1) - move.l #0x0a0d,(a1) - bra sd_c_error -sd_not: - move.l #'non!',(a1) - move.l #0x0a0d,(a1) - bra sd_c_not -buffer: dc.l 0,0,0,0,0,0,0,0 - } -sd_c_ok: - return az_sectors; -sd_c_not: - return -2; -sd_c_error: - return -1; - -#endif /* _NOT_USED_ */ } -#ifdef _NOT_USED_ -void sd_rcv_sector(void) // 1 sector daten holen ---------------------------- -{ - if (sd_get_status() == 0xfe) - { - for (i = 0; i < 512; i++) - } - } - asm - { - bsr sd_get_status - cmp.b #0xfe,d5 // daten bereit? - bne sd_rs_end // nein-> error - move.l #512,d3 // sonst 512 byts abholen -sd_rs_loop: - bsr sd_com - move.b d5,(a2)+ - subq.l #1,d3 - bne sd_rs_loop -// crc holen - bsr sd_com - bsr sd_com - clr.l d5 // alles ok -sd_rs_end: - } -} - -int sd_card_sector_read(long sec_nr,long buf_adr) -{ - int status ; - asm - { - lea MCF_DSPI_DMCR,a0 - move.l #0x082000ff,d4 // tx vorbesetzen - - move.l sec_nr,d0 - move.l buf_adr,a2 - - lsl.l #8,d0 - add.l d0,d0 // x 512 ! - move.l d0,d1 // byts kehren - swap d1 - move.l d1,d2 - lsr.l #8,d1 - - move.b #0xff,d4 // clocks - bsr sd_com - - move.b #0x51,d4 - bsr sd_com - move.b d1,d4 - bsr sd_com - move.b d2,d4 - bsr sd_com - move.l d0,d2 - lsr.l #8,d2 - move.b d2,d4 - bsr sd_com - move.b d0,d4 - bsr sd_com - move.b #0x01,d4 - bsr sd_com - - clr.l d5 // alles auf no error - clr.l status - - bsr sd_get_status // status holen - tst.b d5 - bne sd_csr_end // wenn nicht ok -> weg -// sector holen - bsr sd_rcv_sector -sd_csr_end: - tst.b d5 - beq sd_csr_ok - neg.l d5 // wenn nicht ok status auf negativ - move.l d5,status -sd_csr_ok: - } - return status; -} - -void sd_send_sector(void) // 1 sector daten senden ---------------------------- -{ - asm - { - move.l #512,d3 - move.b #0xfe,d4 // start token - bsr sd_com // senden -sd_send_wr_wb: - move.b (a2)+,d4 // data - bsr sd_com // senden - subq.l #1,d3 - bne sd_send_wr_wb -// send crc - move.b #1,d4 - bsr sd_com // crc 1.byt - move.b #1,d4 - bsr sd_com // crc 2.byt -sd_send_wr_ww: - bsr sd_get_status - and.l #0x1f,d5 - clr.l d6 //status auf OK - cmp.b #5,d5 //data accepted? - beq sd_send_end //ja -> - move.l d5,d6 //sonst status sichern -sd_send_end: - bsr sd_com - tst.b d5 // warte auf geschrieben - beq sd_send_end - move.l d6,d5 // status zur�ck - } -} - -int sd_card_sector_write(long sec_nr,long buf_adr) -{ - int status; - asm - { - lea MCF_DSPI_DMCR,a0 - move.l #0x082000ff,d4 // tx vorbesetzen - - move.l sec_nr,d0 - move.l buf_adr,a2 - - lsl.l #8,d0 - add.l d0,d0 // x 512 ! - move.l d0,d1 // byts kehren - swap d1 - move.l d1,d2 - lsr.l #8,d1 - - move.b #0xff,d4 // clocks - bsr sd_com - move.b #0x58,d4 - bsr sd_com - move.b d1,d4 - bsr sd_com - move.b d2,d4 - bsr sd_com - move.l d0,d2 - lsr.l #8,d2 - move.b d2,d4 - bsr sd_com - move.b d0,d4 - bsr sd_com - move.b #0x01,d4 - bsr sd_com - - clr.l d5 // alles auf no error - clr.l status - bsr sd_get_status // status holen - tst.b d5 - bne sd_csw_end // wenn nicht ok -> weg -// sector schreiben - bsr sd_send_sector -sd_csw_end: - tst.b d5 - beq sd_csw_ok - neg.l d5 // wenn nicht ok status auf negativ - move.l d5,status -sd_csw_ok: - } - return status; -} -#endif /* _NOT_USED */ diff --git a/BaS_GNU/sources/sd_card.s b/BaS_GNU/sources/sd_card_asm.S similarity index 78% rename from BaS_GNU/sources/sd_card.s rename to BaS_GNU/sources/sd_card_asm.S index 2a3fefe..5d8453d 100644 --- a/BaS_GNU/sources/sd_card.s +++ b/BaS_GNU/sources/sd_card_asm.S @@ -1,18 +1,26 @@ /********************************************************************/ // sd card /********************************************************************/ -#define dspi_dtar0 0x0c -#define dspi_dsr 0x2c -#define dspi_dtfr 0x34 -#define dspi_drfr 0x38 +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 + +#define LONGASC(a, b, c, d) ((a << 24) | (b << 16) | (c << 8) | (d)) + +#define MCF_PAD_PAR_DSPI (__MBAR+0xA50) +#define MCF_PSC0_PSCTB_8BIT (__MBAR+0x860C) +#define MCF_DSPI_DMCR (__MBAR+0x8A00) +.text + + .global sd_idle -.text sd_test: lea MCF_PSC0_PSCTB_8BIT,a6 - move.l #'SD-C',(a6) - move.l #'ard ',(a6) + move.l #LONGASC('S', 'D', '-', 'A'),(a6) + move.l #LONGASC('a', 'r', 'd', ' '),(a6) - move.l #__Bas_base,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) + move.l #_Bas_base,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) move.l #0x1fffffff,d0 // normal dspi move.l d0,MCF_PAD_PAR_DSPI lea MCF_DSPI_DMCR,a0 @@ -22,9 +30,9 @@ sd_test: move.l #0x082000ff,d4 // tx vorbesetzen mov3q.l #-1,dspi_dsr(a0) - bsr warte_1ms + bsr.l _wait_1ms move.l #0xc00d3c00,(a0) // 8 bit 4MHz clocken cs off - bsr warte_10ms + bsr.l _wait_10ms move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on bsr sd_com bsr sd_com @@ -45,7 +53,7 @@ sd_test: bsr sd_com bsr sd_com move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off - bsr warte_10ms + bsr.l _wait_10ms // sd idle move.l #100,d6 // 100 versuche @@ -122,8 +130,7 @@ read_ic: bsr sd_com cmp.b #0xaa,d5 bne sd_testd3 - - move.l #'SDHC',(a6) + move.l #LONGASC('S', 'D', 'H', 'C'),(a6) move.b #' ',(a6) sd_v1: @@ -145,7 +152,7 @@ read_ocr: bsr sd_com bsr sd_get_status - move.l #'Ver1',d6 + move.l #LONGASC('V', 'e', 'r', '1'),d6 cmp.b #5,d5 beq read_ocr cmp.b #1,d5 @@ -283,90 +290,90 @@ sd_print_size: swap d1 lsl.l #1,d1 bcc sd_16G - move.l #'32GB',(a6) + move.l #LONGASC('3', '2', 'G', 'B'),(a6) bra sd_ok sd_16G: lsl.l #1,d1 bcc sd_8G - move.l #'16GB',(a6) + move.l #LONGASC('1', '6', 'G', 'B'),(a6) bra sd_ok sd_8G: lsl.l #1,d1 bcc sd_4G - move.l #' 8GB',(a6) + move.l #LONGASC(' ', '4', 'G', 'B'),(a6) bra sd_ok sd_4G: lsl.l #1,d1 bcc sd_2G - move.l #' 4GB',(a6) + move.l #LONGASC(' ', '4', 'G', 'B'),(a6) bra sd_ok sd_2G: lsl.l #1,d1 bcc sd_1G - move.l #' 2GB',(a6) + move.l #LONGASC(' ', '2', 'G', 'B'),(a6) bra sd_ok sd_1G: lsl.l #1,d1 bcc sd_512M - move.l #' 1GB',(a6) + move.l #LONGASC(' ', '1', 'G', 'B'),(a6) bra sd_ok sd_512M: lsl.l #1,d1 bcc sd_256M move.b #'5',(a6) - move.l #'12MB',(a6) + move.l #LONGASC('1', '2', 'M', 'B'),(a6) bra sd_ok sd_256M: lsl.l #1,d1 bcc sd_128M move.b #'2',(a6) - move.l #'56MB',(a6) + move.l #LONGASC('5', '6', 'M', 'B'),(a6) bra sd_ok sd_128M: lsl.l #1,d1 bcc sd_64M move.b #'1',(a6) - move.l #'28MB',(a6) + move.l #LONGASC('2', '8', 'M', 'B'),(a6) bra sd_ok sd_64M: lsl.l #1,d1 bcc sd_32M - move.l #'64MB',(a6) + move.l #LONGASC('6', '4', 'M', 'B'),(a6) bra sd_ok sd_32M: lsl.l #1,d1 bcc sd_16M - move.l #'32MB',(a6) + move.l #LONGASC('3', '2', 'M', 'B'),(a6) bra sd_ok sd_16M: lsl.l #1,d1 bcc sd_8M - move.l #'16MB',(a6) + move.l #LONGASC('1', '6', 'M', 'B'),(a6) bra sd_ok sd_8M: - move.l #'<9MB',(a6) -sd_ok: - move.l #' OK!',(a6) + move.l #LONGASC('<', '9', 'M', 'B'),(a6) +sd_ok: + move.l #LONGASC(' ', 'O', 'K', '!'),(a6) move.l #0x0a0d,(a6) halt halt rts // subs ende ------------------------------- sd_V1: - move.l #'non!',(a6) + move.l #LONGASC('n', 'o', 'n', '!'),(a6) move.l #0x0a0d,(a6) halt halt rts sd_error: - move.l #'Erro',(a6) - move.l #'r!',(a6) + move.l #LONGASC('E', 'r', 'r', 'o'),(a0) + move.l #LONGASC('r', '!', '', ''), (a0) move.l #0x0a0d,(a6) halt halt rts sd_not: - move.l #'non!',(a6) + move.l #LONGASC('n', 'o', 'n', '!'),(a0) move.l #0x0a0d,(a6) halt halt From 49f8728b583561a95db26264b335e7e399c5ea6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 24 Oct 2012 13:49:22 +0000 Subject: [PATCH 191/276] finished incorporating sd_card routines --- BaS_GNU/Makefile | 1 + BaS_GNU/bas.lk.in | 1 + BaS_GNU/sources/BaS.c | 2 +- BaS_GNU/sources/sd_card.c | 13 +++++++++++- BaS_GNU/sources/sd_card_asm.S | 37 +++++++++++++++++++++++++++++------ 5 files changed, 46 insertions(+), 8 deletions(-) diff --git a/BaS_GNU/Makefile b/BaS_GNU/Makefile index 59b61b6..cf10d34 100644 --- a/BaS_GNU/Makefile +++ b/BaS_GNU/Makefile @@ -45,6 +45,7 @@ CSRCS= \ ASRCS= \ $(SRCDIR)/mmu.S \ + $(SRCDIR)/sd_card_asm.S \ $(SRCDIR)/exceptions.S \ $(SRCDIR)/supervisor.S \ $(SRCDIR)/ewf.S \ diff --git a/BaS_GNU/bas.lk.in b/BaS_GNU/bas.lk.in index 6fa0e29..52a25de 100644 --- a/BaS_GNU/bas.lk.in +++ b/BaS_GNU/bas.lk.in @@ -75,6 +75,7 @@ SECTIONS { { objs/BaS.o(.text) /* put other routines into the same segment (RAM) as BaS.o */ + objs/sd_card_asm.o(.text) objs/sd_card.o(.text) objs/mmu.o(.text) objs/exceptions.o(.text) diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index d6117d7..86dd0df 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -40,7 +40,7 @@ void BaS(void) az_sectors = sd_card_init(); - if(az_sectors>0) + if (az_sectors > 0) { sd_card_idle(); } diff --git a/BaS_GNU/sources/sd_card.c b/BaS_GNU/sources/sd_card.c index af22cb6..13b1f2d 100644 --- a/BaS_GNU/sources/sd_card.c +++ b/BaS_GNU/sources/sd_card.c @@ -10,8 +10,8 @@ void sd_card_idle(void) __asm__ __volatile__ ( ".extern sd_idle\n\t" "bsr sd_idle\n\t" - /* input */ : /* output */: + /* input */ : /* clobber */: "a0","a1","a2","a3","a4","a5","a6", "d0","d1","d2","d3","d4","d5","d6","d7","memory" ); @@ -21,6 +21,17 @@ void sd_card_idle(void) int sd_card_init(void) { + register int ret __asm__("d0"); + __asm__ __volatile__ ( + ".extern sd_init\n\t" + "bsr.l sd_init\n\t" + /* output */: "=r" (ret) + /* input */ : + /* clobber */: "a0","a1","a2","a3","a4","a5","a6", + "d1","d2","d3","d4","d5","d6","d7","memory" + ); + + return ret; } diff --git a/BaS_GNU/sources/sd_card_asm.S b/BaS_GNU/sources/sd_card_asm.S index 5d8453d..431f52a 100644 --- a/BaS_GNU/sources/sd_card_asm.S +++ b/BaS_GNU/sources/sd_card_asm.S @@ -11,16 +11,38 @@ #define MCF_PAD_PAR_DSPI (__MBAR+0xA50) #define MCF_PSC0_PSCTB_8BIT (__MBAR+0x860C) #define MCF_DSPI_DMCR (__MBAR+0x8A00) -.text +#define MCF_SLT0_SCNT (__MBAR + 0x908) + +warte_10ms: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #1320000,d0 +warte_d6: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d6 + move.l (sp)+,d0 + rts + +warte_1ms: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #132000,d0 +warte_d5: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d5 + move.l (sp)+,d0 + rts + .text .global sd_idle + .global sd_init -sd_test: +sd_init: lea MCF_PSC0_PSCTB_8BIT,a6 move.l #LONGASC('S', 'D', '-', 'A'),(a6) move.l #LONGASC('a', 'r', 'd', ' '),(a6) - move.l #_Bas_base,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) + move.l buffer,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) move.l #0x1fffffff,d0 // normal dspi move.l d0,MCF_PAD_PAR_DSPI lea MCF_DSPI_DMCR,a0 @@ -30,9 +52,9 @@ sd_test: move.l #0x082000ff,d4 // tx vorbesetzen mov3q.l #-1,dspi_dsr(a0) - bsr.l _wait_1ms + bsr.l warte_1ms move.l #0xc00d3c00,(a0) // 8 bit 4MHz clocken cs off - bsr.l _wait_10ms + bsr.l warte_10ms move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on bsr sd_com bsr sd_com @@ -53,7 +75,7 @@ sd_test: bsr sd_com bsr sd_com move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off - bsr.l _wait_10ms + bsr.l warte_10ms // sd idle move.l #100,d6 // 100 versuche @@ -411,3 +433,6 @@ sd_rcv_rd_rb: bne sd_rcv_rd_rb rts /******************************************/ + + .data +buffer: dc.l 0, 0, 0, 0, 0, 0, 0, 0 From dd8135df4b51ce28ab88c8469cece53b007ac9f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 24 Oct 2012 14:17:02 +0000 Subject: [PATCH 192/276] fixed typo --- BaS_GNU/sources/sd_card_asm.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/BaS_GNU/sources/sd_card_asm.S b/BaS_GNU/sources/sd_card_asm.S index 431f52a..901a2c5 100644 --- a/BaS_GNU/sources/sd_card_asm.S +++ b/BaS_GNU/sources/sd_card_asm.S @@ -13,6 +13,8 @@ #define MCF_DSPI_DMCR (__MBAR+0x8A00) #define MCF_SLT0_SCNT (__MBAR + 0x908) + .text + warte_10ms: move.l d0,-(sp) move.l MCF_SLT0_SCNT,d0 @@ -32,14 +34,13 @@ warte_d5: bcs warte_d5 move.l (sp)+,d0 rts - .text .global sd_idle .global sd_init sd_init: lea MCF_PSC0_PSCTB_8BIT,a6 - move.l #LONGASC('S', 'D', '-', 'A'),(a6) + move.l #LONGASC('S', 'D', '-', 'C'),(a6) move.l #LONGASC('a', 'r', 'd', ' '),(a6) move.l buffer,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) From b033ba948bd1f4ccc31410dac2b6f9db735570f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 24 Oct 2012 19:40:12 +0000 Subject: [PATCH 193/276] fixed alignment for (at least for some) registers that can be used 8, 16 or 32 bit wide --- BaS_GNU/.gdbinit | 8 ++++++++ BaS_GNU/sources/BaS.c | 33 +++++++++++++++++++++++++-------- BaS_GNU/sources/sysinit.c | 2 +- 3 files changed, 34 insertions(+), 9 deletions(-) create mode 100644 BaS_GNU/.gdbinit diff --git a/BaS_GNU/.gdbinit b/BaS_GNU/.gdbinit new file mode 100644 index 0000000..62b7fb0 --- /dev/null +++ b/BaS_GNU/.gdbinit @@ -0,0 +1,8 @@ +set disassemble-next-line on +define tr + target remote | m68k-atari-mint-gdbserver pipe /dev/bdmcf3 +end +tr +source 5474.gdb + + diff --git a/BaS_GNU/sources/BaS.c b/BaS_GNU/sources/BaS.c index 86dd0df..afcae15 100644 --- a/BaS_GNU/sources/BaS.c +++ b/BaS_GNU/sources/BaS.c @@ -9,6 +9,7 @@ #include "startcf.h" #include "cache.h" +#define uart_out_word(a) MCF_PSC3_PSCTB_8BIT = (a) extern uint32_t Bas_base[]; extern uint8_t tos_base[]; @@ -38,34 +39,42 @@ void BaS(void) uint8_t *dst = tos_base; uint32_t *adr; +#ifdef _NOT_USED_ az_sectors = sd_card_init(); if (az_sectors > 0) { sd_card_idle(); } +#endif /* _NOT_USED_ */ /* Initialize the NVRAM */ MCF_PSC3_PSCTB_8BIT = 'ACPF'; wait_10ms(); - MCF_PSC0_PSCTB_8BIT = 'PIC '; + uart_out_word('PIC '); - MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; - MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; - MCF_PSC0_PSCTB_8BIT = MCF_PSC3_PSCRB_8BIT; - MCF_PSC0_PSCTB_8BIT = 0x0d0a; + * (volatile uint8_t *) &_MBAR[0x860C] = (uint8_t) (MCF_PSC3_PSCRB_8BIT); + * (volatile uint8_t *) &_MBAR[0x860C] = (uint8_t) (MCF_PSC3_PSCRB_8BIT); + * (volatile uint8_t *) &_MBAR[0x860C] = (uint8_t) (MCF_PSC3_PSCRB_8BIT); - MCF_PSC3_PSCTB_8BIT = 0x01; /* request RTC data */ + uart_out_word(0x0d0a); - if (MCF_PSC3_PSCRB_8BIT == 0x81) + //MCF_PSC3_PSCTB_8BIT = 0x01; /* request RTC data */ + + * (uint8_t *) &_MBAR[0x890C] = 0x01; + + //if (MCF_PSC3_PSCRB_8BIT == 0x81) + if (* (uint8_t *) &_MBAR[0X890C] == 0x81) { for (i = 0; i < 64; i++) { - * (uint8_t *) 0xffff8963 = MCF_PSC3_PSCRB_8BIT; /* Copy the NVRAM data from the PIC to the FPGA */ + * (uint8_t *) 0xffff8963 = (uint8_t) MCF_PSC3_PSCRB_8BIT; /* Copy the NVRAM data from the PIC to the FPGA */ } + uart_out_word(' OK!'); } + /* copy EMUTOS */ src = (uint8_t *)EMUTOS; while (src < (uint8_t *)(EMUTOS + EMUTOS_SIZE)) @@ -76,9 +85,17 @@ void BaS(void) /* we have copied a code area, so flush the caches */ flush_and_invalidate_caches(); + uart_out_word('MMU '); mmu_init(); + uart_out_word(' OK!'); + + uart_out_word('EXC '); vec_init(); + uart_out_word(' OK!'); + + uart_out_word('ILLG'); illegal_table_make(); + uart_out_word(' OK!'); /* interrupts */ diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index a58c6ba..84b2ec3 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -73,7 +73,7 @@ void wait_1us(void) void init_slt(void) { MCF_SLT0_STCNT = 0xffffffff; - MCF_SLT0_SCR = 0x05; + MCF_SLT0_SCR = 0x05000000; uart_out_word('SLT '); uart_out_word('OK! '); From 02f5ee92f6eaf9d864c84dc616555744017dbb71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 25 Oct 2012 06:32:04 +0000 Subject: [PATCH 194/276] fixed comments --- BaS_GNU/sources/sysinit.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/BaS_GNU/sources/sysinit.c b/BaS_GNU/sources/sysinit.c index 84b2ec3..c9e9fb3 100644 --- a/BaS_GNU/sources/sysinit.c +++ b/BaS_GNU/sources/sysinit.c @@ -160,13 +160,14 @@ void init_serial(void) /********************************************************************/ /* Initialize DDR DIMMs on the EVB board */ /********************************************************************/ -/* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ void init_ddram(void) { uart_out_word('DDRA'); + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) { /* Basic configuration and initialization */ MCF_SDRAMC_SDRAMDS = 0x000002AA; // SDRAMDS configuration @@ -420,7 +421,7 @@ void test_upd720101(void) */ void dvi_on(void) { uint8_t RBYT; - uint8_t DBYT; /* FIXME: produces a warning about being unused when it is in fact (for a dummy read) */ + uint8_t DBYT; /* only used for a dummy read */ int tries; uart_out_word('DVI '); From 5bbda57debf47cf41063bfbf6549442bccab2a9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 25 Oct 2012 12:01:48 +0000 Subject: [PATCH 195/276] added free (BSD-source) tiny-printf to support better diagnostic messages --- BaS_GNU/.cproject | 63 ++++-- BaS_GNU/.project | 4 + BaS_GNU/Makefile | 5 + BaS_GNU/bas.lk.in | 2 + BaS_GNU/include/printf.h | 9 + BaS_GNU/sources/printf.c | 376 ++++++++++++++++++++++++++++++++ BaS_GNU/sources/printf_helper.S | 8 + 7 files changed, 444 insertions(+), 23 deletions(-) create mode 100644 BaS_GNU/include/printf.h create mode 100644 BaS_GNU/sources/printf.c create mode 100644 BaS_GNU/sources/printf_helper.S diff --git a/BaS_GNU/.cproject b/BaS_GNU/.cproject index 096d23a..6d797d4 100644 --- a/BaS_GNU/.cproject +++ b/BaS_GNU/.cproject @@ -51,7 +51,12 @@