diff --git a/BaS_gcc/.cproject b/BaS_gcc/.cproject new file mode 100644 index 0000000..54c8f8f --- /dev/null +++ b/BaS_gcc/.cproject @@ -0,0 +1,150 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + make + + all + true + true + true + + + make + clean + true + true + true + + + make + + ram + true + true + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/BaS_gcc/.gdbinit b/BaS_gcc/.gdbinit new file mode 100644 index 0000000..1a0b467 --- /dev/null +++ b/BaS_gcc/.gdbinit @@ -0,0 +1,12 @@ +set disassemble-next-line on +define tr + target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3 +end +define tbtr + target remote | m68k-bdm-gdbserver pipe /dev/tblcf3 +end + +tr +source mcf5474.gdb + + diff --git a/BaS_gcc/.project b/BaS_gcc/.project new file mode 100644 index 0000000..dda49c4 --- /dev/null +++ b/BaS_gcc/.project @@ -0,0 +1,66 @@ + + + BaS_gcc + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/BaS_gcc/.settings/org.eclipse.cdt.codan.core.prefs b/BaS_gcc/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..1a2799f --- /dev/null +++ b/BaS_gcc/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,66 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true},implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true}} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true},implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true}} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true}} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true},no_break_comment\=>"no break",last_case_param\=>true,empty_case_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true},unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info +org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true},pattern\=>"^[a-z]",macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning 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+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true}} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true}} +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning +org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true},macro\=>true,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true},paramNot\=>false} +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning +org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true},else\=>false,afterelse\=>false} +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true},macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true},macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning 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+org.eclipse.cdt.core.formatter.brace_position_for_array_initializer=next_line +org.eclipse.cdt.core.formatter.brace_position_for_block=next_line +org.eclipse.cdt.core.formatter.brace_position_for_block_in_case=next_line +org.eclipse.cdt.core.formatter.brace_position_for_method_declaration=next_line +org.eclipse.cdt.core.formatter.brace_position_for_namespace_declaration=next_line +org.eclipse.cdt.core.formatter.brace_position_for_switch=next_line +org.eclipse.cdt.core.formatter.brace_position_for_type_declaration=next_line +org.eclipse.cdt.core.formatter.comment.min_distance_between_code_and_line_comment=1 +org.eclipse.cdt.core.formatter.comment.preserve_white_space_between_code_and_line_comments=false +org.eclipse.cdt.core.formatter.compact_else_if=true +org.eclipse.cdt.core.formatter.continuation_indentation=2 +org.eclipse.cdt.core.formatter.continuation_indentation_for_array_initializer=2 +org.eclipse.cdt.core.formatter.format_guardian_clause_on_one_line=false +org.eclipse.cdt.core.formatter.indent_access_specifier_compare_to_type_header=false +org.eclipse.cdt.core.formatter.indent_access_specifier_extra_spaces=0 +org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_access_specifier=true +org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_namespace_header=false +org.eclipse.cdt.core.formatter.indent_breaks_compare_to_cases=true +org.eclipse.cdt.core.formatter.indent_declaration_compare_to_template_header=false +org.eclipse.cdt.core.formatter.indent_empty_lines=false +org.eclipse.cdt.core.formatter.indent_statements_compare_to_block=true +org.eclipse.cdt.core.formatter.indent_statements_compare_to_body=true +org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_cases=true +org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_switch=false +org.eclipse.cdt.core.formatter.indentation.size=4 +org.eclipse.cdt.core.formatter.insert_new_line_after_opening_brace_in_array_initializer=do not insert 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+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_invocation=do not insert +org.eclipse.cdt.core.formatter.join_wrapped_lines=true +org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line=false +org.eclipse.cdt.core.formatter.keep_empty_array_initializer_on_one_line=false +org.eclipse.cdt.core.formatter.keep_imple_if_on_one_line=false +org.eclipse.cdt.core.formatter.keep_then_statement_on_same_line=false +org.eclipse.cdt.core.formatter.lineSplit=80 +org.eclipse.cdt.core.formatter.number_of_empty_lines_to_preserve=1 +org.eclipse.cdt.core.formatter.put_empty_statement_on_new_line=true +org.eclipse.cdt.core.formatter.tabulation.char=tab +org.eclipse.cdt.core.formatter.tabulation.size=4 +org.eclipse.cdt.core.formatter.use_tabs_only_for_leading_indentations=false diff --git a/BaS_gcc/.settings/org.eclipse.cdt.ui.prefs b/BaS_gcc/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 0000000..48a50c7 --- /dev/null +++ b/BaS_gcc/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +formatter_profile=org.eclipse.cdt.ui.default.allman_profile +formatter_settings_version=1 diff --git a/BaS_gcc/.settings/org.eclipse.ltk.core.refactoring.prefs b/BaS_gcc/.settings/org.eclipse.ltk.core.refactoring.prefs new file mode 100644 index 0000000..b196c64 --- /dev/null +++ b/BaS_gcc/.settings/org.eclipse.ltk.core.refactoring.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false diff --git a/BaS_gcc/Makefile b/BaS_gcc/Makefile new file mode 100644 index 0000000..676e5c9 --- /dev/null +++ b/BaS_gcc/Makefile @@ -0,0 +1,117 @@ +# +# Makefile for Firebee BaS +# +# This Makefile is meant for cross compiling the BaS with Vincent Riviere's cross compilers. +# If you want to compile native on an Atari (you will need at least GCC 4.6.3), set +# TCPREFIX to be empty. +# If you want to compile with the m68k-elf- toolchain, set TCPREFIX accordingly. Requires an extra +# installation, but allows source level debugging over BDM with a recent gdb (tested with 7.5), +# the m68k BDM tools from sourceforge (http://bdm.sourceforge.net) and a BDM pod (TBLCF and P&E tested). + +# can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint +# toolchain +COMPILE_ELF=Y + +ifeq (Y,$(COMPILE_ELF)) +TCPREFIX=m68k-elf- +EXE=elf +FORMAT=elf32-m68k +else +TCPREFIX=m68k-atari-mint- +EXE=s19 +FORMAT=srec +endif + +CC=$(TCPREFIX)gcc +LD=$(TCPREFIX)ld +CPP=$(TCPREFIX)cpp +OBJCOPY=$(TCPREFIX)objcopy + +INCLUDE=-Iinclude +CFLAGS=-mcpu=5474\ + -Wall\ + -g\ + -Wno-multichar\ + -Os\ + -fomit-frame-pointer\ + -fno-strict-aliasing\ + -ffreestanding\ + -fleading-underscore\ + -Wa,--register-prefix-optional + +SRCDIR=sources +OBJDIR=objs + +MAPFILE=bas.map + +# Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC) +LDCFILE=bas.lk +LDCSRC=bas.lk.in + +# this Makefile can create the BaS to flash or an arbitrary ram address (for BDM debugging). See +# below for the definition of TARGET_ADDRESS +FLASH_EXEC=bas.$(EXE) +RAM_EXEC=ram.$(EXE) + +CSRCS= \ + $(SRCDIR)/sysinit.c \ + $(SRCDIR)/init_fpga.c \ + $(SRCDIR)/bas_printf.c \ + $(SRCDIR)/BaS.c \ + $(SRCDIR)/cache.c \ + $(SRCDIR)/sd_card.c + +ASRCS= \ + $(SRCDIR)/startcf.S \ + $(SRCDIR)/printf_helper.S \ + $(SRCDIR)/mmu.S \ + $(SRCDIR)/sd_card_asm.S \ + $(SRCDIR)/exceptions.S \ + $(SRCDIR)/supervisor.S \ + $(SRCDIR)/ewf.S \ + $(SRCDIR)/illegal_instruction.S + +COBJS=$(patsubst $(SRCDIR)/%.o,$(OBJDIR)/%.o,$(patsubst %.c,%.o,$(CSRCS))) +AOBJS=$(patsubst $(SRCDIR)/%.o,$(OBJDIR)/%.o,$(patsubst %.S,%.o,$(ASRCS))) + +OBJS=$(COBJS) $(AOBJS) + +all: $(FLASH_EXEC) +ram: $(RAM_EXEC) +.PHONY clean: + @ rm -f $(FLASH_EXEC) $(FLASH_EXEC).elf $(FLASH_EXEC).s19\ + $(RAM_EXEC) $(RAM_EXEC).elf $(RAM_EXEC).s19\ + $(OBJS) $(MAPFILE) $(LDCFILE) depend + +$(FLASH_EXEC): TARGET_ADDRESS=0xe0000000 +$(RAM_EXEC): TARGET_ADDRESS=0x10000000 + +$(FLASH_EXEC) $(RAM_EXEC): $(OBJS) $(LDCSRC) + $(CPP) -P -DTARGET_ADDRESS=$(TARGET_ADDRESS) -DFORMAT=$(FORMAT) $(LDCSRC) -o $(LDCFILE) + $(LD) --oformat $(FORMAT) -Map $(MAPFILE) --cref -T $(LDCFILE) -o $@ +ifeq ($(COMPILE_ELF),Y) + $(OBJCOPY) -O srec $@ $@.s19 +else + objcopy -I srec -O elf32-big --alt-machine-code 4 $@ $@.elf +endif + +# compile init_fpga with -mbitfield for testing purposes +$(OBJDIR)/init_fpga.o: CFLAGS += -mbitfield + +# compile printf pc-relative so it can be used as well before and after copy of BaS +$(OBJDIR)/bas_printf.o: CFLAGS += -mpcrel +# the same for flush_and_invalidate_cache() +$(OBJDIR)/cache.o: CFLAGS += -mpcrel + +$(OBJDIR)/%.o:$(SRCDIR)/%.c + $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ + +$(OBJDIR)/%.o:$(SRCDIR)/%.S + $(CC) -c $(CFLAGS) -Wa,--bitwise-or $(INCLUDE) $< -o $@ + +depend: $(ASRCS) $(CSRCS) + $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) > depend + +ifneq (clean,$(MAKECMDGOALS)) +-include depend +endif diff --git a/BaS_gcc/bas.lk.in b/BaS_gcc/bas.lk.in new file mode 100644 index 0000000..e69f739 --- /dev/null +++ b/BaS_gcc/bas.lk.in @@ -0,0 +1,137 @@ +MEMORY +{ + bas_rom (RX) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00200000 + bas_ram (WX) : ORIGIN = 0x1FE00000, LENGTH = 0x00100000 /* target to copy BaS to */ +} + +SECTIONS +{ + /* BaS in ROM */ + .text : + { + objs/startcf.o(.text) /* this one is the entry point so it must be the first */ + objs/sysinit.o(.text) + objs/init_fpga.o(.text) +#if (FORMAT == elf32-m68k) + *(.rodata) + *(.rodata.*) +#endif + } > bas_rom + + /* BaS in RAM */ + .bas : + /* The BaS is stored in the flash, just after the init part. + * Then it will be copied to its final location in the RAM. + * This data must be aligned for optimal copy loop speed. + */ + AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4)) + { + objs/BaS.o(.text) + /* put other routines into the same segment (RAM) as BaS.o */ + objs/sd_card_asm.o(.text) + objs/bas_printf.o(.text) + objs/printf_helper.o(.text) + objs/cache.o(.text) + objs/sd_card.o(.text) + objs/mmu.o(.text) + objs/exceptions.o(.text) + objs/supervisor.o(.text) + objs/ewf.o(.text) + objs/illegal_instruction.o(.text) + *(.data) + *(.bss) + + /* The BaS copy routine assumes that tha BaS size + * is a multiple of the following value. + */ + . = ALIGN(16); + } > bas_ram + + /* The following labels are BaS routines in the flash, + * before they are copied to their final location in the RAM. + * This is to allow using them before and after the actual copy. + * Hence they must contain only pc-relative code (compiled with -mpcrel). + */ +#define BAS_LABEL_LMA(x) ((x) + (__BAS_LMA - __BAS_IN_RAM)) + _xprintf_before_copy = BAS_LABEL_LMA(_xprintf); + _display_progress_before_copy = BAS_LABEL_LMA(_display_progress); + _flush_and_invalidate_caches_before_copy = BAS_LABEL_LMA(_flush_and_invalidate_caches); + + /* + * Global memory map + */ + + /* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */ + ___SDRAM = 0x00000000; + ___SDRAM_SIZE = 0x20000000; + + /* ST-RAM */ + __STRAM = ___SDRAM; + __STRAM_END = __TOS; + + /* TOS */ + __TOS = 0x00e00000; + + /* FastRAM */ + __FASTRAM = 0x10000000; + __FASTRAM_END = __BAS_IN_RAM; + + /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */ + ___BOOT_FLASH = 0xe0000000; + ___BOOT_FLASH_SIZE = 0x00800000; + + /* BaS */ + __BAS_LMA = LOADADDR(.bas); + __BAS_IN_RAM = ADDR(.bas); + __BAS_SIZE = SIZEOF(.bas); + + /* Other flash components */ + __FIRETOS = 0xe0400000; + __EMUTOS = 0xe0600000; + __EMUTOS_SIZE = 0x00100000; + + /* VIDEO RAM BASIS */ + __VRAM = 0x60000000; + + /* Memory mapped registers */ + __MBAR = 0xFF000000; + + /* 32KB on-chip System SRAM */ + __SYS_SRAM = 0xFF010000; + __SYS_SRAM_SIZE = 0x00008000; + + /* MMU memory mapped registers */ + __MMUBAR = 0xFF040000; + + /* + * 4KB on-chip Core SRAM0: -> exception table and exception stack + */ + __RAMBAR0 = 0xFF100000; + __RAMBAR0_SIZE = 0x00001000; + __SUP_SP = __RAMBAR0 + __RAMBAR0_SIZE - 4; + + /* system variables */ + + /* RAMBAR0 0 to 0x7FF -> exception vectors */ + _rt_mod = __RAMBAR0 + 0x800; + _rt_ssp = __RAMBAR0 + 0x804; + _rt_usp = __RAMBAR0 + 0x808; + _rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */ + _rt_cacr = __RAMBAR0 + 0x810; /* 002 */ + _rt_asid = __RAMBAR0 + 0x814; /* 003 */ + _rt_acr0 = __RAMBAR0 + 0x818; /* 004 */ + _rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */ + _rt_acr2 = __RAMBAR0 + 0x820; /* 006 */ + _rt_acr3 = __RAMBAR0 + 0x824; /* 007 */ + _rt_mmubar = __RAMBAR0 + 0x828; /* 008 */ + _rt_sr = __RAMBAR0 + 0x82c; + _d0_save = __RAMBAR0 + 0x830; + _a7_save = __RAMBAR0 + 0x834; + _video_tlb = __RAMBAR0 + 0x838; + _video_sbt = __RAMBAR0 + 0x83C; + _rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */ + + /* 4KB on-chip Core SRAM1: -> modified code */ + __RAMBAR1 = 0xFF101000; + __RAMBAR1_SIZE = 0x00001000; +} diff --git a/BaS_gcc/cfg/DDRAM.cfg b/BaS_gcc/cfg/DDRAM.cfg new file mode 100644 index 0000000..7545850 --- /dev/null +++ b/BaS_gcc/cfg/DDRAM.cfg @@ -0,0 +1,57 @@ +; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture +; $RCSfile: M5475EVB.cfg,v $ +; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $ +; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file. + +ResetHalt + +;Set VBR - debugger must know this in order +; to do exception capture +writecontrolreg 0x0801 0x00000000 + +; If MBAR changes all following writes must change +; and if a memory configuration file is used, +; the reserved areas in the register block must +; change also. +;Turn on MBAR at 0xFF00_0000 +writecontrolreg 0x0C0F 0xFF000000 + +;Turn on RAMBAR0 at address FF10_0000 +writecontrolreg 0x0C04 0xFF100035 + +;Turn on RAMBAR1 at address FF10_1000 +writecontrolreg 0x0C05 0xFF101035 + +;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +writemem.l 0xFF000500 0xE0000000; +writemem.l 0xFF000508 0x00101980; 16-bit port +writemem.l 0xFF000504 0x007F0001; + +;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration +writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF) +writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +;writemem.l 0xFF000108 0x73611730; SDCFG1 +writemem.l 0xFF000108 0x53611730; SDCFG1 +;writemem.l 0xFF00010C 0x46770000; SDCFG2 +writemem.l 0xFF00010C 0x24730000; SDCFG2 + +;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR) +;writemem.l 0xFF000100 0x048D0000; SDMR (write to LMR) +writemem.l 0xFF000100 0x04890000; SDMR (write to LMR) +;writemem.l 0xFF000104 0xE10D0002; SDCR + IPALL +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (first refresh) +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh) +;writemem.l 0xFF000104 0xE10D0004; SDCR + IREF (second refresh) +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh) +;writemem.l 0xFF000100 0x008D0000; SDMR (write to LMR) +writemem.l 0xFF000100 0x00890000; SDMR (write to LMR) +;writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh) +writemem.l 0xFF000104 0x71100F00; SDCR (lock SDMR and enable refresh) + +delay 1000 diff --git a/BaS_gcc/cfg/DDRAM.mem b/BaS_gcc/cfg/DDRAM.mem new file mode 100644 index 0000000..1bc400b --- /dev/null +++ b/BaS_gcc/cfg/DDRAM.mem @@ -0,0 +1,47 @@ +// Memory Configuration File +// +// Description: +// A memory configuration file contains commands that define the legally accessible +// areas of memory for your specific board. Useful for example when the debugger +// tries to display the content of a "char *" variable, that has not yet been initialized. +// In this case the debugger may try to read from a bogus address, which could cause a +// bus error. +// +// Board: +// LogicPD COLDARI1 +// +// Reference: +// MCF5475RM.pdf + + +// All reserved ranges read back 0xBABA... +reservedchar 0xBA + +address MBAR_BASE 0xFF000000 +address MMUBAR_BASE 0xFF040000 + +usederivative "MCF5475" + +// Memory Map: +// ---------------------------------------------------------------------- +range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM +reserved 0x20000000 0x5FFFFFFF + +range 0x60000000 0x7FFFFFFF 4 ReadWrite + +range 0x80000000 0xCFFFFFFF 4 ReadWrite + +range 0xD0000000 0xFBFFFFFF 4 ReadWrite + +reserved 0xFC000000 $MBAR_BASE-1 + + $MBAR_BASE $MBAR_BASE+0x3FFFF // Memory Mapped Registers +range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM + +range $MMUBAR_BASE $MMUBAR_BASE+0xFFFF +reserved $MMUBAR_BASE+1x0000 0xFF0FFFFF // Added to fill gap in MMR + +range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0) +range 0xFF101000 0xFFFFFFFF 4 ReadWrite // 4K SRAM1 (RAMBAR1) + + diff --git a/BaS_gcc/cfg/flash.cfg b/BaS_gcc/cfg/flash.cfg new file mode 100644 index 0000000..cfa2772 --- /dev/null +++ b/BaS_gcc/cfg/flash.cfg @@ -0,0 +1,11 @@ +; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture +; $RCSfile: M5475EVB.cfg,v $ +; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $ +; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file. + + +;Init CS0 (BootFLASH @ FE00_0000 - FE7F_FFFF 8Mbytes) +writemem.l 0xFF000500 0xFE000000; +writemem.l 0xFF000508 0x00101980; 16-bit port +writemem.l 0xFF000504 0x007F0001; + diff --git a/BaS_gcc/cfg/mem.cfg b/BaS_gcc/cfg/mem.cfg new file mode 100644 index 0000000..20830c0 --- /dev/null +++ b/BaS_gcc/cfg/mem.cfg @@ -0,0 +1,48 @@ +; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture +; $RCSfile: M5475EVB.cfg,v $ +; $Revision: 1.4 $ $Date: 2008/01/09 11:46:41 $ +; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file. + +ResetHalt + +;Set VBR - debugger must know this in order +; to do exception capture +writecontrolreg 0x0801 0x00000000 + +; If MBAR changes all following writes must change +; and if a memory configuration file is used, +; the reserved areas in the register block must +; change also. +;Turn on MBAR at 0xFF00_0000 +writecontrolreg 0x0C0F 0xFF000000 + +;Turn on RAMBAR0 at address FF10_0000 +writecontrolreg 0x0C04 0xFF100035 + +;Turn on RAMBAR1 at address FF10_1000 +writecontrolreg 0x0C05 0xFF101035 + +;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +writemem.l 0xFF000500 0xE0000000; +writemem.l 0xFF000508 0x00001180; 16-bit port +writemem.l 0xFF000504 0x007F0001; + +;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +writemem.l 0xFF000004 0x000002AA; SDRAMDS configuration +writemem.l 0xFF000020 0x0000001A; SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +writemem.l 0xFF000024 0x0800001A; SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +writemem.l 0xFF000028 0x1000001A; SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +writemem.l 0xFF00002C 0x1800001A; SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +writemem.l 0xFF000108 0x53722938; SDCFG1 +writemem.l 0xFF00010C 0x24330000; SDCFG2 + +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +writemem.l 0xFF000100 0x40010000; SDMR (write to LEMR) +writemem.l 0xFF000100 0x05890000; SDRM (write to LMR) +writemem.l 0xFF000104 0xE10F0002; SDCR + IPALL +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (first refresh) +writemem.l 0xFF000104 0xE10F0004; SDCR + IREF (second refresh) +writemem.l 0xFF000100 0x01890000; SDMR (write to LMR) +writemem.l 0xFF000104 0x710F0F00; SDCR (lock SDMR and enable refresh) + +delay 1000 diff --git a/BaS_gcc/cfg/mem.mem b/BaS_gcc/cfg/mem.mem new file mode 100644 index 0000000..46bda65 --- /dev/null +++ b/BaS_gcc/cfg/mem.mem @@ -0,0 +1,38 @@ +// Memory Configuration File +// +// Description: +// A memory configuration file contains commands that define the legally accessible +// areas of memory for your specific board. Useful for example when the debugger +// tries to display the content of a "char *" variable, that has not yet been initialized. +// In this case the debugger may try to read from a bogus address, which could cause a +// bus error. +// +// Board: +// LogicPD COLDARI1 +// +// Reference: +// MCF5475RM.pdf + + +// All reserved ranges read back 0xBABA... +reservedchar 0xBA + +address MBAR_BASE 0xFF000000 +address MMUBAR_BASE 0xFF040000 + +usederivative "MCF5475" + +// Memory Map: +// ---------------------------------------------------------------------- +range 0x00000000 0x1FFFFFFF 4 ReadWrite // 512MB DDR SDRAM +reserved 0x20000000 $MBAR_BASE-1 + + $MBAR_BASE $MBAR_BASE+0x3FFFF 4 ReadWrite // Memory Mapped Registers +range $MBAR_BASE+0x10000 $MBAR_BASE+0x17FFC 4 ReadWrite // 32K Internal SRAM +reserved $MBAR_BASE+0x17FFD $MBAR_BASE+0x1FFBF + + $MMUBAR_BASE $MMUBAR_BASE+0x001B +reserved $MMUBAR_BASE+0x001C 0xFF0FFFFF + +range 0xFF100000 0xFF100FFF 4 ReadWrite // 4K SRAM0 (RAMBAR0) +range 0xFF101000 0xFF101FFF 4 ReadWrite // 4K SRAM1 (RAMBAR1) diff --git a/BaS_gcc/include/MCF5475.h b/BaS_gcc/include/MCF5475.h new file mode 100644 index 0000000..fa08e81 --- /dev/null +++ b/BaS_gcc/include/MCF5475.h @@ -0,0 +1,65 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_H__ +#define __MCF5475_H__ + +#include +/*** + * MCF5475 Derivative Memory map definitions from linker command files: + * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE + * linker symbols must be defined in the linker command file. + */ + +extern uint8_t _MBAR[]; +extern uint8_t _MMUBAR[]; +extern uint8_t _RAMBAR0[]; +extern uint8_t _RAMBAR0_SIZE[]; +extern uint8_t _RAMBAR1[]; +extern uint8_t _RAMBAR1_SIZE[]; + +#define MBAR_ADDRESS (uint32_t)_MBAR +#define MMUBAR_ADDRESS (uint32_t)_MMUBAR +#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0 +#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE +#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1 +#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE + + +#include "MCF5475_SIU.h" +#include "MCF5475_MMU.h" +#include "MCF5475_SDRAMC.h" +#include "MCF5475_XLB.h" +#include "MCF5475_CLOCK.h" +#include "MCF5475_FBCS.h" +#include "MCF5475_INTC.h" +#include "MCF5475_GPT.h" +#include "MCF5475_SLT.h" +#include "MCF5475_GPIO.h" +#include "MCF5475_PAD.h" +#include "MCF5475_PCI.h" +#include "MCF5475_PCIARB.h" +#include "MCF5475_EPORT.h" +#include "MCF5475_CTM.h" +#include "MCF5475_DMA.h" +#include "MCF5475_PSC.h" +#include "MCF5475_DSPI.h" +#include "MCF5475_I2C.h" +#include "MCF5475_FEC.h" +#include "MCF5475_USB.h" +#include "MCF5475_SRAM.h" +#include "MCF5475_SEC.h" + +#endif /* __MCF5475_H__ */ diff --git a/BaS_gcc/include/MCF5475_CLOCK.h b/BaS_gcc/include/MCF5475_CLOCK.h new file mode 100644 index 0000000..4603098 --- /dev/null +++ b/BaS_gcc/include/MCF5475_CLOCK.h @@ -0,0 +1,47 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CLOCK_H__ +#define __MCF5475_CLOCK_H__ + + +/********************************************************************* +* +* Clock Module (CLOCK) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300])) + + +/* Bit definitions and macros for MCF_CLOCK_SPCR */ +#define MCF_CLOCK_SPCR_MEMEN (0x1) +#define MCF_CLOCK_SPCR_PCIEN (0x2) +#define MCF_CLOCK_SPCR_FBEN (0x4) +#define MCF_CLOCK_SPCR_CAN0EN (0x8) +#define MCF_CLOCK_SPCR_DMAEN (0x10) +#define MCF_CLOCK_SPCR_FEC0EN (0x20) +#define MCF_CLOCK_SPCR_FEC1EN (0x40) +#define MCF_CLOCK_SPCR_USBEN (0x80) +#define MCF_CLOCK_SPCR_PSCEN (0x200) +#define MCF_CLOCK_SPCR_CAN1EN (0x800) +#define MCF_CLOCK_SPCR_CRYENA (0x1000) +#define MCF_CLOCK_SPCR_CRYENB (0x2000) +#define MCF_CLOCK_SPCR_COREN (0x4000) +#define MCF_CLOCK_SPCR_PLLK (0x80000000) + + +#endif /* __MCF5475_CLOCK_H__ */ diff --git a/BaS_gcc/include/MCF5475_CTM.h b/BaS_gcc/include/MCF5475_CTM.h new file mode 100644 index 0000000..5ba86e4 --- /dev/null +++ b/BaS_gcc/include/MCF5475_CTM.h @@ -0,0 +1,76 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_CTM_H__ +#define __MCF5475_CTM_H__ + + +/********************************************************************* +* +* Comm Timer Module (CTM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00])) +#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04])) +#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08])) +#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C])) +#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10])) +#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14])) +#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18])) +#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C])) +#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)])) +#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)])) + + +/* Bit definitions and macros for MCF_CTM_CTCRF */ +#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0) +#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10) +#define MCF_CTM_CTCRF_S_CLK_1 (0) +#define MCF_CTM_CTCRF_S_CLK_2 (0x10000) +#define MCF_CTM_CTCRF_S_CLK_4 (0x20000) +#define MCF_CTM_CTCRF_S_CLK_8 (0x30000) +#define MCF_CTM_CTCRF_S_CLK_16 (0x40000) +#define MCF_CTM_CTCRF_S_CLK_32 (0x50000) +#define MCF_CTM_CTCRF_S_CLK_64 (0x60000) +#define MCF_CTM_CTCRF_S_CLK_128 (0x70000) +#define MCF_CTM_CTCRF_S_CLK_256 (0x80000) +#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000) +#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14) +#define MCF_CTM_CTCRF_PCT_100 (0) +#define MCF_CTM_CTCRF_PCT_50 (0x100000) +#define MCF_CTM_CTCRF_PCT_25 (0x200000) +#define MCF_CTM_CTCRF_PCT_12p5 (0x300000) +#define MCF_CTM_CTCRF_PCT_6p25 (0x400000) +#define MCF_CTM_CTCRF_PCT_OFF (0x500000) +#define MCF_CTM_CTCRF_M (0x800000) +#define MCF_CTM_CTCRF_IM (0x1000000) +#define MCF_CTM_CTCRF_I (0x80000000) + +/* Bit definitions and macros for MCF_CTM_CTCRV */ +#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0) +#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18) +#define MCF_CTM_CTCRV_PCT_100 (0) +#define MCF_CTM_CTCRV_PCT_50 (0x1000000) +#define MCF_CTM_CTCRV_PCT_25 (0x2000000) +#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000) +#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000) +#define MCF_CTM_CTCRV_PCT_OFF (0x5000000) +#define MCF_CTM_CTCRV_M (0x8000000) +#define MCF_CTM_CTCRV_S (0x10000000) + + +#endif /* __MCF5475_CTM_H__ */ diff --git a/BaS_gcc/include/MCF5475_DMA.h b/BaS_gcc/include/MCF5475_DMA.h new file mode 100644 index 0000000..3334cca --- /dev/null +++ b/BaS_gcc/include/MCF5475_DMA.h @@ -0,0 +1,202 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DMA_H__ +#define __MCF5475_DMA_H__ + + +/********************************************************************* +* +* Multichannel DMA (DMA) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000])) +#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004])) +#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008])) +#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C])) +#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010])) +#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014])) +#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018])) +#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C])) +#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E])) +#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020])) +#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022])) +#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024])) +#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026])) +#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028])) +#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A])) +#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C])) +#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E])) +#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030])) +#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032])) +#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034])) +#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036])) +#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038])) +#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A])) +#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C])) +#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D])) +#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E])) +#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F])) +#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040])) +#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041])) +#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042])) +#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043])) +#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044])) +#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045])) +#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046])) +#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047])) +#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048])) +#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049])) +#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A])) +#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B])) +#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C])) +#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D])) +#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E])) +#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F])) +#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050])) +#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051])) +#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052])) +#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053])) +#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054])) +#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055])) +#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056])) +#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057])) +#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058])) +#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059])) +#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A])) +#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B])) +#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C])) +#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060])) +#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064])) +#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070])) +#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074])) +#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078])) +#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)])) +#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)])) + + +/* Bit definitions and macros for MCF_DMA_TASKBAR */ +#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_CP */ +#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_EP */ +#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_VP */ +#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_PTD */ +#define MCF_DMA_PTD_PCTL0 (0x1) +#define MCF_DMA_PTD_PCTL1 (0x2) +#define MCF_DMA_PTD_PCTL13 (0x2000) +#define MCF_DMA_PTD_PCTL14 (0x4000) +#define MCF_DMA_PTD_PCTL15 (0x8000) + +/* Bit definitions and macros for MCF_DMA_DIPR */ +#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DIMR */ +#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_TCR */ +#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0) +#define MCF_DMA_TCR_HLDINITNUM (0x20) +#define MCF_DMA_TCR_HIPRITSKEN (0x40) +#define MCF_DMA_TCR_ASTRT (0x80) +#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8) +#define MCF_DMA_TCR_ALWINIT (0x2000) +#define MCF_DMA_TCR_V (0x4000) +#define MCF_DMA_TCR_EN (0x8000) + +/* Bit definitions and macros for MCF_DMA_PRIOR */ +#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0) +#define MCF_DMA_PRIOR_HLD (0x80) + +/* Bit definitions and macros for MCF_DMA_IMCR */ +#define MCF_DMA_IMCR_IMC0(x) (((x)&0x3)<<0) +#define MCF_DMA_IMCR_IMC1(x) (((x)&0x3)<<0x2) +#define MCF_DMA_IMCR_IMC2(x) (((x)&0x3)<<0x4) +#define MCF_DMA_IMCR_IMC3(x) (((x)&0x3)<<0x6) +#define MCF_DMA_IMCR_IMC4(x) (((x)&0x3)<<0x8) +#define MCF_DMA_IMCR_IMC5(x) (((x)&0x3)<<0xA) +#define MCF_DMA_IMCR_IMC6(x) (((x)&0x3)<<0xC) +#define MCF_DMA_IMCR_IMC7(x) (((x)&0x3)<<0xE) +#define MCF_DMA_IMCR_IMC8(x) (((x)&0x3)<<0x10) +#define MCF_DMA_IMCR_IMC9(x) (((x)&0x3)<<0x12) +#define MCF_DMA_IMCR_IMC10(x) (((x)&0x3)<<0x14) +#define MCF_DMA_IMCR_IMC11(x) (((x)&0x3)<<0x16) +#define MCF_DMA_IMCR_IMC12(x) (((x)&0x3)<<0x18) +#define MCF_DMA_IMCR_IMC13(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_IMCR_IMC14(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_IMCR_IMC15(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_TSKSZ0 */ +#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_TSKSZ1 */ +#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0) +#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2) +#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4) +#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6) +#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8) +#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA) +#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC) +#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE) +#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10) +#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12) +#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14) +#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16) +#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18) +#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A) +#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C) +#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */ +#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */ +#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DMA_DBGCTL */ +#define MCF_DMA_DBGCTL_I (0x2) +#define MCF_DMA_DBGCTL_E (0x4) +#define MCF_DMA_DBGCTL_AND_OR (0x80) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8) +#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB) +#define MCF_DMA_DBGCTL_B (0x4000) +#define MCF_DMA_DBGCTL_AA (0x8000) +#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_DMA_H__ */ diff --git a/BaS_gcc/include/MCF5475_DSPI.h b/BaS_gcc/include/MCF5475_DSPI.h new file mode 100644 index 0000000..76cac28 --- /dev/null +++ b/BaS_gcc/include/MCF5475_DSPI.h @@ -0,0 +1,150 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_DSPI_H__ +#define __MCF5475_DSPI_H__ + + +/********************************************************************* +* +* DMA Serial Peripheral Interface (DSPI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00])) +#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08])) +#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C])) +#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10])) +#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14])) +#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18])) +#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C])) +#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20])) +#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24])) +#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28])) +#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C])) +#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30])) +#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34])) +#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38])) +#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C])) +#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40])) +#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44])) +#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48])) +#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C])) +#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80])) +#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84])) +#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88])) +#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)])) +#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)])) +#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_DSPI_DMCR */ +#define MCF_DSPI_DMCR_HALT (0x1) +#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8) +#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0) +#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100) +#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200) +#define MCF_DSPI_DMCR_CRXF (0x400) +#define MCF_DSPI_DMCR_CTXF (0x800) +#define MCF_DSPI_DMCR_DRXF (0x1000) +#define MCF_DSPI_DMCR_DTXF (0x2000) +#define MCF_DSPI_DMCR_CSIS0 (0x10000) +#define MCF_DSPI_DMCR_CSIS2 (0x40000) +#define MCF_DSPI_DMCR_CSIS3 (0x80000) +#define MCF_DSPI_DMCR_CSIS5 (0x200000) +#define MCF_DSPI_DMCR_ROOE (0x1000000) +#define MCF_DSPI_DMCR_PCSSE (0x2000000) +#define MCF_DSPI_DMCR_MTFE (0x4000000) +#define MCF_DSPI_DMCR_FRZ (0x8000000) +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C) +#define MCF_DSPI_DMCR_CSCK (0x40000000) +#define MCF_DSPI_DMCR_MSTR (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTCR */ +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DCTAR */ +#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10) +#define MCF_DSPI_DCTAR_PBR_1CLK (0) +#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000) +#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000) +#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000) +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12) +#define MCF_DSPI_DCTAR_PDT_1CLK (0) +#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000) +#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000) +#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000) +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14) +#define MCF_DSPI_DCTAR_PASC_1CLK (0) +#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000) +#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000) +#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000) +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16) +#define MCF_DSPI_DCTAR_LSBFE (0x1000000) +#define MCF_DSPI_DCTAR_CPHA (0x2000000) +#define MCF_DSPI_DCTAR_CPOL (0x4000000) +#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B) + +/* Bit definitions and macros for MCF_DSPI_DSR */ +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0) +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4) +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8) +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC) +#define MCF_DSPI_DSR_RFDF (0x20000) +#define MCF_DSPI_DSR_RFOF (0x80000) +#define MCF_DSPI_DSR_TFFF (0x2000000) +#define MCF_DSPI_DSR_TFUF (0x8000000) +#define MCF_DSPI_DSR_EOQF (0x10000000) +#define MCF_DSPI_DSR_TXRXS (0x40000000) +#define MCF_DSPI_DSR_TCF (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DIRSR */ +#define MCF_DSPI_DIRSR_RFDFS (0x10000) +#define MCF_DSPI_DIRSR_RFDFE (0x20000) +#define MCF_DSPI_DIRSR_RFOFE (0x80000) +#define MCF_DSPI_DIRSR_TFFFS (0x1000000) +#define MCF_DSPI_DIRSR_TFFFE (0x2000000) +#define MCF_DSPI_DIRSR_TFUFE (0x8000000) +#define MCF_DSPI_DIRSR_EOQFE (0x10000000) +#define MCF_DSPI_DIRSR_TCFE (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DTFR */ +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFR_CS0 (0x10000) +#define MCF_DSPI_DTFR_CS2 (0x40000) +#define MCF_DSPI_DTFR_CS3 (0x80000) +#define MCF_DSPI_DTFR_CS5 (0x200000) +#define MCF_DSPI_DTFR_CTCNT (0x4000000) +#define MCF_DSPI_DTFR_EOQ (0x8000000) +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C) +#define MCF_DSPI_DTFR_CONT (0x80000000) + +/* Bit definitions and macros for MCF_DSPI_DRFR */ +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_DSPI_DTFDR */ +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0) +#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_DSPI_DRFDR */ +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0) + + +#endif /* __MCF5475_DSPI_H__ */ diff --git a/BaS_gcc/include/MCF5475_EPORT.h b/BaS_gcc/include/MCF5475_EPORT.h new file mode 100644 index 0000000..6506196 --- /dev/null +++ b/BaS_gcc/include/MCF5475_EPORT.h @@ -0,0 +1,123 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_EPORT_H__ +#define __MCF5475_EPORT_H__ + + +/********************************************************************* +* +* Edge Port Module (EPORT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00])) +#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04])) +#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05])) +#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08])) +#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09])) +#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C])) + + + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (0x1) +#define MCF_EPORT_EPPAR_FALLING (0x2) +#define MCF_EPORT_EPPAR_BOTH (0x3) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x2) +#define MCF_EPORT_EPDDR_EPDD2 (0x4) +#define MCF_EPORT_EPDDR_EPDD3 (0x8) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x2) +#define MCF_EPORT_EPIER_EPIE2 (0x4) +#define MCF_EPORT_EPIER_EPIE3 (0x8) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x2) +#define MCF_EPORT_EPDR_EPD2 (0x4) +#define MCF_EPORT_EPDR_EPD3 (0x8) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x2) +#define MCF_EPORT_EPPDR_EPPD2 (0x4) +#define MCF_EPORT_EPPDR_EPPD3 (0x8) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x2) +#define MCF_EPORT_EPFR_EPF2 (0x4) +#define MCF_EPORT_EPFR_EPF3 (0x8) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + + +#endif /* __MCF5475_EPORT_H__ */ diff --git a/BaS_gcc/include/MCF5475_FBCS.h b/BaS_gcc/include/MCF5475_FBCS.h new file mode 100644 index 0000000..37daf00 --- /dev/null +++ b/BaS_gcc/include/MCF5475_FBCS.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FBCS_H__ +#define __MCF5475_FBCS_H__ + + +/********************************************************************* +* +* FlexBus Chip Select Module (FBCS) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500])) +#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504])) +#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508])) + +#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C])) +#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510])) +#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514])) + +#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518])) +#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C])) +#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520])) + +#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524])) +#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528])) +#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C])) + +#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530])) +#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534])) +#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538])) + +#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C])) +#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540])) +#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544])) + +#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)])) +#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)])) +#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)])) + + +/* Bit definitions and macros for MCF_FBCS_CSAR */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_FBCS_CSMR */ +#define MCF_FBCS_CSMR_V (0x1) +#define MCF_FBCS_CSMR_WP (0x100) +#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10) +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0xFF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x7F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x3F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x1F0000) +#define MCF_FBCS_CSMR_BAM_1M (0xF0000) +#define MCF_FBCS_CSMR_BAM_1024K (0xF0000) +#define MCF_FBCS_CSMR_BAM_512K (0x70000) +#define MCF_FBCS_CSMR_BAM_256K (0x30000) +#define MCF_FBCS_CSMR_BAM_128K (0x10000) +#define MCF_FBCS_CSMR_BAM_64K (0) + +/* Bit definitions and macros for MCF_FBCS_CSCR */ +#define MCF_FBCS_CSCR_BSTW (0x8) +#define MCF_FBCS_CSCR_BSTR (0x10) +#define MCF_FBCS_CSCR_BEM (0x20) +#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6) +#define MCF_FBCS_CSCR_PS_32 (0) +#define MCF_FBCS_CSCR_PS_8 (0x40) +#define MCF_FBCS_CSCR_PS_16 (0x80) +#define MCF_FBCS_CSCR_AA (0x100) +#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA) +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10) +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12) +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14) +#define MCF_FBCS_CSCR_SWSEN (0x800000) +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A) + + +#endif /* __MCF5475_FBCS_H__ */ diff --git a/BaS_gcc/include/MCF5475_FEC.h b/BaS_gcc/include/MCF5475_FEC.h new file mode 100644 index 0000000..fdd9403 --- /dev/null +++ b/BaS_gcc/include/MCF5475_FEC.h @@ -0,0 +1,680 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_FEC_H__ +#define __MCF5475_FEC_H__ + + +/********************************************************************* +* +* Fast Ethernet Controller(FEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004])) +#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008])) +#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024])) +#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040])) +#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044])) +#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064])) +#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084])) +#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088])) +#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4])) +#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4])) +#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8])) +#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC])) +#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118])) +#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C])) +#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120])) +#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124])) +#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144])) +#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184])) +#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188])) +#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C])) +#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190])) +#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194])) +#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198])) +#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C])) +#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0])) +#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4])) +#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8])) +#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC])) +#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0])) +#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4])) +#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8])) +#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC])) +#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0])) +#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4])) +#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8])) +#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200])) +#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204])) +#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208])) +#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C])) +#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210])) +#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214])) +#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218])) +#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C])) +#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220])) +#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224])) +#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228])) +#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C])) +#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230])) +#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234])) +#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238])) +#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C])) +#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240])) +#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244])) +#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248])) +#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C])) +#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250])) +#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254])) +#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258])) +#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C])) +#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260])) +#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264])) +#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268])) +#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C])) +#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270])) +#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274])) +#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280])) +#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284])) +#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288])) +#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C])) +#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290])) +#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294])) +#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298])) +#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C])) +#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0])) +#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4])) +#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8])) +#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC])) +#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0])) +#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4])) +#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8])) +#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC])) +#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0])) +#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4])) +#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8])) +#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC])) +#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0])) +#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4])) +#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8])) +#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC])) +#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0])) + +#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804])) +#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808])) +#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824])) +#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840])) +#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844])) +#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864])) +#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884])) +#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888])) +#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4])) +#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4])) +#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8])) +#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC])) +#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918])) +#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C])) +#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920])) +#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924])) +#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944])) +#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984])) +#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988])) +#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C])) +#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990])) +#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994])) +#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998])) +#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C])) +#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0])) +#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4])) +#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8])) +#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC])) +#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0])) +#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4])) +#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8])) +#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC])) +#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0])) +#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4])) +#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8])) +#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00])) +#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04])) +#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08])) +#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C])) +#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10])) +#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14])) +#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18])) +#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C])) +#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20])) +#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24])) +#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28])) +#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C])) +#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30])) +#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34])) +#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38])) +#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C])) +#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40])) +#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44])) +#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48])) +#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C])) +#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50])) +#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54])) +#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58])) +#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C])) +#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60])) +#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64])) +#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68])) +#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C])) +#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70])) +#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74])) +#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80])) +#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84])) +#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88])) +#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C])) +#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90])) +#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94])) +#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98])) +#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C])) +#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0])) +#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4])) +#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8])) +#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC])) +#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0])) +#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4])) +#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8])) +#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC])) +#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0])) +#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4])) +#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8])) +#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC])) +#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0])) +#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4])) +#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8])) +#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC])) +#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0])) + +#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)])) +#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)])) +#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)])) +#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)])) +#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)])) +#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)])) +#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)])) +#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)])) +#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)])) +#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)])) +#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)])) +#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)])) +#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)])) +#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)])) +#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)])) +#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)])) +#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)])) +#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)])) +#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)])) +#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)])) +#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)])) +#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)])) +#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)])) +#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)])) +#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)])) +#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)])) +#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)])) +#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)])) +#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)])) +#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)])) +#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)])) +#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)])) +#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)])) +#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)])) +#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)])) +#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)])) +#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)])) +#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)])) +#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)])) +#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)])) +#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)])) +#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)])) + + +/* Bit definitions and macros for MCF_FEC_EIR */ +#define MCF_FEC_EIR_RFERR (0x20000) +#define MCF_FEC_EIR_XFERR (0x40000) +#define MCF_FEC_EIR_XFUN (0x80000) +#define MCF_FEC_EIR_RL (0x100000) +#define MCF_FEC_EIR_LC (0x200000) +#define MCF_FEC_EIR_MII (0x800000) +#define MCF_FEC_EIR_TXF (0x8000000) +#define MCF_FEC_EIR_GRA (0x10000000) +#define MCF_FEC_EIR_BABT (0x20000000) +#define MCF_FEC_EIR_BABR (0x40000000) +#define MCF_FEC_EIR_HBERR (0x80000000) +#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_EIMR */ +#define MCF_FEC_EIMR_RFERR (0x20000) +#define MCF_FEC_EIMR_XFERR (0x40000) +#define MCF_FEC_EIMR_XFUN (0x80000) +#define MCF_FEC_EIMR_RL (0x100000) +#define MCF_FEC_EIMR_LC (0x200000) +#define MCF_FEC_EIMR_MII (0x800000) +#define MCF_FEC_EIMR_TXF (0x8000000) +#define MCF_FEC_EIMR_GRA (0x10000000) +#define MCF_FEC_EIMR_BABT (0x20000000) +#define MCF_FEC_EIMR_BABR (0x40000000) +#define MCF_FEC_EIMR_HBERR (0x80000000) +#define MCF_FEC_EIMR_MASK_ALL (0) +#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) + +/* Bit definitions and macros for MCF_FEC_ECR */ +#define MCF_FEC_ECR_RESET (0x1) +#define MCF_FEC_ECR_ETHER_EN (0x2) + +/* Bit definitions and macros for MCF_FEC_MMFR */ +#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10) +#define MCF_FEC_MMFR_TA_10 (0x20000) +#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12) +#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17) +#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C) +#define MCF_FEC_MMFR_OP_READ (0x20000000) +#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E) +#define MCF_FEC_MMFR_ST_01 (0x40000000) + +/* Bit definitions and macros for MCF_FEC_MSCR */ +#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1) +#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80) +#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1) +#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1) + +/* Bit definitions and macros for MCF_FEC_MIBC */ +#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_RCR */ +#define MCF_FEC_RCR_LOOP (0x1) +#define MCF_FEC_RCR_DRT (0x2) +#define MCF_FEC_RCR_MII_MODE (0x4) +#define MCF_FEC_RCR_PROM (0x8) +#define MCF_FEC_RCR_BC_REJ (0x10) +#define MCF_FEC_RCR_FCE (0x20) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_RHR */ +#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18) +#define MCF_FEC_RHR_MULTCAST (0x40000000) +#define MCF_FEC_RHR_FCE (0x80000000) + +/* Bit definitions and macros for MCF_FEC_TCR */ +#define MCF_FEC_TCR_GTS (0x1) +#define MCF_FEC_TCR_HBC (0x2) +#define MCF_FEC_TCR_FDEN (0x4) +#define MCF_FEC_TCR_TFC_PAUSE (0x8) +#define MCF_FEC_TCR_RFC_PAUSE (0x10) + +/* Bit definitions and macros for MCF_FEC_PALR */ +#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_PAHR */ +#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_OPD */ +#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_FEC_IAUR */ +#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IALR */ +#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GAUR */ +#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_GALR */ +#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWR */ +#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0) +#define MCF_FEC_FECTFWR_X_WMRK_64 (0) +#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1) +#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2) +#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3) +#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4) +#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5) +#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6) +#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7) +#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8) +#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9) +#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA) +#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB) +#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC) +#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD) +#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE) +#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF) + +/* Bit definitions and macros for MCF_FEC_FECRFDR */ +#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFSR */ +#define MCF_FEC_FECRFSR_EMT (0x10000) +#define MCF_FEC_FECRFSR_ALARM (0x20000) +#define MCF_FEC_FECRFSR_FU (0x40000) +#define MCF_FEC_FECRFSR_FRMRDY (0x80000) +#define MCF_FEC_FECRFSR_OF (0x100000) +#define MCF_FEC_FECRFSR_UF (0x200000) +#define MCF_FEC_FECRFSR_RXW (0x400000) +#define MCF_FEC_FECRFSR_FAE (0x800000) +#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECRFCR */ +#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_FEC_FECRFCR_OF_MSK (0x80000) +#define MCF_FEC_FECRFCR_UF_MSK (0x100000) +#define MCF_FEC_FECRFCR_RXW_MSK (0x200000) +#define MCF_FEC_FECRFCR_FAE_MSK (0x400000) +#define MCF_FEC_FECRFCR_IP_MSK (0x800000) +#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_FEC_FECRFCR_FRMEN (0x8000000) +#define MCF_FEC_FECRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_FEC_FECRLRFP */ +#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRLWFP */ +#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFAR */ +#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFRP */ +#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECRFWP */ +#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFDR */ +#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFSR */ +#define MCF_FEC_FECTFSR_EMT (0x10000) +#define MCF_FEC_FECTFSR_ALARM (0x20000) +#define MCF_FEC_FECTFSR_FU (0x40000) +#define MCF_FEC_FECTFSR_FRMRDY (0x80000) +#define MCF_FEC_FECTFSR_OF (0x100000) +#define MCF_FEC_FECTFSR_UF (0x200000) +#define MCF_FEC_FECTFSR_FAE (0x800000) +#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_FEC_FECTFSR_TXW (0x40000000) +#define MCF_FEC_FECTFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_FEC_FECTFCR */ +#define MCF_FEC_FECTFCR_RESERVED (0x200000) +#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000) +#define MCF_FEC_FECTFCR_TXW_MASK (0x240000) +#define MCF_FEC_FECTFCR_OF_MSK (0x280000) +#define MCF_FEC_FECTFCR_UF_MSK (0x300000) +#define MCF_FEC_FECTFCR_FAE_MSK (0x600000) +#define MCF_FEC_FECTFCR_IP_MSK (0xA00000) +#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000) +#define MCF_FEC_FECTFCR_FRMEN (0x8200000) +#define MCF_FEC_FECTFCR_TIMER (0x10200000) +#define MCF_FEC_FECTFCR_WFR (0x20200000) +#define MCF_FEC_FECTFCR_WCTL (0x40200000) + +/* Bit definitions and macros for MCF_FEC_FECTLRFP */ +#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTLWFP */ +#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFAR */ +#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFRP */ +#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECTFWP */ +#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0) + +/* Bit definitions and macros for MCF_FEC_FECFRST */ +#define MCF_FEC_FECFRST_RST_CTL (0x1000000) +#define MCF_FEC_FECFRST_SW_RST (0x2000000) + +/* Bit definitions and macros for MCF_FEC_FECCTCWR */ +#define MCF_FEC_FECCTCWR_TFCW (0x1000000) +#define MCF_FEC_FECCTCWR_CRC (0x2000000) + +/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */ +#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */ +#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */ +#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */ +#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */ +#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */ +#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */ +#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */ +#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */ +#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_COL */ +#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */ +#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */ +#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */ +#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */ +#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */ +#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */ +#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */ +#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */ +#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */ +#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */ +#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */ +#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */ +#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */ +#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */ +#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */ +#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */ +#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */ +#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */ +#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */ +#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */ +#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */ +#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */ +#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */ +#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */ +#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */ +#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */ +#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */ +#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */ +#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */ +#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */ +#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */ +#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */ +#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */ +#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */ +#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */ +#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */ +#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */ +#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */ +#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */ +#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */ +#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */ +#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */ +#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */ +#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */ +#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */ +#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF5475_FEC_H__ */ diff --git a/BaS_gcc/include/MCF5475_GPIO.h b/BaS_gcc/include/MCF5475_GPIO.h new file mode 100644 index 0000000..5dd2583 --- /dev/null +++ b/BaS_gcc/include/MCF5475_GPIO.h @@ -0,0 +1,543 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPIO_H__ +#define __MCF5475_GPIO_H__ + + +/********************************************************************* +* +* General Purpose I/O (GPIO) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00])) +#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10])) +#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20])) +#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30])) + +#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01])) +#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11])) +#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21])) +#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31])) + +#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02])) +#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12])) +#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22])) +#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32])) + +#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04])) +#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14])) +#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24])) +#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34])) + +#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05])) +#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15])) +#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25])) +#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35])) + +#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06])) +#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16])) +#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26])) +#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36])) + +#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07])) +#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17])) +#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27])) +#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37])) + +#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08])) +#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18])) +#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28])) +#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38])) + +#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09])) +#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19])) +#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29])) +#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39])) + +#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A])) +#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A])) +#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A])) +#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A])) + +#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C])) +#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C])) +#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C])) +#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C])) + +#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D])) +#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D])) +#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D])) +#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D])) + +#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E])) +#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E])) +#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E])) +#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E])) + + + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ +#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ +#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1) +#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2) +#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4) +#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ +#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4) +#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4) +#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4) +#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40) +#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8) +#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8) +#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8) +#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8) +#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8) +#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8) +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8) +#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */ +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40) +#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */ +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */ +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40) +#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */ +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40) +#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */ +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40) +#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */ +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */ +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40) +#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */ +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40) +#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ +#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) + + +#endif /* __MCF5475_GPIO_H__ */ diff --git a/BaS_gcc/include/MCF5475_GPT.h b/BaS_gcc/include/MCF5475_GPT.h new file mode 100644 index 0000000..f9fbc98 --- /dev/null +++ b/BaS_gcc/include/MCF5475_GPT.h @@ -0,0 +1,100 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_GPT_H__ +#define __MCF5475_GPT_H__ + + +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800])) +#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804])) +#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808])) +#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C])) + +#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810])) +#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814])) +#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818])) +#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C])) + +#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820])) +#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824])) +#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828])) +#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C])) + +#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830])) +#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834])) +#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838])) +#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C])) + +#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)])) +#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)])) +#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)])) +#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_GPT_GMS */ +#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0) +#define MCF_GPT_GMS_TMS_DISABLE (0) +#define MCF_GPT_GMS_TMS_INCAPT (0x1) +#define MCF_GPT_GMS_TMS_OUTCAPT (0x2) +#define MCF_GPT_GMS_TMS_PWM (0x3) +#define MCF_GPT_GMS_TMS_GPIO (0x4) +#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4) +#define MCF_GPT_GMS_GPIO_INPUT (0) +#define MCF_GPT_GMS_GPIO_OUTLO (0x20) +#define MCF_GPT_GMS_GPIO_OUTHI (0x30) +#define MCF_GPT_GMS_IEN (0x100) +#define MCF_GPT_GMS_OD (0x200) +#define MCF_GPT_GMS_SC (0x400) +#define MCF_GPT_GMS_CE (0x1000) +#define MCF_GPT_GMS_WDEN (0x8000) +#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10) +#define MCF_GPT_GMS_ICT_ANY (0) +#define MCF_GPT_GMS_ICT_RISE (0x10000) +#define MCF_GPT_GMS_ICT_FALL (0x20000) +#define MCF_GPT_GMS_ICT_PULSE (0x30000) +#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14) +#define MCF_GPT_GMS_OCT_FRCLOW (0) +#define MCF_GPT_GMS_OCT_PULSEHI (0x100000) +#define MCF_GPT_GMS_OCT_PULSELO (0x200000) +#define MCF_GPT_GMS_OCT_TOGGLE (0x300000) +#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_GPT_GCIR */ +#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0) +#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GPWM */ +#define MCF_GPT_GPWM_LOAD (0x1) +#define MCF_GPT_GPWM_PWMOP (0x100) +#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_GPT_GSR */ +#define MCF_GPT_GSR_CAPT (0x1) +#define MCF_GPT_GSR_COMP (0x2) +#define MCF_GPT_GSR_PWMP (0x4) +#define MCF_GPT_GSR_TEXP (0x8) +#define MCF_GPT_GSR_PIN (0x100) +#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC) +#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10) + + +#endif /* __MCF5475_GPT_H__ */ diff --git a/BaS_gcc/include/MCF5475_I2C.h b/BaS_gcc/include/MCF5475_I2C.h new file mode 100644 index 0000000..1e8a85b --- /dev/null +++ b/BaS_gcc/include/MCF5475_I2C.h @@ -0,0 +1,69 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_I2C_H__ +#define __MCF5475_I2C_H__ + + +/********************************************************************* +* +* I2C Module (I2C) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&_MBAR[0x8F00])) +#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&_MBAR[0x8F04])) +#define MCF_I2C_I2CR (*(volatile uint8_t *)(&_MBAR[0x8F08])) +#define MCF_I2C_I2SR (*(volatile uint8_t *)(&_MBAR[0x8F0C])) +#define MCF_I2C_I2DR (*(volatile uint8_t *)(&_MBAR[0x8F10])) +#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&_MBAR[0x8F20])) + + + +/* Bit definitions and macros for MCF_I2C_I2ADR */ +#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_I2C_I2FDR */ +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) + +/* Bit definitions and macros for MCF_I2C_I2CR */ +#define MCF_I2C_I2CR_RSTA (0x4) +#define MCF_I2C_I2CR_TXAK (0x8) +#define MCF_I2C_I2CR_MTX (0x10) +#define MCF_I2C_I2CR_MSTA (0x20) +#define MCF_I2C_I2CR_IIEN (0x40) +#define MCF_I2C_I2CR_IEN (0x80) + +/* Bit definitions and macros for MCF_I2C_I2SR */ +#define MCF_I2C_I2SR_RXAK (0x1) +#define MCF_I2C_I2SR_IIF (0x2) +#define MCF_I2C_I2SR_SRW (0x4) +#define MCF_I2C_I2SR_IAL (0x10) +#define MCF_I2C_I2SR_IBB (0x20) +#define MCF_I2C_I2SR_IAAS (0x40) +#define MCF_I2C_I2SR_ICF (0x80) + +/* Bit definitions and macros for MCF_I2C_I2DR */ +#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_I2C_I2ICR */ +#define MCF_I2C_I2ICR_IE (0x1) +#define MCF_I2C_I2ICR_RE (0x2) +#define MCF_I2C_I2ICR_TE (0x4) +#define MCF_I2C_I2ICR_BNBE (0x8) + + +#endif /* __MCF5475_I2C_H__ */ diff --git a/BaS_gcc/include/MCF5475_INTC.h b/BaS_gcc/include/MCF5475_INTC.h new file mode 100644 index 0000000..61265ed --- /dev/null +++ b/BaS_gcc/include/MCF5475_INTC.h @@ -0,0 +1,331 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_INTC_H__ +#define __MCF5475_INTC_H__ + + +/********************************************************************* +* +* Interrupt Controller (INTC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700])) +#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704])) +#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708])) +#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C])) +#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710])) +#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714])) +#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718])) +#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719])) +#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741])) +#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742])) +#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743])) +#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744])) +#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745])) +#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746])) +#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747])) +#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748])) +#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749])) +#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A])) +#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B])) +#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C])) +#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D])) +#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E])) +#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F])) +#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750])) +#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751])) +#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752])) +#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753])) +#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754])) +#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755])) +#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756])) +#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757])) +#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758])) +#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759])) +#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A])) +#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B])) +#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C])) +#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D])) +#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E])) +#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F])) +#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760])) +#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761])) +#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762])) +#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763])) +#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764])) +#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765])) +#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766])) +#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767])) +#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768])) +#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769])) +#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A])) +#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B])) +#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C])) +#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D])) +#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E])) +#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F])) +#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770])) +#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771])) +#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772])) +#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773])) +#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774])) +#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775])) +#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776])) +#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777])) +#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778])) +#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779])) +#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A])) +#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B])) +#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C])) +#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D])) +#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E])) +#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F])) +#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0])) +#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4])) +#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8])) +#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC])) +#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0])) +#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4])) +#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8])) +#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC])) +#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)])) +#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)])) + + + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x1) +#define MCF_INTC_IPRH_INT33 (0x2) +#define MCF_INTC_IPRH_INT34 (0x4) +#define MCF_INTC_IPRH_INT35 (0x8) +#define MCF_INTC_IPRH_INT36 (0x10) +#define MCF_INTC_IPRH_INT37 (0x20) +#define MCF_INTC_IPRH_INT38 (0x40) +#define MCF_INTC_IPRH_INT39 (0x80) +#define MCF_INTC_IPRH_INT40 (0x100) +#define MCF_INTC_IPRH_INT41 (0x200) +#define MCF_INTC_IPRH_INT42 (0x400) +#define MCF_INTC_IPRH_INT43 (0x800) +#define MCF_INTC_IPRH_INT44 (0x1000) +#define MCF_INTC_IPRH_INT45 (0x2000) +#define MCF_INTC_IPRH_INT46 (0x4000) +#define MCF_INTC_IPRH_INT47 (0x8000) +#define MCF_INTC_IPRH_INT48 (0x10000) +#define MCF_INTC_IPRH_INT49 (0x20000) +#define MCF_INTC_IPRH_INT50 (0x40000) +#define MCF_INTC_IPRH_INT51 (0x80000) +#define MCF_INTC_IPRH_INT52 (0x100000) +#define MCF_INTC_IPRH_INT53 (0x200000) +#define MCF_INTC_IPRH_INT54 (0x400000) +#define MCF_INTC_IPRH_INT55 (0x800000) +#define MCF_INTC_IPRH_INT56 (0x1000000) +#define MCF_INTC_IPRH_INT57 (0x2000000) +#define MCF_INTC_IPRH_INT58 (0x4000000) +#define MCF_INTC_IPRH_INT59 (0x8000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT1 (0x2) +#define MCF_INTC_IPRL_INT2 (0x4) +#define MCF_INTC_IPRL_INT3 (0x8) +#define MCF_INTC_IPRL_INT4 (0x10) +#define MCF_INTC_IPRL_INT5 (0x20) +#define MCF_INTC_IPRL_INT6 (0x40) +#define MCF_INTC_IPRL_INT7 (0x80) +#define MCF_INTC_IPRL_INT8 (0x100) +#define MCF_INTC_IPRL_INT9 (0x200) +#define MCF_INTC_IPRL_INT10 (0x400) +#define MCF_INTC_IPRL_INT11 (0x800) +#define MCF_INTC_IPRL_INT12 (0x1000) +#define MCF_INTC_IPRL_INT13 (0x2000) +#define MCF_INTC_IPRL_INT14 (0x4000) +#define MCF_INTC_IPRL_INT15 (0x8000) +#define MCF_INTC_IPRL_INT16 (0x10000) +#define MCF_INTC_IPRL_INT17 (0x20000) +#define MCF_INTC_IPRL_INT18 (0x40000) +#define MCF_INTC_IPRL_INT19 (0x80000) +#define MCF_INTC_IPRL_INT20 (0x100000) +#define MCF_INTC_IPRL_INT21 (0x200000) +#define MCF_INTC_IPRL_INT22 (0x400000) +#define MCF_INTC_IPRL_INT23 (0x800000) +#define MCF_INTC_IPRL_INT24 (0x1000000) +#define MCF_INTC_IPRL_INT25 (0x2000000) +#define MCF_INTC_IPRL_INT26 (0x4000000) +#define MCF_INTC_IPRL_INT27 (0x8000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x1) +#define MCF_INTC_IMRH_INT_MASK33 (0x2) +#define MCF_INTC_IMRH_INT_MASK34 (0x4) +#define MCF_INTC_IMRH_INT_MASK35 (0x8) +#define MCF_INTC_IMRH_INT_MASK36 (0x10) +#define MCF_INTC_IMRH_INT_MASK37 (0x20) +#define MCF_INTC_IMRH_INT_MASK38 (0x40) +#define MCF_INTC_IMRH_INT_MASK39 (0x80) +#define MCF_INTC_IMRH_INT_MASK40 (0x100) +#define MCF_INTC_IMRH_INT_MASK41 (0x200) +#define MCF_INTC_IMRH_INT_MASK42 (0x400) +#define MCF_INTC_IMRH_INT_MASK43 (0x800) +#define MCF_INTC_IMRH_INT_MASK44 (0x1000) +#define MCF_INTC_IMRH_INT_MASK45 (0x2000) +#define MCF_INTC_IMRH_INT_MASK46 (0x4000) +#define MCF_INTC_IMRH_INT_MASK47 (0x8000) +#define MCF_INTC_IMRH_INT_MASK48 (0x10000) +#define MCF_INTC_IMRH_INT_MASK49 (0x20000) +#define MCF_INTC_IMRH_INT_MASK50 (0x40000) +#define MCF_INTC_IMRH_INT_MASK51 (0x80000) +#define MCF_INTC_IMRH_INT_MASK52 (0x100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x1000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x2000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x4000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x8000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_MASKALL (0x1) +#define MCF_INTC_IMRL_INT_MASK1 (0x2) +#define MCF_INTC_IMRL_INT_MASK2 (0x4) +#define MCF_INTC_IMRL_INT_MASK3 (0x8) +#define MCF_INTC_IMRL_INT_MASK4 (0x10) +#define MCF_INTC_IMRL_INT_MASK5 (0x20) +#define MCF_INTC_IMRL_INT_MASK6 (0x40) +#define MCF_INTC_IMRL_INT_MASK7 (0x80) +#define MCF_INTC_IMRL_INT_MASK8 (0x100) +#define MCF_INTC_IMRL_INT_MASK9 (0x200) +#define MCF_INTC_IMRL_INT_MASK10 (0x400) +#define MCF_INTC_IMRL_INT_MASK11 (0x800) +#define MCF_INTC_IMRL_INT_MASK12 (0x1000) +#define MCF_INTC_IMRL_INT_MASK13 (0x2000) +#define MCF_INTC_IMRL_INT_MASK14 (0x4000) +#define MCF_INTC_IMRL_INT_MASK15 (0x8000) +#define MCF_INTC_IMRL_INT_MASK16 (0x10000) +#define MCF_INTC_IMRL_INT_MASK17 (0x20000) +#define MCF_INTC_IMRL_INT_MASK18 (0x40000) +#define MCF_INTC_IMRL_INT_MASK19 (0x80000) +#define MCF_INTC_IMRL_INT_MASK20 (0x100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x1000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x2000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x4000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x8000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x1) +#define MCF_INTC_INTFRCH_INTFRC33 (0x2) +#define MCF_INTC_INTFRCH_INTFRC34 (0x4) +#define MCF_INTC_INTFRCH_INTFRC35 (0x8) +#define MCF_INTC_INTFRCH_INTFRC36 (0x10) +#define MCF_INTC_INTFRCH_INTFRC37 (0x20) +#define MCF_INTC_INTFRCH_INTFRC38 (0x40) +#define MCF_INTC_INTFRCH_INTFRC39 (0x80) +#define MCF_INTC_INTFRCH_INTFRC40 (0x100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x1000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x2000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x4000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x8000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x10000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x20000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x40000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x80000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC1 (0x2) +#define MCF_INTC_INTFRCL_INTFRC2 (0x4) +#define MCF_INTC_INTFRCL_INTFRC3 (0x8) +#define MCF_INTC_INTFRCL_INTFRC4 (0x10) +#define MCF_INTC_INTFRCL_INTFRC5 (0x20) +#define MCF_INTC_INTFRCL_INTFRC6 (0x40) +#define MCF_INTC_INTFRCL_INTFRC7 (0x80) +#define MCF_INTC_INTFRCL_INTFRC8 (0x100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x1000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x2000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x4000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x8000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x10000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x20000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x40000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x80000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IRLR */ +#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1) + +/* Bit definitions and macros for MCF_INTC_IACKLPR */ +#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0) +#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0) +#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + + +#endif /* __MCF5475_INTC_H__ */ diff --git a/BaS_gcc/include/MCF5475_MMU.h b/BaS_gcc/include/MCF5475_MMU.h new file mode 100644 index 0000000..a865fd8 --- /dev/null +++ b/BaS_gcc/include/MCF5475_MMU.h @@ -0,0 +1,77 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_MMU_H__ +#define __MCF5475_MMU_H__ + + +/********************************************************************* +* +* Memory Management Unit (MMU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_MMU_MMUCR (*(volatile uint32_t*)(&_MMUBAR[0])) +#define MCF_MMU_MMUOR (*(volatile uint32_t*)(&_MMUBAR[0x4])) +#define MCF_MMU_MMUSR (*(volatile uint32_t*)(&_MMUBAR[0x8])) +#define MCF_MMU_MMUAR (*(volatile uint32_t*)(&_MMUBAR[0x10])) +#define MCF_MMU_MMUTR (*(volatile uint32_t*)(&_MMUBAR[0x14])) +#define MCF_MMU_MMUDR (*(volatile uint32_t*)(&_MMUBAR[0x18])) + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + + +#endif /* __MCF5475_MMU_H__ */ diff --git a/BaS_gcc/include/MCF5475_PAD.h b/BaS_gcc/include/MCF5475_PAD.h new file mode 100644 index 0000000..1d87e2e --- /dev/null +++ b/BaS_gcc/include/MCF5475_PAD.h @@ -0,0 +1,233 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PAD_H__ +#define __MCF5475_PAD_H__ + + +/********************************************************************* +* +* Common GPIO +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&_MBAR[0xA40])) +#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA42])) +#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&_MBAR[0xA43])) +#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&_MBAR[0xA44])) +#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&_MBAR[0xA48])) +#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&_MBAR[0xA4A])) +#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&_MBAR[0xA4C])) +#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&_MBAR[0xA4D])) +#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&_MBAR[0xA4E])) +#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&_MBAR[0xA4F])) +#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&_MBAR[0xA50])) +#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&_MBAR[0xA52])) + + +/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */ +#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2) +#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3) +#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20) +#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30) +#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40) +#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100) +#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400) +#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000) +#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000) + +/* Bit definitions and macros for MCF_PAD_PAR_FBCS */ +#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2) +#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4) +#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8) +#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10) +#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20) + +/* Bit definitions and macros for MCF_PAD_PAR_DMA */ +#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3) +#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8) +#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC) +#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20) +#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30) +#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0) +#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80) +#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */ +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */ +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200) +#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */ +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200) +#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */ +#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4) +#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8) +#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30) +#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80) +#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */ +#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4) +#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8) +#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30) +#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80) +#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */ +#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4) +#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8) +#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30) +#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80) +#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */ +#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4) +#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8) +#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30) +#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80) +#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0) + +/* Bit definitions and macros for MCF_PAD_PAR_DSPI */ +#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2) +#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3) +#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2) +#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8) +#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC) +#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10) +#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20) +#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30) +#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6) +#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40) +#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80) +#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0) +#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8) +#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200) +#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300) +#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA) +#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0) +#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800) +#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00) +#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000) + +/* Bit definitions and macros for MCF_PAD_PAR_TIMER */ +#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6) +#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8) +#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20) +#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30) + + +#endif /* __MCF5475_PAD_H__ */ diff --git a/BaS_gcc/include/MCF5475_PCI.h b/BaS_gcc/include/MCF5475_PCI.h new file mode 100644 index 0000000..3eb3341 --- /dev/null +++ b/BaS_gcc/include/MCF5475_PCI.h @@ -0,0 +1,376 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCI_H__ +#define __MCF5475_PCI_H__ + + +/********************************************************************* +* +* PCI Bus Controller (PCI) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&_MBAR[0xB00])) +#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&_MBAR[0xB04])) +#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&_MBAR[0xB08])) +#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&_MBAR[0xB0C])) +#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&_MBAR[0xB10])) +#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&_MBAR[0xB14])) +#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&_MBAR[0xB28])) +#define MCF_PCI_PCISID (*(volatile uint32_t*)(&_MBAR[0xB2C])) +#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&_MBAR[0xB3C])) +#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&_MBAR[0xB60])) +#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&_MBAR[0xB64])) +#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&_MBAR[0xB68])) +#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&_MBAR[0xB6C])) +#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&_MBAR[0xB70])) +#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&_MBAR[0xB74])) +#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&_MBAR[0xB78])) +#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&_MBAR[0xB80])) +#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&_MBAR[0xB84])) +#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&_MBAR[0xB88])) +#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&_MBAR[0xBF8])) +#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&_MBAR[0x8400])) +#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&_MBAR[0x8404])) +#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&_MBAR[0x8408])) +#define MCF_PCI_PCITER (*(volatile uint32_t*)(&_MBAR[0x840C])) +#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&_MBAR[0x8410])) +#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&_MBAR[0x8414])) +#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&_MBAR[0x8418])) +#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&_MBAR[0x841C])) +#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&_MBAR[0x8440])) +#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&_MBAR[0x8444])) +#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&_MBAR[0x8448])) +#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&_MBAR[0x844C])) +#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&_MBAR[0x8450])) +#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&_MBAR[0x8454])) +#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&_MBAR[0x8480])) +#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&_MBAR[0x8484])) +#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&_MBAR[0x8488])) +#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&_MBAR[0x848C])) +#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&_MBAR[0x8490])) +#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&_MBAR[0x8498])) +#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&_MBAR[0x849C])) +#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&_MBAR[0x84C0])) +#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&_MBAR[0x84C4])) +#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&_MBAR[0x84C8])) +#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&_MBAR[0x84CC])) +#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&_MBAR[0x84D0])) +#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&_MBAR[0x84D4])) + + +/* Bit definitions and macros for MCF_PCI_PCIIDR */ +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCISCR */ +#define MCF_PCI_PCISCR_IO (0x1) +#define MCF_PCI_PCISCR_M (0x2) +#define MCF_PCI_PCISCR_B (0x4) +#define MCF_PCI_PCISCR_SP (0x8) +#define MCF_PCI_PCISCR_MW (0x10) +#define MCF_PCI_PCISCR_V (0x20) +#define MCF_PCI_PCISCR_PER (0x40) +#define MCF_PCI_PCISCR_ST (0x80) +#define MCF_PCI_PCISCR_S (0x100) +#define MCF_PCI_PCISCR_F (0x200) +#define MCF_PCI_PCISCR_C (0x100000) +#define MCF_PCI_PCISCR_66M (0x200000) +#define MCF_PCI_PCISCR_R (0x400000) +#define MCF_PCI_PCISCR_FC (0x800000) +#define MCF_PCI_PCISCR_DP (0x1000000) +#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCISCR_TS (0x8000000) +#define MCF_PCI_PCISCR_TR (0x10000000) +#define MCF_PCI_PCISCR_MA (0x20000000) +#define MCF_PCI_PCISCR_SE (0x40000000) +#define MCF_PCI_PCISCR_PE (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCICCRIR */ +#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8) + +/* Bit definitions and macros for MCF_PCI_PCICR1 */ +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ +#define MCF_PCI_PCIBAR0_IOM (0x1) +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR0_PREF (0x8) +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ +#define MCF_PCI_PCIBAR1_IOM (0x1) +#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1) +#define MCF_PCI_PCIBAR1_PREF (0x8) +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCICCPR */ +#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCISID */ +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCICR2 */ +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIGSCR */ +#define MCF_PCI_PCIGSCR_PR (0x1) +#define MCF_PCI_PCIGSCR_SEE (0x1000) +#define MCF_PCI_PCIGSCR_PEE (0x2000) +#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10) +#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIGSCR_SE (0x10000000) +#define MCF_PCI_PCIGSCR_PE (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ +#define MCF_PCI_PCITBATR0_EN (0x1) +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12) + +/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ +#define MCF_PCI_PCITBATR1_EN (0x1) +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E) + +/* Bit definitions and macros for MCF_PCI_PCITCR */ +#define MCF_PCI_PCITCR_P (0x10000) +#define MCF_PCI_PCITCR_LD (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ +#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ +#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ +#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8) +#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIIWCR */ +#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9) +#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800) +#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11) +#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000) +#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19) +#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300) +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500) +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000) +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000) +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000) +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000) + +/* Bit definitions and macros for MCF_PCI_PCIICR */ +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0) +#define MCF_PCI_PCIICR_TAE (0x1000000) +#define MCF_PCI_PCIICR_IAE (0x2000000) +#define MCF_PCI_PCIICR_REE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCIISR */ +#define MCF_PCI_PCIISR_TA (0x1000000) +#define MCF_PCI_PCIISR_IA (0x2000000) +#define MCF_PCI_PCIISR_RE (0x4000000) + +/* Bit definitions and macros for MCF_PCI_PCICAR */ +#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2) +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB) +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCICAR_E (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITPSR */ +#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSAR */ +#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITTCR */ +#define MCF_PCI_PCITTCR_DI (0x1) +#define MCF_PCI_PCITTCR_W (0x10) +#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCITER */ +#define MCF_PCI_PCITER_NE (0x10000) +#define MCF_PCI_PCITER_IAE (0x20000) +#define MCF_PCI_PCITER_TAE (0x40000) +#define MCF_PCI_PCITER_RE (0x80000) +#define MCF_PCI_PCITER_SE (0x100000) +#define MCF_PCI_PCITER_FEE (0x200000) +#define MCF_PCI_PCITER_ME (0x1000000) +#define MCF_PCI_PCITER_BE (0x8000000) +#define MCF_PCI_PCITER_CM (0x10000000) +#define MCF_PCI_PCITER_RF (0x40000000) +#define MCF_PCI_PCITER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITNAR */ +#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITLWR */ +#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITDCR */ +#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCITSR */ +#define MCF_PCI_PCITSR_IA (0x10000) +#define MCF_PCI_PCITSR_TA (0x20000) +#define MCF_PCI_PCITSR_RE (0x40000) +#define MCF_PCI_PCITSR_SE (0x80000) +#define MCF_PCI_PCITSR_FE (0x100000) +#define MCF_PCI_PCITSR_BE1 (0x200000) +#define MCF_PCI_PCITSR_BE2 (0x400000) +#define MCF_PCI_PCITSR_BE3 (0x800000) +#define MCF_PCI_PCITSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCITFDR */ +#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFSR */ +#define MCF_PCI_PCITFSR_EMPTY (0x10000) +#define MCF_PCI_PCITFSR_ALARM (0x20000) +#define MCF_PCI_PCITFSR_FULL (0x40000) +#define MCF_PCI_PCITFSR_FR (0x80000) +#define MCF_PCI_PCITFSR_OF (0x100000) +#define MCF_PCI_PCITFSR_UF (0x200000) +#define MCF_PCI_PCITFSR_RXW (0x400000) +#define MCF_PCI_PCITFSR_FAE (0x800000) +#define MCF_PCI_PCITFSR_TXW (0x40000000) +#define MCF_PCI_PCITFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCITFCR */ +#define MCF_PCI_PCITFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCITFCR_OF_MASK (0x80000) +#define MCF_PCI_PCITFCR_UF_MASK (0x100000) +#define MCF_PCI_PCITFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCITFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCITFCR_IP_MASK (0x800000) +#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCITFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCITFAR */ +#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFRPR */ +#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCITFWPR */ +#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRPSR */ +#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSAR */ +#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRTCR */ +#define MCF_PCI_PCIRTCR_DI (0x1) +#define MCF_PCI_PCIRTCR_W (0x10) +#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8) +#define MCF_PCI_PCIRTCR_FB (0x1000) +#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10) +#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_PCI_PCIRER */ +#define MCF_PCI_PCIRER_NE (0x10000) +#define MCF_PCI_PCIRER_IAE (0x20000) +#define MCF_PCI_PCIRER_TAE (0x40000) +#define MCF_PCI_PCIRER_RE (0x80000) +#define MCF_PCI_PCIRER_SE (0x100000) +#define MCF_PCI_PCIRER_FEE (0x200000) +#define MCF_PCI_PCIRER_ME (0x1000000) +#define MCF_PCI_PCIRER_BE (0x8000000) +#define MCF_PCI_PCIRER_CM (0x10000000) +#define MCF_PCI_PCIRER_FE (0x20000000) +#define MCF_PCI_PCIRER_RF (0x40000000) +#define MCF_PCI_PCIRER_RC (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRNAR */ +#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRDCR */ +#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0) +#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PCI_PCIRSR */ +#define MCF_PCI_PCIRSR_IA (0x10000) +#define MCF_PCI_PCIRSR_TA (0x20000) +#define MCF_PCI_PCIRSR_RE (0x40000) +#define MCF_PCI_PCIRSR_SE (0x80000) +#define MCF_PCI_PCIRSR_FE (0x100000) +#define MCF_PCI_PCIRSR_BE1 (0x200000) +#define MCF_PCI_PCIRSR_BE2 (0x400000) +#define MCF_PCI_PCIRSR_BE3 (0x800000) +#define MCF_PCI_PCIRSR_NT (0x1000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFDR */ +#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFSR */ +#define MCF_PCI_PCIRFSR_EMPTY (0x10000) +#define MCF_PCI_PCIRFSR_ALARM (0x20000) +#define MCF_PCI_PCIRFSR_FULL (0x40000) +#define MCF_PCI_PCIRFSR_FR (0x80000) +#define MCF_PCI_PCIRFSR_OF (0x100000) +#define MCF_PCI_PCIRFSR_UF (0x200000) +#define MCF_PCI_PCIRFSR_RXW (0x400000) +#define MCF_PCI_PCIRFSR_FAE (0x800000) +#define MCF_PCI_PCIRFSR_TXW (0x40000000) +#define MCF_PCI_PCIRFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFCR */ +#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000) +#define MCF_PCI_PCIRFCR_OF_MASK (0x80000) +#define MCF_PCI_PCIRFCR_UF_MASK (0x100000) +#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000) +#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000) +#define MCF_PCI_PCIRFCR_IP_MASK (0x800000) +#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PCI_PCIRFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PCI_PCIRFAR */ +#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ +#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ +#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0) + + +#endif /* __MCF5475_PCI_H__ */ diff --git a/BaS_gcc/include/MCF5475_PCIARB.h b/BaS_gcc/include/MCF5475_PCIARB.h new file mode 100644 index 0000000..9e8c05b --- /dev/null +++ b/BaS_gcc/include/MCF5475_PCIARB.h @@ -0,0 +1,43 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PCIARB_H__ +#define __MCF5475_PCIARB_H__ + + +/********************************************************************* +* +* PCI Bus Arbiter Module (PCIARB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&_MBAR[0xC00])) +#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&_MBAR[0xC04])) + + +/* Bit definitions and macros for MCF_PCIARB_PACR */ +#define MCF_PCIARB_PACR_INTMPRI (0x1) +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1) +#define MCF_PCIARB_PACR_INTMINTEN (0x10000) +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11) +#define MCF_PCIARB_PACR_DS (0x80000000) + +/* Bit definitions and macros for MCF_PCIARB_PASR */ +#define MCF_PCIARB_PASR_ITLMBK (0x10000) +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11) + + +#endif /* __MCF5475_PCIARB_H__ */ diff --git a/BaS_gcc/include/MCF5475_PSC.h b/BaS_gcc/include/MCF5475_PSC.h new file mode 100644 index 0000000..ffa9f3e --- /dev/null +++ b/BaS_gcc/include/MCF5475_PSC.h @@ -0,0 +1,527 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_PSC_H__ +#define __MCF5475_PSC_H__ + + +/********************************************************************* +* +* Programmable Serial Controller (PSC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8600])) +#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8604])) +#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8608])) +#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C])) +#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8610])) +#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8614])) +#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8618])) +#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x861C])) +#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8634])) +#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8638])) +#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x863C])) +#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8640])) +#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8644])) +#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8648])) +#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x864C])) +#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8650])) +#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8654])) +#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8658])) +#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x865C])) +#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8660])) +#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8664])) +#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8668])) +#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x866E])) +#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8672])) +#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8676])) +#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x867A])) +#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x867E])) +#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8680])) +#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8684])) +#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8688])) +#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x868E])) +#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8692])) +#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8696])) +#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x869A])) +#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x869E])) + +#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8700])) +#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8704])) +#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8708])) +#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C])) +#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8710])) +#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8714])) +#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8718])) +#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x871C])) +#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8734])) +#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8738])) +#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x873C])) +#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8740])) +#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8744])) +#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8748])) +#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x874C])) +#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8750])) +#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8754])) +#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8758])) +#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x875C])) +#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8760])) +#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8764])) +#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8768])) +#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x876E])) +#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8772])) +#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8776])) +#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x877A])) +#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x877E])) +#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8780])) +#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8784])) +#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8788])) +#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x878E])) +#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8792])) +#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8796])) +#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x879A])) +#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x879E])) + +#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8800])) +#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8804])) +#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8808])) +#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C])) +#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8810])) +#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8814])) +#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8818])) +#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x881C])) +#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8834])) +#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8838])) +#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x883C])) +#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8840])) +#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8844])) +#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8848])) +#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x884C])) +#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8850])) +#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8854])) +#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8858])) +#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x885C])) +#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8860])) +#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8864])) +#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8868])) +#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x886E])) +#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8872])) +#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8876])) +#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x887A])) +#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x887E])) +#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8880])) +#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8884])) +#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8888])) +#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x888E])) +#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8892])) +#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8896])) +#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x889A])) +#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x889E])) + +#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8900])) +#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8904])) +#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8908])) +#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C])) +#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8910])) +#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8914])) +#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8918])) +#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x891C])) +#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8934])) +#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8938])) +#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x893C])) +#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8940])) +#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8944])) +#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8948])) +#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x894C])) +#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8950])) +#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8954])) +#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8958])) +#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x895C])) +#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8960])) +#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8964])) +#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8968])) +#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x896E])) +#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8972])) +#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8976])) +#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x897A])) +#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x897E])) +#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8980])) +#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8984])) +#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8988])) +#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x898E])) +#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8992])) +#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8996])) +#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x899A])) +#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x899E])) + +#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)])) +#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)])) +#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)])) +#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)])) +#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)])) +#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)])) +#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)])) +#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)])) +#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)])) +#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)])) +#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)])) +#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)])) +#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)])) +#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)])) +#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)])) +#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)])) +#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)])) +#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)])) +#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)])) +#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)])) +#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)])) +#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)])) +#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)])) +#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)])) +#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)])) +#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)])) +#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)])) +#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)])) +#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)])) +#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)])) +#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)])) +#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)])) + +/* Bit definitions and macros for MCF_PSC_PSCMR */ +#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCMR_TXCTS (0x10) +#define MCF_PSC_PSCMR_TXRTS (0x20) +#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6) +#define MCF_PSC_PSCMR_CM_NORMAL (0) +#define MCF_PSC_PSCMR_CM_ECHO (0x40) +#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80) +#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0) +#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7) +#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8) +#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF) +#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C) +#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18) +#define MCF_PSC_PSCMR_PM_NONE (0x10) +#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC) +#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8) +#define MCF_PSC_PSCMR_PM_ODD (0x4) +#define MCF_PSC_PSCMR_PM_EVEN (0) +#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCMR_BC_5 (0) +#define MCF_PSC_PSCMR_BC_6 (0x1) +#define MCF_PSC_PSCMR_BC_7 (0x2) +#define MCF_PSC_PSCMR_BC_8 (0x3) +#define MCF_PSC_PSCMR_PT (0x4) +#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3) +#define MCF_PSC_PSCMR_ERR (0x20) +#define MCF_PSC_PSCMR_RXIRQ_FU (0x40) +#define MCF_PSC_PSCMR_RXRTS (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCCSR */ +#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0) +#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4) +#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D) +#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E) +#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F) +#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0) +#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0) +#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0) + +/* Bit definitions and macros for MCF_PSC_PSCSR */ +#define MCF_PSC_PSCSR_ERR (0x40) +#define MCF_PSC_PSCSR_CDE_DEOF (0x80) +#define MCF_PSC_PSCSR_RXRDY (0x100) +#define MCF_PSC_PSCSR_FU (0x200) +#define MCF_PSC_PSCSR_TXRDY (0x400) +#define MCF_PSC_PSCSR_TXEMP_URERR (0x800) +#define MCF_PSC_PSCSR_OE (0x1000) +#define MCF_PSC_PSCSR_PE_CRCERR (0x2000) +#define MCF_PSC_PSCSR_FE_PHYERR (0x4000) +#define MCF_PSC_PSCSR_RB_NEOF (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCR */ +#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0) +#define MCF_PSC_PSCCR_RX_ENABLED (0x1) +#define MCF_PSC_PSCCR_RX_DISABLED (0x2) +#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2) +#define MCF_PSC_PSCCR_TX_ENABLED (0x4) +#define MCF_PSC_PSCCR_TX_DISABLED (0x8) +#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4) +#define MCF_PSC_PSCCR_NONE (0) +#define MCF_PSC_PSCCR_RESET_MR (0x10) +#define MCF_PSC_PSCCR_RESET_RX (0x20) +#define MCF_PSC_PSCCR_RESET_TX (0x30) +#define MCF_PSC_PSCCR_RESET_ERROR (0x40) +#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50) +#define MCF_PSC_PSCCR_START_BREAK (0x60) +#define MCF_PSC_PSCCR_STOP_BREAK (0x70) + +/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */ +#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */ +#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0) +#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8) +#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10) +#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18) + +/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */ +#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */ +#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */ +#define MCF_PSC_PSCRB_AC97_SOF (0x800) +#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */ +#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC) + +/* Bit definitions and macros for MCF_PSC_PSCIPCR */ +#define MCF_PSC_PSCIPCR_RESERVED (0xC) +#define MCF_PSC_PSCIPCR_CTS (0xD) +#define MCF_PSC_PSCIPCR_D_CTS (0x1C) +#define MCF_PSC_PSCIPCR_SYNC (0x8C) + +/* Bit definitions and macros for MCF_PSC_PSCACR */ +#define MCF_PSC_PSCACR_IEC0 (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCIMR */ +#define MCF_PSC_PSCIMR_ERR (0x40) +#define MCF_PSC_PSCIMR_DEOF (0x80) +#define MCF_PSC_PSCIMR_TXRDY (0x100) +#define MCF_PSC_PSCIMR_RXRDY_FU (0x200) +#define MCF_PSC_PSCIMR_DB (0x400) +#define MCF_PSC_PSCIMR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCISR */ +#define MCF_PSC_PSCISR_ERR (0x40) +#define MCF_PSC_PSCISR_DEOF (0x80) +#define MCF_PSC_PSCISR_TXRDY (0x100) +#define MCF_PSC_PSCISR_RXRDY_FU (0x200) +#define MCF_PSC_PSCISR_DB (0x400) +#define MCF_PSC_PSCISR_IPC (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCCTUR */ +#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCCTLR */ +#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIP */ +#define MCF_PSC_PSCIP_CTS (0x1) +#define MCF_PSC_PSCIP_TGL (0x40) +#define MCF_PSC_PSCIP_LPWR_B (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCOPSET */ +#define MCF_PSC_PSCOPSET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCOPRESET */ +#define MCF_PSC_PSCOPRESET_RTS (0x1) + +/* Bit definitions and macros for MCF_PSC_PSCSICR */ +#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0) +#define MCF_PSC_PSCSICR_SIM_UART (0) +#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1) +#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2) +#define MCF_PSC_PSCSICR_SIM_AC97 (0x3) +#define MCF_PSC_PSCSICR_SIM_SIR (0x4) +#define MCF_PSC_PSCSICR_SIM_MIR (0x5) +#define MCF_PSC_PSCSICR_SIM_FIR (0x6) +#define MCF_PSC_PSCSICR_SHDIR (0x10) +#define MCF_PSC_PSCSICR_DTS1 (0x20) +#define MCF_PSC_PSCSICR_AWR (0x40) +#define MCF_PSC_PSCSICR_ACRB (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */ +#define MCF_PSC_PSCIRCR1_SPUL (0x1) +#define MCF_PSC_PSCIRCR1_SIPEN (0x2) +#define MCF_PSC_PSCIRCR1_FD (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */ +#define MCF_PSC_PSCIRCR2_NXTEOF (0x1) +#define MCF_PSC_PSCIRCR2_ABORT (0x2) +#define MCF_PSC_PSCIRCR2_SIPREQ (0x4) + +/* Bit definitions and macros for MCF_PSC_PSCIRSDR */ +#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCIRMDR */ +#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0) +#define MCF_PSC_PSCIRMDR_FREQ (0x80) + +/* Bit definitions and macros for MCF_PSC_PSCIRFDR */ +#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFCNT */ +#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFCNT */ +#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFDR */ +#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFSR */ +#define MCF_PSC_PSCRFSR_EMT (0x1) +#define MCF_PSC_PSCRFSR_ALARM (0x2) +#define MCF_PSC_PSCRFSR_FU (0x4) +#define MCF_PSC_PSCRFSR_FRMRDY (0x8) +#define MCF_PSC_PSCRFSR_OF (0x10) +#define MCF_PSC_PSCRFSR_UF (0x20) +#define MCF_PSC_PSCRFSR_RXW (0x40) +#define MCF_PSC_PSCRFSR_FAE (0x80) +#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCRFSR_TXW (0x4000) +#define MCF_PSC_PSCRFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCRFCR */ +#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCRFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCRFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCRFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCRFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCRFCR_TIMER (0x10000000) + +/* Bit definitions and macros for MCF_PSC_PSCRFAR */ +#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFRP */ +#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRFWP */ +#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLRFP */ +#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCRLWFP */ +#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFDR */ +#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFSR */ +#define MCF_PSC_PSCTFSR_EMT (0x1) +#define MCF_PSC_PSCTFSR_ALARM (0x2) +#define MCF_PSC_PSCTFSR_FU (0x4) +#define MCF_PSC_PSCTFSR_FRMRDY (0x8) +#define MCF_PSC_PSCTFSR_OF (0x10) +#define MCF_PSC_PSCTFSR_UF (0x20) +#define MCF_PSC_PSCTFSR_RXW (0x40) +#define MCF_PSC_PSCTFSR_FAE (0x80) +#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8) +#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800) +#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400) +#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200) +#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100) +#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC) +#define MCF_PSC_PSCTFSR_TXW (0x4000) +#define MCF_PSC_PSCTFSR_IP (0x8000) + +/* Bit definitions and macros for MCF_PSC_PSCTFCR */ +#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0) +#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000) +#define MCF_PSC_PSCTFCR_OF_MSK (0x80000) +#define MCF_PSC_PSCTFCR_UF_MSK (0x100000) +#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000) +#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000) +#define MCF_PSC_PSCTFCR_IP_MSK (0x800000) +#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_PSC_PSCTFCR_FRMEN (0x8000000) +#define MCF_PSC_PSCTFCR_TIMER (0x10000000) +#define MCF_PSC_PSCTFCR_WFR (0x20000000) + +/* Bit definitions and macros for MCF_PSC_PSCTFAR */ +#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFRP */ +#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTFWP */ +#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLRFP */ +#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0) + +/* Bit definitions and macros for MCF_PSC_PSCTLWFP */ +#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0) + + +#endif /* __MCF5475_PSC_H__ */ diff --git a/BaS_gcc/include/MCF5475_SDRAMC.h b/BaS_gcc/include/MCF5475_SDRAMC.h new file mode 100644 index 0000000..6cdbd68 --- /dev/null +++ b/BaS_gcc/include/MCF5475_SDRAMC.h @@ -0,0 +1,106 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SDRAMC_H__ +#define __MCF5475_SDRAMC_H__ + + +/********************************************************************* +* +* Synchronous DRAM Controller (SDRAMC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&_MBAR[0x4])) +#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&_MBAR[0x20])) +#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&_MBAR[0x24])) +#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&_MBAR[0x28])) +#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&_MBAR[0x2C])) +#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&_MBAR[0x100])) +#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&_MBAR[0x104])) +#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&_MBAR[0x108])) +#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&_MBAR[0x10C])) +#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)])) + + +/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ +#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0) +#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2) +#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4) +#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6) +#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8) +#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0) +#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1) +#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2) +#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3) + +/* Bit definitions and macros for MCF_SDRAMC_CSCFG */ +#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0) +#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0) +#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13) +#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14) +#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15) +#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16) +#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17) +#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18) +#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19) +#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A) +#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B) +#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C) +#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D) +#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E) +#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F) +#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14) +#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000) + +/* Bit definitions and macros for MCF_SDRAMC_SDMR */ +#define MCF_SDRAMC_SDMR_CMD (0x10000) +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12) +#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E) +#define MCF_SDRAMC_SDMR_BK_LMR (0) +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCR */ +#define MCF_SDRAMC_SDCR_IPALL (0x2) +#define MCF_SDRAMC_SDCR_IREF (0x4) +#define MCF_SDRAMC_SDCR_BUFF (0x10) +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10) +#define MCF_SDRAMC_SDCR_DRIVE (0x400000) +#define MCF_SDRAMC_SDCR_AP (0x800000) +#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18) +#define MCF_SDRAMC_SDCR_REF (0x10000000) +#define MCF_SDRAMC_SDCR_DDR (0x20000000) +#define MCF_SDRAMC_SDCR_CKE (0x40000000) +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ +#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4) +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8) +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC) +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10) +#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18) +#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10) +#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14) +#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18) +#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C) + + +#endif /* __MCF5475_SDRAMC_H__ */ diff --git a/BaS_gcc/include/MCF5475_SEC.h b/BaS_gcc/include/MCF5475_SEC.h new file mode 100644 index 0000000..8deff0b --- /dev/null +++ b/BaS_gcc/include/MCF5475_SEC.h @@ -0,0 +1,398 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SEC_H__ +#define __MCF5475_SEC_H__ + + +/********************************************************************* +* +* Integrated Security Engine (SEC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&_MBAR[0x21000])) +#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&_MBAR[0x21004])) +#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&_MBAR[0x21008])) +#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&_MBAR[0x2100C])) +#define MCF_SEC_SISRH (*(volatile uint32_t*)(&_MBAR[0x21010])) +#define MCF_SEC_SISRL (*(volatile uint32_t*)(&_MBAR[0x21014])) +#define MCF_SEC_SICRH (*(volatile uint32_t*)(&_MBAR[0x21018])) +#define MCF_SEC_SICRL (*(volatile uint32_t*)(&_MBAR[0x2101C])) +#define MCF_SEC_SIDR (*(volatile uint32_t*)(&_MBAR[0x21020])) +#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&_MBAR[0x21028])) +#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&_MBAR[0x2102C])) +#define MCF_SEC_SMCR (*(volatile uint32_t*)(&_MBAR[0x21030])) +#define MCF_SEC_MEAR (*(volatile uint32_t*)(&_MBAR[0x21038])) +#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&_MBAR[0x2200C])) +#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&_MBAR[0x22010])) +#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&_MBAR[0x22014])) +#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&_MBAR[0x22044])) +#define MCF_SEC_FR0 (*(volatile uint32_t*)(&_MBAR[0x2204C])) +#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&_MBAR[0x2300C])) +#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&_MBAR[0x23010])) +#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&_MBAR[0x23014])) +#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&_MBAR[0x23044])) +#define MCF_SEC_FR1 (*(volatile uint32_t*)(&_MBAR[0x2304C])) +#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&_MBAR[0x28018])) +#define MCF_SEC_AFSR (*(volatile uint32_t*)(&_MBAR[0x28028])) +#define MCF_SEC_AFISR (*(volatile uint32_t*)(&_MBAR[0x28030])) +#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&_MBAR[0x28038])) +#define MCF_SEC_DRCR (*(volatile uint32_t*)(&_MBAR[0x2A018])) +#define MCF_SEC_DSR (*(volatile uint32_t*)(&_MBAR[0x2A028])) +#define MCF_SEC_DISR (*(volatile uint32_t*)(&_MBAR[0x2A030])) +#define MCF_SEC_DIMR (*(volatile uint32_t*)(&_MBAR[0x2A038])) +#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&_MBAR[0x2C018])) +#define MCF_SEC_MDSR (*(volatile uint32_t*)(&_MBAR[0x2C028])) +#define MCF_SEC_MDISR (*(volatile uint32_t*)(&_MBAR[0x2C030])) +#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&_MBAR[0x2C038])) +#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&_MBAR[0x2E018])) +#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&_MBAR[0x2E028])) +#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&_MBAR[0x2E030])) +#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&_MBAR[0x2E038])) +#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&_MBAR[0x32018])) +#define MCF_SEC_AESSR (*(volatile uint32_t*)(&_MBAR[0x32028])) +#define MCF_SEC_AESISR (*(volatile uint32_t*)(&_MBAR[0x32030])) +#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&_MBAR[0x32038])) +#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)])) +#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)])) +#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)])) +#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)])) +#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)])) + + +/* Bit definitions and macros for MCF_SEC_EUACRH */ +#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1) +#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2) +#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0) +#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100) +#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200) +#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18) +#define MCF_SEC_EUACRH_RNG_NOASSIGN (0) +#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000) +#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000) + +/* Bit definitions and macros for MCF_SEC_EUACRL */ +#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUACRL_AESU_NOASSIGN (0) +#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000) +#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000) +#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SIMRH */ +#define MCF_SEC_SIMRH_AERR (0x8000000) +#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SIMRL */ +#define MCF_SEC_SIMRL_TEA (0x40) +#define MCF_SEC_SIMRL_DEU_DN (0x100) +#define MCF_SEC_SIMRL_DEU_ERR (0x200) +#define MCF_SEC_SIMRL_AESU_DN (0x1000) +#define MCF_SEC_SIMRL_AESU_ERR (0x2000) +#define MCF_SEC_SIMRL_MDEU_DN (0x10000) +#define MCF_SEC_SIMRL_MDEU_ERR (0x20000) +#define MCF_SEC_SIMRL_AFEU_DN (0x100000) +#define MCF_SEC_SIMRL_AFEU_ERR (0x200000) +#define MCF_SEC_SIMRL_RNG_DN (0x1000000) +#define MCF_SEC_SIMRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SISRH */ +#define MCF_SEC_SISRH_AERR (0x8000000) +#define MCF_SEC_SISRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SISRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SISRL */ +#define MCF_SEC_SISRL_TEA (0x40) +#define MCF_SEC_SISRL_DEU_DN (0x100) +#define MCF_SEC_SISRL_DEU_ERR (0x200) +#define MCF_SEC_SISRL_AESU_DN (0x1000) +#define MCF_SEC_SISRL_AESU_ERR (0x2000) +#define MCF_SEC_SISRL_MDEU_DN (0x10000) +#define MCF_SEC_SISRL_MDEU_ERR (0x20000) +#define MCF_SEC_SISRL_AFEU_DN (0x100000) +#define MCF_SEC_SISRL_AFEU_ERR (0x200000) +#define MCF_SEC_SISRL_RNG_DN (0x1000000) +#define MCF_SEC_SISRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SICRH */ +#define MCF_SEC_SICRH_AERR (0x8000000) +#define MCF_SEC_SICRH_CHA_0_DN (0x10000000) +#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000) +#define MCF_SEC_SICRH_CHA_1_DN (0x40000000) +#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000) + +/* Bit definitions and macros for MCF_SEC_SICRL */ +#define MCF_SEC_SICRL_TEA (0x40) +#define MCF_SEC_SICRL_DEU_DN (0x100) +#define MCF_SEC_SICRL_DEU_ERR (0x200) +#define MCF_SEC_SICRL_AESU_DN (0x1000) +#define MCF_SEC_SICRL_AESU_ERR (0x2000) +#define MCF_SEC_SICRL_MDEU_DN (0x10000) +#define MCF_SEC_SICRL_MDEU_ERR (0x20000) +#define MCF_SEC_SICRL_AFEU_DN (0x100000) +#define MCF_SEC_SICRL_AFEU_ERR (0x200000) +#define MCF_SEC_SICRL_RNG_DN (0x1000000) +#define MCF_SEC_SICRL_RNG_ERR (0x2000000) + +/* Bit definitions and macros for MCF_SEC_SIDR */ +#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_EUASRH */ +#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0) +#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8) +#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_EUASRL */ +#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10) +#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SEC_SMCR */ +#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4) +#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10) +#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20) +#define MCF_SEC_SMCR_SWR (0x1000000) + +/* Bit definitions and macros for MCF_SEC_MEAR */ +#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCCRn */ +#define MCF_SEC_CCCRn_RST (0x1) +#define MCF_SEC_CCCRn_CDIE (0x2) +#define MCF_SEC_CCCRn_NT (0x4) +#define MCF_SEC_CCCRn_NE (0x8) +#define MCF_SEC_CCCRn_WE (0x10) +#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8) +#define MCF_SEC_CCCRn_BURST_SIZE_2 (0) +#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100) +#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200) +#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300) +#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400) +#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500) +#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600) +#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700) + +/* Bit definitions and macros for MCF_SEC_CCPSRHn */ +#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_SEC_CCPSRLn */ +#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0) +#define MCF_SEC_CCPSRLn_EUERR (0x100) +#define MCF_SEC_CCPSRLn_SERR (0x200) +#define MCF_SEC_CCPSRLn_DERR (0x400) +#define MCF_SEC_CCPSRLn_PERR (0x1000) +#define MCF_SEC_CCPSRLn_TEA (0x2000) +#define MCF_SEC_CCPSRLn_SD (0x10000) +#define MCF_SEC_CCPSRLn_PD (0x20000) +#define MCF_SEC_CCPSRLn_SRD (0x40000) +#define MCF_SEC_CCPSRLn_PRD (0x80000) +#define MCF_SEC_CCPSRLn_SG (0x100000) +#define MCF_SEC_CCPSRLn_PG (0x200000) +#define MCF_SEC_CCPSRLn_SR (0x400000) +#define MCF_SEC_CCPSRLn_PR (0x800000) +#define MCF_SEC_CCPSRLn_MO (0x1000000) +#define MCF_SEC_CCPSRLn_MI (0x2000000) +#define MCF_SEC_CCPSRLn_STAT (0x4000000) + +/* Bit definitions and macros for MCF_SEC_CDPRn */ +#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_FRn */ +#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SEC_AFRCR */ +#define MCF_SEC_AFRCR_SR (0x1000000) +#define MCF_SEC_AFRCR_MI (0x2000000) +#define MCF_SEC_AFRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AFSR */ +#define MCF_SEC_AFSR_RD (0x1000000) +#define MCF_SEC_AFSR_ID (0x2000000) +#define MCF_SEC_AFSR_IE (0x4000000) +#define MCF_SEC_AFSR_OFR (0x8000000) +#define MCF_SEC_AFSR_IFW (0x10000000) +#define MCF_SEC_AFSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AFISR */ +#define MCF_SEC_AFISR_DSE (0x10000) +#define MCF_SEC_AFISR_KSE (0x20000) +#define MCF_SEC_AFISR_CE (0x40000) +#define MCF_SEC_AFISR_ERE (0x80000) +#define MCF_SEC_AFISR_IE (0x100000) +#define MCF_SEC_AFISR_OFU (0x2000000) +#define MCF_SEC_AFISR_IFO (0x4000000) +#define MCF_SEC_AFISR_IFE (0x10000000) +#define MCF_SEC_AFISR_OFE (0x20000000) +#define MCF_SEC_AFISR_AE (0x40000000) +#define MCF_SEC_AFISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AFIMR */ +#define MCF_SEC_AFIMR_DSE (0x10000) +#define MCF_SEC_AFIMR_KSE (0x20000) +#define MCF_SEC_AFIMR_CE (0x40000) +#define MCF_SEC_AFIMR_ERE (0x80000) +#define MCF_SEC_AFIMR_IE (0x100000) +#define MCF_SEC_AFIMR_OFU (0x2000000) +#define MCF_SEC_AFIMR_IFO (0x4000000) +#define MCF_SEC_AFIMR_IFE (0x10000000) +#define MCF_SEC_AFIMR_OFE (0x20000000) +#define MCF_SEC_AFIMR_AE (0x40000000) +#define MCF_SEC_AFIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DRCR */ +#define MCF_SEC_DRCR_SR (0x1000000) +#define MCF_SEC_DRCR_MI (0x2000000) +#define MCF_SEC_DRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_DSR */ +#define MCF_SEC_DSR_RD (0x1000000) +#define MCF_SEC_DSR_ID (0x2000000) +#define MCF_SEC_DSR_IE (0x4000000) +#define MCF_SEC_DSR_OFR (0x8000000) +#define MCF_SEC_DSR_IFW (0x10000000) +#define MCF_SEC_DSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_DISR */ +#define MCF_SEC_DISR_DSE (0x10000) +#define MCF_SEC_DISR_KSE (0x20000) +#define MCF_SEC_DISR_CE (0x40000) +#define MCF_SEC_DISR_ERE (0x80000) +#define MCF_SEC_DISR_IE (0x100000) +#define MCF_SEC_DISR_KPE (0x200000) +#define MCF_SEC_DISR_OFU (0x2000000) +#define MCF_SEC_DISR_IFO (0x4000000) +#define MCF_SEC_DISR_IFE (0x10000000) +#define MCF_SEC_DISR_OFE (0x20000000) +#define MCF_SEC_DISR_AE (0x40000000) +#define MCF_SEC_DISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_DIMR */ +#define MCF_SEC_DIMR_DSE (0x10000) +#define MCF_SEC_DIMR_KSE (0x20000) +#define MCF_SEC_DIMR_CE (0x40000) +#define MCF_SEC_DIMR_ERE (0x80000) +#define MCF_SEC_DIMR_IE (0x100000) +#define MCF_SEC_DIMR_KPE (0x200000) +#define MCF_SEC_DIMR_OFU (0x2000000) +#define MCF_SEC_DIMR_IFO (0x4000000) +#define MCF_SEC_DIMR_IFE (0x10000000) +#define MCF_SEC_DIMR_OFE (0x20000000) +#define MCF_SEC_DIMR_AE (0x40000000) +#define MCF_SEC_DIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDRCR */ +#define MCF_SEC_MDRCR_SR (0x1000000) +#define MCF_SEC_MDRCR_MI (0x2000000) +#define MCF_SEC_MDRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_MDSR */ +#define MCF_SEC_MDSR_RD (0x1000000) +#define MCF_SEC_MDSR_ID (0x2000000) +#define MCF_SEC_MDSR_IE (0x4000000) +#define MCF_SEC_MDSR_IFW (0x10000000) +#define MCF_SEC_MDSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_MDISR */ +#define MCF_SEC_MDISR_DSE (0x10000) +#define MCF_SEC_MDISR_KSE (0x20000) +#define MCF_SEC_MDISR_CE (0x40000) +#define MCF_SEC_MDISR_ERE (0x80000) +#define MCF_SEC_MDISR_IE (0x100000) +#define MCF_SEC_MDISR_IFO (0x4000000) +#define MCF_SEC_MDISR_AE (0x40000000) +#define MCF_SEC_MDISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_MDIMR */ +#define MCF_SEC_MDIMR_DSE (0x10000) +#define MCF_SEC_MDIMR_KSE (0x20000) +#define MCF_SEC_MDIMR_CE (0x40000) +#define MCF_SEC_MDIMR_ERE (0x80000) +#define MCF_SEC_MDIMR_IE (0x100000) +#define MCF_SEC_MDIMR_IFO (0x4000000) +#define MCF_SEC_MDIMR_AE (0x40000000) +#define MCF_SEC_MDIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGRCR */ +#define MCF_SEC_RNGRCR_SR (0x1000000) +#define MCF_SEC_RNGRCR_MI (0x2000000) +#define MCF_SEC_RNGRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_RNGSR */ +#define MCF_SEC_RNGSR_RD (0x1000000) +#define MCF_SEC_RNGSR_IE (0x4000000) +#define MCF_SEC_RNGSR_OFR (0x8000000) +#define MCF_SEC_RNGSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_RNGISR */ +#define MCF_SEC_RNGISR_IE (0x100000) +#define MCF_SEC_RNGISR_OFU (0x2000000) +#define MCF_SEC_RNGISR_AE (0x40000000) +#define MCF_SEC_RNGISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_RNGIMR */ +#define MCF_SEC_RNGIMR_IE (0x100000) +#define MCF_SEC_RNGIMR_OFU (0x2000000) +#define MCF_SEC_RNGIMR_AE (0x40000000) +#define MCF_SEC_RNGIMR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESRCR */ +#define MCF_SEC_AESRCR_SR (0x1000000) +#define MCF_SEC_AESRCR_MI (0x2000000) +#define MCF_SEC_AESRCR_RI (0x4000000) + +/* Bit definitions and macros for MCF_SEC_AESSR */ +#define MCF_SEC_AESSR_RD (0x1000000) +#define MCF_SEC_AESSR_ID (0x2000000) +#define MCF_SEC_AESSR_IE (0x4000000) +#define MCF_SEC_AESSR_OFR (0x8000000) +#define MCF_SEC_AESSR_IFW (0x10000000) +#define MCF_SEC_AESSR_HALT (0x20000000) + +/* Bit definitions and macros for MCF_SEC_AESISR */ +#define MCF_SEC_AESISR_DSE (0x10000) +#define MCF_SEC_AESISR_KSE (0x20000) +#define MCF_SEC_AESISR_CE (0x40000) +#define MCF_SEC_AESISR_ERE (0x80000) +#define MCF_SEC_AESISR_IE (0x100000) +#define MCF_SEC_AESISR_OFU (0x2000000) +#define MCF_SEC_AESISR_IFO (0x4000000) +#define MCF_SEC_AESISR_IFE (0x10000000) +#define MCF_SEC_AESISR_OFE (0x20000000) +#define MCF_SEC_AESISR_AE (0x40000000) +#define MCF_SEC_AESISR_ME (0x80000000) + +/* Bit definitions and macros for MCF_SEC_AESIMR */ +#define MCF_SEC_AESIMR_DSE (0x10000) +#define MCF_SEC_AESIMR_KSE (0x20000) +#define MCF_SEC_AESIMR_CE (0x40000) +#define MCF_SEC_AESIMR_ERE (0x80000) +#define MCF_SEC_AESIMR_IE (0x100000) +#define MCF_SEC_AESIMR_OFU (0x2000000) +#define MCF_SEC_AESIMR_IFO (0x4000000) +#define MCF_SEC_AESIMR_IFE (0x10000000) +#define MCF_SEC_AESIMR_OFE (0x20000000) +#define MCF_SEC_AESIMR_AE (0x40000000) +#define MCF_SEC_AESIMR_ME (0x80000000) + + +#endif /* __MCF5475_SEC_H__ */ diff --git a/BaS_gcc/include/MCF5475_SIU.h b/BaS_gcc/include/MCF5475_SIU.h new file mode 100644 index 0000000..4dda666 --- /dev/null +++ b/BaS_gcc/include/MCF5475_SIU.h @@ -0,0 +1,52 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SIU_H__ +#define __MCF5475_SIU_H__ + + +/********************************************************************* +* +* System Integration Unit (SIU) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SIU_SBCR (*(volatile uint32_t*)(&_MBAR[0x10])) +#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&_MBAR[0x38])) +#define MCF_SIU_RSR (*(volatile uint32_t*)(&_MBAR[0x44])) +#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&_MBAR[0x50])) + + +/* Bit definitions and macros for MCF_SIU_SBCR */ +#define MCF_SIU_SBCR_PIN2DSPI (0x8000000) +#define MCF_SIU_SBCR_DMA2CPU (0x10000000) +#define MCF_SIU_SBCR_CPU2DMA (0x20000000) +#define MCF_SIU_SBCR_PIN2DMA (0x40000000) +#define MCF_SIU_SBCR_PIN2CPU (0x80000000) + +/* Bit definitions and macros for MCF_SIU_SECSACR */ +#define MCF_SIU_SECSACR_SEQEN (0x1) + +/* Bit definitions and macros for MCF_SIU_RSR */ +#define MCF_SIU_RSR_RST (0x1) +#define MCF_SIU_RSR_RSTWD (0x2) +#define MCF_SIU_RSR_RSTJTG (0x8) + +/* Bit definitions and macros for MCF_SIU_JTAGID */ +#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0) + + +#endif /* __MCF5475_SIU_H__ */ diff --git a/BaS_gcc/include/MCF5475_SLT.h b/BaS_gcc/include/MCF5475_SLT.h new file mode 100644 index 0000000..f66fdc9 --- /dev/null +++ b/BaS_gcc/include/MCF5475_SLT.h @@ -0,0 +1,59 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SLT_H__ +#define __MCF5475_SLT_H__ + + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&_MBAR[0x900])) +#define MCF_SLT0_SCR (*(volatile uint32_t*)(&_MBAR[0x904])) +#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&_MBAR[0x908])) +#define MCF_SLT0_SSR (*(volatile uint32_t*)(&_MBAR[0x90C])) + +#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&_MBAR[0x910])) +#define MCF_SLT1_SCR (*(volatile uint32_t*)(&_MBAR[0x914])) +#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&_MBAR[0x918])) +#define MCF_SLT1_SSR (*(volatile uint32_t*)(&_MBAR[0x91C])) + +#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)])) +#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)])) +#define MCF_SLT_SCNT(x) (*(volatile uint32_t*)(&_MBAR[0x908 + ((x)*0x10)])) +#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)])) + + +/* Bit definitions and macros for MCF_SLT_STCNT */ +#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SCR */ +#define MCF_SLT_SCR_TEN (0x1000000) +#define MCF_SLT_SCR_IEN (0x2000000) +#define MCF_SLT_SCR_RUN (0x4000000) + +/* Bit definitions and macros for MCF_SLT_SCNT */ +#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_SLT_SSR */ +#define MCF_SLT_SSR_ST (0x1000000) +#define MCF_SLT_SSR_BE (0x2000000) + + +#endif /* __MCF5475_SLT_H__ */ diff --git a/BaS_gcc/include/MCF5475_SRAM.h b/BaS_gcc/include/MCF5475_SRAM.h new file mode 100644 index 0000000..d111f13 --- /dev/null +++ b/BaS_gcc/include/MCF5475_SRAM.h @@ -0,0 +1,62 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_SRAM_H__ +#define __MCF5475_SRAM_H__ + + +/********************************************************************* +* +* System SRAM Module (SRAM) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_SRAM_SSCR (*(volatile uint32_t*)(&__MBAR[0x1FFC0])) +#define MCF_SRAM_TCCR (*(volatile uint32_t*)(&__MBAR[0x1FFC4])) +#define MCF_SRAM_TCCRDR (*(volatile uint32_t*)(&__MBAR[0x1FFC8])) +#define MCF_SRAM_TCCRDW (*(volatile uint32_t*)(&__MBAR[0x1FFCC])) +#define MCF_SRAM_TCCRSEC (*(volatile uint32_t*)(&__MBAR[0x1FFD0])) + + +/* Bit definitions and macros for MCF_SRAM_SSCR */ +#define MCF_SRAM_SSCR_INLV (0x10000) + +/* Bit definitions and macros for MCF_SRAM_TCCR */ +#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDR */ +#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRDW */ +#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18) + +/* Bit definitions and macros for MCF_SRAM_TCCRSEC */ +#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0) +#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8) +#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10) +#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18) + + +#endif /* __MCF5475_SRAM_H__ */ diff --git a/BaS_gcc/include/MCF5475_USB.h b/BaS_gcc/include/MCF5475_USB.h new file mode 100644 index 0000000..c60273c --- /dev/null +++ b/BaS_gcc/include/MCF5475_USB.h @@ -0,0 +1,554 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_USB_H__ +#define __MCF5475_USB_H__ + + +/********************************************************************* +* +* Universal Serial Bus Interface (USB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_USB_USBAISR (*(volatile uint8_t *)(&__MBAR[0xB000])) +#define MCF_USB_USBAIMR (*(volatile uint8_t *)(&__MBAR[0xB001])) +#define MCF_USB_EPINFO (*(volatile uint8_t *)(&__MBAR[0xB003])) +#define MCF_USB_CFGR (*(volatile uint8_t *)(&__MBAR[0xB004])) +#define MCF_USB_CFGAR (*(volatile uint8_t *)(&__MBAR[0xB005])) +#define MCF_USB_SPEEDR (*(volatile uint8_t *)(&__MBAR[0xB006])) +#define MCF_USB_FRMNUMR (*(volatile uint16_t*)(&__MBAR[0xB00E])) +#define MCF_USB_EPTNR (*(volatile uint16_t*)(&__MBAR[0xB010])) +#define MCF_USB_IFUR (*(volatile uint16_t*)(&__MBAR[0xB014])) +#define MCF_USB_IFR0 (*(volatile uint16_t*)(&__MBAR[0xB040])) +#define MCF_USB_IFR1 (*(volatile uint16_t*)(&__MBAR[0xB042])) +#define MCF_USB_IFR2 (*(volatile uint16_t*)(&__MBAR[0xB044])) +#define MCF_USB_IFR3 (*(volatile uint16_t*)(&__MBAR[0xB046])) +#define MCF_USB_IFR4 (*(volatile uint16_t*)(&__MBAR[0xB048])) +#define MCF_USB_IFR5 (*(volatile uint16_t*)(&__MBAR[0xB04A])) +#define MCF_USB_IFR6 (*(volatile uint16_t*)(&__MBAR[0xB04C])) +#define MCF_USB_IFR7 (*(volatile uint16_t*)(&__MBAR[0xB04E])) +#define MCF_USB_IFR8 (*(volatile uint16_t*)(&__MBAR[0xB050])) +#define MCF_USB_IFR9 (*(volatile uint16_t*)(&__MBAR[0xB052])) +#define MCF_USB_IFR10 (*(volatile uint16_t*)(&__MBAR[0xB054])) +#define MCF_USB_IFR11 (*(volatile uint16_t*)(&__MBAR[0xB056])) +#define MCF_USB_IFR12 (*(volatile uint16_t*)(&__MBAR[0xB058])) +#define MCF_USB_IFR13 (*(volatile uint16_t*)(&__MBAR[0xB05A])) +#define MCF_USB_IFR14 (*(volatile uint16_t*)(&__MBAR[0xB05C])) +#define MCF_USB_IFR15 (*(volatile uint16_t*)(&__MBAR[0xB05E])) +#define MCF_USB_IFR16 (*(volatile uint16_t*)(&__MBAR[0xB060])) +#define MCF_USB_IFR17 (*(volatile uint16_t*)(&__MBAR[0xB062])) +#define MCF_USB_IFR18 (*(volatile uint16_t*)(&__MBAR[0xB064])) +#define MCF_USB_IFR19 (*(volatile uint16_t*)(&__MBAR[0xB066])) +#define MCF_USB_IFR20 (*(volatile uint16_t*)(&__MBAR[0xB068])) +#define MCF_USB_IFR21 (*(volatile uint16_t*)(&__MBAR[0xB06A])) +#define MCF_USB_IFR22 (*(volatile uint16_t*)(&__MBAR[0xB06C])) +#define MCF_USB_IFR23 (*(volatile uint16_t*)(&__MBAR[0xB06E])) +#define MCF_USB_IFR24 (*(volatile uint16_t*)(&__MBAR[0xB070])) +#define MCF_USB_IFR25 (*(volatile uint16_t*)(&__MBAR[0xB072])) +#define MCF_USB_IFR26 (*(volatile uint16_t*)(&__MBAR[0xB074])) +#define MCF_USB_IFR27 (*(volatile uint16_t*)(&__MBAR[0xB076])) +#define MCF_USB_IFR28 (*(volatile uint16_t*)(&__MBAR[0xB078])) +#define MCF_USB_IFR29 (*(volatile uint16_t*)(&__MBAR[0xB07A])) +#define MCF_USB_IFR30 (*(volatile uint16_t*)(&__MBAR[0xB07C])) +#define MCF_USB_IFR31 (*(volatile uint16_t*)(&__MBAR[0xB07E])) +#define MCF_USB_PPCNT (*(volatile uint16_t*)(&__MBAR[0xB080])) +#define MCF_USB_DPCNT (*(volatile uint16_t*)(&__MBAR[0xB082])) +#define MCF_USB_CRCECNT (*(volatile uint16_t*)(&__MBAR[0xB084])) +#define MCF_USB_BSECNT (*(volatile uint16_t*)(&__MBAR[0xB086])) +#define MCF_USB_PIDECNT (*(volatile uint16_t*)(&__MBAR[0xB088])) +#define MCF_USB_FRMECNT (*(volatile uint16_t*)(&__MBAR[0xB08A])) +#define MCF_USB_TXPCNT (*(volatile uint16_t*)(&__MBAR[0xB08C])) +#define MCF_USB_CNTOVR (*(volatile uint8_t *)(&__MBAR[0xB08E])) +#define MCF_USB_EP0ACR (*(volatile uint8_t *)(&__MBAR[0xB101])) +#define MCF_USB_EP0MPSR (*(volatile uint16_t*)(&__MBAR[0xB102])) +#define MCF_USB_EP0IFR (*(volatile uint8_t *)(&__MBAR[0xB104])) +#define MCF_USB_EP0SR (*(volatile uint8_t *)(&__MBAR[0xB105])) +#define MCF_USB_BMRTR (*(volatile uint8_t *)(&__MBAR[0xB106])) +#define MCF_USB_BRTR (*(volatile uint8_t *)(&__MBAR[0xB107])) +#define MCF_USB_WVALUER (*(volatile uint16_t*)(&__MBAR[0xB108])) +#define MCF_USB_WINDEXR (*(volatile uint16_t*)(&__MBAR[0xB10A])) +#define MCF_USB_WLENGTHR (*(volatile uint16_t*)(&__MBAR[0xB10C])) +#define MCF_USB_EP1OUTACR (*(volatile uint8_t *)(&__MBAR[0xB131])) +#define MCF_USB_EP1OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB132])) +#define MCF_USB_EP1OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB134])) +#define MCF_USB_EP1OUTSR (*(volatile uint8_t *)(&__MBAR[0xB135])) +#define MCF_USB_EP1OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB13E])) +#define MCF_USB_EP1INACR (*(volatile uint8_t *)(&__MBAR[0xB149])) +#define MCF_USB_EP1INMPSR (*(volatile uint16_t*)(&__MBAR[0xB14A])) +#define MCF_USB_EP1INIFR (*(volatile uint8_t *)(&__MBAR[0xB14C])) +#define MCF_USB_EP1INSR (*(volatile uint8_t *)(&__MBAR[0xB14D])) +#define MCF_USB_EP1INSFR (*(volatile uint16_t*)(&__MBAR[0xB156])) +#define MCF_USB_EP2OUTACR (*(volatile uint8_t *)(&__MBAR[0xB161])) +#define MCF_USB_EP2OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB162])) +#define MCF_USB_EP2OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB164])) +#define MCF_USB_EP2OUTSR (*(volatile uint8_t *)(&__MBAR[0xB165])) +#define MCF_USB_EP2OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB16E])) +#define MCF_USB_EP2INACR (*(volatile uint8_t *)(&__MBAR[0xB179])) +#define MCF_USB_EP2INMPSR (*(volatile uint16_t*)(&__MBAR[0xB17A])) +#define MCF_USB_EP2INIFR (*(volatile uint8_t *)(&__MBAR[0xB17C])) +#define MCF_USB_EP2INSR (*(volatile uint8_t *)(&__MBAR[0xB17D])) +#define MCF_USB_EP2INSFR (*(volatile uint16_t*)(&__MBAR[0xB186])) +#define MCF_USB_EP3OUTACR (*(volatile uint8_t *)(&__MBAR[0xB191])) +#define MCF_USB_EP3OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB192])) +#define MCF_USB_EP3OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB194])) +#define MCF_USB_EP3OUTSR (*(volatile uint8_t *)(&__MBAR[0xB195])) +#define MCF_USB_EP3OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB19E])) +#define MCF_USB_EP3INACR (*(volatile uint8_t *)(&__MBAR[0xB1A9])) +#define MCF_USB_EP3INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1AA])) +#define MCF_USB_EP3INIFR (*(volatile uint8_t *)(&__MBAR[0xB1AC])) +#define MCF_USB_EP3INSR (*(volatile uint8_t *)(&__MBAR[0xB1AD])) +#define MCF_USB_EP3INSFR (*(volatile uint16_t*)(&__MBAR[0xB1B6])) +#define MCF_USB_EP4OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1C1])) +#define MCF_USB_EP4OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1C2])) +#define MCF_USB_EP4OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1C4])) +#define MCF_USB_EP4OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1C5])) +#define MCF_USB_EP4OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1CE])) +#define MCF_USB_EP4INACR (*(volatile uint8_t *)(&__MBAR[0xB1D9])) +#define MCF_USB_EP4INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1DA])) +#define MCF_USB_EP4INIFR (*(volatile uint8_t *)(&__MBAR[0xB1DC])) +#define MCF_USB_EP4INSR (*(volatile uint8_t *)(&__MBAR[0xB1DD])) +#define MCF_USB_EP4INSFR (*(volatile uint16_t*)(&__MBAR[0xB1E6])) +#define MCF_USB_EP5OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1F1])) +#define MCF_USB_EP5OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1F2])) +#define MCF_USB_EP5OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1F4])) +#define MCF_USB_EP5OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1F5])) +#define MCF_USB_EP5OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1FE])) +#define MCF_USB_EP5INACR (*(volatile uint8_t *)(&__MBAR[0xB209])) +#define MCF_USB_EP5INMPSR (*(volatile uint16_t*)(&__MBAR[0xB20A])) +#define MCF_USB_EP5INIFR (*(volatile uint8_t *)(&__MBAR[0xB20C])) +#define MCF_USB_EP5INSR (*(volatile uint8_t *)(&__MBAR[0xB20D])) +#define MCF_USB_EP5INSFR (*(volatile uint16_t*)(&__MBAR[0xB216])) +#define MCF_USB_EP6OUTACR (*(volatile uint8_t *)(&__MBAR[0xB221])) +#define MCF_USB_EP6OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB222])) +#define MCF_USB_EP6OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB224])) +#define MCF_USB_EP6OUTSR (*(volatile uint8_t *)(&__MBAR[0xB225])) +#define MCF_USB_EP6OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB22E])) +#define MCF_USB_EP6INACR (*(volatile uint8_t *)(&__MBAR[0xB239])) +#define MCF_USB_EP6INMPSR (*(volatile uint16_t*)(&__MBAR[0xB23A])) +#define MCF_USB_EP6INIFR (*(volatile uint8_t *)(&__MBAR[0xB23C])) +#define MCF_USB_EP6INSR (*(volatile uint8_t *)(&__MBAR[0xB23D])) +#define MCF_USB_EP6INSFR (*(volatile uint16_t*)(&__MBAR[0xB246])) +#define MCF_USB_USBSR (*(volatile uint32_t*)(&__MBAR[0xB400])) +#define MCF_USB_USBCR (*(volatile uint32_t*)(&__MBAR[0xB404])) +#define MCF_USB_DRAMCR (*(volatile uint32_t*)(&__MBAR[0xB408])) +#define MCF_USB_DRAMDR (*(volatile uint32_t*)(&__MBAR[0xB40C])) +#define MCF_USB_USBISR (*(volatile uint32_t*)(&__MBAR[0xB410])) +#define MCF_USB_USBIMR (*(volatile uint32_t*)(&__MBAR[0xB414])) +#define MCF_USB_EP0STAT (*(volatile uint32_t*)(&__MBAR[0xB440])) +#define MCF_USB_EP0ISR (*(volatile uint32_t*)(&__MBAR[0xB444])) +#define MCF_USB_EP0IMR (*(volatile uint32_t*)(&__MBAR[0xB448])) +#define MCF_USB_EP0FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB44C])) +#define MCF_USB_EP0FDR (*(volatile uint32_t*)(&__MBAR[0xB450])) +#define MCF_USB_EP0FSR (*(volatile uint32_t*)(&__MBAR[0xB454])) +#define MCF_USB_EP0FCR (*(volatile uint32_t*)(&__MBAR[0xB458])) +#define MCF_USB_EP0FAR (*(volatile uint32_t*)(&__MBAR[0xB45C])) +#define MCF_USB_EP0FRP (*(volatile uint32_t*)(&__MBAR[0xB460])) +#define MCF_USB_EP0FWP (*(volatile uint32_t*)(&__MBAR[0xB464])) +#define MCF_USB_EP0LRFP (*(volatile uint32_t*)(&__MBAR[0xB468])) +#define MCF_USB_EP0LWFP (*(volatile uint32_t*)(&__MBAR[0xB46C])) +#define MCF_USB_EP1STAT (*(volatile uint32_t*)(&__MBAR[0xB470])) +#define MCF_USB_EP1ISR (*(volatile uint32_t*)(&__MBAR[0xB474])) +#define MCF_USB_EP1IMR (*(volatile uint32_t*)(&__MBAR[0xB478])) +#define MCF_USB_EP1FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB47C])) +#define MCF_USB_EP1FDR (*(volatile uint32_t*)(&__MBAR[0xB480])) +#define MCF_USB_EP1FSR (*(volatile uint32_t*)(&__MBAR[0xB484])) +#define MCF_USB_EP1FCR (*(volatile uint32_t*)(&__MBAR[0xB488])) +#define MCF_USB_EP1FAR (*(volatile uint32_t*)(&__MBAR[0xB48C])) +#define MCF_USB_EP1FRP (*(volatile uint32_t*)(&__MBAR[0xB490])) +#define MCF_USB_EP1FWP (*(volatile uint32_t*)(&__MBAR[0xB494])) +#define MCF_USB_EP1LRFP (*(volatile uint32_t*)(&__MBAR[0xB498])) +#define MCF_USB_EP1LWFP (*(volatile uint32_t*)(&__MBAR[0xB49C])) +#define MCF_USB_EP2STAT (*(volatile uint32_t*)(&__MBAR[0xB4A0])) +#define MCF_USB_EP2ISR (*(volatile uint32_t*)(&__MBAR[0xB4A4])) +#define MCF_USB_EP2IMR (*(volatile uint32_t*)(&__MBAR[0xB4A8])) +#define MCF_USB_EP2FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4AC])) +#define MCF_USB_EP2FDR (*(volatile uint32_t*)(&__MBAR[0xB4B0])) +#define MCF_USB_EP2FSR (*(volatile uint32_t*)(&__MBAR[0xB4B4])) +#define MCF_USB_EP2FCR (*(volatile uint32_t*)(&__MBAR[0xB4B8])) +#define MCF_USB_EP2FAR (*(volatile uint32_t*)(&__MBAR[0xB4BC])) +#define MCF_USB_EP2FRP (*(volatile uint32_t*)(&__MBAR[0xB4C0])) +#define MCF_USB_EP2FWP (*(volatile uint32_t*)(&__MBAR[0xB4C4])) +#define MCF_USB_EP2LRFP (*(volatile uint32_t*)(&__MBAR[0xB4C8])) +#define MCF_USB_EP2LWFP (*(volatile uint32_t*)(&__MBAR[0xB4CC])) +#define MCF_USB_EP3STAT (*(volatile uint32_t*)(&__MBAR[0xB4D0])) +#define MCF_USB_EP3ISR (*(volatile uint32_t*)(&__MBAR[0xB4D4])) +#define MCF_USB_EP3IMR (*(volatile uint32_t*)(&__MBAR[0xB4D8])) +#define MCF_USB_EP3FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4DC])) +#define MCF_USB_EP3FDR (*(volatile uint32_t*)(&__MBAR[0xB4E0])) +#define MCF_USB_EP3FSR (*(volatile uint32_t*)(&__MBAR[0xB4E4])) +#define MCF_USB_EP3FCR (*(volatile uint32_t*)(&__MBAR[0xB4E8])) +#define MCF_USB_EP3FAR (*(volatile uint32_t*)(&__MBAR[0xB4EC])) +#define MCF_USB_EP3FRP (*(volatile uint32_t*)(&__MBAR[0xB4F0])) +#define MCF_USB_EP3FWP (*(volatile uint32_t*)(&__MBAR[0xB4F4])) +#define MCF_USB_EP3LRFP (*(volatile uint32_t*)(&__MBAR[0xB4F8])) +#define MCF_USB_EP3LWFP (*(volatile uint32_t*)(&__MBAR[0xB4FC])) +#define MCF_USB_EP4STAT (*(volatile uint32_t*)(&__MBAR[0xB500])) +#define MCF_USB_EP4ISR (*(volatile uint32_t*)(&__MBAR[0xB504])) +#define MCF_USB_EP4IMR (*(volatile uint32_t*)(&__MBAR[0xB508])) +#define MCF_USB_EP4FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB50C])) +#define MCF_USB_EP4FDR (*(volatile uint32_t*)(&__MBAR[0xB510])) +#define MCF_USB_EP4FSR (*(volatile uint32_t*)(&__MBAR[0xB514])) +#define MCF_USB_EP4FCR (*(volatile uint32_t*)(&__MBAR[0xB518])) +#define MCF_USB_EP4FAR (*(volatile uint32_t*)(&__MBAR[0xB51C])) +#define MCF_USB_EP4FRP (*(volatile uint32_t*)(&__MBAR[0xB520])) +#define MCF_USB_EP4FWP (*(volatile uint32_t*)(&__MBAR[0xB524])) +#define MCF_USB_EP4LRFP (*(volatile uint32_t*)(&__MBAR[0xB528])) +#define MCF_USB_EP4LWFP (*(volatile uint32_t*)(&__MBAR[0xB52C])) +#define MCF_USB_EP5STAT (*(volatile uint32_t*)(&__MBAR[0xB530])) +#define MCF_USB_EP5ISR (*(volatile uint32_t*)(&__MBAR[0xB534])) +#define MCF_USB_EP5IMR (*(volatile uint32_t*)(&__MBAR[0xB538])) +#define MCF_USB_EP5FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB53C])) +#define MCF_USB_EP5FDR (*(volatile uint32_t*)(&__MBAR[0xB540])) +#define MCF_USB_EP5FSR (*(volatile uint32_t*)(&__MBAR[0xB544])) +#define MCF_USB_EP5FCR (*(volatile uint32_t*)(&__MBAR[0xB548])) +#define MCF_USB_EP5FAR (*(volatile uint32_t*)(&__MBAR[0xB54C])) +#define MCF_USB_EP5FRP (*(volatile uint32_t*)(&__MBAR[0xB550])) +#define MCF_USB_EP5FWP (*(volatile uint32_t*)(&__MBAR[0xB554])) +#define MCF_USB_EP5LRFP (*(volatile uint32_t*)(&__MBAR[0xB558])) +#define MCF_USB_EP5LWFP (*(volatile uint32_t*)(&__MBAR[0xB55C])) +#define MCF_USB_EP6STAT (*(volatile uint32_t*)(&__MBAR[0xB560])) +#define MCF_USB_EP6ISR (*(volatile uint32_t*)(&__MBAR[0xB564])) +#define MCF_USB_EP6IMR (*(volatile uint32_t*)(&__MBAR[0xB568])) +#define MCF_USB_EP6FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB56C])) +#define MCF_USB_EP6FDR (*(volatile uint32_t*)(&__MBAR[0xB570])) +#define MCF_USB_EP6FSR (*(volatile uint32_t*)(&__MBAR[0xB574])) +#define MCF_USB_EP6FCR (*(volatile uint32_t*)(&__MBAR[0xB578])) +#define MCF_USB_EP6FAR (*(volatile uint32_t*)(&__MBAR[0xB57C])) +#define MCF_USB_EP6FRP (*(volatile uint32_t*)(&__MBAR[0xB580])) +#define MCF_USB_EP6FWP (*(volatile uint32_t*)(&__MBAR[0xB584])) +#define MCF_USB_EP6LRFP (*(volatile uint32_t*)(&__MBAR[0xB588])) +#define MCF_USB_EP6LWFP (*(volatile uint32_t*)(&__MBAR[0xB58C])) +#define MCF_USB_IFR(x) (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)])) +#define MCF_USB_EPOUTACR(x) (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSR(x) (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)])) +#define MCF_USB_EPOUTSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)])) +#define MCF_USB_EPINACR(x) (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)])) +#define MCF_USB_EPINMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)])) +#define MCF_USB_EPINIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)])) +#define MCF_USB_EPINSR(x) (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)])) +#define MCF_USB_EPINSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)])) +#define MCF_USB_EPSTAT(x) (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)])) +#define MCF_USB_EPISR(x) (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)])) +#define MCF_USB_EPIMR(x) (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)])) +#define MCF_USB_EPFRCFGR(x) (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)])) +#define MCF_USB_EPFDR(x) (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)])) +#define MCF_USB_EPFSR(x) (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)])) +#define MCF_USB_EPFCR(x) (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)])) +#define MCF_USB_EPFAR(x) (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)])) +#define MCF_USB_EPFRP(x) (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)])) +#define MCF_USB_EPFWP(x) (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)])) +#define MCF_USB_EPLRFP(x) (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)])) +#define MCF_USB_EPLWFP(x) (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)])) + + +/* Bit definitions and macros for MCF_USB_USBAISR */ +#define MCF_USB_USBAISR_SETUP (0x1) +#define MCF_USB_USBAISR_IN (0x2) +#define MCF_USB_USBAISR_OUT (0x4) +#define MCF_USB_USBAISR_EPHALT (0x8) +#define MCF_USB_USBAISR_TRANSERR (0x10) +#define MCF_USB_USBAISR_ACK (0x20) +#define MCF_USB_USBAISR_CTROVFL (0x40) +#define MCF_USB_USBAISR_EPSTALL (0x80) + +/* Bit definitions and macros for MCF_USB_USBAIMR */ +#define MCF_USB_USBAIMR_SETUPEN (0x1) +#define MCF_USB_USBAIMR_INEN (0x2) +#define MCF_USB_USBAIMR_OUTEN (0x4) +#define MCF_USB_USBAIMR_EPHALTEN (0x8) +#define MCF_USB_USBAIMR_TRANSERREN (0x10) +#define MCF_USB_USBAIMR_ACKEN (0x20) +#define MCF_USB_USBAIMR_CTROVFLEN (0x40) +#define MCF_USB_USBAIMR_EPSTALLEN (0x80) + +/* Bit definitions and macros for MCF_USB_EPINFO */ +#define MCF_USB_EPINFO_EPDIR (0x1) +#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1) + +/* Bit definitions and macros for MCF_USB_CFGR */ +#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_CFGAR */ +#define MCF_USB_CFGAR_RESERVED (0xA0) +#define MCF_USB_CFGAR_RMTWKEUP (0xE0) + +/* Bit definitions and macros for MCF_USB_SPEEDR */ +#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0) + +/* Bit definitions and macros for MCF_USB_FRMNUMR */ +#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPTNR */ +#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0) +#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2) +#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4) +#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6) +#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8) +#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA) +#define MCF_USB_EPTNR_EPnT1 (0) +#define MCF_USB_EPTNR_EPnT2 (0x1) +#define MCF_USB_EPTNR_EPnT3 (0x2) + +/* Bit definitions and macros for MCF_USB_IFUR */ +#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_IFR */ +#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0) +#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8) + +/* Bit definitions and macros for MCF_USB_PPCNT */ +#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_DPCNT */ +#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CRCECNT */ +#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_BSECNT */ +#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_PIDECNT */ +#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_FRMECNT */ +#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_TXPCNT */ +#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_CNTOVR */ +#define MCF_USB_CNTOVR_PPCNT (0x1) +#define MCF_USB_CNTOVR_DPCNT (0x2) +#define MCF_USB_CNTOVR_CRCECNT (0x4) +#define MCF_USB_CNTOVR_BSECNT (0x8) +#define MCF_USB_CNTOVR_PIDECNT (0x10) +#define MCF_USB_CNTOVR_FRMECNT (0x20) +#define MCF_USB_CNTOVR_TXPCNT (0x40) + +/* Bit definitions and macros for MCF_USB_EP0ACR */ +#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EP0ACR_TTYPE_CTRL (0) +#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1) +#define MCF_USB_EP0ACR_TTYPE_BULK (0x2) +#define MCF_USB_EP0ACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EP0MPSR */ +#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EP0IFR */ +#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EP0SR */ +#define MCF_USB_EP0SR_HALT (0x1) +#define MCF_USB_EP0SR_ACTIVE (0x2) +#define MCF_USB_EP0SR_PSTALL (0x4) +#define MCF_USB_EP0SR_CCOMP (0x8) +#define MCF_USB_EP0SR_TXZERO (0x20) +#define MCF_USB_EP0SR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_BMRTR */ +#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0) +#define MCF_USB_BMRTR_REC_DEVICE (0) +#define MCF_USB_BMRTR_REC_INTERFACE (0x1) +#define MCF_USB_BMRTR_REC_ENDPOINT (0x2) +#define MCF_USB_BMRTR_REC_OTHER (0x3) +#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5) +#define MCF_USB_BMRTR_TYPE_STANDARD (0) +#define MCF_USB_BMRTR_TYPE_CLASS (0x20) +#define MCF_USB_BMRTR_TYPE_VENDOR (0x40) +#define MCF_USB_BMRTR_DIR (0x80) + +/* Bit definitions and macros for MCF_USB_BRTR */ +#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_WVALUER */ +#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WINDEXR */ +#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_WLENGTHR */ +#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTACR */ +#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2) +#define MCF_USB_EPOUTACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPOUTMPSR */ +#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPOUTIFR */ +#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPOUTSR */ +#define MCF_USB_EPOUTSR_HALT (0x1) +#define MCF_USB_EPOUTSR_ACTIVE (0x2) +#define MCF_USB_EPOUTSR_PSTALL (0x4) +#define MCF_USB_EPOUTSR_CCOMP (0x8) +#define MCF_USB_EPOUTSR_TXZERO (0x20) +#define MCF_USB_EPOUTSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPOUTSFR */ +#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINACR */ +#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0) +#define MCF_USB_EPINACR_TTYPE_ISOC (0x1) +#define MCF_USB_EPINACR_TTYPE_BULK (0x2) +#define MCF_USB_EPINACR_TTYPE_INT (0x3) + +/* Bit definitions and macros for MCF_USB_EPINMPSR */ +#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0) +#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB) + +/* Bit definitions and macros for MCF_USB_EPINIFR */ +#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPINSR */ +#define MCF_USB_EPINSR_HALT (0x1) +#define MCF_USB_EPINSR_ACTIVE (0x2) +#define MCF_USB_EPINSR_PSTALL (0x4) +#define MCF_USB_EPINSR_CCOMP (0x8) +#define MCF_USB_EPINSR_TXZERO (0x20) +#define MCF_USB_EPINSR_INT (0x80) + +/* Bit definitions and macros for MCF_USB_EPINSFR */ +#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0) + +/* Bit definitions and macros for MCF_USB_USBSR */ +#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0) +#define MCF_USB_USBSR_SUSP (0x80) + +/* Bit definitions and macros for MCF_USB_USBCR */ +#define MCF_USB_USBCR_RESUME (0x1) +#define MCF_USB_USBCR_APPLOCK (0x2) +#define MCF_USB_USBCR_RST (0x4) +#define MCF_USB_USBCR_RAMEN (0x8) +#define MCF_USB_USBCR_RAMSPLIT (0x20) + +/* Bit definitions and macros for MCF_USB_DRAMCR */ +#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0) +#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10) +#define MCF_USB_DRAMCR_BSY (0x40000000) +#define MCF_USB_DRAMCR_START (0x80000000) + +/* Bit definitions and macros for MCF_USB_DRAMDR */ +#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_USB_USBISR */ +#define MCF_USB_USBISR_ISOERR (0x1) +#define MCF_USB_USBISR_FTUNLCK (0x2) +#define MCF_USB_USBISR_SUSP (0x4) +#define MCF_USB_USBISR_RES (0x8) +#define MCF_USB_USBISR_UPDSOF (0x10) +#define MCF_USB_USBISR_RSTSTOP (0x20) +#define MCF_USB_USBISR_SOF (0x40) +#define MCF_USB_USBISR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_USBIMR */ +#define MCF_USB_USBIMR_ISOERR (0x1) +#define MCF_USB_USBIMR_FTUNLCK (0x2) +#define MCF_USB_USBIMR_SUSP (0x4) +#define MCF_USB_USBIMR_RES (0x8) +#define MCF_USB_USBIMR_UPDSOF (0x10) +#define MCF_USB_USBIMR_RSTSTOP (0x20) +#define MCF_USB_USBIMR_SOF (0x40) +#define MCF_USB_USBIMR_MSOF (0x80) + +/* Bit definitions and macros for MCF_USB_EPSTAT */ +#define MCF_USB_EPSTAT_RST (0x1) +#define MCF_USB_EPSTAT_FLUSH (0x2) +#define MCF_USB_EPSTAT_DIR (0x80) +#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPISR */ +#define MCF_USB_EPISR_EOF (0x1) +#define MCF_USB_EPISR_EOT (0x4) +#define MCF_USB_EPISR_FIFOLO (0x10) +#define MCF_USB_EPISR_FIFOHI (0x20) +#define MCF_USB_EPISR_ERR (0x40) +#define MCF_USB_EPISR_EMT (0x80) +#define MCF_USB_EPISR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPIMR */ +#define MCF_USB_EPIMR_EOF (0x1) +#define MCF_USB_EPIMR_EOT (0x4) +#define MCF_USB_EPIMR_FIFOLO (0x10) +#define MCF_USB_EPIMR_FIFOHI (0x20) +#define MCF_USB_EPIMR_ERR (0x40) +#define MCF_USB_EPIMR_EMT (0x80) +#define MCF_USB_EPIMR_FU (0x100) + +/* Bit definitions and macros for MCF_USB_EPFRCFGR */ +#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0) +#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10) + +/* Bit definitions and macros for MCF_USB_EPFDR */ +#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFSR */ +#define MCF_USB_EPFSR_EMT (0x10000) +#define MCF_USB_EPFSR_ALRM (0x20000) +#define MCF_USB_EPFSR_FU (0x40000) +#define MCF_USB_EPFSR_FR (0x80000) +#define MCF_USB_EPFSR_OF (0x100000) +#define MCF_USB_EPFSR_UF (0x200000) +#define MCF_USB_EPFSR_RXW (0x400000) +#define MCF_USB_EPFSR_FAE (0x800000) +#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18) +#define MCF_USB_EPFSR_TXW (0x40000000) +#define MCF_USB_EPFSR_IP (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFCR */ +#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0) +#define MCF_USB_EPFCR_TXWMSK (0x40000) +#define MCF_USB_EPFCR_OFMSK (0x80000) +#define MCF_USB_EPFCR_UFMSK (0x100000) +#define MCF_USB_EPFCR_RXWMSK (0x200000) +#define MCF_USB_EPFCR_FAEMSK (0x400000) +#define MCF_USB_EPFCR_IPMSK (0x800000) +#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18) +#define MCF_USB_EPFCR_FRM (0x8000000) +#define MCF_USB_EPFCR_TMR (0x10000000) +#define MCF_USB_EPFCR_WFR (0x20000000) +#define MCF_USB_EPFCR_SHAD (0x80000000) + +/* Bit definitions and macros for MCF_USB_EPFAR */ +#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFRP */ +#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPFWP */ +#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLRFP */ +#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0) + +/* Bit definitions and macros for MCF_USB_EPLWFP */ +#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0) + + +#endif /* __MCF5475_USB_H__ */ diff --git a/BaS_gcc/include/MCF5475_XLB.h b/BaS_gcc/include/MCF5475_XLB.h new file mode 100644 index 0000000..d995dd2 --- /dev/null +++ b/BaS_gcc/include/MCF5475_XLB.h @@ -0,0 +1,101 @@ +/* Coldfire C Header File + * Copyright Freescale Semiconductor Inc + * All rights reserved. + * + * 2008/05/23 Revision: 0.81 + * + * (c) Copyright UNIS, a.s. 1997-2008 + * UNIS, a.s. + * Jundrovska 33 + * 624 00 Brno + * Czech Republic + * http : www.processorexpert.com + * mail : info@processorexpert.com + */ + +#ifndef __MCF5475_XLB_H__ +#define __MCF5475_XLB_H__ + + +/********************************************************************* +* +* XL Bus Arbiter (XLB) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_XLB_XARB_CFG (*(volatile uint32_t*)(&__MBAR[0x240])) +#define MCF_XLB_XARB_VER (*(volatile uint32_t*)(&__MBAR[0x244])) +#define MCF_XLB_XARB_SR (*(volatile uint32_t*)(&__MBAR[0x248])) +#define MCF_XLB_XARB_IMR (*(volatile uint32_t*)(&__MBAR[0x24C])) +#define MCF_XLB_XARB_ADRCAP (*(volatile uint32_t*)(&__MBAR[0x250])) +#define MCF_XLB_XARB_SIGCAP (*(volatile uint32_t*)(&__MBAR[0x254])) +#define MCF_XLB_XARB_ADRTO (*(volatile uint32_t*)(&__MBAR[0x258])) +#define MCF_XLB_XARB_DATTO (*(volatile uint32_t*)(&__MBAR[0x25C])) +#define MCF_XLB_XARB_BUSTO (*(volatile uint32_t*)(&__MBAR[0x260])) +#define MCF_XLB_XARB_PRIEN (*(volatile uint32_t*)(&__MBAR[0x264])) +#define MCF_XLB_XARB_PRI (*(volatile uint32_t*)(&__MBAR[0x268])) + + +/* Bit definitions and macros for MCF_XLB_XARB_CFG */ +#define MCF_XLB_XARB_CFG_AT (0x2) +#define MCF_XLB_XARB_CFG_DT (0x4) +#define MCF_XLB_XARB_CFG_BA (0x8) +#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5) +#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_CFG_PLDIS (0x80000000) + +/* Bit definitions and macros for MCF_XLB_XARB_VER */ +#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SR */ +#define MCF_XLB_XARB_SR_AT (0x1) +#define MCF_XLB_XARB_SR_DT (0x2) +#define MCF_XLB_XARB_SR_BA (0x4) +#define MCF_XLB_XARB_SR_TTM (0x8) +#define MCF_XLB_XARB_SR_ECW (0x10) +#define MCF_XLB_XARB_SR_TTR (0x20) +#define MCF_XLB_XARB_SR_TTA (0x40) +#define MCF_XLB_XARB_SR_MM (0x80) +#define MCF_XLB_XARB_SR_SEA (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_IMR */ +#define MCF_XLB_XARB_IMR_ATE (0x1) +#define MCF_XLB_XARB_IMR_DTE (0x2) +#define MCF_XLB_XARB_IMR_BAE (0x4) +#define MCF_XLB_XARB_IMR_TTME (0x8) +#define MCF_XLB_XARB_IMR_ECWE (0x10) +#define MCF_XLB_XARB_IMR_TTRE (0x20) +#define MCF_XLB_XARB_IMR_TTAE (0x40) +#define MCF_XLB_XARB_IMR_MME (0x80) +#define MCF_XLB_XARB_IMR_SEAE (0x100) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */ +#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */ +#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0) +#define MCF_XLB_XARB_SIGCAP_TBST (0x20) +#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7) + +/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */ +#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_DATTO */ +#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */ +#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */ +#define MCF_XLB_XARB_PRIEN_M0 (0x1) +#define MCF_XLB_XARB_PRIEN_M2 (0x4) +#define MCF_XLB_XARB_PRIEN_M3 (0x8) + +/* Bit definitions and macros for MCF_XLB_XARB_PRI */ +#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0) +#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8) +#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC) + + +#endif /* __MCF5475_XLB_H__ */ diff --git a/BaS_gcc/include/bas_printf.h b/BaS_gcc/include/bas_printf.h new file mode 100644 index 0000000..68209e8 --- /dev/null +++ b/BaS_gcc/include/bas_printf.h @@ -0,0 +1,13 @@ +#ifndef _BAS_PRINTF_H_ +#define _BAS_PRINTF_H_ +#include +typedef uint32_t size_t; + +extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va); +extern void xvprintf(const char *fmt, va_list va); +extern void xprintf(const char *fmt, ...); +extern void xsnprintf(char *str, size_t size, const char *fmt, ...); + +extern void display_progress(void); + +#endif /* _BAS_PRINTF_H_ */ diff --git a/BaS_gcc/mcf5474.bdm b/BaS_gcc/mcf5474.bdm new file mode 100755 index 0000000..40975b6 --- /dev/null +++ b/BaS_gcc/mcf5474.bdm @@ -0,0 +1,75 @@ +#!/usr/local/bin/bdmctrl +# +# firebee board initialization for bdmctrl +# +open $1 +reset + +wait + +# set VBR +#write-ctrl 0x0801 0x00000000 +sleep 10 +# Turn on MBAR at 0xFF00_0000 +write-ctrl 0x0C0F 0xFF000000 + +# Turn on MMUBAR at 0xFF04_0000 +write-ctrl 0x0008 0xFF040001 + +# Turn on RAMBAR0 at address FF10_0000 +write-ctrl 0x0C04 0xFF100007 +sleep 10 +# Turn on RAMBAR1 at address FF10_1000 +write-ctrl 0x0C05 0xFF101001 +sleep 10 + +# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +write 0xFF000500 0xE0000000 4 +write 0xFF000508 0x00001180 4 +write 0xFF000504 0x007F0001 4 +# Init CS1 (Atari I/O address range) +#write 0xFF00050C 0xFFF00000 4 +#write 0xFF000514 0x00002180 4 +#write 0xFF000510 0x000F0001 4 +# Init CS2 (FireBee 32 bit I/O address range) +#write 0xFF000518 0xF0000000 4 +#write 0xFF000520 0x00002100 4 +#write 0xFF00051C 0x07FF0001 4 +# Init CS3 (FireBee 16 bit I/O address range) +#write 0xFF000524 0xF8000000 4 +#write 0xFF00052C 0x00000180 4 +#write 0xFF000528 0x03FF0001 4 +# Init CS4 (FireBee video address range) +#write 0xFF000530 0x40000000 4 +#write 0xFF000538 0x00000018 4 +#write 0xFF000534 0x003F0001 4 + + +# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +write 0xFF000004 0x000002AA 4 # SDRAMDS configuration +write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) +write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) +write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF) +write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) +write 0xFF000108 0x73622830 4 # SDCFG1 +write 0xFF00010C 0x46770000 4 # SDCFG2 + +write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +write 0xFF000100 0x40010000 4 # SDMR (write to LEMR) +write 0xFF000100 0x048D0000 4 # SDMR (write to LMR) +write 0xFF000104 0xE10D0002 4 # SDCR + IPALL +write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh) +write 0xFF000100 0x008D0000 4 # SDMR (write to LMR) +write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh) + +write 0xFF000240 0x80000000 4 # disable watchdog arbiter + +# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29 +flash 0xE0000000 flash29 +# do not flash yet. First check if board can be initialized correctly + +load -v ram.elf +wait +sleep 1000 +execute diff --git a/BaS_gcc/mcf5474.gdb b/BaS_gcc/mcf5474.gdb new file mode 100644 index 0000000..7b65166 --- /dev/null +++ b/BaS_gcc/mcf5474.gdb @@ -0,0 +1,60 @@ +# +# GDB Init script for the Coldfire 5474 processor (firebee). +# + +define addresses +set $vbr = 0x00000000 +monitor bdm-ctl-set 0x0801 0x00000000 +set $mbar = 0xFF000000 +monitor bdm-ctl-set 0x0C0F 0xFF000000 +set $rambar0 = 0xFF100000 +monitor bdm-ctl-set 0x0C04 0xFF100007 +set $rambar1 = 0xFF101000 +monitor bdm-ctl-set 0x0C05 0xFF101001 +end + +# +# Setup the DRAM controller. +# + +define setup-dram +# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) +set *((long *) 0xFF000500) = 0xE0000000 +set *((long *) 0xFF000508) = 0x00041180 +set *((long *) 0xFF000504) = 0x007F0001 + +# set *((long *) 0xFF00050C) = 0xFFF00000 # ATARI I/O address + +# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes +set *((long *) 0xFF000004) = 0x000002AA +set *((long *) 0xFF000020) = 0x0000001A +set *((long *) 0xFF000024) = 0x0800001A +set *((long *) 0xFF000028) = 0x1000001A +set *((long *) 0xFF00002C) = 0x1800001A +set *((long *) 0xFF000108) = 0x73622830 +set *((long *) 0xFF00010C) = 0x46770000 + + +set *((long *) 0xFF000104) = 0xE10D0002 +set *((long *) 0xFF000100) = 0x40010000 +set *((long *) 0xFF000100) = 0x048D0000 +set *((long *) 0xFF000104) = 0xE10D0002 +set *((long *) 0xFF000104) = 0xE10D0004 +set *((long *) 0xFF000104) = 0xE10D0004 +set *((long *) 0xFF000100) = 0x008D0000 +set *((long *) 0xFF000104) = 0x710D0F00 +end + +define cu +!killall m68k-bdm-gdbserver +end + +# +# Wake up the board +# + +define ib +addresses +setup-dram +end +ib diff --git a/BaS_gcc/sources/BaS.c b/BaS_gcc/sources/BaS.c new file mode 100644 index 0000000..6d42ea2 --- /dev/null +++ b/BaS_gcc/sources/BaS.c @@ -0,0 +1,256 @@ +/* + * BaS + * + */ +#include + +#include "MCF5475.h" +#include "MCF5475_SLT.h" +#include "startcf.h" +#include "cache.h" +#include "bas_printf.h" + +/* imported routines */ +extern int mmu_init(); +extern int vec_init(); +extern int illegal_table_make(); +extern void sd_card_idle(); +extern int sd_card_init(); + +/* wait...() routines moved to sysinit.c */ +extern void wait(uint32_t us); + +/* Symbols from the linker script */ +extern uint8_t _STRAM_END[]; +#define STRAM_END ((uint32_t)_STRAM_END) +extern uint8_t _TOS[]; +#define TOS ((uint32_t)_TOS) /* final TOS location */ +extern uint8_t _FASTRAM_END[]; +#define FASTRAM_END ((uint32_t)_FASTRAM_END) +extern uint8_t _EMUTOS[]; +#define EMUTOS ((uint32_t)_EMUTOS) /* where EmuTOS is stored in flash */ +extern uint8_t _EMUTOS_SIZE[]; +#define EMUTOS_SIZE ((uint32_t)_EMUTOS_SIZE) /* size of EmuTOS, in bytes */ + +void write_pic_byte(uint8_t value) +{ + /* Wait until the tramsmitter is ready */ + while (!(MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)); + + /* Transmit the byte */ + //MCF_PSC3_PSCTB_8BIT = value; // This define is actually 32-bit + *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit +} + +uint8_t read_pic_byte(void) +{ + /* Wait until a byte has been received */ + while (!(MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)); + + /* Return the received byte */ + //return MCF_PSC3_PSCRB_8BIT; // This define is actually 32-bit + return *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT); // Really 8-bit +} + +void pic_init(void) +{ + char answer[4]; + + xprintf("initialize the PIC: "); + + /* Send the PIC initialization string */ + write_pic_byte('A'); + write_pic_byte('C'); + write_pic_byte('P'); + write_pic_byte('F'); + + /* Read the 3-char answer string. Should be "OK!". */ + answer[0] = read_pic_byte(); + answer[1] = read_pic_byte(); + answer[2] = read_pic_byte(); + answer[3] = '\0'; + + xprintf("%s\r\n", answer); +} + +void nvram_init(void) +{ + int i; + + xprintf("Restore the NVRAM data: "); + + /* Request for NVRAM backup data */ + write_pic_byte(0x01); + + /* Check answer type */ + if (read_pic_byte() != 0x81) + { + // FIXME: PIC protocol error + xprintf("FAILED\r\n"); + return; + } + + /* Restore the NVRAM backup to the FPGA */ + for (i = 0; i < 64; i++) + { + uint8_t data = read_pic_byte(); + *(volatile uint8_t*)0xffff8961 = i; + *(volatile uint8_t*)0xffff8963 = data; + } + + xprintf("finished\r\n"); +} + +/********************************************************************/ +void BaS(void) +{ + int az_sectors; + uint8_t *src; + uint8_t *dst = (uint8_t *)TOS; + uint32_t *adr; + + + az_sectors = sd_card_init(); + + if (az_sectors > 0) + { + //sd_card_idle(); + } + + pic_init(); + nvram_init(); + + xprintf("copy EmuTOS: "); + + /* copy EMUTOS */ + src = (uint8_t *) EMUTOS; + while (src < (uint8_t *)(EMUTOS + EMUTOS_SIZE)) + { + *dst++ = *src++; + } + + xprintf("finished\r\n"); + + /* we have copied a code area, so flush the caches */ + flush_and_invalidate_caches(); + + xprintf("initialize MMU: "); + mmu_init(); + xprintf("finished\r\n"); + + xprintf("initialize exception vector table: "); + vec_init(); + illegal_table_make(); + xprintf("finished\r\n"); + + /* interrupts */ + + xprintf("enable interrupts: "); + * (volatile uint32_t *) 0xf0010004 = 0L; /* disable all interrupts */ + MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */ + + MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */ + MCF_GPT_GMS_IEN | + MCF_GPT_GMS_TMS(1); + MCF_INTC_ICR62 = 0x3f; + + * (volatile uint8_t *) 0xf0010004 = 0xfe; /* enable int 1-7 */ + MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */ + MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */ + MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */ + MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */ + + MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */ + xprintf("finished\r\n"); + + xprintf("IDE reset: "); + /* IDE reset */ + * (volatile uint8_t *) (0xffff8802 - 2) = 14; + * (volatile uint8_t *) (0xffff8802 - 0) = 0x80; + wait(1); + + * (volatile uint8_t *) (0xffff8802 - 0) = 0; + + xprintf("finished\r\n"); + + xprintf("enable video: "); + /* + * video setup (25MHz) + */ + * (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba; /* horizontal 640x480 */ + * (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a; /* vertical 640x480 */ + * (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d; /* horizontal 320x240 */ + * (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */ + +#ifdef _NOT_USED_ +// 32MHz + move.l #0x037002ba,(a0)+ // horizontal 640x480 + move.l #0x020d020a,(a0)+ // vertikal 640x480 + move.l #0x02A001e0,(a0)+ // horizontal 320x240 + move.l #0x05a00160,(a0)+ // vertikal 320x240 +#endif /* _NOT_USED_ */ + + /* fifo on, refresh on, ddrcs and cke on, video dac on */ + * (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002; + + xprintf("finished\r\n"); + + + /* + * memory setup + */ + for (adr = (uint32_t *) 0x400L; adr < (uint32_t *) 0x800L; ) { + *adr++ = 0x0L; + *adr++ = 0x0L; + *adr++ = 0x0L; + *adr++ = 0x0L; + } + + * (volatile uint8_t *) 0xffff8007 = 0x48; /* FIXME: what's that ? */ + + /* ST RAM */ + + * (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */ + * (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */ + * (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */ + * (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */ + + /* TT-RAM */ + + * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */ + * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ + + xprintf("init ACIA: "); + /* init ACIA */ + * (uint8_t *) 0xfffffc00 = 3; + __asm__ __volatile__("nop \n\t" : : : "memory"); + * (uint8_t *) 0xfffffc04 = 3; + __asm__ __volatile__("nop \n\t" : : : "memory"); + * (uint8_t *) 0xfffffc00 = 0x96; + __asm__ __volatile__("nop \n\t" : : : "memory"); + * (uint8_t *) 0xfffffa0f = -1; + __asm__ __volatile__("nop \n\t" : : : "memory"); + * (uint8_t *) 0xfffffa11 = -1; + __asm__ __volatile__("nop \n\t" : : : "memory"); + + xprintf("finished\r\n"); + + /* Test for pseudo-supervisor mode: DIP switch #6 down */ + if (DIP_SWITCH & (1 << 7)) { + /* In this mode, the OS actually runs in user mode + * and all the supervisor instructions are emulated. */ + __asm__ __volatile__("move.w #0x0700,sr \n\t" : : : "memory"); + } + + /* Jump into the OS */ + typedef void void_func(void); + typedef struct { + void *initial_sp; + void_func *initial_pc; + } ROM_HEADER; + + xprintf("Call OS. BaS finished...\r\n"); + + ROM_HEADER* os_header = (ROM_HEADER*)TOS; + os_header->initial_pc(); +} diff --git a/BaS_gcc/sources/bas_printf.c b/BaS_gcc/sources/bas_printf.c new file mode 100644 index 0000000..4772912 --- /dev/null +++ b/BaS_gcc/sources/bas_printf.c @@ -0,0 +1,391 @@ +/* + * tc.printf.c: A public-domain, minimal printf/sprintf routine that prints + * through the putchar() routine. Feel free to use for + * anything... -- 7/17/87 Paul Placeway + */ +/*- + * Copyright (c) 1980, 1991 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "MCF5475.h" +#include +/* + * Lexical definitions. + * + * All lexical space is allocated dynamically. + * The eighth/sixteenth bit of characters is used to prevent recognition, + * and eventually stripped. + */ +#define META 0200 +#define ASCII 0177 +#define QUOTE ((char) 0200) /* Eighth char bit used for 'ing */ +#define TRIM 0177 /* Mask to strip quote bit */ +#define UNDER 0000000 /* No extra bits to do both */ +#define BOLD 0000000 /* Bold flag */ +#define STANDOUT META /* Standout flag */ +#define LITERAL 0000000 /* Literal character flag */ +#define ATTRIBUTES 0200 /* The bits used for attributes */ +#define CHAR 0000177 /* Mask to mask out the character */ + +#define INF 32766 /* should be bigger than any field to print */ + +static char buf[128]; +static char snil[] = "(nil)"; + +static void xputchar(int c) +{ + __asm__ __volatile__ + ( + ".extern printf_helper\n\t" + "move.b %0,d0\n\t" + "bsr printf_helper\n\t" + /* output */: + /* input */: "r" (c) + /* clobber */: "d0","d2","a0","memory" + ); +} + +#define isdigit(c) (((c) >= '0') && ((c) <= '9')) +#define isupper(c) ((c) >= 'A' && ((c) <= 'Z')) +#define islower(c) ((c) >= 'a' && ((c) <= 'z')) +#define isalpha(c) (isupper((c)) || islower(c)) +#define tolower(c) (isupper(c) ? ((c) + 'a' - 'A') : (c)) + +static int atoi(const char *c) +{ + int value = 0; + while (isdigit(*c)) + { + value *= 10; + value += (int) (*c - '0'); + c++; + } + return value; +} + +size_t strlen(const char *s) +{ + int length = 0; + + while (*s++) + { + length++; + } + return length; +} + +static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap) +{ + char *bp; + const char *f; + long l; + unsigned long u; + int i; + int fmt; + unsigned char pad = ' '; + int flush_left = 0; + int f_width = 0; + int prec = INF; + int hash = 0; + int do_long = 0; + int sign = 0; + int attributes = 0; + + f = sfmt; + for (; *f; f++) + { + if (*f != '%') + { + /* then just out the char */ + (*addchar)((int) (((unsigned char) *f) | attributes)); + } + else + { + f++; /* skip the % */ + + if (*f == '-') + { /* minus: flush left */ + flush_left = 1; + f++; + } + + if (*f == '0' || *f == '.') + { + /* padding with 0 rather than blank */ + pad = '0'; + f++; + } + if (*f == '*') + { + /* field width */ + f_width = va_arg(ap, int); + f++; + } + else if (isdigit((unsigned char)*f)) + { + f_width = atoi(f); + while (isdigit((unsigned char)*f)) + f++; /* skip the digits */ + } + + if (*f == '.') + { /* precision */ + f++; + if (*f == '*') + { + prec = va_arg(ap, int); + f++; + } + else if (isdigit((unsigned char)*f)) + { + prec = atoi(f); + while (isdigit((unsigned char)*f)) + f++; /* skip the digits */ + } + } + + if (*f == '#') + { /* alternate form */ + hash = 1; + f++; + } + + if (*f == 'l') + { /* long format */ + do_long++; + f++; + if (*f == 'l') + { + do_long++; + f++; + } + } + + fmt = (unsigned char) *f; + if (fmt != 'S' && fmt != 'Q' && isupper(fmt)) + { + do_long = 1; + fmt = tolower(fmt); + } + bp = buf; + switch (fmt) + { /* do the format */ + case 'd': + switch (do_long) + { + case 0: + l = (long) (va_arg(ap, int)); + break; + case 1: + default: + l = va_arg(ap, long); + break; + } + + if (l < 0) + { + sign = 1; + l = -l; + } + do + { + *bp++ = (char) (l % 10) + '0'; + } while ((l /= 10) > 0); + if (sign) + *bp++ = '-'; + f_width = f_width - (int) (bp - buf); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'p': + do_long = 1; + hash = 1; + fmt = 'x'; + /* no break */ + case 'o': + case 'x': + case 'u': + switch (do_long) + { + case 0: + u = (unsigned long) (va_arg(ap, unsigned int)); + break; + case 1: + default: + u = va_arg(ap, unsigned long); + break; + } + if (fmt == 'u') + { /* unsigned decimal */ + do + { + *bp++ = (char) (u % 10) + '0'; + } while ((u /= 10) > 0); + } + else if (fmt == 'o') + { /* octal */ + do + { + *bp++ = (char) (u % 8) + '0'; + } while ((u /= 8) > 0); + if (hash) + *bp++ = '0'; + } + else if (fmt == 'x') + { /* hex */ + do + { + i = (int) (u % 16); + if (i < 10) + *bp++ = i + '0'; + else + *bp++ = i - 10 + 'a'; + } while ((u /= 16) > 0); + if (hash) + { + *bp++ = 'x'; + *bp++ = '0'; + } + } + i = f_width - (int) (bp - buf); + if (!flush_left) + while (i-- > 0) + (*addchar)((int) (pad | attributes)); + for (bp--; bp >= buf; bp--) + (*addchar)((int) (((unsigned char) *bp) | attributes)); + if (flush_left) + while (i-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'c': + i = va_arg(ap, int); + (*addchar)((int) (i | attributes)); + break; + + case 'S': + case 'Q': + case 's': + case 'q': + bp = va_arg(ap, char *); + if (!bp) + bp = snil; + f_width = f_width - strlen((char *) bp); + if (!flush_left) + while (f_width-- > 0) + (*addchar)((int) (pad | attributes)); + for (i = 0; *bp && i < prec; i++) + { + if (fmt == 'q' && (*bp & QUOTE)) + (*addchar)((int) ('\\' | attributes)); + (*addchar)( + (int) (((unsigned char) *bp & TRIM) | attributes)); + bp++; + } + if (flush_left) + while (f_width-- > 0) + (*addchar)((int) (' ' | attributes)); + break; + + case 'a': + attributes = va_arg(ap, int); + break; + + case '%': + (*addchar)((int) ('%' | attributes)); + break; + + default: + break; + } + flush_left = 0, f_width = 0, prec = INF, hash = 0, do_long = 0; + sign = 0; + pad = ' '; + } + } +} + +static char *xstring, *xestring; + +static void xaddchar(int c) +{ + if (xestring == xstring) + *xstring = '\0'; + else + *xstring++ = (char) c; +} + +void xsnprintf(char *str, size_t size, const char *fmt, ...) +{ + va_list va; + va_start(va, fmt); + + xstring = str; + xestring = str + size - 1; + doprnt(xaddchar, fmt, va); + va_end(va); + *xstring++ = '\0'; +} + +void xprintf(const char *fmt, ...) +{ + va_list va; + va_start(va, fmt); + doprnt(xputchar, fmt, va); + va_end(va); +} + +void xvprintf(const char *fmt, va_list va) +{ + doprnt(xputchar, fmt, va); +} + +void xvsnprintf(char *str, size_t size, const char *fmt, va_list va) +{ + xstring = str; + xestring = str + size - 1; + doprnt(xaddchar, fmt, va); + *xstring++ = '\0'; +} + + +void display_progress() +{ + static int _progress_index; + char progress_char[] = "|/-\\"; + xputchar(progress_char[_progress_index++ % strlen(progress_char)]); + xputchar('\r'); +} + diff --git a/BaS_gcc/sources/cache.c b/BaS_gcc/sources/cache.c new file mode 100644 index 0000000..940b7e5 --- /dev/null +++ b/BaS_gcc/sources/cache.c @@ -0,0 +1,27 @@ +/* + * cache handling + */ +#include "cache.h" + +void flush_and_invalidate_caches(void) +{ + __asm__ ( + " clr.l d0\n\t" + " clr.l d1\n\t" + " move.l d0,a0\n\t" + "cfa_setloop:\n\t" + " cpushl bc,(a0) | flush\n\t" + " lea 0x10(a0),a0 | index+1\n\t" + " addq.l #1,d1 | index+1\n\t" + " cmpi.w #512,d1 | all sets?\n\t" + " bne.s cfa_setloop | no->\n\t" + " clr.l d1\n\t" + " addq.l #1,d0\n\t" + " move.l d0,a0\n\t" + " cmpi.w #4,d0 | all ways?\n\t" + " bne.s cfa_setloop | no->\n\t" + /* input */ : + /* output */ : + /* clobber */ : "d0", "d1", "a0" + ); +} diff --git a/BaS_gcc/sources/cache.h b/BaS_gcc/sources/cache.h new file mode 100644 index 0000000..a8d788d --- /dev/null +++ b/BaS_gcc/sources/cache.h @@ -0,0 +1,8 @@ +#ifndef _CACHE_H_ +#define _CACHE_H_ + +#include + +extern void flush_and_invalidate_caches(void); + +#endif /* _CACHE_H_ */ diff --git a/BaS_gcc/sources/div.s b/BaS_gcc/sources/div.s new file mode 100644 index 0000000..f5f151c --- /dev/null +++ b/BaS_gcc/sources/div.s @@ -0,0 +1,1326 @@ + +/********************************************************************/ +// sd card +/********************************************************************/ +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 + +sd_test: + lea 0x40000,a5 // basis addresse + move.l #0x1fffffff,d0 // normal dspi + move.l d0,MCF_PAD_PAR_DSPI + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) // 8 bit 4MHz + move.l #0x38551120,d0 + move.l d0,dspi_dtar0(a0) // + move.l #0x08200000,d4 // tx vorbesetzen + mov3q.l #-1,dspi_dsr(a0) + + move.b #0xc0,(a0) // 8 bit 4MHz + bsr warte_1ms + move.b #0x80,(a0) // 8 bit 4MHz +// sd idle + moveq.l #100,d6 // 100 versuche +sd_idle: + bsr sd_16clk + move.b #0x40,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x01,d5 + beq wait_of_aktiv + subq.l #1,d6 + beq sd_not + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + move.b #0x77,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x05,d5 + beq wait_of_aktiv + + +wait_of_aktiv2: + bsr sd_16clk + move.b #0x69,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x02,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq wait_of_aktiv2 + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + move.b #0x50,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #02,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + move.b #0x51,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_rb + + move.l a5,a4 // adresse setzen + bsr sd_rcv_block + +// write block +sd_wb: + bsr sd_16clk + move.b #0x58,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_wb + + bsr sd_send_block + +// read block 2 +sd_rb2: + bsr sd_16clk + move.b #0x51,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x08,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + bne sd_rb + + bsr sd_rcv_block + clr.l d0 + halt + halt + rts +// status holen ------------------------------- +sd_not: + moveq.l #-1,d0 + halt + halt + rts + +// status holen ------------------------------- +sd_get_status: + move.b #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_get_status + rts +// byt senden und holen --------------------- +sd_com: + move.l d4,dspi_dtfr(a0) +wait_auf_complett: + btst.b #7,dspi_dsr(a0) + beq wait_auf_complett + move.l dspi_drfr(a0),d5 + mov3q.l #-1,dspi_dsr(a0) // clr status register + rts + +// daten holen ---------------------------- +sd_rcv_block: + move.l #512,d3 // 512 byts + 2 ccr byts + move.b #0xff,d4 +sd_rcv_rb_w: + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rcv_rb_w // nein-> +sd_rcv_rd_rb: + bsr sd_com + move.b d5,(a4)+ + subq.l #1,d3 + bne sd_rcv_rd_rb +// crc holen + bsr sd_com // crc 1.byt + move.b d5,d1 + bsr sd_com // crc 2.byt + move.b d5,d2 + rts + +// daten schreiben ----------------------- +sd_send_block: + move.l #512,d3 + move.b #0xfe,d4 // start token + bsr sd_com // senden +sd_send_wr_wb: + move.b #0xc7,d4 // data + bsr sd_com // senden + subq.l #1,d3 + bne sd_send_wr_wb +// send crc + move.b d1,d4 + bsr sd_com // crc 1.byt + move.b d2,d4 + bsr sd_com // crc 2.byt +sd_send_wr_ww: + bsr sd_get_status + and.l #0x1f,d5 + cmp.b #0x05,d5 + bne sd_send_wr_ww +sd_sendwait_wr_f: + bsr sd_com + cmp.b #0xff,d5 + bne sd_sendwait_wr_f + rts +// clock einfügen ------------------------------------- +sd_16clk: + move.b #0xc0,(a0) // 8 bit 4MHz + nop + move.b #0x80,(a0) // 8 bit 4MHz + rts +// cdm 58 +read_ocr: + bsr sd_16clk + move.b #0x7a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + move.b #0xaa,d4 + bsr sd_com + move.b #0x87,d4 + bsr sd_com + + bsr sd_get_status + + halt + + move.l #'Ver1',d6 + cmp.b #5,d5 + beq sd_v1 + cmp.b #1,d5 + bne read_csd + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com +/******************************************/ +#include "MCF5475.h" +#include "startcf.h" + +extern unsigned long far __SP_AFTER_RESET[]; +extern unsigned long far __Bas_base[]; + + /* imported routines */ +//extern int warten_20ms(); +//extern int warten_200us(); +//extern int warten_10us(); + +/********************************************************************/ +void asm sd_test(void) +{ + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} + + +/**************************************************/ +void asm ide_test(void) +{ + lea MCF_PAD_PAR_DSPI,a0 + move.w #0x1fff,(a0) + lea MCF_DSPI_DCTAR0,a0 + move.l #0x38a644e4,(a0) + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) + clr.l MCF_DSPI_DTCR + bsr warten_20ms + lea MCF_DSPI_DTFR,a0 + lea MCF_DSPI_DRFR,a1 + + moveq #10,d0 +sd_reset: + move.l #0x000100ff,(a0) + bsr warten_20ms + and.l (a1),d0 + subq.l #1,d0 + bne sd_reset + + moveq #10,d1 +sd_loop1: + bsr warten_20ms + moveq #-1,d0 +// cmd 0 set to idle + move.l #0x00200040,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200095,(a0) + bsr warten_20ms + and.l (a1),d0 + cmp.w #0x0001,d0 + beq sd_loop2 + subq.l #1,d1 + bne sd_loop1 + moveq #10,d1 + bra sd_test +sd_loop2: + moveq #-1,d0 +// cmd 41 + move.l #0x00200069,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200001,(a0) + bsr warten_20ms + and.l (a1),d0 + tst.w d0 + bne sd_loop2 + + nop + nop +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst.b #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} +/********************************************************************/ +//.include "startcf.h" + +//.extern ___MBAR +//#define MCF_SLT0_SCNT ___MBAR+0x908 + +//.global ide_test + +.text +/********************************************************************/ +// sd card +/********************************************************************/ +sd_test: + lea 0x40000,a5 // basis addresse + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + move.l a5,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + move.l #513,d7 + moveq.l #0xbb,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0xbb,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + +halt +halt + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) // nCS=0 +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + bclr.b #0,(a1) // default 0 bit senden + btst d2,d4 // ist 0? + beq sd_com2 // ja-> + bset.b #0,(a1) // sonst auf 1 +sd_com2: + bsr sd_clk // clocken + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) // nCS=1 + bset.b #0,(a1) // daten = 0 + bsr warten_200us + rts +// clocken +sd_clk: + tst.b 0xfffff700 // wait + tst.b 0xfffff700 + bset.b #2,(a1) // clock high + tst.b 0xfffff700 // wait + tst.b 0xfffff700 // wait + move.b (a2),d3 // bit holen + bclr.b #2,(a1) // clock low + rts + +sd_16clk: + move.l #160,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +/********************************************************************/ +// video pll +/********************************************************************/ + lea 0xf0000800,a1 + + lea 0xf0000600,a0 + move.l #128,d0 +clr_pll: + bsr wait_pll + clr.w (a0) + addq.l #4,a0 + subq.l #1,d0 + bne clr_pll + + lea 0xf0000600,a0 + bsr wait_pll + move.w #27,0x48(a0) // loopfilter r + bsr wait_pll + move.w #1,0x08(a0) // charge pump I + bsr wait_pll + move.w #12,0x0(a0) // N counter high = 12 + bsr wait_pll + move.w #12,0x40(a0) // N counter low = 12 + bsr wait_pll + move.w #1,0x114(a0) // ck1 bypass + bsr wait_pll + move.w #1,0x118(a0) // ck2 bypass + bsr wait_pll + move.w #1,0x11c(a0) // ck3 bypass + bsr wait_pll + move.w #1,0x10(a0) // ck0 high = 1 + bsr wait_pll + move.w #1,0x50(a0) // ck0 low = 1 + + bsr wait_pll + move.w #1,0x144(a0) // M odd division + bsr wait_pll + move.w #1,0x44(a0) // M low = 1 + + bsr wait_pll + move.w #99,0x04(a0) // M high = 100 + + bsr wait_pll + clr.b (a1) // set + +set_pll: + bsr read_pll + halt + move.w d0,(a0) + bsr wait_pll + clr.b (a1) + bra set_pll + +read_pll: + lea 0xf0000600,a3 + lea 0x10000,a2 + move.l #128,d3 +read1_pll: + bsr wait_pll + move.w (a3),d1 + bsr wait_pll + move.w (a3),(a2) + addq.l #4,a3 + addq.l #4,a2 + subq.l #1,d3 + bne read1_pll + rts +wait_pll: + tst.w (a1) + bmi wait_pll + rts + +/********************************************************************/ +void ide_test(void) +/********************************************************************/ +{ + asm + { + halt + lea 0xfff00000,a0 + lea 0x80000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rxl +// read sector normal + move.b #1,seccnt(a0) // 1 sector 0x200 + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rxl +// write pattern 0x400 + move.l a1,a4 //a4=400 + move.l #256,d0 + clr.l d1 +ide_test_loop3: + move.w d1,(a1)+ + addq.l #1,d1 + subq.l #1,d0 + bne ide_test_loop3 + move.l a4,a1 +// write testpattern sector 0x400 + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait + bsr ds_txl + bsr wait_int + move.l a1,a2 //a2=600 + move.l #256,d4 +loop_rw: +// read testpattern sector 0x600 + move.l a2,a1 +// halt + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rxl +// verändere testpattern + move.l a2,a1 +// halt + move.l #256,d0 + move.l #0x100,d1 +verae_loop: + move.w (a1),d2 + add.l d1,d2 + move.w d2,(a1)+ + subq.l #1,d0 + bne verae_loop +// write testpattern sector 0x600 + move.l a2,a1 +// halt + move.b #10,sector(a0) // sector 10 + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait + bsr ds_txl + bsr wait_int + subq.l #1,d4 +// bra verae_loop + bne loop_rw +// sector vergleichen +// halt + move.l #128,d0 + moveq.l #-1,d1 +verg_loop: + move.l (a2)+,d2 + cmp.l (a4)+,d2 + bne error + subq.l #1,d0 + bne verg_loop + clr.l d1 +error: + halt + rts +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_txl + + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben long +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts + } +} +/********************************************************************/ diff --git a/BaS_gcc/sources/ewf.S b/BaS_gcc/sources/ewf.S new file mode 100644 index 0000000..6046a63 --- /dev/null +++ b/BaS_gcc/sources/ewf.S @@ -0,0 +1,1563 @@ +/*************************************************************************************************/ +// extension word format: a0 zeigt auf code, in a1 ist ay, d0/d1 wird zerstört +//------------------------------------------------------------------------------ + +#include "ii_macro.h" + +.global ewf +//----------------------------------------------------------- +.text +ewferr: + nop + halt + nop +//----------------------------------------------------------- +ewf: + mvz.b (a0)+,d1 // 1. byt ewf + mvs.w ewf_table-.-2(pc,d1*2),d1 + jmp ewf_table-.-2(pc,d1) +ewf_table: + .short ewf_00-ewf_table,ewf_01-ewf_table,ewf_02-ewf_table,ewf_03-ewf_table + .short ewf_04-ewf_table,ewf_05-ewf_table,ewf_06-ewf_table,ewf_07-ewf_table + .short ewferr-ewf_table,ewf_09-ewf_table,ewferr-ewf_table,ewf_0b-ewf_table + .short ewferr-ewf_table,ewf_0d-ewf_table,ewferr-ewf_table,ewf_0f-ewf_table + .short ewf_10-ewf_table,ewf_11-ewf_table,ewf_12-ewf_table,ewf_13-ewf_table + .short ewf_14-ewf_table,ewf_15-ewf_table,ewf_16-ewf_table,ewf_17-ewf_table + .short ewferr-ewf_table,ewf_19-ewf_table,ewferr-ewf_table,ewf_1b-ewf_table + .short ewferr-ewf_table,ewf_1d-ewf_table,ewferr-ewf_table,ewf_1f-ewf_table + .short ewf_20-ewf_table,ewf_21-ewf_table,ewf_22-ewf_table,ewf_23-ewf_table + .short ewf_24-ewf_table,ewf_25-ewf_table,ewf_26-ewf_table,ewf_27-ewf_table + .short ewferr-ewf_table,ewf_29-ewf_table,ewferr-ewf_table,ewf_2b-ewf_table + .short ewferr-ewf_table,ewf_2d-ewf_table,ewferr-ewf_table,ewf_2f-ewf_table + .short ewf_30-ewf_table,ewf_31-ewf_table,ewf_32-ewf_table,ewf_33-ewf_table + .short ewf_34-ewf_table,ewf_35-ewf_table,ewf_36-ewf_table,ewf_37-ewf_table + .short ewferr-ewf_table,ewf_39-ewf_table,ewferr-ewf_table,ewf_3b-ewf_table + .short ewferr-ewf_table,ewf_3d-ewf_table,ewferr-ewf_table,ewf_3f-ewf_table + .short ewf_40-ewf_table,ewf_41-ewf_table,ewf_42-ewf_table,ewf_43-ewf_table + .short ewf_44-ewf_table,ewf_45-ewf_table,ewf_46-ewf_table,ewf_47-ewf_table + .short ewferr-ewf_table,ewf_49-ewf_table,ewferr-ewf_table,ewf_4b-ewf_table + .short ewferr-ewf_table,ewf_4d-ewf_table,ewferr-ewf_table,ewf_4f-ewf_table + .short ewf_50-ewf_table,ewf_51-ewf_table,ewf_52-ewf_table,ewf_53-ewf_table + .short ewf_54-ewf_table,ewf_55-ewf_table,ewf_56-ewf_table,ewf_57-ewf_table + .short ewferr-ewf_table,ewf_59-ewf_table,ewferr-ewf_table,ewf_5b-ewf_table + .short ewferr-ewf_table,ewf_5d-ewf_table,ewferr-ewf_table,ewf_5f-ewf_table + .short ewf_60-ewf_table,ewf_61-ewf_table,ewf_62-ewf_table,ewf_63-ewf_table + .short ewf_64-ewf_table,ewf_65-ewf_table,ewf_66-ewf_table,ewf_67-ewf_table + .short ewferr-ewf_table,ewf_69-ewf_table,ewferr-ewf_table,ewf_6b-ewf_table + .short ewferr-ewf_table,ewf_6d-ewf_table,ewferr-ewf_table,ewf_6f-ewf_table + .short ewf_70-ewf_table,ewf_71-ewf_table,ewf_72-ewf_table,ewf_73-ewf_table + .short ewf_74-ewf_table,ewf_75-ewf_table,ewf_76-ewf_table,ewf_77-ewf_table + .short ewferr-ewf_table,ewf_79-ewf_table,ewferr-ewf_table,ewf_7b-ewf_table + .short ewferr-ewf_table,ewf_7d-ewf_table,ewferr-ewf_table,ewf_7f-ewf_table + .short ewf_80-ewf_table,ewf_81-ewf_table,ewf_82-ewf_table,ewf_83-ewf_table + .short ewf_84-ewf_table,ewf_85-ewf_table,ewf_86-ewf_table,ewf_87-ewf_table + .short ewferr-ewf_table,ewf_89-ewf_table,ewferr-ewf_table,ewf_8b-ewf_table + .short ewferr-ewf_table,ewf_8d-ewf_table,ewferr-ewf_table,ewf_8f-ewf_table + .short ewf_90-ewf_table,ewf_91-ewf_table,ewf_92-ewf_table,ewf_93-ewf_table + .short ewf_94-ewf_table,ewf_95-ewf_table,ewf_96-ewf_table,ewf_97-ewf_table + .short ewferr-ewf_table,ewf_99-ewf_table,ewferr-ewf_table,ewf_9b-ewf_table + .short ewferr-ewf_table,ewf_9d-ewf_table,ewferr-ewf_table,ewf_9f-ewf_table + .short ewf_a0-ewf_table,ewf_a1-ewf_table,ewf_a2-ewf_table,ewf_a3-ewf_table + .short ewf_a4-ewf_table,ewf_a5-ewf_table,ewf_a6-ewf_table,ewf_a7-ewf_table + .short ewferr-ewf_table,ewf_a9-ewf_table,ewferr-ewf_table,ewf_ab-ewf_table + .short ewferr-ewf_table,ewf_ad-ewf_table,ewferr-ewf_table,ewf_af-ewf_table + .short ewf_b0-ewf_table,ewf_b1-ewf_table,ewf_b2-ewf_table,ewf_b3-ewf_table + .short ewf_b4-ewf_table,ewf_b5-ewf_table,ewf_b6-ewf_table,ewf_b7-ewf_table + .short ewferr-ewf_table,ewf_b9-ewf_table,ewferr-ewf_table,ewf_bb-ewf_table + .short ewferr-ewf_table,ewf_bd-ewf_table,ewferr-ewf_table,ewf_bf-ewf_table + .short ewf_c0-ewf_table,ewf_c1-ewf_table,ewf_c2-ewf_table,ewf_c3-ewf_table + .short ewf_c4-ewf_table,ewf_c5-ewf_table,ewf_c6-ewf_table,ewf_c7-ewf_table + .short ewferr-ewf_table,ewf_c9-ewf_table,ewferr-ewf_table,ewf_cb-ewf_table + .short ewferr-ewf_table,ewf_cd-ewf_table,ewferr-ewf_table,ewf_cf-ewf_table + .short ewf_d0-ewf_table,ewf_d1-ewf_table,ewf_d2-ewf_table,ewf_d3-ewf_table + .short ewf_d4-ewf_table,ewf_d5-ewf_table,ewf_d6-ewf_table,ewf_d7-ewf_table + .short ewferr-ewf_table,ewf_d9-ewf_table,ewferr-ewf_table,ewf_db-ewf_table + .short ewferr-ewf_table,ewf_dd-ewf_table,ewferr-ewf_table,ewf_df-ewf_table + .short ewf_e0-ewf_table,ewf_e1-ewf_table,ewf_e2-ewf_table,ewf_e3-ewf_table + .short ewf_e4-ewf_table,ewf_e5-ewf_table,ewf_e6-ewf_table,ewf_e7-ewf_table + .short ewferr-ewf_table,ewf_e9-ewf_table,ewferr-ewf_table,ewf_eb-ewf_table + .short ewferr-ewf_table,ewf_ed-ewf_table,ewferr-ewf_table,ewf_ef-ewf_table + .short ewf_f0-ewf_table,ewf_f1-ewf_table,ewf_f2-ewf_table,ewf_f3-ewf_table + .short ewf_f4-ewf_table,ewf_f5-ewf_table,ewf_f6-ewf_table,ewf_f7-ewf_table + .short ewferr-ewf_table,ewf_f9-ewf_table,ewferr-ewf_table,ewf_fb-ewf_table + .short ewferr-ewf_table,ewf_fd-ewf_table,ewferr-ewf_table,ewf_ff-ewf_table +//d0.w * 1 +ewf_00: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_01: + mvs.w d0_off+6(a7),d0 + bra ewf_full +//d0.w * 2 +ewf_02: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_03: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d0.w * 4 +ewf_04: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_05: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d0.w * 8 +ewf_06: + mvs.b (a0)+,d1 + mvs.w d0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_07: + mvs.w d0_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 1 +ewf_09: + move.l d0_off+4(a7),d0 + bra ewf_full +//d0.l * 2 +ewf_0b: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 4 +ewf_0d: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d0.l * 8 +ewf_0f: + move.l d0_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 1 +ewf_10: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_11: + mvs.w d1_off+6(a7),d0 + bra ewf_full +//d1.w * 2 +ewf_12: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_13: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 4 +ewf_14: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_15: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d1.w * 8 +ewf_16: + mvs.b (a0)+,d1 + mvs.w d1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_17: + mvs.w d1_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 1 +ewf_19: + move.l d1_off+4(a7),d0 + bra ewf_full +//d1.l * 2 +ewf_1b: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 4 +ewf_1d: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d1.l * 8 +ewf_1f: + move.l d1_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 1 +ewf_20: + mvs.b (a0)+,d1 + mvs.w d2,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_21: + mvs.w d2,d0 + bra ewf_full +//d2.w * 2 +ewf_22: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_23: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 4 +ewf_24: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_25: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d2.w * 8 +ewf_26: + mvs.b (a0)+,d1 + mvs.w d2,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_27: + mvs.w d2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 1 +ewf_29: + move.l d2,d0 + bra ewf_full +//d2.l * 2 +ewf_2b: + move.l d2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 4 +ewf_2d: + move.l d2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d2.l * 8 +ewf_2f: + move.l d2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 1 +ewf_30: + mvs.b (a0)+,d1 + mvs.w d3,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_31: + mvs.w d3,d0 + bra ewf_full +//d3.w * 2 +ewf_32: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_33: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 4 +ewf_34: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_35: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d3.w * 8 +ewf_36: + mvs.b (a0)+,d1 + mvs.w d3,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_37: + mvs.w d3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 1 +ewf_39: + move.l d3,d0 + bra ewf_full +//d3.l * 3 +ewf_3b: + move.l d3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 4 +ewf_3d: + move.l d3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d3.l * 8 +ewf_3f: + move.l d3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 1 +ewf_40: + mvs.b (a0)+,d1 + mvs.w d4,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_41: + mvs.w d4,d0 + bra ewf_full +//d4.w * 2 +ewf_42: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_43: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 4 +ewf_44: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_45: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d4.w * 8 +ewf_46: + mvs.b (a0)+,d1 + mvs.w d4,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_47: + mvs.w d4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 1 +ewf_49: + move.l d4,d0 + bra ewf_full +//d4.l * 4 +ewf_4b: + move.l d4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 4 +ewf_4d: + move.l d4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d4.l * 8 +ewf_4f: + move.l d4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 1 +ewf_50: + mvs.b (a0)+,d1 + mvs.w d5,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_51: + mvs.w d5,d0 + bra ewf_full +//d5.w * 2 +ewf_52: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_53: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 4 +ewf_54: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_55: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d5.w * 8 +ewf_56: + mvs.b (a0)+,d1 + mvs.w d5,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_57: + mvs.w d5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 1 +ewf_59: + move.l d5,d0 + bra ewf_full +//d5.l * 5 +ewf_5b: + move.l d5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 4 +ewf_5d: + move.l d5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d5.l * 8 +ewf_5f: + move.l d5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 1 +ewf_60: + mvs.b (a0)+,d1 + mvs.w d6,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_61: + mvs.w d6,d0 + bra ewf_full +//d6.w * 2 +ewf_62: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_63: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 4 +ewf_64: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_65: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d6.w * 8 +ewf_66: + mvs.b (a0)+,d1 + mvs.w d6,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_67: + mvs.w d6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 1 +ewf_69: + move.l d6,d0 + bra ewf_full +//d6.l * 6 +ewf_6b: + move.l d6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 4 +ewf_6d: + move.l d6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d6.l * 8 +ewf_6f: + move.l d6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 1 +ewf_70: + mvs.b (a0)+,d1 + mvs.w d7,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_71: + mvs.w d7,d0 + bra ewf_full +//d7.w * 2 +ewf_72: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_73: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 4 +ewf_74: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_75: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d7.w * 8 +ewf_76: + mvs.b (a0)+,d1 + mvs.w d7,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_77: + mvs.w d7,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 1 +ewf_79: + move.l d7,d0 + bra ewf_full +//d7.l * 7 +ewf_7b: + move.l d7,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 4 +ewf_7d: + move.l d7,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//d7.l * 8 +ewf_7f: + move.l d7,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 1 +ewf_80: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_81: + mvs.w a0_off+6(a7),d0 + bra ewf_full +//a0.w * 2 +ewf_82: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_83: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 4 +ewf_84: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_85: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a0.w * 8 +ewf_86: + mvs.b (a0)+,d1 + mvs.w a0_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_87: + mvs.w a0_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 1 +ewf_89: + move.l a0_off+4(a7),d0 + bra ewf_full +//a0.l * 2 +ewf_8b: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 4 +ewf_8d: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a0.l * 8 +ewf_8f: + move.l a0_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 1 +ewf_90: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_91: + mvs.w a1_off+6(a7),d0 + bra ewf_full +//a1.w * 2 +ewf_92: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_93: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 4 +ewf_94: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_95: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a1.w * 8 +ewf_96: + mvs.b (a0)+,d1 + mvs.w a1_off+6(a7),d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_97: + mvs.w a1_off+6(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 1 +ewf_99: + move.l a1_off+4(a7),d0 + bra ewf_full +//a1.l * 2 +ewf_9b: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 4 +ewf_9d: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a1.l * 8 +ewf_9f: + move.l a1_off+4(a7),d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 1 +ewf_a0: + mvs.b (a0)+,d1 + mvs.w a2,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_a1: + mvs.w a2,d0 + bra ewf_full +//a2.w * 2 +ewf_a2: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_a3: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 4 +ewf_a4: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_a5: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a2.w * 8 +ewf_a6: + mvs.b (a0)+,d1 + mvs.w a2,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_a7: + mvs.w a2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 1 +ewf_a9: + move.l a2,d0 + bra ewf_full +//a2.l * 2 +ewf_ab: + move.l a2,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 4 +ewf_ad: + move.l a2,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a2.l * 8 +ewf_af: + move.l a2,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 1 +ewf_b0: + mvs.b (a0)+,d1 + mvs.w a3,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_b1: + mvs.w a3,d0 + bra ewf_full +//a3.w * 2 +ewf_b2: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_b3: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 4 +ewf_b4: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_b5: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a3.w * 8 +ewf_b6: + mvs.b (a0)+,d1 + mvs.w a3,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_b7: + mvs.w a3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 1 +ewf_b9: + move.l a3,d0 + bra ewf_full +//a3.l * 3 +ewf_bb: + move.l a3,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 4 +ewf_bd: + move.l a3,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a3.l * 8 +ewf_bf: + move.l a3,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 1 +ewf_c0: + mvs.b (a0)+,d1 + mvs.w a4,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_c1: + mvs.w a4,d0 + bra ewf_full +//a4.w * 2 +ewf_c2: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_c3: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 4 +ewf_c4: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_c5: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a4.w * 8 +ewf_c6: + mvs.b (a0)+,d1 + mvs.w a4,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_c7: + mvs.w a4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 1 +ewf_c9: + move.l a4,d0 + bra ewf_full +//a4.l * 4 +ewf_cb: + move.l a4,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 4 +ewf_cd: + move.l a4,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a4.l * 8 +ewf_cf: + move.l a4,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 1 +ewf_d0: + mvs.b (a0)+,d1 + mvs.w a5,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_d1: + mvs.w a5,d0 + bra ewf_full +//a5.w * 2 +ewf_d2: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_d3: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 4 +ewf_d4: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_d5: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a5.w * 8 +ewf_d6: + mvs.b (a0)+,d1 + mvs.w a5,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_d7: + mvs.w a5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 1 +ewf_d9: + move.l a5,d0 + bra ewf_full +//a5.l * 5 +ewf_db: + move.l a5,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 4 +ewf_dd: + move.l a5,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a5.l * 8 +ewf_df: + move.l a5,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 1 +ewf_e0: + mvs.b (a0)+,d1 + mvs.w a6,d0 + add.l d0,a1 + add.l d1,a1 + rts +ewf_e1: + mvs.w a6,d0 + bra ewf_full +//a6.w * 2 +ewf_e2: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_e3: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 4 +ewf_e4: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_e5: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a6.w * 8 +ewf_e6: + mvs.b (a0)+,d1 + mvs.w a6,d0 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_e7: + mvs.w a6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 1 +ewf_e9: + move.l a6,d0 + bra ewf_full +//a6.l * 6 +ewf_eb: + move.l a6,d0 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 4 +ewf_ed: + move.l a6,d0 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//a6.l * 8 +ewf_ef: + move.l a6,d0 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 1 +ewf_f0: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + add.l d1,a1 + rts +ewf_f1: + move.l a1,-(a7) + move.l usp,a1 + mvs.w a1,d0 + move.l (a7)+,a1 + bra ewf_full +//usp.w * 2 +ewf_f2: + mvs.b (a0)+,d1 + move.l usp,a1 + mvs.w a1,d0 + move.l (a7)+,a1 + lea 0(a1,d0*2),a1 + add.l d1,a1 + rts +ewf_f3: + move.l usp,a1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 4 +ewf_f4: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_f5: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//usp.w * 8 +ewf_f6: + mvs.b (a0)+,d1 + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + lea 0(a1,d0*4),a1 + lea 0(a1,d0*4),a1 + add.l d1,a1 + rts +ewf_f7: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 1 +ewf_f9: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + bra ewf_full +//usp.l * 7 +ewf_fb: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #1,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 4 +ewf_fd: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #2,d0 + move.w d1,ccr + bra ewf_full +//usp.l * 8 +ewf_ff: + move.l a1,-(a7) + move.l usp,a1 + add.l (a7)+,a1 + move.w ccr,d1 + asl.l #3,d0 + move.w d1,ccr + bra ewf_full +//----------------------------------------------------------------------------------- +// extension full format rest von ewf +//-------------------------------------------------------------------- +ewf_full: + mvz.b (a0)+,d1 + mvs.w ewff_table-.-2(pc,d1*2),d1 + jmp ewff_table-.-2(pc,d1) +ewff_table: + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //00 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //10 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsw-ewff_table,ewff_w0v-ewff_table,ewff_wwv-ewff_table,ewff_wlv-ewff_table //20 + .short ewff_end-ewff_table,ewff_w0n-ewff_table,ewff_wwn-ewff_table,ewff_wln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsl-ewff_table,ewff_l0v-ewff_table,ewff_lwv-ewff_table,ewff_llv-ewff_table //30 + .short ewff_end-ewff_table,ewff_l0n-ewff_table,ewff_lwn-ewff_table,ewff_lln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //40 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //50 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsw-ewff_table,ewff_wi0-ewff_table,ewff_wiw-ewff_table,ewff_wil-ewff_table //60 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_bsl-ewff_table,ewff_li0-ewff_table,ewff_liw-ewff_table,ewff_lil-ewff_table //70 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //80 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //90 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //a0 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table //b0 + .short ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //c0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //d0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //e0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table //f0 + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table + .short ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table +ewff_end: + rts +ewff_bsw: + mvs.w (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_bsl: + move.l (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_i0v: + add.l d0,a1 + move.l (a1),a1 + rts +ewff_iwv: + add.l d0,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_ilv: + add.l d0,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_i0n: + move.l (a1),a1 + add.l d0,a1 + rts +ewff_iwn: + move.l (a1),a1 + add.l d0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_iln: + move.l (a1),a1 + add.l d0,a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_mi0: + add.l d0,a1 + rts +ewff_miw: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_mil: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_wi0: + mvs.w (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_wiw: + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_wil: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_li0: + move.l (a0)+,d1 + add.l d1,a1 + add.l d0,a1 + rts +ewff_liw: + move.l (a0)+,d1 + add.l d1,a1 + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_lil: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + rts +ewff_w0v: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + rts +ewff_wwv: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_wlv: + mvs.w (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_l0v: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + rts +ewff_lwv: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + rts +ewff_llv: + move.l (a0)+,d1 + add.l d0,a1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + rts +ewff_w0n: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + add.l d0,a1 + rts +ewff_wwn: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_wln: + mvs.w (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_l0n: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + add.l d0,a1 + rts +ewff_lwn: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + mvs.w (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts +ewff_lln: + move.l (a0)+,d1 + add.l d1,a1 + move.l (a1),a1 + move.l (a0)+,d0 + add.l d0,a1 + add.l d0,a1 + rts diff --git a/BaS_gcc/sources/exceptions.S b/BaS_gcc/sources/exceptions.S new file mode 100644 index 0000000..396c5c6 --- /dev/null +++ b/BaS_gcc/sources/exceptions.S @@ -0,0 +1,839 @@ +/* + * initialize exception vectors + */ +#include "startcf.h" + + .extern __Bas_base + .extern __SUP_SP + .extern _rom_entry + .extern __RAMBAR0 + .extern _rt_cacr + .extern _rt_mod + .extern _rt_ssp + .extern _rt_usp + .extern _rt_vbr + .extern _illegal_instruction + .extern _privileg_violation + .extern _mmutr_miss + .extern __MBAR + .extern __MMUBAR + .extern _video_tlb + .extern _video_sbt + .extern cpusha + +/* Register read/write macros */ +#define MCF_MMU_MMUCR __MMUBAR +#define MCF_MMU_MMUOR __MMUBAR+0x04 +#define MCF_MMU_MMUSR __MMUBAR+0x08 +#define MCF_MMU_MMUAR __MMUBAR+0x10 +#define MCF_MMU_MMUTR __MMUBAR+0x14 +#define MCF_MMU_MMUDR __MMUBAR+0x18 + +#define MCF_EPORT_EPPAR __MBAR+0xF00 +#define MCF_EPORT_EPDDR __MBAR+0xF04 +#define MCF_EPORT_EPIER __MBAR+0xF05 +#define MCF_EPORT_EPDR __MBAR+0xF08 +#define MCF_EPORT_EPPDR __MBAR+0xF09 +#define MCF_EPORT_EPFR __MBAR+0xF0C + +#define MCF_GPIO_PODR_FEC1L __MBAR+0xA07 + +#define MCF_PSC0_PSCTB_8BIT __MBAR+0x860C + +#define MCF_PSC3_PSCRB_8BIT __MBAR+0x890C +#define MCF_PSC3_PSCTB_8BIT __MBAR+0x890C + + .global _vec_init + +//mmu --------------------------------------------------- +/* Register read/write macros */ +#define MCF_MMU_MMUCR __MMUBAR +#define MCF_MMU_MMUOR __MMUBAR+0x04 +#define MCF_MMU_MMUSR __MMUBAR+0x08 +#define MCF_MMU_MMUAR __MMUBAR+0x10 +#define MCF_MMU_MMUTR __MMUBAR+0x14 +#define MCF_MMU_MMUDR __MMUBAR+0x18 + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + +#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V) +#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +//--------------------------------------------------- +/********************************************************************* +* +* General Purpose Timers (GPT) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPT0_GMS __MBAR+0x800 + +/********************************************************************* +* +* Slice Timers (SLT) +* +*********************************************************************/ + +#define MCF_SLT0_SCNT __MBAR+0x908 + +/**********************************************************/ +// macros +/**********************************************************/ + .altmacro + .macro irq vector,int_mask,clr_int + local irq_protect + local sev_supint + local irq_end + + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern + lea MCF_EPORT_EPFR,a5 + move.b #\clr_int,(a5) // clear int pending +// test auf protect mode --------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne irq_protect // ja-> +// ------------------------------------------- + movem.l (a7),d0/a5 // register zurück + addq.l #8,a7 + move.l \vector,-(a7) + move #0x2\int_mask\()00,sr + rts +irq_protect: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_supint // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben +#endif + bra irq_end +sev_supint: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec + bset #5,2(a5) // auf super setzen +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif +irq_end: + move.l a5,usp // usp setzen + lea \vector,a5 + adda.l _rt_vbr,a5 + move.l (a5),12(a7) // vectoradresse eintragen + move.b #\int_mask,10(a7) // intmaske setzen + movem.l (a7),d0/a5 // register zur�ck + addq.l #8,a7 + rte // und weg + .endm + +/* + * FIXME: this is a GNU gas kludge. Ugly, but I just can't come up with any smarter solution + * + * GNU as does not support multi-character constants. At least I don't know of any way it would. + * The following might look more than strange, but I considered the statement + * + * mchar move.l, 'T,'E,'S,'T,-(SP) + * + * somewhat more readable than + * + * move.l #1413829460,-(SP) + * + * If anybody knows of any better way on how to do this - please do! + * + */ + .macro mchar st,a,b,c,d,tgt + \st #\a << 24|\b<<16|\c<<8|\d,\tgt + .endm + +.text +_vec_init: + move.l a2,-(sp) // Backup registers + + mov3q.l #-1,_rt_mod // rt_mod auf super + clr.l _rt_ssp + clr.l _rt_usp + clr.l _rt_vbr + move.l #__RAMBAR0,d0 // sind in rambar0 + movec d0,VBR + move.l d0,a0 + move.l a0,a2 +init_vec: + move.l #256,d0 + lea std_exc_vec(pc),a1 // standard vector +init_vec_loop: + move.l a1,(a2)+ // mal standard vector f�r alle setzen + subq.l #1,d0 + bne init_vec_loop + + move.l #__SUP_SP,(a0) + lea reset_vector(pc),a1 + move.l a1,0x04(a0) + lea acess(pc),a1 + move.l a1,0x08(a0) + + move.b DIP_SWITCHa,d0 // ++ vr + btst #7,d0 + beq no_protect_vectors + + lea _illegal_instruction(pc),a1 + move.l a1,0x0c(a0) + lea _illegal_instruction(pc),a1 + move.l a1,0x10(a0) + lea zero_divide(pc),a1 + move.l a1,0x14(a0) + lea _privileg_violation(pc),a1 + move.l a1,0x20(a0) + lea linea(pc),a1 + move.l a1,0x28(a0) + lea linef(pc),a1 + move.l a1,0x2c(a0) + lea format(pc),a1 + move.l a1,0x38(a0) + + // floating point overflow + lea flpoow(pc),a1 + move.l a1,0xc0(a0) + lea flpoow(pc),a1 + move.l a1,0xc4(a0) + lea flpoow(pc),a1 + move.l a1,0xc8(a0) + lea flpoow(pc),a1 + move.l a1,0xcc(a0) + lea flpoow(pc),a1 + move.l a1,0xd0(a0) + lea flpoow(pc),a1 + move.l a1,0xd4(a0) + lea flpoow(pc),a1 + move.l a1,0xd8(a0) + lea flpoow(pc),a1 + move.l a1,0xdc(a0) +no_protect_vectors: + + +// int 1-7 + lea irq1(pc),a1 + move.l a1,0x104(a0) + lea irq2(pc),a1 + move.l a1,0x108(a0) + lea irq3(pc),a1 + move.l a1,0x10c(a0) + lea irq4(pc),a1 + move.l a1,0x110(a0) + lea irq5(pc),a1 + move.l a1,0x114(a0) + lea irq6(pc),a1 + move.l a1,0x118(a0) + lea irq7(pc),a1 + move.l a1,0x11c(a0) +//psc_vectors + lea psc3(pc),a1 + move.l a1,0x180(a0) +//timer 1 vectors + lea timer0(pc),a1 + move.l a1,0x1f8(a0) + + move.l (sp)+,a2 // Restore registers + rts +/* + * exception vector routines + */ +vector_table_start: +std_exc_vec: + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern +// test auf protect mode ------------------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne stv_protect // ja-> +//------------------------------------------------------ + move.w 8(a7),d0 // vector holen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),d0 + move.l 4(a7),a5 // a5 zur�ck + move.l d0,4(a7) + move.w 10(a7),d0 + bset #13,d0 // super + move.w d0,sr // orginal sr wert in super setzen + move.l (a7)+,d0 // d0 zur�ck + rts +stv_protect: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_sup // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),d0 // sr holen + move.l d0,-(a5) // sr transferieren + swap d0 // vec -> lw +#else + move.w 8(a7),d0 // vector holen + move.w d0,-(a5) // ablegen + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren +#endif + move.l a5,usp // usp setzen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),12(a7) // hier geht's weiter + movem.l (a7),d0/a5 // register zur�ck + addq.l #8,a7 + rte // und weg +sev_sup: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),d0 // sr holen + bset #13,d0 // war aus rt super + move.l d0,-(a5) // sr transferieren + swap d0 // vec -> lw +#else + move.w 8(a7),d0 // vector holen + move.w d0,-(a5) // ablegen + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren + bset #5,(a5) // war aus super +#endif + move.l a5,usp // usp setzen + and.l #0x3fc,d0 // vector nummer ausmaskieren + add.l _rt_vbr,d0 // + basis + move.l d0,a5 + move.l (a5),12(a7) // hier geht's weiter + movem.l (a7),d0/a5 // register zur�ck + addq.l #8,a7 + rte // und weg +//******************************************* +reset_vector: + move.w #0x2700,sr // disable interrupt + move.l #0x31415926,d0 + cmp.l 0x426,d0 // reset vector g�ltg? + beq std_exc_vec // ja-> + jmp _rom_entry // sonst kaltstart +acess: + move.w #0x2700,sr // disable interrupt + move.l d0,-(sp) // ++ vr + move.w 4(sp),d0 + andi.l #0x0c03,d0 + cmpi.l #0x0401,d0 + beq access_mmu + cmpi.l #0x0402,d0 + beq access_mmu + cmpi.l #0x0802,d0 + beq access_mmu + cmpi.l #0x0c02,d0 + beq access_mmu + bra bus_error +access_mmu: + move.l MCF_MMU_MMUSR,d0 + btst #1,d0 + bne bus_error + move.l MCF_MMU_MMUAR,d0 + cmp.l #__FASTRAM_END,d0 // max User RAM Bereich + bge bus_error // grösser -> bus error + bra _mmutr_miss +bus_error: + move.l (sp)+,d0 + bra std_exc_vec + +zero_divide: + move.w #0x2700,sr // disable interrupt + move.l a0,-(a7) + move.l d0,-(a7) + move.l 12(a7),a0 // pc + move.w (a0)+,d0 // befehlscode + btst #7,d0 // long? + beq zd_word // nein-> + addq.l #2,a0 +zd_word: + and.l 0x3f,d0 // ea ausmaskieren + cmp.w #0x08,d0 // -(ax) oder weniger + ble zd_end + addq.l #2,a0 + cmp.w #0x39,d0 // xxx.L + bne zd_nal + addq.l #2,a0 + bra zd_end +zd_nal: cmp.w #0x3c,d0 // immediate? + bne zd_end // nein-> + btst #7,d0 // long? + beq zd_end // nein + addq.l #2,a0 +zd_end: + move.l a0,12(a7) + move.l (a7)+,d0 + move.l (a7)+,a0 + rte + +linea: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +linef: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +format: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +//floating point +flpoow: + move.w #0x2700,sr // disable interrupt + halt + nop + nop +irq1: + irq 0x64,1,0x02 +irq2: // hbl + // move.b #3,2(a7) + // rte + irq 0x68,2,0x04 +irq3: + irq 0x6c,3,0x08 +irq4: // vbl + irq 0x70,4,0x10 +irq5: // acp + irq 0x74,5,0x20 +irq6: // mfp + move.w #0x2700,sr // disable interrupt + subq.l #8,a7 + movem.l d0/a5,(a7) // register sichern + lea MCF_EPORT_EPFR,a5 + move.b #0x40,(a5) // clear int6 +// test auf timeout screen adr change ------------------------------------------------------- + move.l _video_sbt,d0 + beq irq6_non_sca // wenn 0 nichts zu tun + sub.l #0x70000000,d0 // 14 sec abz�hlen + lea MCF_SLT0_SCNT,a5 + cmp.l (a5),d0 // aktuelle zeit weg + ble irq6_non_sca // noch nicht abgelaufen + lea -28(a7),a7 + movem.l d0-d4/a0-a1,(a7) // register sichern + clr.l d3 // beginn mit 0 + bsr cpusha // cache leeren + // eintrag suchen + irq6_next_sca: + move.l d3,d0 + move.l d0,MCF_MMU_MMUAR // addresse + move.l #0x106,d4 + move.l d4,MCF_MMU_MMUOR // suchen -> + nop + move.l MCF_MMU_MMUOR,d4 + clr.w d4 + swap d4 + move.l d4,MCF_MMU_MMUAR + mvz.w #0x10e,d4 + move.l d4,MCF_MMU_MMUOR // eintr�ge holen aus mmu + nop + move.l MCF_MMU_MMUTR,d4 // ID holen + lsr.l #2,d4 // bit 9 bis 2 + cmp.w #sca_page_ID,d4 // ist screen change ID? + bne irq6_sca_pn // nein -> page keine screen area next +// eintrag �ndern + add.l #std_mmutr,d0 + move.l d3,d1 // page 0? + beq irq6_sca_pn0 // ja -> + add.l #cb_mmudr,d1 // sonst page cb + bra irq6_sca_pn1c +irq6_sca_pn0: + add.l #wt_mmudr|MCF_MMU_MMUDR_LK,d1 // page wt and locked +irq6_sca_pn1c: + mvz.w #0x10b,d2 // MMU update + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setze tlb data only + nop +// page copy + move.l d3,a0 + add.l #0x60000000,a0 + move.l d3,a1 + move.l #0x10000,d4 // die ganze page +irq6_vcd0_loop: + move.l (a0)+,(a1)+ // page copy + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + subq.l #1,d4 + bne irq6_vcd0_loop + nop +irq6_sca_pn: + add.l #0x00100000,d3 // next + cmp.l #0x00d00000,d3 // ende? + blt irq6_next_sca // nein-> + + move.l #0x2000,d0 + move.l d0,_video_tlb // anfangszustand wieder herstellen + clr.l _video_sbt // zeit l�schen + + movem.l (a7),d0-d4/a0-a1 // register zur�ck + lea 28(a7),a7 +irq6_non_sca: +// test auf acsi dma ----------------------------------------------------------------- + lea 0xfffffa0b,a5 + bset #7,-4(a5) // int ena + btst.b #7,(a5) // acsi dma int? + beq non_acsi_dma + bsr acsi_dma +non_acsi_dma: +// ---------------------------------------------------------------------------------- + tst.b (a5) + bne irq6_1 + tst.b 2(a5) + bne irq6_1 + movem.l (a7),d0/a5 + addq.l #8,a7 + rte +irq6_1: + lea MCF_GPIO_PODR_FEC1L,a5 + bclr.b #4,(a5) // led on + lea blinker,a5 + addq.l #1,(a5) // +1 + move.l (a5),d0 + and.l #0x80,d0 + bne irq6_2 + lea MCF_GPIO_PODR_FEC1L,a5 + bset.b #4,(a5) // led off +irq6_2: +// test auf protect mode --------------------- + move.b DIP_SWITCHa,d0 + btst #7,d0 + bne irq6_3 // ja-> +// ------------------------------------------- + move.l 0xF0020000,a5 // vector holen + add.l _rt_vbr,a5 // basis + move.l (a5),d0 // vector holen + move.l 4(a7),a5 // a5 zur�ck + move.l d0,4(a7) // vector eintragen + move.l (a7)+,d0 // d0 zur�ck + move #0x2600,sr + rts +irq6_3: + move.l usp,a5 // usp holen + tst.b _rt_mod // supervisor? + bne sev_sup6 // ja -> + mov3q.l #-1,_rt_mod // auf supervisor setzen + move.l a5,_rt_usp // rt_usp speichern + move.l _rt_ssp,a5 // rt_ssp holen +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr transferieren +#else + move.w 8(a7),-(a5) // vector transferieren + move.l 12(a7),-(a5) // pc transferieren + move.w 10(a7),-(a5) // sr transferieren +#endif + move.l a5,usp // usp setzen + move.l 0xF0020000,a5 // vector holen: intack routine + add.l _rt_vbr,a5 // virtuelle VBR des Systems + move.l (a5),12(a7) // hier gehts weiter + movem.l (a7),d0/a5 // register zur�ck + addq.l #8,a7 + move.b #6,2(a7) // intmaske setzen + rte // und weg +sev_sup6: +#ifdef cf_stack + move.l 12(a7),-(a5) // pc transferieren + move.l 8(a7),-(a5) // sr,vec + bset #5,2(a5) // auf super setzen +#else + move.w 8(a7),-(a5) // vector nr. + move.l 12(a7),-(a5) // pc verschieben + move.w 10(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif + move.l a5,usp // usp setzen + move.l 0xF0020000,a5 // vector holen: intack routine + add.l _rt_vbr,a5 // virtuelle VBR des Systems + move.l (a5),12(a7) // hier gehts weiter + movem.l (a7),d0/a5 // register zur�ck + rts + + .data +blinker:.long 0 + + + .text + +/* + * pseudo dma + */ +acsi_dma: // atari dma + move.l a1,-(a7) + move.l d1,-(a7) + + lea MCF_PSC0_PSCTB_8BIT,a1 // ++ vr + mchar move.l, 'D,'M','A,'\ ,(a1) + //move.l #"DMA ",(a1) + mchar move.l,'I,'N,'T,'!,(a1) + // move.l #'INT!',(a1) + + lea 0xf0020110,a5 // fifo daten +acsi_dma_start: + move.l -12(a5),a1 // dma adresse + move.l -8(a5),d0 // byt counter + ble acsi_dma_end + btst.b #0,-16(a5) // write? (dma modus reg) + bne acsi_dma_wl // ja-> +acsi_dma_rl: + tst.b -4(a5) // dma req? + bpl acsi_dma_fertig // nein-> + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + move.l (a5),(a1)+ // read 4 bytes + + moveq #'.',d1 + move.b d1,MCF_PSC0_PSCTB_8BIT + + sub.l #16,d0 // byt counter -16 + bpl acsi_dma_rl + bra acsi_dma_fertig +acsi_dma_wl: + tst.b -4(a5) // dma req? + bpl acsi_dma_fertig // nein-> + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + move.l (a1)+,(a5) // write 4 byts + + moveq #'.',d1 + move.b d1,MCF_PSC0_PSCTB_8BIT + + sub.l #16,d0 // byt counter -16 + bpl acsi_dma_wl +acsi_dma_fertig: + move.l a1,-12(a5) // adresse zur�ck + move.l d0,-8(a5) // byt counter zur�ck +acsi_dma_end: + tst.b -4(a5) // dma req? + bmi acsi_dma_start // ja-> + lea 0xfffffa0b,a5 + bclr.b #7,4(a5) // clear int in service mfp + bclr.b #7,(a5) // clear int pending mfp 0xfffffa0b + + move.w #0x0d0a,d1 + move.w d1,MCF_PSC0_PSCTB_8BIT + + move.l (a7)+,d1 + move.l (a7)+,a1 + rts +/* + * irq 7 = pseudo bus error + */ +irq7: + lea -12(sp),sp + movem.l d0/a0,(sp) + + move.l __RAMBAR0+0x008,a0 // Real Access Error handler + move.l a0,8(sp) // This will be the return address for rts + + move.w 12(sp),d0 // Format/Vector word + andi.l #0xf000,d0 // Keep only the Format + ori.l #2*4,d0 // Simulate Vector #2, no Fault + move.w d0,12(sp) + + // TODO: Inside an interrupt handler, 16(sp) is the return address. + // For an Access Error, it should be the address of the fault instruction instead + + lea MCF_EPORT_EPFR,a0 + move.b #0x80,(a0) // clear int7 + move.l (sp)+,d0 + move.l (sp)+,a0 + rts // Forward to the Access Error handler + +/* + * psc3 com PIC MCF + */ +psc3: + move.w #0x2700,sr // disable interrupt + lea -20(a7),a7 + movem.l d0-d2/a0/a3,(a7) + lea MCF_PSC3_PSCRB_8BIT,a3 + move.b (a3),d1 + cmp.b #2,d1 // anforderung rtc daten? + bne psc3_fertig + + lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr + mchar move.l,'\P,'\I,'C,' ,(a0) + // move.l #'PIC ',(a0) + mchar move.l,'I,'N,'T,'\ ,(a0) + // move.l #'INT ',(a0) + mchar move.l,'R,'T,'C,'!,(a0) + // move.l #'RTC!',(a0) + mchar move.l,0x0d,0x0a,0,0,(a0) + //move.l #0x0d0a,(a0) + + lea 0xffff8961,a0 + lea MCF_PSC3_PSCTB_8BIT,a3 + clr.l d1 + moveq #64,d2 + move.b #0x82,(a3) // header: rtcd mcf->pic +loop_sr2: + move.b d1,(a0) + move.b 2(a0),d0 + move.b d0,(a3) + addq.l #1,d1 + cmp.b d1,d2 + bne loop_sr2 +psc3_fertig: + movem.l (a7),d0-d2/a0/a3 // register zur�ck + lea 20(a7),a7 + RTE + +/* + * timer 0: video change later also others + */ +timer0: + move #0x2700,sr +// halt + lea -28(a7),a7 + movem.l d0-d4/a0-a1,(a7) + mvz.b 0xffff8201,d0 // l�schen und high byt + cmp.w #2,d0 + blt video_chg_end + cmp.w #0xd0,d0 // normale addresse + blt sca_other // nein-> + lea MCF_SLT0_SCNT,a0 + move.l (a0),d4 + move.l d4,_video_sbt // time sichern +sca_other: + lsl.l #8,d0 + move.b 0xffff8203,d0 // mid byt + lsl.l #8,d0 + move.b 0xffff820d,d0 // low byt + move.l d0,d3 +video_chg_1page: +// test ob page schon gesetzt + moveq #20,d4 + move.l d0,d2 + lsr.l d4,d2 // neue page + move.l _video_tlb,d4 + bset.l d2,d4 // setzen als ge�ndert + bne video_chg_2page // schon gesetzt gewesen? ja->weg + move.l d4,_video_tlb + bsr cpusha // cache leeren +// daten copieren +video_copy_data: + move.l d4,_video_tlb + and.l #0x00f00000,d0 + move.l d0,a0 + move.l a0,a1 + add.l #0x60000000,a1 + move.l #0x10000,d4 // die ganze page +video_copy_data_loop: + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + move.l (a0)+,(a1)+ + subq.l #1,d4 + bne video_copy_data_loop +// eintrag suchen + move.l d0,MCF_MMU_MMUAR // addresse + move.l #0x106,d4 + move.l d4,MCF_MMU_MMUOR // suchen -> schl�gt neuen vor wenn keiner + nop + move.l MCF_MMU_MMUOR,d4 + clr.w d4 + swap d4 + move.l d4,MCF_MMU_MMUAR + move.l d0,d1 + add.l #MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 + add.l #0x60000000|wt_mmudr|MCF_MMU_MMUDR_LK,d1 + mvz.w #0x10b,d2 // MMU update + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen vidoe maped to 60xxx only data + nop +video_chg_2page: +// test ob evt. anschliessende page gesetzt werden muss + move.l d3,d0 + mvz.w 0xffff8210,d4 // byts pro zeile + mvz.w 0xffff82aa,d2 // zeilen ende + mvz.w 0xffff82a8,d1 // zeilenstart + sub.l d1,d2 // differenz = anzahl zeilen + mulu d2,d4 // maximal 480 zeilen + add.l d4,d0 // video gr�sse + cmp.l #__STRAM_END,d0 // maximale addresse + bge video_chg_end // wenn gleich oder gr�sser -> fertig + moveq #20,d4 + move.l d0,d2 + lsr.l d4,d2 // neue page + move.l _video_tlb,d4 + bset.l d2,d4 // setzen als ge�ndert + beq video_copy_data // nein nochmal +video_chg_end: +// int pending l�schen + lea MCF_GPT0_GMS,a0 + bclr.b #0,3(a0) + nop + bset.b #0,3(a0) + + movem.l (a7),d0-d4/a0-a1 + lea 28(a7),a7 +//-------------------------------------------------------------------------------------------------------- + RTE + diff --git a/BaS_gcc/sources/ii_add.h b/BaS_gcc/sources/ii_add.h new file mode 100644 index 0000000..bc23f63 --- /dev/null +++ b/BaS_gcc/sources/ii_add.h @@ -0,0 +1,581 @@ +//-------------------------------------------------------------------- +// add +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// add.b #im,dx +//-------------------------------------------------------------------- +addbir_macro:.macro + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + add.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add ea,dx +//-------------------------------------------------------------------- +adddd:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add ea,dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddd:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add (ea),dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +adddda:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add (ay)+,dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddai:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add -(ay),dx (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addddad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d16(ay),dx +//-------------------------------------------------------------------- +addd16ad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d8(ay,dy),dx +//-------------------------------------------------------------------- +addd8ad:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add xxx.w,dx +//-------------------------------------------------------------------- +addxwd:.macro +#ifdef halten_add + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add xxx.l,dx +//-------------------------------------------------------------------- +addxld:.macro +#ifdef halten_add + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d16(pc),dx +//-------------------------------------------------------------------- +addd16pcd:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add d8(pc,dy),dx +//-------------------------------------------------------------------- +addd8pcd:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// add dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // add dx,(ay) (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addeda:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,(ay)+ (first ea->a1 z.B. für a0,a1,USP) +//-------------------------------------------------------------------- +addedai:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,(ay)+ +//-------------------------------------------------------------------- +addedaid:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,-(ay) +//-------------------------------------------------------------------- +addedad:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,-(ay) +//-------------------------------------------------------------------- +addedadd:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + add.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,d16(ay) +//-------------------------------------------------------------------- +adde16ad:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add.w d8(ay,dy),dx +//-------------------------------------------------------------------- +adde8ad:.macro +#ifdef halten_add + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,xxx.w +//-------------------------------------------------------------------- +addxwe:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // add dx,xxx.l +//-------------------------------------------------------------------- +addxle:.macro +#ifdef halten_add + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + add.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// // adda.w ea,ax (ea = dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addaw:.macro +#ifdef halten_add + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + mvs.w \1,d0 + adda.l d0,\2 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// add.w ea,usp +//-------------------------------------------------------------------- +addawa7:.macro +#ifdef halten_add + halt +#endif + mvs.w \1,d0 + move.l usp,a1 + add.l d0,a1 + move.l a1,usp + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w ea,usp (ea = dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addawu:.macro +#ifdef halten_add + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + move.l a7,_a7_save + move.l usp,a7 + move.l \1,d0 + adda.l d0,\2 + move.l a7,usp + move.l _a7_save,a7 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// // adda.w ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax) +//-------------------------------------------------------------------- +addawua7:.macro + addawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // adda.w d16(ay),ax +//-------------------------------------------------------------------- +addawd16a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + adda.l d0,a1 + mvs.w (a1),d0 + move.l \2,a1 + add.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d8(ay,dy),ax +//-------------------------------------------------------------------- +addawd8a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + add.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w xxx.w,ax +//-------------------------------------------------------------------- +addawxwax:.macro +#ifdef halten_add + halt +#endif + move.w \1,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w xxx.l,ax +//-------------------------------------------------------------------- +addawxlax:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d16(pc),ax +//-------------------------------------------------------------------- +addawd16pcax:.macro +#ifdef halten_add + halt +#endif + move.w \1,a1 + adda.l a0,a1 + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w d8(pc,dy),ax +//-------------------------------------------------------------------- +addawd8pcax:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.w #im,ax +//-------------------------------------------------------------------- +addawim:.macro +#ifdef halten_add + halt +#endif + mvs.w \1,d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.l d8(ay,dy),ax +//-------------------------------------------------------------------- +addald8a:.macro +#ifdef halten_add + halt +#endif + move.l \1,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // adda.l d8(pc,dy),ax +//-------------------------------------------------------------------- +addakd8pcax:.macro +#ifdef halten_add + halt +#endif + move.l a0,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + adda.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//***************************************************************************************** +// addx +//***************************************************************************************** +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +adddx:.macro +#ifdef halten_add + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + mvs.\3 \2,d0 + mvs.\3 \1,d1 + addx.l d0,d1 + set_cc0 + move.\3 d1,\1 + ii_end + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +adddax:.macro +#ifdef halten_add + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + move.l \1,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d0 +.endif + move.l \2,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d1 +.endif + addx.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_gcc/sources/ii_and.h b/BaS_gcc/sources/ii_and.h new file mode 100644 index 0000000..f74afde --- /dev/null +++ b/BaS_gcc/sources/ii_and.h @@ -0,0 +1,441 @@ +//-------------------------------------------------------------------- +// and +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// and.b #im,dx +//-------------------------------------------------------------------- +andbir_macro:.macro + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + and.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea,dx +//-------------------------------------------------------------------- +anddd:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +andddd:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and (ea)->dy,dx +//-------------------------------------------------------------------- +anddda:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +andddai:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and ea->ay,-(ay),dx +//-------------------------------------------------------------------- +andddad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d16(ay),dx +//-------------------------------------------------------------------- +andd16ad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d8(ay,dy),dx +//-------------------------------------------------------------------- +andd8ad:.macro +#ifdef halten_and + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and xxx.w,dx +//-------------------------------------------------------------------- +andxwd:.macro +#ifdef halten_and + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and xxx.l,dx +//-------------------------------------------------------------------- +andxld:.macro +#ifdef halten_and + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d16(pc),dx +//-------------------------------------------------------------------- +andd16pcd:.macro +#ifdef halten_and + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and d8(pc,dy),dx +//-------------------------------------------------------------------- +andd8pcd:.macro +#ifdef halten_and + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// and dx,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // and dx,(ea)->dy +//-------------------------------------------------------------------- +andeda:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +andedai:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +andedaid:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +andedad:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +andedadd:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + and.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,d16(ay) +//-------------------------------------------------------------------- +ande16ad:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and.w dx,d8(ay,dy) +//-------------------------------------------------------------------- +ande8ad:.macro +#ifdef halten_and + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,xxx.w +//-------------------------------------------------------------------- +andxwe:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // and dx,xxx.l +//-------------------------------------------------------------------- +andxle:.macro +#ifdef halten_and + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + and.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // anda.w ea,ax +//-------------------------------------------------------------------- +andaw:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// and.w ea,usp +//-------------------------------------------------------------------- +andawa7:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w usp?,ax +//-------------------------------------------------------------------- +andawu:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w usp?,usp +//-------------------------------------------------------------------- +andawua7:.macro + andawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // anda.w d16(ay),ax +//-------------------------------------------------------------------- +andawd16a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d8(ay,dy),ax +//-------------------------------------------------------------------- +andawd8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w xxx.w,ax +//-------------------------------------------------------------------- +andawxwax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w xxx.l,ax +//-------------------------------------------------------------------- +andawxlax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d16(pc),ax +//-------------------------------------------------------------------- +andawd16pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w d8(pc,dy),ax +//-------------------------------------------------------------------- +andawd8pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.w #im,ax +//-------------------------------------------------------------------- +andawim:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.l d8(ay,dy),ax +//-------------------------------------------------------------------- +andald8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // anda.l d8(pc,dy),ax +//-------------------------------------------------------------------- +andald8pcax:.macro + jmp ii_error + .endm; +//***************************************************************************************** +// spezial addx subx etc. +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +anddx:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +anddax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_gcc/sources/ii_dbcc.h b/BaS_gcc/sources/ii_dbcc.h new file mode 100644 index 0000000..652cdbe --- /dev/null +++ b/BaS_gcc/sources/ii_dbcc.h @@ -0,0 +1,117 @@ +//-------------------------------------------------------------------- +// dbcc,trapcc +//-------------------------------------------------------------------- +.text +ii_lset_dbcc:.macro +// dbra + ii_lset_opeau 51,c + ii_lset_opeau 52,c + ii_lset_opeau 53,c + ii_lset_opeau 54,c + ii_lset_opeau 55,c + ii_lset_opeau 56,c + ii_lset_opeau 57,c + ii_lset_opeau 58,c + ii_lset_opeau 59,c + ii_lset_opeau 5a,c + ii_lset_opeau 5b,c + ii_lset_opeau 5c,c + ii_lset_opeau 5d,c + ii_lset_opeau 5e,c + ii_lset_opeau 5f,c +.endm + +ii_dbcc_func:.macro +ii_0x51c8: + dbra_macro d0_off+2(a7) +ii_0x51c9: + dbra_macro d1_off+2(a7) +ii_0x51ca: + dbra_macro d2 +ii_0x51cb: + dbra_macro d3 +ii_0x51cc: + dbra_macro d4 +ii_0x51cd: + dbra_macro d5 +ii_0x51ce: + dbra_macro d6 +ii_0x51cf: + dbra_macro d7 +//--------------------------------------------------------------------------------------------- +// dbcc dx +//--------------------------------------------------------------------------------------------- + ii_dbcc 2,hi + ii_dbcc 3,ls + ii_dbcc 4,cc + ii_dbcc 5,cs + ii_dbcc 6,ne + ii_dbcc 7,eq + ii_dbcc 8,vc + ii_dbcc 9,vs + ii_dbcc a,pl + ii_dbcc b,mi + ii_dbcc c,ge + ii_dbcc d,lt + ii_dbcc e,gt + ii_dbcc f,le +.endm +//--------------------------------------------------------------------------------------------- +// dbra dx +//--------------------------------------------------------------------------------------------- +dbra_macro:.macro +#ifdef halten_dbcc + halt +#endif + mvz.w \1,d1 // dx holen + subq.l #1,d1 // dx-1 + bcc dbra\@ // bra if plus? + addq.l #2,a0 // offset überspringen + move.w d1,\1 // dx sichern + ii_end +dbra\@: + move.w (a0),a1 // offset (wird auf long erweitert) + add.l a1,a0 // dazuadieren + move.w d1,\1 // dx sichern + ii_end +.endm +//--------------------------------------------------------------------------------------------- +// dbcc dx +//--------------------------------------------------------------------------------------------- +dbcc_macro:.macro +#ifdef halten_dbcc + halt +#endif + b\2 dbncc\@ + mvz.w \1,d1 // dx holen + subq.l #1,d1 // dx-1 + bcc dbcc\@ // bra if plus? +dbncc\@: + addq.l #2,a0 // offset überspringen + move.w d1,\1 // dx sichern + ii_end +dbcc\@: + move.w (a0),a1 // offset (wird auf long erweitert) + add.l a1,a0 // dazuadieren + move.w d1,\1 // dx sichern + ii_end +.endm +//db +ii_dbcc:.macro +ii_0x5\1c8: + dbcc_macro d0_off+2(a7),\2 +ii_0x5\1c9: + dbcc_macro d1_off+2(a7),\2 +ii_0x5\1ca: + dbcc_macro d2,\2 +ii_0x5\1cb: + dbcc_macro d3,\2 +ii_0x5\1cc: + dbcc_macro d4,\2 +ii_0x5\1cd: + dbcc_macro d5,\2 +ii_0x5\1ce: + dbcc_macro d6,\2 +ii_0x5\1cf: + dbcc_macro d7,\2 +.endm \ No newline at end of file diff --git a/BaS_gcc/sources/ii_ewf.h b/BaS_gcc/sources/ii_ewf.h new file mode 100644 index 0000000..34d2483 --- /dev/null +++ b/BaS_gcc/sources/ii_ewf.h @@ -0,0 +1,181 @@ +//-------------------------------------------------------------------- +// extension word format missing +//-------------------------------------------------------------------- +.text +ii_ewf_lset:.macro +// pea + ii_lset_opeag 48,7 + ii_lset 0x487b +// jmp + ii_lset_opeag 4e,f + ii_lset 0x4efb +// jsr + ii_lset_opeag 4e,b + ii_lset 0x4ebb +// tas + ii_lset_opeag 4a,f + ii_lset 0x4ebb +// tst.b + ii_lset_opeag 4a,3 + ii_lset 0x4ebb +// tst.w + ii_lset_opeag 4a,7 + ii_lset 0x4ebb +// tst.l + ii_lset_opeag 4a,b + ii_lset 0x4ebb +// clr.b + ii_lset_opeag 42,3 + ii_lset 0x423b +// clr.w + ii_lset_opeag 42,7 + ii_lset 0x423b +// clr.l + ii_lset_opeag 42,b + ii_lset 0x423b +.endm +//--------------------------------------------------------------------------------------------- +ii_ewf_func:.macro + ewf_func_macro pea,487 + ewf_func_macro jmp,4ef + ewf_func_macro jsr,4eb + ewf_func_macro tas,4af + ewf_func_macro tstb,4a3 + ewf_func_macro tstw,4a7 + ewf_func_macro tstl,4ab + ewf_func_macro clrb,423 + ewf_func_macro clrw,427 + ewf_func_macro clrl,42b +.endm +//--------------------------------------------------------------------------------------------- +pea_macro:.macro + jsr ewf + move.l (a1),d0 + move.l usp,a1 + move.l d0,-(a1) + move.l a1,usp + ii_end +.endm + +jmp_macro:.macro + jsr ewf + move.l a1,a0 + ii_end +.endm + +jsr_macro:.macro + jsr ewf + move.l a1,d0 + move.l usp,a1 + move.l a0,-(a1) + move.l a1,usp + move.l d0,a0 + ii_end +.endm + +tas_macro:.macro + jsr ewf + tas (a1) + set_cc0 + ii_end +.endm + +tstb_macro:.macro + jsr ewf + tst.b (a1) + set_cc0 + ii_end +.endm + +tstw_macro:.macro + jsr ewf + tst.w (a1) + set_cc0 + ii_end +.endm + +tstl_macro:.macro + jsr ewf + tst.l (a1) + set_cc0 + ii_end +.endm + +clrb_macro:.macro + jsr ewf + clr.b (a1) + set_cc0 + ii_end +.endm + +clrw_macro:.macro + jsr ewf + clr.w (a1) + set_cc0 + ii_end +.endm + +clrl_macro:.macro + jsr ewf + clr.l (a1) + set_cc0 + ii_end +.endm +//-------------------------------------------------------------------- +ewf_func_macro:.macro //1=art 2=code +ii_0x\20: +#ifdef halten_ewf + halt +#endif + move.l a0_off(a7),a1 + \1_macro +ii_0x\21: +#ifdef halten_ewf + halt +#endif + move.l a1_off(a7),a1 + \1_macro +ii_0x\22: +#ifdef halten_ewf + halt +#endif + move.l a2,a1 + \1_macro +ii_0x\23: +#ifdef halten_ewf + halt +#endif + move.l a3,a1 + \1_macro +ii_0x\24: +#ifdef halten_ewf + halt +#endif + move.l a4,a1 + \1_macro +ii_0x\25: +#ifdef halten_ewf + halt +#endif + move.l a5,a1 + \1_macro +ii_0x\26: +#ifdef halten_ewf + halt +#endif + move.l a6,a1 + \1_macro +ii_0x\27: +#ifdef halten_ewf + halt +#endif + move.l usp,a1 + \1_macro +ii_0x\2b: +#ifdef halten_ewf + halt +#endif + move.l a0,a1 + \1_macro +.endm + diff --git a/BaS_gcc/sources/ii_exg.h b/BaS_gcc/sources/ii_exg.h new file mode 100644 index 0000000..a0544af --- /dev/null +++ b/BaS_gcc/sources/ii_exg.h @@ -0,0 +1,120 @@ +//-------------------------------------------------------------------- +// exg +//-------------------------------------------------------------------- +.text +ii_exg_lset:.macro +/* ii_lset_dxu c,40 //dx,d0 + ii_lset_dxu c,41 //dx,d1 + ii_lset_dxu c,42 //dx,d2 + ii_lset_dxu c,43 //dx,d3 + ii_lset_dxu c,44 //dx,d4 + ii_lset_dxu c,45 //dx,d5 + ii_lset_dxu c,46 //dx,d6 + ii_lset_dxu c,47 //dx,d7 + ii_lset_dxu c,48 //ax,a0 + ii_lset_dxu c,49 //ax,a1 + ii_lset_dxu c,4a //ax,a2 + ii_lset_dxu c,4b //ax,a3 + ii_lset_dxu c,4c //ax,a4 + ii_lset_dxu c,4d //ax,a5 + ii_lset_dxu c,4e //ax,a6 + ii_lset_dxu c,4f //ax,a7 */ -->setting by "and" + ii_lset_dxu c,88 //dx,a0 + ii_lset_dxu c,89 //dx,a1 + ii_lset_dxu c,8a //dx,a2 + ii_lset_dxu c,8b //dx,a3 + ii_lset_dxu c,8c //dx,a4 + ii_lset_dxu c,8d //dx,a5 + ii_lset_dxu c,8e //dx,a6 + ii_lset_dxu c,8f //dx,a7 +.endm +//--------------------------------------------------------------------------------------------- +ii_exg_func:.macro +// exg dx,dy + ii_exg_dx_dx 14,d0_off(a7) + ii_exg_dx_dx 34,d1_off(a7) + ii_exg_dx_dx 54,d2 + ii_exg_dx_dx 74,d3 + ii_exg_dx_dx 94,d4 + ii_exg_dx_dx b4,d5 + ii_exg_dx_dx d4,d6 + ii_exg_dx_dx f4,d7 +// exg ax,ay + ii_exg_to_ax 14,a0_off(a7) + ii_exg_to_ax 34,a1_off(a7) + ii_exg_to_ax 54,a2 + ii_exg_to_ax 74,a3 + ii_exg_to_ax 94,a4 + ii_exg_to_ax b4,a5 + ii_exg_to_ax d4,a6 + ii_exg_to_ax f4,usp +// exg dx,ay + ii_exg_to_ax 18,d0_off(a7) + ii_exg_to_ax 38,d1_off(a7) + ii_exg_to_ax 58,d2 + ii_exg_to_ax 78,d3 + ii_exg_to_ax 98,d4 + ii_exg_to_ax b8,d5 + ii_exg_to_ax d8,d6 + ii_exg_to_ax f8,d7 +.endm +//--------------------------------------------------------------------------------------------- +exg_macro:.macro +#ifdef halten_exg + halt +#endif + move.l \1,a1 +.ifc \2,usp + move.l a1,d0 + move.l \2,a1 + move.l a1,\1 + move.l d0,a1 +.else + .ifc \1,usp + move.l a1,d0 + move.l \2,a1 + move.l a1,\1 + move.l d0,a1 + .else + move.l \2,\1 + .endif +.endif + move.l a1,\2 + ii_end +.endm +ii_exg_dx_dx:.macro +ii_0xc\10: + exg_macro \2,d0_off(a7) +ii_0xc\11: + exg_macro \2,d1_off(a7) +ii_0xc\12: + exg_macro \2,d2 +ii_0xc\13: + exg_macro \2,d3 +ii_0xc\14: + exg_macro \2,d4 +ii_0xc\15: + exg_macro \2,d5 +ii_0xc\16: + exg_macro \2,d6 +ii_0xc\17: + exg_macro \2,d7 +.endm +ii_exg_to_ax:.macro +ii_0xc\18: + exg_macro \2,a0_off(a7) +ii_0xc\19: + exg_macro \2,a1_off(a7) +ii_0xc\1a: + exg_macro \2,a2 +ii_0xc\1b: + exg_macro \2,a3 +ii_0xc\1c: + exg_macro \2,a4 +ii_0xc\1d: + exg_macro \2,a5 +ii_0xc\1e: + exg_macro \2,a6 +ii_0xc\1f: + exg_macro \2,usp +.endm \ No newline at end of file diff --git a/BaS_gcc/sources/ii_func.h b/BaS_gcc/sources/ii_func.h new file mode 100644 index 0000000..f545f47 --- /dev/null +++ b/BaS_gcc/sources/ii_func.h @@ -0,0 +1,945 @@ +//-------------------------------------------------------------------- +// functionen macros +//-------------------------------------------------------------------- +ii_lset_func:.macro +/******************************************************/ +// byt +/******************************************************/ +// func.b dy,dx + ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,01 + ii_lset_dx \1,02 + ii_lset_dx \1,03 + ii_lset_dx \1,04 + ii_lset_dx \1,05 + ii_lset_dx \1,06 + ii_lset_dx \1,07 +// func.b ax,dx + ii_lset_dxu \1,08 + ii_lset_dxu \1,09 + ii_lset_dxu \1,0a + ii_lset_dxu \1,0b + ii_lset_dxu \1,0c + ii_lset_dxu \1,0d + ii_lset_dxu \1,0e + ii_lset_dxu \1,0f +// func.b (ax),dx + ii_lset_dx \1,10 + ii_lset_dx \1,11 + ii_lset_dx \1,12 + ii_lset_dx \1,13 + ii_lset_dx \1,14 + ii_lset_dx \1,15 + ii_lset_dx \1,16 + ii_lset_dx \1,17 +// func.b (ax)+,dx + ii_lset_dx \1,18 + ii_lset_dx \1,19 + ii_lset_dx \1,1a + ii_lset_dx \1,1b + ii_lset_dx \1,1c + ii_lset_dx \1,1d + ii_lset_dx \1,1e + ii_lset_dx \1,1f +// func.b -(ax),dx + ii_lset_dx \1,20 + ii_lset_dx \1,21 + ii_lset_dx \1,22 + ii_lset_dx \1,23 + ii_lset_dx \1,24 + ii_lset_dx \1,25 + ii_lset_dx \1,26 + ii_lset_dx \1,27 +// func.b d16(ax),dx + ii_lset_dx \1,28 + ii_lset_dx \1,29 + ii_lset_dx \1,2a + ii_lset_dx \1,2b + ii_lset_dx \1,2c + ii_lset_dx \1,2d + ii_lset_dx \1,2e + ii_lset_dx \1,2f +// func.b dd8(ax,dy),dx + ii_lset_dx \1,30 + ii_lset_dx \1,31 + ii_lset_dx \1,32 + ii_lset_dx \1,33 + ii_lset_dx \1,34 + ii_lset_dx \1,35 + ii_lset_dx \1,36 + ii_lset_dx \1,37 +// func.b xxx.w,dx + ii_lset_dx \1,38 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b xxx.l,dx + ii_lset_dx \1,39 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b d16(pc),dx + ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b d8(pc,dy),dx + ii_lset_dxg \1,3b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.b #im,dx + ii_lset_dxg \1,3c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// word +/******************************************************/ +// func.w dy,dx + ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,41 + ii_lset_dx \1,42 + ii_lset_dx \1,43 + ii_lset_dx \1,44 + ii_lset_dx \1,45 + ii_lset_dx \1,46 + ii_lset_dx \1,47 +// func.w ax,dx + ii_lset_dx \1,48 + ii_lset_dx \1,49 + ii_lset_dx \1,4a + ii_lset_dx \1,4b + ii_lset_dx \1,4c + ii_lset_dx \1,4d + ii_lset_dx \1,4e + ii_lset_dx \1,4f +// func.w (ax),dx + ii_lset_dx \1,50 + ii_lset_dx \1,51 + ii_lset_dx \1,52 + ii_lset_dx \1,53 + ii_lset_dx \1,54 + ii_lset_dx \1,55 + ii_lset_dx \1,56 + ii_lset_dx \1,57 +// func.w (ax)+,dx + ii_lset_dx \1,58 + ii_lset_dx \1,59 + ii_lset_dx \1,5a + ii_lset_dx \1,5b + ii_lset_dx \1,5c + ii_lset_dx \1,5d + ii_lset_dx \1,5e + ii_lset_dx \1,5f +// func.w -(ax),dx + ii_lset_dx \1,60 + ii_lset_dx \1,61 + ii_lset_dx \1,62 + ii_lset_dx \1,63 + ii_lset_dx \1,64 + ii_lset_dx \1,65 + ii_lset_dx \1,66 + ii_lset_dx \1,67 +// func.w d16(ax),dx + ii_lset_dx \1,68 + ii_lset_dx \1,69 + ii_lset_dx \1,6a + ii_lset_dx \1,6b + ii_lset_dx \1,6c + ii_lset_dx \1,6d + ii_lset_dx \1,6e + ii_lset_dx \1,6f +// func.w d8(ax,dy),dx + ii_lset_dx \1,70 + ii_lset_dx \1,71 + ii_lset_dx \1,72 + ii_lset_dx \1,73 + ii_lset_dx \1,74 + ii_lset_dx \1,75 + ii_lset_dx \1,76 + ii_lset_dx \1,77 +// func.w xxx.w,dx + ii_lset_dx \1,78 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w xxx.l,dx + ii_lset_dx \1,79 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w d16(pc),dx + ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w d8(pc,dy),dx + ii_lset_dxg \1,7b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +// func.w #im,dx + ii_lset_dxg \1,7c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// long +/******************************************************/ +// func.l ax,dx -> -(ay),-(ax) + ii_lset_dxu \1,c8 + ii_lset_dxu \1,c9 + ii_lset_dxu \1,ca + ii_lset_dxu \1,cb + ii_lset_dxu \1,cc + ii_lset_dxu \1,cd + ii_lset_dxu \1,ce + ii_lset_dxu \1,cf +// func.w d8(ax,dy),dx + ii_lset_dx \1,b0 + ii_lset_dx \1,b1 + ii_lset_dx \1,b2 + ii_lset_dx \1,b3 + ii_lset_dx \1,b4 + ii_lset_dx \1,b5 + ii_lset_dx \1,b6 + ii_lset_dx \1,b7 +// func.l d8(pc,dy),dx + ii_lset_dxg \1,bb // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c +/******************************************************/ +// adress register +/******************************************************/ +//func.w dy,ax + ii_lset_dxg \1,c0 + ii_lset_dxg \1,c1 + ii_lset_dxg \1,c2 + ii_lset_dxg \1,c3 + ii_lset_dxg \1,c4 + ii_lset_dxg \1,c5 + ii_lset_dxg \1,c6 + ii_lset_dxg \1,c7 +//func.w ay,ax + ii_lset_dxg \1,c8 + ii_lset_dxg \1,c9 + ii_lset_dxg \1,ca + ii_lset_dxg \1,cb + ii_lset_dxg \1,cc + ii_lset_dxg \1,cd + ii_lset_dxg \1,ce + ii_lset_dxg \1,cf +//func.w (ay),ax + ii_lset_dxg \1,d0 + ii_lset_dxg \1,d1 + ii_lset_dxg \1,d2 + ii_lset_dxg \1,d3 + ii_lset_dxg \1,d4 + ii_lset_dxg \1,d5 + ii_lset_dxg \1,d6 + ii_lset_dxg \1,d7 +//func.w (ay)+,ax + ii_lset_dxg \1,d8 + ii_lset_dxg \1,d9 + ii_lset_dxg \1,da + ii_lset_dxg \1,db + ii_lset_dxg \1,dc + ii_lset_dxg \1,dd + ii_lset_dxg \1,de + ii_lset_dxg \1,df +//func.w -(ay),ax + ii_lset_dxg \1,e0 + ii_lset_dxg \1,e1 + ii_lset_dxg \1,e2 + ii_lset_dxg \1,e3 + ii_lset_dxg \1,e4 + ii_lset_dxg \1,e5 + ii_lset_dxg \1,e6 + ii_lset_dxg \1,e7 +//func.w d16(ay),ax + ii_lset_dxg \1,e8 + ii_lset_dxg \1,e9 + ii_lset_dxg \1,ea + ii_lset_dxg \1,eb + ii_lset_dxg \1,ec + ii_lset_dxg \1,ed + ii_lset_dxg \1,ee + ii_lset_dxg \1,ef +//func.w d8(ay,dy),ax + ii_lset_dxg \1,f0 + ii_lset_dxg \1,f1 + ii_lset_dxg \1,f2 + ii_lset_dxg \1,f3 + ii_lset_dxg \1,f4 + ii_lset_dxg \1,f5 + ii_lset_dxg \1,f6 + ii_lset_dxg \1,f7 +// func.w xxx.w,ax + ii_lset_dxg \1,f8 +// func.w xxx.l,ax + ii_lset_dxg \1,f9 +// func.w d16(pc),ax + ii_lset_dxg \1,fa +// func.w d8(pc,dy),ax + ii_lset_dxg \1,fb +// func.w #im,ax + ii_lset_dxg \1,fc +//-------------------------------------------------------------------- +// ende + .endm; +/*****************************************************************************************/ +ii_func:.macro +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.b ds,dx +//-------------------------------------------------------------------- + funcbeadx \1,00,\2dd,d0_off+3(a7) + funcbeadx \1,01,\2dd,d1_off+3(a7) + funcbeadx \1,02,\2dd,d2 + funcbeadx \1,03,\2dd,d3 + funcbeadx \1,04,\2dd,d4 + funcbeadx \1,05,\2dd,d5 + funcbeadx \1,06,\2dd,d6 + funcbeadx \1,07,\2dd,d7 +//-------------------------------------------------------------------- +// func.b (ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,10,\2dda,a0_off(a7) + funcbeadx \1,11,\2dda,a1_off(a7) + funcbeadx \1,12,\2dd,(a2) + funcbeadx \1,13,\2dd,(a3) + funcbeadx \1,14,\2dd,(a4) + funcbeadx \1,15,\2dd,(a5) + funcbeadx \1,16,\2dd,(a6) + funcbeadx \1,17,\2dda,usp +//-------------------------------------------------------------------- +// func.b (ax)+,dx +//-------------------------------------------------------------------- + funcbeadx \1,18,\2ddai,a0_off(a7) + funcbeadx \1,19,\2ddai,a1_off(a7) + funcbeadx \1,1a,\2dd,(a2)+ + funcbeadx \1,1b,\2dd,(a3)+ + funcbeadx \1,1c,\2dd,(a4)+ + funcbeadx \1,1d,\2dd,(a5)+ + funcbeadx \1,1e,\2dd,(a6)+ + funcbeadx \1,1f,\2ddai,usp +//-------------------------------------------------------------------- +// func.b -(ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,20,\2ddad,a0_off(a7) + funcbeadx \1,21,\2ddad,a1_off(a7) + funcbeadx \1,22,\2dd,-(a2) + funcbeadx \1,23,\2dd,-(a3) + funcbeadx \1,24,\2dd,-(a4) + funcbeadx \1,25,\2dd,-(a5) + funcbeadx \1,26,\2dd,-(a6) + funcbeadx \1,27,\2ddad,usp +//-------------------------------------------------------------------- +// func.b d16(ax),dx +//-------------------------------------------------------------------- + funcbeadx \1,28,\2d16ad,a0_off(a7) + funcbeadx \1,29,\2d16ad,a1_off(a7) + funcbeadx \1,2a,\2d16ad,a2 + funcbeadx \1,2b,\2d16ad,a3 + funcbeadx \1,2c,\2d16ad,a4 + funcbeadx \1,2d,\2d16ad,a5 + funcbeadx \1,2e,\2d16ad,a6 + funcbeadx \1,2f,\2d16ad,usp +//-------------------------------------------------------------------- +// func.b d8(ax,dy),dx +//-------------------------------------------------------------------- + funcbeadx \1,30,\2d8ad,a0_off(a7) + funcbeadx \1,31,\2d8ad,a1_off(a7) + funcbeadx \1,32,\2d8ad,a2 + funcbeadx \1,33,\2d8ad,a3 + funcbeadx \1,34,\2d8ad,a4 + funcbeadx \1,35,\2d8ad,a5 + funcbeadx \1,36,\2d8ad,a6 + funcbeadx \1,37,\2d8ad,usp +//-------------------------------------------------------------------- +// func.b xxx.w,dx +//-------------------------------------------------------------------- + funcbeadx \1,38,\2xwd,(a0)+ +//-------------------------------------------------------------------- +// func.b xxx.w,dx +//-------------------------------------------------------------------- + funcbeadx \1,39,\2xld,(a0)+ +//-------------------------------------------------------------------- +// func.b d16(pc),dx +//-------------------------------------------------------------------- + funcbeadx \1,3a,\2d16pcd,(a0)+ +//-------------------------------------------------------------------- +// func.b d8(pc,dy),dx +//-------------------------------------------------------------------- + funcbeadx \1,3b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.b #im,dx +//-------------------------------------------------------------------- + funcbeadx \1,3c,\2bir_macro,(a0)+ +//-------------------------------------------------------------------- +// func.b dy,ea +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.b dx,dd -> addx subx etc. src und dest vertauscht! +//-------------------------------------------------------------------- + funcbdxea \1,00,\2dx,d0_off+3(a7) + funcbdxea \1,01,\2dx,d1_off+3(a7) + funcbdxea \1,02,\2dx,d2 + funcbdxea \1,03,\2dx,d3 + funcbdxea \1,04,\2dx,d4 + funcbdxea \1,05,\2dx,d5 + funcbdxea \1,06,\2dx,d6 + funcbdxea \1,07,\2dx,d7 +//-------------------------------------------------------------------- +// func.b -(ax),-(ay) addx subx etc. src und dest vertauscht! +//-------------------------------------------------------------------- + funcaxay \1,08,\2dax,a0_off(a7),b + funcaxay \1,09,\2dax,a1_off(a7).b + funcaxay \1,0a,\2dax,a2,b + funcaxay \1,0b,\2dax,a3,b + funcaxay \1,0c,\2dax,a4,b + funcaxay \1,0d,\2dax,a5,b + funcaxay \1,0e,\2dax,a6,b + funcaxay \1,0f,\2dax,usp,b +//-------------------------------------------------------------------- +// func.b dy,(ax) +//-------------------------------------------------------------------- + funcbdxea \1,10,\2eda,a0_off(a7) + funcbdxea \1,11,\2eda,a1_off(a7) + funcbdxea \1,12,\2dd,(a2) + funcbdxea \1,13,\2dd,(a3) + funcbdxea \1,14,\2dd,(a4) + funcbdxea \1,15,\2dd,(a5) + funcbdxea \1,16,\2dd,(a6) + funcbdxea \1,17,\2eda,usp +//-------------------------------------------------------------------- +// func.b dy,(ax)+ +//-------------------------------------------------------------------- + funcbdxea \1,18,\2edai,a0_off(a7) + funcbdxea \1,19,\2edai,a1_off(a7) + funcbdxea \1,1a,\2edaid,(a2) + funcbdxea \1,1b,\2edaid,(a3) + funcbdxea \1,1c,\2edaid,(a4) + funcbdxea \1,1d,\2edaid,(a5) + funcbdxea \1,1e,\2edaid,(a6) + funcbdxea \1,1f,\2edai,usp +//-------------------------------------------------------------------- +// func.b dy,-(ax) +//-------------------------------------------------------------------- + funcbdxea \1,20,\2edad,a0_off(a7) + funcbdxea \1,21,\2edad,a1_off(a7) + funcbdxea \1,22,\2edadd,(a2) + funcbdxea \1,23,\2edadd,(a3) + funcbdxea \1,24,\2edadd,(a4) + funcbdxea \1,25,\2edadd,(a5) + funcbdxea \1,26,\2edadd,(a6) + funcbdxea \1,27,\2edad,usp +//-------------------------------------------------------------------- +// func.b dy,d16(ax) +//-------------------------------------------------------------------- + funcbdxea \1,28,\2e16ad,a0_off(a7) + funcbdxea \1,29,\2e16ad,a1_off(a7) + funcbdxea \1,2a,\2e16ad,a2 + funcbdxea \1,2b,\2e16ad,a3 + funcbdxea \1,2c,\2e16ad,a4 + funcbdxea \1,2d,\2e16ad,a5 + funcbdxea \1,2e,\2e16ad,a6 + funcbdxea \1,2f,\2e16ad,usp +//-------------------------------------------------------------------- +// func.b dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcbdxea \1,30,\2e8ad,a0_off(a7) + funcbdxea \1,31,\2e8ad,a1_off(a7) + funcbdxea \1,32,\2e8ad,a2 + funcbdxea \1,33,\2e8ad,a3 + funcbdxea \1,34,\2e8ad,a4 + funcbdxea \1,35,\2e8ad,a5 + funcbdxea \1,36,\2e8ad,a6 + funcbdxea \1,37,\2e8ad,usp +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,38,\2xwe,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,39,\2xld,(a0)+ +/*****************************************************************************************/ +// word +/*****************************************************************************************/ +// func.w ds,dx +//-------------------------------------------------------------------- + funcweadx \1,40,\2dd,d0_off+2(a7) + funcweadx \1,41,\2dd,d1_off+2(a7) + funcweadx \1,42,\2dd,d2 + funcweadx \1,43,\2dd,d3 + funcweadx \1,44,\2dd,d4 + funcweadx \1,45,\2dd,d5 + funcweadx \1,46,\2dd,d6 + funcweadx \1,47,\2dd,d7 +//-------------------------------------------------------------------- +// func.w ax,dx +//-------------------------------------------------------------------- + funcweadx \1,48,\2dd,a0_off+2(a7) + funcweadx \1,49,\2dd,a1_off+2(a7) + funcweadx \1,4a,\2dd,a2 + funcweadx \1,4b,\2dd,a3 + funcweadx \1,4c,\2dd,a4 + funcweadx \1,4d,\2dd,a5 + funcweadx \1,4e,\2dd,a6 + funcweadx \1,4f,\2ddd,usp +//-------------------------------------------------------------------- +// func.w (ax),dx +//-------------------------------------------------------------------- + funcweadx \1,50,\2dda,a0_off(a7) + funcweadx \1,51,\2dda,a1_off(a7) + funcweadx \1,52,\2dd,(a2) + funcweadx \1,53,\2dd,(a3) + funcweadx \1,54,\2dd,(a4) + funcweadx \1,55,\2dd,(a5) + funcweadx \1,56,\2dd,(a6) + funcweadx \1,57,\2dda,usp +//-------------------------------------------------------------------- +// func.w (ax)+,dx +//-------------------------------------------------------------------- + funcweadx \1,58,\2ddai,a0_off(a7) + funcweadx \1,59,\2ddai,a1_off(a7) + funcweadx \1,5a,\2dd,(a2)+ + funcweadx \1,5b,\2dd,(a3)+ + funcweadx \1,5c,\2dd,(a4)+ + funcweadx \1,5d,\2dd,(a5)+ + funcweadx \1,5e,\2dd,(a6)+ + funcweadx \1,5f,\2ddai,usp +//-------------------------------------------------------------------- +// func.w -(ax),dx +//-------------------------------------------------------------------- + funcweadx \1,60,\2ddad,a0_off(a7) + funcweadx \1,61,\2ddad,a1_off(a7) + funcweadx \1,62,\2dd,-(a2) + funcweadx \1,63,\2dd,-(a3) + funcweadx \1,64,\2dd,-(a4) + funcweadx \1,65,\2dd,-(a5) + funcweadx \1,66,\2dd,-(a6) + funcweadx \1,67,\2ddad,usp +//-------------------------------------------------------------------- +// func.w d16(ax),dx +//-------------------------------------------------------------------- + funcweadx \1,68,\2d16ad,a0_off(a7) + funcweadx \1,69,\2d16ad,a1_off(a7) + funcweadx \1,6a,\2d16ad,a2 + funcweadx \1,6b,\2d16ad,a3 + funcweadx \1,6c,\2d16ad,a4 + funcweadx \1,6d,\2d16ad,a5 + funcweadx \1,6e,\2d16ad,a6 + funcweadx \1,6f,\2d16ad,usp +//-------------------------------------------------------------------- +// func.w d8(ax,dy),dx +//-------------------------------------------------------------------- + funcweadx \1,70,\2d8ad,a0_off(a7) + funcweadx \1,71,\2d8ad,a1_off(a7) + funcweadx \1,72,\2d8ad,a2 + funcweadx \1,73,\2d8ad,a3 + funcweadx \1,74,\2d8ad,a4 + funcweadx \1,75,\2d8ad,a5 + funcweadx \1,76,\2d8ad,a6 + funcweadx \1,77,\2d8ad,usp +//-------------------------------------------------------------------- +// func.w xxx.w,dx +//-------------------------------------------------------------------- + funcweadx \1,78,\2xwd,(a0)+ +//-------------------------------------------------------------------- +// func.w xxx.w,dx +//-------------------------------------------------------------------- + funcweadx \1,79,\2xld,(a0)+ +//-------------------------------------------------------------------- +// func.w d16(pc),dx +//-------------------------------------------------------------------- + funcweadx \1,7a,\2d16pcd,(a0)+ +//-------------------------------------------------------------------- +// func.w d8(pc,dy),dx +//-------------------------------------------------------------------- + funcweadx \1,7b,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.w #im,dx +//-------------------------------------------------------------------- + funcweadx \1,7c,\2dd,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,ea +//-------------------------------------------------------------------- +///-------------------------------------------------------------------- +// func.w dx,dd -> addx subx etc. +//-------------------------------------------------------------------- +.ifnc \2,and //platz für exg + funcwdxea \1,40,\2dx,d0_off+2(a7) + funcwdxea \1,41,\2dx,d1_off+2(a7) + funcwdxea \1,42,\2dx,d2 + funcwdxea \1,43,\2dx,d3 + funcwdxea \1,44,\2dx,d4 + funcwdxea \1,45,\2dx,d5 + funcwdxea \1,46,\2dx,d6 + funcwdxea \1,47,\2dx,d7 +//-------------------------------------------------------------------- +// func.w -(ax),-(ay) -> addx,subx +//-------------------------------------------------------------------- + funcaxay \1,48,\2dax,a0_off(a7),w + funcaxay \1,49,\2dax,a1_off(a7).w + funcaxay \1,4a,\2dax,a2,w + funcaxay \1,4b,\2dax,a3,w + funcaxay \1,4c,\2dax,a4,w + funcaxay \1,4d,\2dax,a5,w + funcaxay \1,4e,\2dax,a6,w + funcaxay \1,4f,\2dax,usp,w +.endif +//-------------------------------------------------------------------- +// func.w dy,(ax) +//-------------------------------------------------------------------- + funcwdxea \1,50,\2eda,a0_off(a7) + funcwdxea \1,51,\2eda,a1_off(a7) + funcwdxea \1,52,\2dd,(a2) + funcwdxea \1,53,\2dd,(a3) + funcwdxea \1,54,\2dd,(a4) + funcwdxea \1,55,\2dd,(a5) + funcwdxea \1,56,\2dd,(a6) + funcwdxea \1,57,\2eda,usp +//-------------------------------------------------------------------- +// func.w dy,(ax)+ +//-------------------------------------------------------------------- + funcwdxea \1,58,\2edai,a0_off(a7) + funcwdxea \1,59,\2edai,a1_off(a7) + funcwdxea \1,5a,\2edaid,(a2) + funcwdxea \1,5b,\2edaid,(a3) + funcwdxea \1,5c,\2edaid,(a4) + funcwdxea \1,5d,\2edaid,(a5) + funcwdxea \1,5e,\2edaid,(a6) + funcwdxea \1,5f,\2edai,usp +//-------------------------------------------------------------------- +// func.w dy,-(ax) +//-------------------------------------------------------------------- + funcwdxea \1,60,\2edad,a0_off(a7) + funcwdxea \1,61,\2edad,a1_off(a7) + funcwdxea \1,62,\2edadd,(a2) + funcwdxea \1,63,\2edadd,(a3) + funcwdxea \1,64,\2edadd,(a4) + funcwdxea \1,65,\2edadd,(a5) + funcwdxea \1,66,\2edadd,(a6) + funcwdxea \1,67,\2edad,usp +//-------------------------------------------------------------------- +// func.w dy,d16(ax) +//-------------------------------------------------------------------- + funcwdxea \1,68,\2e16ad,a0_off(a7) + funcwdxea \1,69,\2e16ad,a1_off(a7) + funcwdxea \1,6a,\2e16ad,a2 + funcwdxea \1,6b,\2e16ad,a3 + funcwdxea \1,6c,\2e16ad,a4 + funcwdxea \1,6d,\2e16ad,a5 + funcwdxea \1,6e,\2e16ad,a6 + funcwdxea \1,6f,\2e16ad,usp +//-------------------------------------------------------------------- +// func.w dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcwdxea \1,70,\2e8ad,a0_off(a7) + funcwdxea \1,71,\2e8ad,a1_off(a7) + funcwdxea \1,72,\2e8ad,a2 + funcwdxea \1,73,\2e8ad,a3 + funcwdxea \1,74,\2e8ad,a4 + funcwdxea \1,75,\2e8ad,a5 + funcwdxea \1,76,\2e8ad,a6 + funcwdxea \1,77,\2e8ad,usp +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,78,\2xwe,(a0)+ +//-------------------------------------------------------------------- +// func.w dy,xxx.w +//-------------------------------------------------------------------- + funcwdxea \1,79,\2xld,(a0)+ +/*****************************************************************************************/ +// long +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// func.l -(ax),-(ay) +//-------------------------------------------------------------------- + funcaxay \1,c8,\2dax,a0_off(a7),l + funcaxay \1,c9,\2dax,a1_off(a7).l + funcaxay \1,ca,\2dax,a2,l + funcaxay \1,cb,\2dax,a3,l + funcaxay \1,cc,\2dax,a4,l + funcaxay \1,cd,\2dax,a5,l + funcaxay \1,ce,\2dax,a6,l + funcaxay \1,cf,\2dax,usp,l +//-------------------------------------------------------------------- +// func.l d8(ax,dy),dx +//-------------------------------------------------------------------- + funcleadx \1,b0,\2d8ad,a0_off(a7) + funcleadx \1,b1,\2d8ad,a1_off(a7) + funcleadx \1,b2,\2d8ad,a2 + funcleadx \1,b3,\2d8ad,a3 + funcleadx \1,b4,\2d8ad,a4 + funcleadx \1,b5,\2d8ad,a5 + funcleadx \1,b6,\2d8ad,a6 + funcleadx \1,b7,\2d8ad,usp +//-------------------------------------------------------------------- +// func.l d8(pc,dy),dx +//-------------------------------------------------------------------- + funcleadx \1,bb,\2d8pcd,(a0)+ (a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.l dy,d8(ax,dy) +//-------------------------------------------------------------------- + funcldxea \1,b0,\2e8ad,a0_off(a7) + funcldxea \1,b1,\2e8ad,a1_off(a7) + funcldxea \1,b2,\2e8ad,a2 + funcldxea \1,b3,\2e8ad,a3 + funcldxea \1,b4,\2e8ad,a4 + funcldxea \1,b5,\2e8ad,a5 + funcldxea \1,b6,\2e8ad,a6 + funcldxea \1,b7,\2e8ad,usp +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// func.w ea,ax +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// func.w dx,ax +//-------------------------------------------------------------------- + funcweaax \1,c0,\2aw,d0 + funcweaax \1,c1,\2aw,d1 + funcweaax \1,c2,\2aw,d2 + funcweaax \1,c3,\2aw,d3 + funcweaax \1,c4,\2aw,d4 + funcweaax \1,c5,\2aw,d5 + funcweaax \1,c6,\2aw,d6 + funcweaax \1,c7,\2aw,d7 +//-------------------------------------------------------------------- +// func.w ay,ax +//-------------------------------------------------------------------- + funcweaax \1,c8,\2aw,a0 + funcweaax \1,c9,\2aw,a1 + funcweaax \1,ca,\2aw,a2 + funcweaax \1,cb,\2aw,a3 + funcweaax \1,cc,\2aw,a4 + funcweaax \1,cd,\2aw,a5 + funcweaax \1,ce,\2aw,a6 + funcweaax \1,cf,\2awu,a7 +//-------------------------------------------------------------------- +// func.w (ay),ax +//-------------------------------------------------------------------- + funcweaax \1,d0,\2aw,(a0) + funcweaax \1,d1,\2aw,(a1) + funcweaax \1,d2,\2aw,(a2) + funcweaax \1,d3,\2aw,(a3) + funcweaax \1,d4,\2aw,(a4) + funcweaax \1,d5,\2aw,(a5) + funcweaax \1,d6,\2aw,(a6) + funcweaax \1,d7,\2awu,(a7) +//-------------------------------------------------------------------- +// func.w (ay)+,ax +//-------------------------------------------------------------------- + funcweaax \1,d8,\2aw,(a0)+ + funcweaax \1,d9,\2aw,(a1)+ + funcweaax \1,da,\2aw,(a2)+ + funcweaax \1,db,\2aw,(a3)+ + funcweaax \1,dc,\2aw,(a4)+ + funcweaax \1,dd,\2aw,(a5)+ + funcweaax \1,de,\2aw,(a6)+ + funcweaax \1,df,\2awu,(a7)+ +//-------------------------------------------------------------------- +// func.w -(ay),ax +//-------------------------------------------------------------------- + funcweaax \1,e0,\2aw,-(a0) + funcweaax \1,e1,\2aw,-(a1) + funcweaax \1,e2,\2aw,-(a2) + funcweaax \1,e3,\2aw,-(a3) + funcweaax \1,e4,\2aw,-(a4) + funcweaax \1,e5,\2aw,-(a5) + funcweaax \1,e6,\2aw,-(a6) + funcweaax \1,e7,\2awu,-(a7) +//-------------------------------------------------------------------- +// func.w d16(ay),ax +//-------------------------------------------------------------------- + funcweaaxn \1,e8,\2awd16a,a0_off(a7) + funcweaaxn \1,e9,\2awd16a,a1_off(a7) + funcweaaxn \1,ea,\2awd16a,a2 + funcweaaxn \1,eb,\2awd16a,a3 + funcweaaxn \1,ec,\2awd16a,a4 + funcweaaxn \1,ed,\2awd16a,a5 + funcweaaxn \1,ee,\2awd16a,a6 + funcweaaxn \1,ef,\2awd16a,usp +//-------------------------------------------------------------------- +// func.w d8(ay,dy),ax +//-------------------------------------------------------------------- + funcweaaxn \1,f0,\2awd8a,a0_off(a7) + funcweaaxn \1,f1,\2awd8a,a1_off(a7) + funcweaaxn \1,f2,\2awd8a,a2 + funcweaaxn \1,f3,\2awd8a,a3 + funcweaaxn \1,f4,\2awd8a,a4 + funcweaaxn \1,f5,\2awd8a,a5 + funcweaaxn \1,f6,\2awd8a,a6 + funcweaaxn \1,f7,\2awd8a,usp +//-------------------------------------------------------------------- +// func.w xxx.w,ax +//-------------------------------------------------------------------- + funcweaaxn \1,f8,\2awxwax,(a0)+ +//-------------------------------------------------------------------- +// func.w xxxlw,ax +//-------------------------------------------------------------------- + funcweaaxn \1,f9,\2awxlax,(a0)+ +//-------------------------------------------------------------------- +// func.w d16(pc),ax +//-------------------------------------------------------------------- + funcweaaxn \1,fa,\2awd16pcax,(a0)+ +//-------------------------------------------------------------------- +// func.w d8(pc,dy),ax +//-------------------------------------------------------------------- + funcweaaxn \1,fb,\2awd8pcax,(a0)+ //(a0 wird nicht verwendet) +//-------------------------------------------------------------------- +// func.w #im,ax +//-------------------------------------------------------------------- + funcweaaxn \1,fc,\2awim,(a0)+ +//-------------------------------------------------------------------- +// ende + .endm; +//-------------------------------------------------------------------- +// byt +funcbeadx:.macro // function byt: im,dx +ii_0x\10\2: + \3 \4,d0_off+3(a7),b +ii_0x\12\2: + \3 \4,d1_off+3(a7),b +ii_0x\14\2: + \3 \4,d2,b +ii_0x\16\2: + \3 \4,d3,b +ii_0x\18\2: + \3 \4,d4,b +ii_0x\1a\2: + \3 \4,d5,b +ii_0x\1c\2: + \3 \4,d6,b +ii_0x\1e\2: + \3 \4,d7,b + .endm; +funcbdxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off+3(a7),\4,b +ii_0x\13\2: + \3 d1_off+3(a7),\4,b +ii_0x\15\2: + \3 d2,\4,b +ii_0x\17\2: + \3 d3,\4,b +ii_0x\19\2: + \3 d4,\4,b +ii_0x\1b\2: + \3 d5,\4,b +ii_0x\1d\2: + \3 d6,\4,b +ii_0x\1f\2: + \3 d7,\4,b + .endm; +//-------------------------------------------------------------------- +// word +funcweadx:.macro // dx function(\3) ea(\4) -> dx +ii_0x\10\2: + \3 \4,d0_off+2(a7),w +ii_0x\12\2: + \3 \4,d1_off+2(a7),w +ii_0x\14\2: + \3 \4,d2,w +ii_0x\16\2: + \3 \4,d3,w +ii_0x\18\2: + \3 \4,d4,w +ii_0x\1a\2: + \3 \4,d5,w +ii_0x\1c\2: + \3 \4,d6,w +ii_0x\1e\2: + \3 \4,d7,w + .endm; +funcwdxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off+2(a7),\4,w +ii_0x\13\2: + \3 d1_off+2(a7),\4,w +ii_0x\15\2: + \3 d2,\4,w +ii_0x\17\2: + \3 d3,\4,w +ii_0x\19\2: + \3 d4,\4,w +ii_0x\1b\2: + \3 d5,\4,w +ii_0x\1d\2: + \3 d6,\4,w +ii_0x\1f\2: + \3 d7,\4,w + .endm; +//-------------------------------------------------------------------- +// long +funcleadx:.macro // dx function(\3) ea(\4) -> dx +ii_0x\10\2: + \3 \4,d0_off(a7),w +ii_0x\12\2: + \3 \4,d1_off(a7),w +ii_0x\14\2: + \3 \4,d2,w +ii_0x\16\2: + \3 \4,d3,w +ii_0x\18\2: + \3 \4,d4,w +ii_0x\1a\2: + \3 \4,d5,w +ii_0x\1c\2: + \3 \4,d6,w +ii_0x\1e\2: + \3 \4,d7,w + .endm; +funcldxea:.macro // ea(\4) function(\3) dx -> ea +ii_0x\11\2: + \3 d0_off(a7),\4,w +ii_0x\13\2: + \3 d1_off(a7),\4,w +ii_0x\15\2: + \3 d2,\4,w +ii_0x\17\2: + \3 d3,\4,w +ii_0x\19\2: + \3 d4,\4,w +ii_0x\1b\2: + \3 d5,\4,w +ii_0x\1d\2: + \3 d6,\4,w +ii_0x\1f\2: + \3 d7,\4,w + .endm; +//-------------------------------------------------------------- +// address +funcweaax:.macro // ax function(\3) ea(\4)(ext long!) -> ax +ii_0x\10\2: + \3 \4,a0 +ii_0x\12\2: + \3 \4,a1 +ii_0x\14\2: + \3 \4,a2 +ii_0x\16\2: + \3 \4,a3 +ii_0x\18\2: + \3 \4,a4 +ii_0x\1a\2: + \3 \4,a5 +ii_0x\1c\2: + \3 \4,a6 +ii_0x\1e\2: + \3a7 \4,a7 // "a7" beachten wegen usp + .endm; +funcweaaxn:.macro // ax function(\3) ea(\4)(ext long!) -> ax +ii_0x\10\2: + \3 \4,a0_off(a7) +ii_0x\12\2: + \3 \4,a1_off(a7) +ii_0x\14\2: + \3 \4,a2 +ii_0x\16\2: + \3 \4,a3 +ii_0x\18\2: + \3 \4,a4 +ii_0x\1a\2: + \3 \4,a5 +ii_0x\1c\2: + \3 \4,a6 +ii_0x\1e\2: + \3 \4,usp + .endm; +//-------------------------------------------------------------- +// byt, word, long +//-------------------------------------------------------------- +funcaxay:.macro // ea(\4) function(\3) dx -> ea,\5 = size +ii_0x\11\2: + \3 a0_off(a7),\4,\5 +ii_0x\13\2: + \3 a1_off(a7),\4,\5 +ii_0x\15\2: + \3 a2,\4,\5 +ii_0x\17\2: + \3 a3,\4,\5 +ii_0x\19\2: + \3 a4,\4,\5 +ii_0x\1b\2: + \3 a5,\4,\5 +ii_0x\1d\2: + \3 a6,\4,\5 +ii_0x\1f\2: + \3 usp,\4,\5 + .endm; diff --git a/BaS_gcc/sources/ii_jmp.h b/BaS_gcc/sources/ii_jmp.h new file mode 100644 index 0000000..1896118 --- /dev/null +++ b/BaS_gcc/sources/ii_jmp.h @@ -0,0 +1,59 @@ +//-------------------------------------------------------------------- +// extension word format missing +//-------------------------------------------------------------------- +ii_\1_func:.macro +ii_0x\20: +#ifdef halten_\1 + halt +#endif + move.l a0_off(a7),a1 + \1_macro +ii_0x\21: +#ifdef halten_\1 + halt +#endif + move.l a1_off(a7),a1 + \1_macro +ii_0x\22: +#ifdef halten_\1 + halt +#endif + move.l a2,a1 + \1_macro +ii_0x\23: +#ifdef halten_\1 + halt +#endif + move.l a3,a1 + \1_macro +ii_0x\24: +#ifdef halten_\1 + halt +#endif + move.l a4,a1 + \1_macro +ii_0x\25: +#ifdef halten_\1 + halt +#endif + move.l a5,a1 + \1_macro +ii_0x\26: +#ifdef halten_\1 + halt +#endif + move.l a6,a1 + \1_macro +ii_0x\27: +#ifdef halten_\1 + halt +#endif + move.l usp,a1 + \1_macro +ii_0x\2b: +#ifdef halten_\1 + halt +#endif + move.l a0,a1 + \1_macro +.endm diff --git a/BaS_gcc/sources/ii_lea.h b/BaS_gcc/sources/ii_lea.h new file mode 100644 index 0000000..7a422a7 --- /dev/null +++ b/BaS_gcc/sources/ii_lea.h @@ -0,0 +1,105 @@ +//------------------------------------------------------------------- +// lea +//------------------------------------------------------------------- +.text +ii_lea_lset:.macro + ii_lset_dxu 4,f0 // lea d8(a0,dy.w),a0-a7 + ii_lset_dxu 4,f1 // lea d8(a1,dy.w),a0-a7 + ii_lset_dxu 4,f2 // lea d8(a2,dy.w),a0-a7 + ii_lset_dxu 4,f3 // lea d8(a3,dy.w),a0-a7 + ii_lset_dxu 4,f4 // lea d8(a4,dy.w),a0-a7 + ii_lset_dxu 4,f5 // lea d8(a5,dy.w),a0-a7 + ii_lset_dxu 4,f6 // lea d8(a6,dy.w),a0-a7 + ii_lset_dxu 4,f7 // lea d8(a7,dy.w),a0-a7 + ii_lset_dxu 4,fb // lea d8(pc,dy.w),a0-a7 +.endm + +//--------------------------------------------------------------------------------------------- +// function +//--------------------------------------------------------------------------------------------- +ii_lea_sub:.macro +ii_0x4\1\2: +#ifdef halten_lea + halt +#endif + move.l \4,a1 + jsr ewf + move.l a1,\3 + ii_end +.endm +ii_lea_func:.macro +//lea d8(ax,dy.w),a0-a7 + ii_lea_sub 1,f0,a0_off(a7),a0_off(a7) + ii_lea_sub 1,f1,a0_off(a7),a1_off(a7) + ii_lea_sub 1,f2,a0_off(a7),a2 + ii_lea_sub 1,f3,a0_off(a7),a3 + ii_lea_sub 1,f4,a0_off(a7),a4 + ii_lea_sub 1,f5,a0_off(a7),a5 + ii_lea_sub 1,f6,a0_off(a7),a6 + ii_lea_sub 1,f7,a0_off(a7),usp + ii_lea_sub 3,f0,a1_off(a7),a0_off(a7) + ii_lea_sub 3,f1,a1_off(a7),a1_off(a7) + ii_lea_sub 3,f2,a1_off(a7),a2 + ii_lea_sub 3,f3,a1_off(a7),a3 + ii_lea_sub 3,f4,a1_off(a7),a4 + ii_lea_sub 3,f5,a1_off(a7),a5 + ii_lea_sub 3,f6,a1_off(a7),a6 + ii_lea_sub 3,f7,a1_off(a7),usp + ii_lea_sub 5,f0,a2,a0_off(a7) + ii_lea_sub 5,f1,a2,a1_off(a7) + ii_lea_sub 5,f2,a2,a2 + ii_lea_sub 5,f3,a2,a3 + ii_lea_sub 5,f4,a2,a4 + ii_lea_sub 5,f5,a2,a5 + ii_lea_sub 5,f6,a2,a6 + ii_lea_sub 5,f7,a2,usp + ii_lea_sub 7,f0,a3,a0_off(a7) + ii_lea_sub 7,f1,a3,a1_off(a7) + ii_lea_sub 7,f2,a3,a2 + ii_lea_sub 7,f3,a3,a3 + ii_lea_sub 7,f4,a3,a4 + ii_lea_sub 7,f5,a3,a5 + ii_lea_sub 7,f6,a3,a6 + ii_lea_sub 7,f7,a3,usp + ii_lea_sub 9,f0,a4,a0_off(a7) + ii_lea_sub 9,f1,a4,a1_off(a7) + ii_lea_sub 9,f2,a4,a2 + ii_lea_sub 9,f3,a4,a3 + ii_lea_sub 9,f4,a4,a4 + ii_lea_sub 9,f5,a4,a5 + ii_lea_sub 9,f6,a4,a6 + ii_lea_sub 9,f7,a4,usp + ii_lea_sub b,f0,a5,a0_off(a7) + ii_lea_sub b,f1,a5,a1_off(a7) + ii_lea_sub b,f2,a5,a2 + ii_lea_sub b,f3,a5,a3 + ii_lea_sub b,f4,a5,a4 + ii_lea_sub b,f5,a5,a5 + ii_lea_sub b,f6,a5,a6 + ii_lea_sub b,f7,a6,usp + ii_lea_sub d,f0,a6,a0_off(a7) + ii_lea_sub d,f1,a6,a1_off(a7) + ii_lea_sub d,f2,a6,a2 + ii_lea_sub d,f3,a6,a3 + ii_lea_sub d,f4,a6,a4 + ii_lea_sub d,f5,a6,a5 + ii_lea_sub d,f6,a6,a6 + ii_lea_sub d,f7,a6,usp + ii_lea_sub f,f0,usp,a0_off(a7) + ii_lea_sub f,f1,usp,a1_off(a7) + ii_lea_sub f,f2,usp,a2 + ii_lea_sub f,f3,usp,a3 + ii_lea_sub f,f4,usp,a4 + ii_lea_sub f,f5,usp,a5 + ii_lea_sub f,f6,usp,a6 + ii_lea_sub f,f7,usp,usp +// lea d8(pc,dy.w),az + ii_lea_sub 1,fb,a0_off(a7),a0 + ii_lea_sub 3,fb,a1_off(a7),a0 + ii_lea_sub 5,fb,a2,a0 + ii_lea_sub 7,fb,a3,a0 + ii_lea_sub 9,fb,a4,a0 + ii_lea_sub b,fb,a5,a0 + ii_lea_sub d,fb,a6,a0 + ii_lea_sub f,fb,usp,a0 +.endm \ No newline at end of file diff --git a/BaS_gcc/sources/ii_macro.h b/BaS_gcc/sources/ii_macro.h new file mode 100644 index 0000000..eca557e --- /dev/null +++ b/BaS_gcc/sources/ii_macro.h @@ -0,0 +1,144 @@ +/*******************************************************/ +// constanten +/*******************************************************/ +.extern ___RAMBAR1 +.extern _rt_cacr +.extern _rt_mod +.extern _rt_ssp +.extern _rt_usp +.extern _rt_vbr +.extern _d0_save +.extern _a7_save + +ii_ss = 16 +d0_off = 0 +d1_off = 4 +a0_off = 8 +a1_off = 12 +format_off = 16 +sr_off = 18 +ccr_off = 19 +pc_off = 20 + +#define table 0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle -> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle + +/*******************************************************/ +// allgemeine macros +/*******************************************************/ +ii_end: .macro + move.l a0,pc_off(a7) + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 + rte + .endm; + +set_cc0:.macro + move.w ccr,d0 + move.b d0,ccr_off(a7) + .endm; + +ii_esr: .macro // geht nicht!!?? + movem.l (a7),d0/d1/a0/a1 + lea ii_ss+8(a7),a7 // stack erhöhen + move.w d0,_d0_save // d0.w sicheren + move.w -6(a7),d0 // sr holen + move.w d0,sr // sr setzen + nop + move.w _d0_save,d0 // d0.w zurück + .endm; + +ii_end_mvm:.macro + move.l a0_off(a7),a0 + lea 16(a7),a7 + rte + .endm; + +ii_endj:.macro + movem.l (a7),d0/d1/a0/a1 // register zurück + lea ii_ss(a7),a7 // korr + rte // ende + .endm; + +set_nzvc:.macro // set ccr bits nzvc + move.w ccr,d1 + bclr #4,d1 + btst #4,ccr_off(a7) + beq snzvc2\@ + bset #4,d1 +snzvc2\@: + move.b d1,ccr_off(a7) + .endm; + +set_cc1:.macro + move.w ccr,d1 + move.b d1,ccr_off(a7) + .endm; + +set_cc_b:.macro + move.w ccr,d1 + btst #7,d0 // byt negativ? + beq set_cc_b2\@ + bset #3,d1 // make negativ +set_cc_b2\@: + move.b d1,ccr_off(a7) + .endm; + +set_cc_w:.macro + move.w ccr,d1 + btst #15,d0 // byt negativ? + beq set_cc_w2\@ + bset #3,d1 // make negativ +set_cc_w2\@: + move.b d1,ccr_off(a7) + .endm; + +get_pc: .macro + lea.l (a0),a1 + .endm; + +//-------------------------------------------------------------------- +ii_lset:.macro offs + lea table+\offs*4,a0 + move.l #ii_\offs,(a0) + .endm; +ii_lset_dx:.macro // 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 + ii_lset_dxg \1,\2 + ii_lset_dxu \1,\2 + .endm; +ii_lset_dxg:.macro // gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40 + lea table+0x\10\2*4,a0 + move.l #ii_0x\10\2,(a0) + lea 0x800(a0),a0 // 4 * 0x200 + move.l #ii_0x\12\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\14\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\16\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\18\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1a\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1c\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1e\2,(a0) + .endm; +ii_lset_dxu:.macro // ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40 + lea table+0x\11\2*4,a0 + move.l #ii_0x\11\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\13\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\15\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\17\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\19\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1b\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1d\2,(a0) + lea 0x800(a0),a0 + move.l #ii_0x\1f\2,(a0) + .endm; + diff --git a/BaS_gcc/sources/ii_move.h b/BaS_gcc/sources/ii_move.h new file mode 100644 index 0000000..4fb5832 --- /dev/null +++ b/BaS_gcc/sources/ii_move.h @@ -0,0 +1,1270 @@ +//------------------------------------------------------------------- +// move +//------------------------------------------------------------------- +.extern ewf + +.text +ii_move_lset:.macro +//------------------------------------------------------------------------- +// 0x1000 move.b +//------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 11,e +// move.x d16(ax),xxx.l + ii_lset_opeau 13,e +// move.x d16(pc),xxx.w + ii_lset 0x11fa +// move.x d16(pc),xxx.l + ii_lset 0x13fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 1,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 1,79 +// move.x #xx,d16(ax) + ii_lset_dxu 1,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x11f8 +// move.x xxx.l,xxx.w + ii_lset 0x11f9 +// move.x xxx.w,xxx.l + ii_lset 0x13f8 +// move.x xxx.l,xxx.l + ii_lset 0x13f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x11fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x13fc +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 11,8 + ii_lset_opeag 13,8 + ii_lset_opeag 15,8 + ii_lset_opeag 17,8 + ii_lset_opeag 19,8 + ii_lset_opeag 1b,8 + ii_lset_opeag 1d,8 + ii_lset_opeag 1f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 11,9 + ii_lset_opea 13,9 + ii_lset_opea 15,9 + ii_lset_opea 17,9 + ii_lset_opea 19,9 + ii_lset_opea 1b,9 + ii_lset_opea 1d,9 + ii_lset_opea 1f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 11,a + ii_lset_opeag 13,a + ii_lset_opeag 15,a + ii_lset_opeag 17,a + ii_lset_opeag 19,a + ii_lset_opeag 1b,a + ii_lset_opeag 1d,a + ii_lset_opeag 1f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) + ii_lset_opeag 17,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 17,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 17,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 10,3 + ii_lset_opeag 12,3 + ii_lset_opeag 14,3 + ii_lset_opeag 16,3 + ii_lset_opeag 18,3 + ii_lset_opeag 1a,3 + ii_lset_opeag 1c,3 + ii_lset_opeag 1e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 10,7 + ii_lset_opeag 12,7 + ii_lset_opeag 14,7 + ii_lset_opeag 16,7 + ii_lset_opeag 18,7 + ii_lset_opeag 1a,7 + ii_lset_opeag 1c,7 + ii_lset_opeag 1e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 10,b + ii_lset_opeag 12,b + ii_lset_opeag 14,b + ii_lset_opeag 16,b + ii_lset_opeag 18,b + ii_lset_opeag 1a,b + ii_lset_opeag 1c,b + ii_lset_opeag 1e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 10,f + ii_lset_opeag 12,f + ii_lset_opeag 14,f + ii_lset_opeag 16,f + ii_lset_opeag 18,f + ii_lset_opeag 1a,f + ii_lset_opeag 1c,f + ii_lset_opeag 1e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 11,3 + ii_lset_opeag 13,3 + ii_lset_opeag 15,3 + ii_lset_opeag 17,3 + ii_lset_opeag 19,3 + ii_lset_opeag 1b,3 + ii_lset_opeag 1d,3 + ii_lset_opeag 1f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 1,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 1,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 1,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 1,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 1,3b +//------------------------------------------------------------------------- +// 0x2000 move.l +//------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 21,e +// move.x d16(ax),xxx.l + ii_lset_opeau 23,e +// move.x d16(pc),xxx.w + ii_lset 0x21fa +// move.x d16(pc),xxx.l + ii_lset 0x23fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 2,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 2,79 +// move.x #xx,d16(ax) + ii_lset_dxu 2,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x21f8 +// move.x xxx.l,xxx.w + ii_lset 0x21f9 +// move.x xxx.w,xxx.l + ii_lset 0x23f8 +// move.x xxx.l,xxx.l + ii_lset 0x23f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x21fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x23fc +// move.x ea,d8(ax,dy) ------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 21,8 + ii_lset_opeag 23,8 + ii_lset_opeag 25,8 + ii_lset_opeag 27,8 + ii_lset_opeag 29,8 + ii_lset_opeag 2b,8 + ii_lset_opeag 2d,8 + ii_lset_opeag 2f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 21,9 + ii_lset_opea 23,9 + ii_lset_opea 25,9 + ii_lset_opea 27,9 + ii_lset_opea 29,9 + ii_lset_opea 2b,9 + ii_lset_opea 2d,9 + ii_lset_opea 2f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 21,a + ii_lset_opeag 23,a + ii_lset_opeag 25,a + ii_lset_opeag 27,a + ii_lset_opeag 29,a + ii_lset_opeag 2b,a + ii_lset_opeag 2d,a + ii_lset_opeag 2f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) +// move.x ax,d8(pc,dy) + ii_lset_opea 27,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 27,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 27,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 20,3 + ii_lset_opeag 22,3 + ii_lset_opeag 24,3 + ii_lset_opeag 26,3 + ii_lset_opeag 28,3 + ii_lset_opeag 2a,3 + ii_lset_opeag 2c,3 + ii_lset_opeag 2e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 20,7 + ii_lset_opeag 22,7 + ii_lset_opeag 24,7 + ii_lset_opeag 26,7 + ii_lset_opeag 28,7 + ii_lset_opeag 2a,7 + ii_lset_opeag 2c,7 + ii_lset_opeag 2e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 20,b + ii_lset_opeag 22,b + ii_lset_opeag 24,b + ii_lset_opeag 26,b + ii_lset_opeag 28,b + ii_lset_opeag 2a,b + ii_lset_opeag 2c,b + ii_lset_opeag 2e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 20,f + ii_lset_opeag 22,f + ii_lset_opeag 24,f + ii_lset_opeag 26,f + ii_lset_opeag 28,f + ii_lset_opeag 2a,f + ii_lset_opeag 2c,f + ii_lset_opeag 2e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 21,3 + ii_lset_opeag 23,3 + ii_lset_opeag 25,3 + ii_lset_opeag 27,3 + ii_lset_opeag 29,3 + ii_lset_opeag 2b,3 + ii_lset_opeag 2d,3 + ii_lset_opeag 2f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 2,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 2,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 2,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 2,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 2,3b +//------------------------------------------------------------------------- +// 0x3000 move.w +///------------------------------------------------------------------------- +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_lset_opeau 31,e +// move.x d16(ax),xxx.l + ii_lset_opeau 33,e +// move.x d16(pc),xxx.w + ii_lset 0x31fa +// move.x d16(pc),xxx.l + ii_lset 0x33fa +// move.x xxx.w,d16(ax) + ii_lset_dxu 3,78 +// move.x xxx.l,d16(ax) + ii_lset_dxu 3,79 +// move.x #xx,d16(ax) + ii_lset_dxu 3,7c +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_lset 0x31f8 +// move.x xxx.l,xxx.w + ii_lset 0x31f9 +// move.x xxx.w,xxx.l + ii_lset 0x33f8 +// move.x xxx.l,xxx.l + ii_lset 0x33f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_lset 0x31fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_lset 0x33fc +// move.x ea,d8(ax,dy) ------------------------------------------- +// move.x dx,d8(a0-a7,dy) + ii_lset_opeag 31,8 + ii_lset_opeag 33,8 + ii_lset_opeag 35,8 + ii_lset_opeag 37,8 + ii_lset_opeag 39,8 + ii_lset_opeag 3b,8 + ii_lset_opeag 3d,8 + ii_lset_opeag 3f,8 +// move.x (ax),d8(a0-a7,dy) +// move.x (ax)+,d8(a0-a7,dy) + ii_lset_opea 31,9 + ii_lset_opea 33,9 + ii_lset_opea 35,9 + ii_lset_opea 37,9 + ii_lset_opea 39,9 + ii_lset_opea 3b,9 + ii_lset_opea 3d,9 + ii_lset_opea 3f,9 +// move.x -(ax),d8(a0-a7,dy) + ii_lset_opeag 31,a + ii_lset_opeag 33,a + ii_lset_opeag 35,a + ii_lset_opeag 37,a + ii_lset_opeag 39,a + ii_lset_opeag 3b,a + ii_lset_opeag 3d,a + ii_lset_opeag 3f,a +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(pc,dy) +// move.x ax,d8(pc,dy) + ii_lset_opea 37,c +// move.x (ax),d8(pc,dy) +// move.x (ax)+,d8(pc,dy) + ii_lset_opea 37,d +// move.x -(ax),d8(pc,dy) + ii_lset_opeag 37,e +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax,dy),d0-d7 + ii_lset_opeag 30,3 + ii_lset_opeag 32,3 + ii_lset_opeag 34,3 + ii_lset_opeag 36,3 + ii_lset_opeag 38,3 + ii_lset_opeag 3a,3 + ii_lset_opeag 3c,3 + ii_lset_opeag 3e,3 +// move.x d8(ax,dy),a0-a7 + ii_lset_opeag 30,7 + ii_lset_opeag 32,7 + ii_lset_opeag 34,7 + ii_lset_opeag 36,7 + ii_lset_opeag 38,7 + ii_lset_opeag 3a,7 + ii_lset_opeag 3c,7 + ii_lset_opeag 3e,7 +// move.x d8(ax,dy),(a0)-(a7) + ii_lset_opeag 30,b + ii_lset_opeag 32,b + ii_lset_opeag 34,b + ii_lset_opeag 36,b + ii_lset_opeag 38,b + ii_lset_opeag 3a,b + ii_lset_opeag 3c,b + ii_lset_opeag 3e,b +// move.x d8(ax,dy),(a0)+-(a7)+ + ii_lset_opeag 30,f + ii_lset_opeag 32,f + ii_lset_opeag 34,f + ii_lset_opeag 36,f + ii_lset_opeag 38,f + ii_lset_opeag 3a,f + ii_lset_opeag 3c,f + ii_lset_opeag 3e,f +// move.x d8(ax,dy),-(a0) bis -(a7) + ii_lset_opeag 31,3 + ii_lset_opeag 33,3 + ii_lset_opeag 35,3 + ii_lset_opeag 37,3 + ii_lset_opeag 39,3 + ii_lset_opeag 3b,3 + ii_lset_opeag 3d,3 + ii_lset_opeag 3f,3 +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(pc,dy),d0-d7 + ii_lset_dxg 3,3b +// move.x d8(pc,dy),a0-a7 + ii_lset_dxg 3,7b +// move.x d8(pc,dy),(a0-a7) + ii_lset_dxg 3,bb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxg 3,fb +// move.x d8(pc,dy),(a0-a7)+ + ii_lset_dxu 3,3b +.endm +//--------------------------------------------------------------------------------------------- +// function +//--------------------------------------------------------------------------------------------- +ii_move_op:.macro +// move.x d16(ax),xxx.w 1=size 2=adress register + ii_move_d16ax_xxx 1e8,a0_off(a7),w + ii_move_d16ax_xxx 1e9,a1_off(a7),w + ii_move_d16ax_xxx 1ea,a2,w + ii_move_d16ax_xxx 1eb,a3,w + ii_move_d16ax_xxx 1ec,a4,w + ii_move_d16ax_xxx 1ed,a5,w + ii_move_d16ax_xxx 1ee,a6,w + ii_move_d16ax_xxx 1ef,usp,w +// move.x d16(ax),xxx.l + ii_move_d16ax_xxx 3e8,a0_off(a7),l + ii_move_d16ax_xxx 3e9,a1_off(a7),l + ii_move_d16ax_xxx 3ea,a2,l + ii_move_d16ax_xxx 3eb,a3,l + ii_move_d16ax_xxx 3ec,a4,l + ii_move_d16ax_xxx 3ed,a5,l + ii_move_d16ax_xxx 3ee,a6,l + ii_move_d16ax_xxx 3ef,usp,l +// move.x d16(pc),xxx.w + ii_move_d16ax_xxx 1fa,a0,w +// move.x d16(pc),xxx.l + ii_move_d16ax_xxx 3fa,a0,l +// move.x xxx.w,d16(ax) +// move.x xxx.l,d16(ax) +// move.x #xx,d16(ax) + ii_move_xxx_d16ax 1,a0_off(a7) + ii_move_xxx_d16ax 3,a1_off(a7) + ii_move_xxx_d16ax 5,a2 + ii_move_xxx_d16ax 7,a3 + ii_move_xxx_d16ax 9,a4 + ii_move_xxx_d16ax b,a5 + ii_move_xxx_d16ax d,a6 + ii_move_xxx_d16ax f,usp +// move.x xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code + ii_move_xxx_xxx b,w,w,11f8 + ii_move_xxx_xxx l,w,w,21f8 + ii_move_xxx_xxx w,w,w,31f8 +// move.x xxx.l,xxx.w + ii_move_xxx_xxx b,l,w,11f9 + ii_move_xxx_xxx l,l,w,21f9 + ii_move_xxx_xxx w,l,w,31f9 +// move.x xxx.w,xxx.l + ii_move_xxx_xxx b,w,l,13f8 + ii_move_xxx_xxx l,w,l,23f8 + ii_move_xxx_xxx w,w,l,33f8 +// move.x xxx.l,xxx.l + ii_move_xxx_xxx b,l,l,13f9 + ii_move_xxx_xxx l,l,l,23f9 + ii_move_xxx_xxx w,l,l,33f9 +// move.x #xx,xxx.w //1=size 2=size dest adr 3=code + ii_move_im_xxx b,w,11fc + ii_move_im_xxx l,w,21fc + ii_move_im_xxx w,w,31fc +// move.x #xx,xxx.l //1=size 2=size dest adr 3=code + ii_move_im_xxx b,l,13fc + ii_move_im_xxx l,l,23fc + ii_move_im_xxx w,l,33fc +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// move.x dx,d8(ax/pc,dy) + ii_move_dxxia d0_off(a7),80,id,d,c0 + ii_move_dxxia d1_off(a7),81,id,d,c1 + ii_move_dxxia d2,82,d,d,c2 + ii_move_dxxia d3,83,d,d,c3 + ii_move_dxxia d4,84,d,d,c4 + ii_move_dxxia d5,85,d,d,c5 + ii_move_dxxia d6,86,d,d,c6 + ii_move_dxxia d7,87,d,d,c7 +// move.x ax,d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),88,id,d,c8 + ii_move_dxxia a1_off(a7),89,id,d,c9 + ii_move_dxxia a2,8a,d,da,ca + ii_move_dxxia a3,8b,d,da,cb + ii_move_dxxia a4,8c,d,da,cc + ii_move_dxxia a5,8d,d,da,cd + ii_move_dxxia a6,8e,d,da,ce + ii_move_dxxia a7,8f,a7,da,cf +// move.x (ax),d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),90,ia,d,d0 + ii_move_dxxia a1_off(a7),91,ia,d,d1 + ii_move_dxxia (a2),92,d,d,d2 + ii_move_dxxia (a3),93,d,d,d3 + ii_move_dxxia (a4),94,d,d,d4 + ii_move_dxxia (a5),95,d,d,d5 + ii_move_dxxia (a6),96,d,d,d6 + ii_move_dxxia (a7),97,a7,d,d7 +// move.x (ax)+,d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),98,iap,d,d8 + ii_move_dxxia a1_off(a7),99,iap,d,d9 + ii_move_dxxia (a2)+,9a,d,d,da + ii_move_dxxia (a3)+,9b,d,d,db + ii_move_dxxia (a4)+,9c,d,d,dc + ii_move_dxxia (a5)+,9d,d,d,dd + ii_move_dxxia (a6)+,9e,d,d,de + ii_move_dxxia (a7)+,9f,a7,d,df +// move.x -(ax),d8(ax/pc,dy) + ii_move_dxxia a0_off(a7),a0,iam,d,e0 + ii_move_dxxia a1_off(a7),a1,iam,d,e1 + ii_move_dxxia -(a2),a2,d,d,e2 + ii_move_dxxia -(a3),a3,d,d,e3 + ii_move_dxxia -(a4),a4,d,d,e4 + ii_move_dxxia -(a5),a5,d,d,e5 + ii_move_dxxia -(a6),a6,d,d,e6 + ii_move_dxxia -(a7),a7,a7,d,e7 +//--------------------------------------------------------------------- +// move.x d8(ax/pc,dy),ea -------------------------------------------- +//--------------------------------------------------------------------- +// move.x d8(ax/pc,dy),dz + ii_move_d8_dest d0,id,03,dx + ii_move_d8_dest d1,id,23,dx + ii_move_d8_dest d2,d,43,dx + ii_move_d8_dest d3,d,63,dx + ii_move_d8_dest d4,d,83,dx + ii_move_d8_dest d5,d,a3,dx + ii_move_d8_dest d6,d,c3,dx + ii_move_d8_dest d7,d,e3,dx +// move.x d8(ax/pc,dy),az + ii_move_d8_dest a0,id,07,ax + ii_move_d8_dest a1,id,27,ax + ii_move_d8_dest a2,d,47,ax + ii_move_d8_dest a3,d,67,ax + ii_move_d8_dest a4,d,87,ax + ii_move_d8_dest a5,d,a7,ax + ii_move_d8_dest a6,d,c7,ax + ii_move_d8_dest usp,id,e7,ax +// move.x d8(ax/pc,dy),(az) + ii_move_d8_dest a0_off(a7),id,0b,ia + ii_move_d8_dest a1_off(a7),id,2b,ia + ii_move_d8_dest (a2),d,4b,ia + ii_move_d8_dest (a3),d,6b,ia + ii_move_d8_dest (a4),d,8b,ia + ii_move_d8_dest (a5),d,ab,ia + ii_move_d8_dest (a6),d,cb,ia + ii_move_d8_dest usp,id,eb,ia +// move.x d8(ax/pc,dy),(az)+ + ii_move_d8_dest a0_off(a7),id,0f,iap + ii_move_d8_dest a1_off(a7),id,2f,iap + ii_move_d8_dest (a2)+,d,4f,iap + ii_move_d8_dest (a3)+,d,6f,iap + ii_move_d8_dest (a4)+,d,8f,iap + ii_move_d8_dest (a5)+,d,af,iap + ii_move_d8_dest (a6)+,d,cf,iap + ii_move_d8_dest usp,id,ef,iap +// move.x d8(ax/pc,dy),-(az) + ii_move_d8_dest a0_off(a7),id,13,iam + ii_move_d8_dest a1_off(a7),id,33,iam + ii_move_d8_dest -(a2),d,53,iam + ii_move_d8_dest -(a3),d,73,iam + ii_move_d8_dest -(a4),d,93,iam + ii_move_d8_dest -(a5),d,b3,iam + ii_move_d8_dest -(a6),d,d3,iam + ii_move_d8_dest usp,id,f3,iam +.endm //end function +//==================================================================== +// subs ---------------------------------------------------------- +//==================================================================== +// move.x d16(ax),xxx.w/l 1=code 2=adress register 3=dest adr size +ii_move_d16ax_xxx:.macro +ii_0x1\1: //byt: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.b (a1),d0 + move.\3 (a0)+,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x2\1: //long: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.l (a1),d0 + move.\3 (a0)+,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x3\1: //word: +#ifdef halten_move + halt +#endif + mvs.w (a0)+,d0 + move.l \2,a1 + add.l d0,a1 + move.w (a1),d0 + move.\3 (a0)+,a1 + move.w d0,(a1) + set_cc0 + ii_end +.endm +//---------------------------------------- +// move.x xxx.w,d16(ax) +// move.x xxx.l,d16(ax) +// move.x #xx,d16(ax) +ii_move_xxx_d16ax:.macro //1=code 2=adress register +ii_0x1\178: //byt xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.b (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x1\179: //byt xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.b (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x1\17c: //byt #x +#ifdef halten_move + halt +#endif + mvs.b (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.b d0,(a1) + set_cc0 + ii_end +ii_0x2\178: //long xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.l (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x2\179: //long xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.l (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end +ii_0x2\17c: //long #x +#ifdef halten_move + halt +#endif + move.l (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.l d0,(a1) + set_cc0 + ii_end + ii_end +ii_0x3\178: //word xxx.w +#ifdef halten_move + halt +#endif + move.w (a0)+,a1 + move.w (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +ii_0x3\179: //word xxx.l +#ifdef halten_move + halt +#endif + move.l (a0)+,a1 + move.w (a1),d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +ii_0x3\17c: //word #x +#ifdef halten_move + halt +#endif + move.w (a0)+,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + move.w d0,(a1) + set_cc0 + ii_end +.endm +// move.x xxx,xxx +ii_move_xxx_xxx:.macro //1=size 2=size source adr 3=size dest adr 4=code +ii_0x\4: +#ifdef halten_move + halt +#endif + move.\2 (a0)+,a1 + move.\1 (a1),d0 + move.\3 (a0)+,d1 + move.\1 d0,(a1) + set_cc0 + ii_end +.endm +// move.x im,xxx +ii_move_im_xxx:.macro //1=size 2=size dest adr 3=code +ii_0x\3: +#ifdef halten_move + halt +#endif +.ifc 1,b + move.w (a0)+,d0 +.else + move.\1 (a0)+,d0 +.endif + move.\2 (a0)+,a1 + move.\1 d0,(a1) + set_cc0 + ii_end +.endm +//--------------------------------------------------------------------- +// move.x ea,d8(ax,dy) ------------------------------------------- +//--------------------------------------------------------------------- +// ea=dx,ax,(ax),(ax)+,-(ax) +//--------------------------------------------------------------------- +ii_move_dxxia:.macro //1=source 2=code 1.stelle 3=code 2 letzte Stellen 4=art 5=code d8(pc,dy) +.ifc \3,id + ii_move_dxxi b,\1+3,1,\2,\3,\5 + ii_move_dxxi w,\1+2,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 +.else + .ifc \4,da + ii_move_dxxi w,\1,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 + .else + ii_move_dxxi b,\1,1,\2,\3,\5 + ii_move_dxxi w,\1,2,\2,\3,\5 + ii_move_dxxi l,\1,3,\2,\3,\5 + .endif +.endif +.endm + +ii_move_dxxi:.macro +ii_0x\31\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + move_end \1,\2,\5 +ii_0x\33\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + move_end \1,\2,\5 +ii_0x\35\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a2,a1 + move_end \1,\2,\5 +ii_0x\37\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a3,a1 + move_end \1,\2,\5 +ii_0x\39\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a4,a1 + move_end \1,\2,\5 +ii_0x\3b\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a5,a1 + move_end \1,\2,\5 +ii_0x\3d\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a6,a1 + move_end \1,\2,\5 +ii_0x\3f\4: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l usp,a1 + move_end \1,\2,\5 +ii_0x\37\6: //1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen +#ifdef halten_move + halt +#endif + move.l a0,a1 + move_end \1,\2,\5 +.endm +//------------------------------------ +move_end:.macro + jsr ewf +.ifc 3,a7 + move.l a7,d1 // a7 sichern + move.l usp,a7 // a7 holen +.endif +.ifc 3,ia + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 (a2),(a1) + move.l d1,a2 // a2 zurück +.else + .ifc 3,iap + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 (a2)+,(a1) + .else + .ifc 3,iam + move.l a2,d1 // a2 sichern + move.l \2,a2 + move.\2 -(a2),(a1) + .else + move.\1 \2,(a1) + .endif + .endif +.endif +.ifc 3,a7 + movea.l a7,usp // a7 zurück + movea.l d1,a7 // a7 setzen +.endif + set_cc0 +.ifc 3,iap + move.l d1,a2 // a2 zurück +.endif +.ifc 3,iam + move.l d1,a2 // a2 zurück +.endif + ii_end +.endm +//--------------------------------------------------------------------- +// move.x ea,d8(pc,dy) +//--------------------------------------------------------------------- + +//--------------------------------------------------------------------- +// move.x d8(ax,dy),ea --------------------------------------------- +//--------------------------------------------------------------------- +ii_move_d8_dest:.macro //1=dest 2=art 3=code 2.+3.stelle 4=art adresse +//byt +ii_0x1\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + moveb_a1_src\4 \1,\2 +ii_0x1\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + moveb_a1_src\4 \1,\2 +ii_0x1\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + moveb_a1_src\4 \1,\2 +ii_0x1\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +//long +ii_0x2\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + movel_a1_src\4 \1,\2 +ii_0x2\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + movel_a1_src\4 \1,\2 +ii_0x2\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + movel_a1_src\4 \1,\2 +ii_0x2\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + movel_a1_src\4 \1,\2 +ii_0x2\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + movel_a1_src\4 \1,\2 +ii_0x2\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + movel_a1_src\4 \1,\2 +ii_0x2\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + movel_a1_src\4 \1,\2 +ii_0x2\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + movel_a1_src\4 \1,\2 +ii_0x2\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +//word +ii_0x3\30: +#ifdef halten_move + halt +#endif + move.l a0_off(a7),a1 + movew_a1_src\4 \1,\2 +ii_0x3\31: +#ifdef halten_move + halt +#endif + move.l a1_off(a7),a1 + movew_a1_src\4 \1,\2 +ii_0x3\32: +#ifdef halten_move + halt +#endif + move.l a2,a1 + movew_a1_src\4 \1,\2 +ii_0x3\33: +#ifdef halten_move + halt +#endif + move.l a3,a1 + movew_a1_src\4 \1,\2 +ii_0x3\34: +#ifdef halten_move + halt +#endif + move.l a4,a1 + movew_a1_src\4 \1,\2 +ii_0x3\35: +#ifdef halten_move + halt +#endif + move.l a5,a1 + movew_a1_src\4 \1,\2 +ii_0x3\36: +#ifdef halten_move + halt +#endif + move.l a6,a1 + movew_a1_src\4 \1,\2 +ii_0x3\37: +#ifdef halten_move + halt +#endif + move.l usp,a1 + movew_a1_src\4 \1,\2 +ii_0x3\3b: +#ifdef halten_move + halt +#endif + move.l a0,a1 + moveb_a1_src\4 \1,\2 +.endm +//--------------------------------------------------------------------- +//dx +moveb_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.b (a1),\1_off+3(a7) +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.l (a1),\1_off(a7) +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcdx:.macro + jsr ewf +.ifc \2,id + move.w (a1),\1_off+2(a7) +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// ax +moveb_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.w (a1),a1 + move.l a1,usp + .else + move.w (a1),\1_off+2(a7) + .endif +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.l (a1),a1 + move.l a1,usp + .else + move.l (a1),\1_off(a7) + .endif +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcax:.macro + jsr ewf +.ifc \2,id + .ifc \1,usp + move.w (a1),a1 + move.l a1,usp + .else + move.w (a1),\1_off+2(a7) + .endif +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// (ax) +moveb_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,(a1) +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,(a1) +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srcia:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,(a1) +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// (ax)+ +moveb_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,(a1)+ + move.l a1,\1 +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,(a1)+ + move.l a1,\1 +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srciap:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,(a1)+ + move.l a1,\1 +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm +// -(ax) +moveb_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.b (a1),d0 + move.l \1,a1 + move.b d0,-(a1) + move.l a1,\1 +.else + move.b (a1),\1 +.endif + set_cc0 + ii_end +.endm +movel_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.l (a1),d0 + move.l \1,a1 + move.l d0,-(a1) + move.l a1,\1 +.else + move.l (a1),\1 +.endif + set_cc0 + ii_end +.endm +movew_a1_srciam:.macro + jsr ewf +.ifc \2,id + move.w (a1),d0 + move.l \1,a1 + move.w d0,-(a1) + move.l a1,\1 +.else + move.w (a1),\1 +.endif + set_cc0 + ii_end +.endm + +//--------------------------------------------------------------------- +// move.x d8(pc,dy),ea +//--------------------------------------------------------------------- + + + +// move.w dx,(a0,dx.w*SF) + ii_lset 0x3180 + ii_lset 0x3181 + ii_lset 0x3182 + ii_lset 0x3183 + ii_lset 0x3184 + ii_lset 0x3185 + ii_lset 0x3186 + ii_lset 0x3187 + +//-------------------------------------------------------------------- +// // move.w dx,d(ay,dz.w*sf) +//-------------------------------------------------------------------- +movew_ewfw:.macro off1, off2 + move.l \off2,a1 + jsr ewf + move.w \off1,(a1) + set_cc0 + ii_end + .endm +ii_0x3180: + movew_ewfw d0_off+2(a7),a0_off(a7) +ii_0x3181: + movew_ewfw d0_off+2(a7),a0_off(a7) +ii_0x3182: + movew_ewfw d2,a0_off(a7) +ii_0x3183: + movew_ewfw d3,a0_off(a7) +ii_0x3184: + movew_ewfw d4,a0_off(a7) +ii_0x3185: + movew_ewfw d5,a0_off(a7) +ii_0x3186: + movew_ewfw d6,a0_off(a7) +ii_0x3187: + movew_ewfw d7,a0_off(a7) diff --git a/BaS_gcc/sources/ii_movem.h b/BaS_gcc/sources/ii_movem.h new file mode 100644 index 0000000..5e8a470 --- /dev/null +++ b/BaS_gcc/sources/ii_movem.h @@ -0,0 +1,374 @@ +//***********************************************************************************/ +// movem +//***********************************************************************************/ +ii_movem_lset: .macro +// movem.l rx,xxx.L + ii_lset 0x48f9 +// movem.l xxx.L,rx + ii_lset 0x4cf9 +// movem.w rx,xxx.L + ii_lset 0x48b9 +// movem.w xxx.L,rx + ii_lset 0x4cb9 +// movem.l rx,-(ax) + ii_lset 0x48e0 + ii_lset 0x48e1 + ii_lset 0x48e2 + ii_lset 0x48e3 + ii_lset 0x48e4 + ii_lset 0x48e5 + ii_lset 0x48e6 + ii_lset 0x48e7 +// movem.l (ax)+,rx + ii_lset 0x4cd8 + ii_lset 0x4cd9 + ii_lset 0x4cda + ii_lset 0x4cdb + ii_lset 0x4cdc + ii_lset 0x4cdd + ii_lset 0x4cde + ii_lset 0x4cdf +.endm +//***********************************************************************************/ +ii_movem_func: .macro +//------------------------------------------------------------------- +// movem.l +//-------------------------------------------------------------------- +// movem.l (ax)+,reg +//-------------------------------------------------------------------- + .long 0 +az_reg_table: + .byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70 + .byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0 + .byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0 + .byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0 + .byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0 +//------------------------------------------------------------------------------- +ii_0x48e0: // movem.l reglist,-(a0) + mvm_mem_macro 0x48d0,a0_off(a7),2 +ii_0x48e1: // movem.l reglist,-(a1) + mvm_mem_macro 0x48d1,a1_off(a7),2 +ii_0x48e2: // movem.l reglist,-(a2) + mvm_mem_macro 0x48d2,a2,2 +ii_0x48e3: // movem.l reglist,-(a3) + mvm_mem_macro 0x48d3,a3,2 +ii_0x48e4: // movem.l reglist,-(a4) + mvm_mem_macro 0x48d4,a4,2 +ii_0x48e5: // movem.l reglist,-(a5) + mvm_mem_macro 0x48d5,a5,2 +ii_0x48e6: // movem.l reglist,-(a6) + mvm_mem_macro 0x48d6,a6,2 +ii_0x48e7: // movem.l reglist,-(a7) + mvm_mem_macro 0x48d7,usp,2 +//------------------------------------------------------------------------------- +ii_0x4cd8: // movem.l (a0)+,reglist + mvm_reg_macro 0x4cd0,0x41e8,2 +ii_0x4cd9: // movem.l (a1)+,reglist + mvm_reg_macro 0x4cd1,0x43e9,2 +ii_0x4cda: // movem.l (a2)+,reglist + mvm_reg_macro 0x4cd2,0x45ea,2 +ii_0x4cdb: // movem.l (a3)+,reglist + mvm_reg_macro 0x4cd3,0x47eb,2 +ii_0x4cdc: // movem.l (a4)+,reglist + mvm_reg_macro 0x4cd4,0x49ec,2 +ii_0x4cdd: // movem.l (a5)+,reglist + mvm_reg_macro 0x4cd5,0x4bed,2 +ii_0x4cde: // movem.l (a6)+,reglist + mvm_reg_macro 0x4cd6,0x4dee,2 +ii_0x4cdf: // movem.l (a7)+,reglist + mvm_reg_macro 0x4cd7,0x4fef,2 +//---------------------------------------------------------------------------- +ii_0x48f9: // movem.l reg,xxx.L +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro l +//--------------------------------------------------------------------------------------------- +ii_0x4cf9: // movem.l xxx.L,reg +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro l +//---------------------------------------------------------------------------- +ii_0x48b9: // movem.w reg,xxx.L +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemrm_macro w +//--------------------------------------------------------------------------------------------- +ii_0x4cb9: // movem.w xxx.L,reg +#ifdef halten_movem + halt +#endif + move.w (a0)+,d0 + move.l (a0)+,a1 + movemmr_macro w +.endm +//============================================================== +mvm_mem_macro:.macro +#ifdef halten_movem + halt +#endif + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lsl.l #\3,d1 // * anzahl byts pro wert + move.l \2,a1 + sub.l d1,a1 // ax-anzahl byts + move.l a1,\2 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x reg_list,-(a7) + move.w (a0)+,(a1)+ // register list + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte +.endm +//--------------------------------------------------------------------------------- +mvm_reg_macro:.macro +#ifdef halten_movem + halt +#endif + lea az_reg_table,a1 + mvz.b (a0),d1 + mvz.b 0(a1,d1)+,d0 + mvz.b 1(a0),d1 + mvz.b 0(a1,d1)+,d1 + add.l d0,d1 + lea ___RAMBAR1,a1 + move.l a1,pc_off(a7) + move.l a1,d0 + addq.l #1,d0 + movec d0,RAMBAR1 + move.w #\1,(a1)+ // movem.x (ax),reg_list + move.w (a0)+,(a1)+ // register list + move.w #\2,(a1)+ // lea 0(ax),ax + lsl.l #\3,d1 // * anzahl byts pro wert + move.w d1,(a1)+ // offset von lea + move.w #0x4ef9,(a1)+ // jmp.l + move.l a0,(a1) // rücksprungadresse + move.l #___RAMBAR1 + 0x81,d0 // instruction + movec d0,RAMBAR1 + movem.l (a7),d0/d1/a0/a1 + lea ii_ss(a7),a7 // stack erhöhen + rte +.endm +//--------------------------------------------------------------------------------- +movemrm_macro:.macro // in d0 register liste, in a1 zieladresse +#ifdef halten_movem + halt +#endif + tst.b d0 // datenregister zu verschieben? + bne mrm_dx\@ // ja-> + lsr.l #8,d0 // sonst zu addressregister + jmp mmrm_nd7\@ // -> +mrm_dx\@: + lsr.l #1,d0 + bcc mmrm_nd0\@ +.ifc 1,l + move.l d0_off(a7),(a1)+ +.else + move.w d0_off+2(a7),(a1)+ +.endif +mmrm_nd0\@: + lsr.l #1,d0 + bcc mmrm_nd1\@ +.ifc 1,l + move.l d1_off(a7),(a1)+ +.else + move.w d1_off+2(a7),(a1)+ +.endif +mmrm_nd1\@: + lsr.l #1,d0 + bcc mmrm_nd2\@ + move.\1 d2,(a1)+ +mmrm_nd2\@: + lsr.l #1,d0 + bcc mmrm_nd3\@ + move.\1 d3,(a1)+ +mmrm_nd3\@: + lsr.l #1,d0 + bcc mmrm_nd4\@ + move.\1 d4,(a1)+ +mmrm_nd4\@: + lsr.l #1,d0 + bcc mmrm_nd5\@ + move.\1 d5,(a1)+ +mmrm_nd5\@: + lsr.l #1,d0 + bcc mmrm_nd6\@ + move.l d6,(a1)+ +mmrm_nd6\@: + lsr.l #1,d0 + bcc mmrm_nd7\@ + move.\1 d7,(a1)+ +mmrm_nd7\@: + tst.b d0 // addressregister zu verschieben? + beq mmrm_na7\@ + lsr.l #1,d0 + bcc mmrm_na0\@ +.ifc 1,l + move.l a0_off(a7),(a1)+ +.else + move.w a0_off+2(a7),(a1)+ +.endif +mmrm_na0\@: + lsr.l #1,d0 + bcc mmrm_na1\@ +.ifc 1,l + move.l a1_off(a7),(a1)+ +.else + move.w a1_off+2(a7),(a1)+ +.endif +mmrm_na1\@: + lsr.l #1,d0 + bcc mmrm_na2\@ + move.\1 a2,(a1)+ +mmrm_na2\@: + lsr.l #1,d0 + bcc mmrm_na3\@ + move.\1 a3,(a1)+ +mmrm_na3\@: + lsr.l #1,d0 + bcc mmrm_na4\@ + move.\1 a4,(a1)+ +mmrm_na4\@: + lsr.l #1,d0 + bcc mmrm_na5\@ + move.\1 a5,(a1)+ +mmrm_na5\@: + lsr.l #1,d0 + bcc mmrm_na6\@ + move.\1 a6,(a1)+ +mmrm_na6\@: + lsr.l #1,d0 + bcc mmrm_na7\@ + move.l a0,d1 // sichern + move.l usp,a0 // ist ja usp + move.\1 a0,(a1)+ // nach a0 + move.l d1,a0 // pc zurück +mmrm_na7\@: + ii_end + .endm +//--------------------------------------------------------------------------------------------- +movemmr_macro:.macro // in d0 register liste, in a1 source adr +#ifdef halten_movem + halt +#endif + tst.b d0 // datenregister zu verschieben? + bne mmr_dx\@ // ja-> + lsr.l #8,d0 // sonst zu addressregister + bra mmmr_nd7\@ // -> +mmr_dx\@: + lsr.l #1,d0 + bcc mmmr_nd0\@ +.ifc 1,l + move.l (a1)+,d0_off(a7) +.else + move.w (a1)+,d0_off+2(a7) +.endif +mmmr_nd0\@: + lsr.l #1,d0 + bcc mmmr_nd1\@ +.ifc 1,l + move.l (a1)+,d1_off(a7) +.else + move.w (a1)+,d1_off+2(a7) +.endif +mmmr_nd1\@: + lsr.l #1,d0 + bcc mmmr_nd2\@ + move.\1 (a1)+,d2 +mmmr_nd2\@: + lsr.l #1,d0 + bcc mmmr_nd3\@ + move.\1 (a1)+,d3 +mmmr_nd3\@: + lsr.l #1,d0 + bcc mmmr_nd4\@ + move.\1 (a1)+,d4 +mmmr_nd4\@: + lsr.l #1,d0 + bcc mmmr_nd5\@ + move.\1 (a1)+,d5 +mmmr_nd5\@: + lsr.l #1,d0 + bcc mmmr_nd6\@ + move.\1 (a1)+,d6 +mmmr_nd6\@: + lsr.l #1,d0 + bcc mmmr_nd7\@ + move.\1 (a1)+,d7 +mmmr_nd7\@: + tst.b d0 // addressregister zu verschieben? + beq mmmr_na7\@ // nein-> + lsr.l #1,d0 + bcc mmmr_na0\@ +.ifc 1,l + move.l (a1)+,a0_off(a7) +.else + move.w (a1)+,a0_off+2(a7) +.endif +mmmr_na0\@: + lsr.l #1,d0 + bcc mmmr_na1\@ +.ifc 1,l + move.l (a1)+,a1_off(a7) +.else + move.w (a1)+,a1_off+2(a7) +.endif +mmmr_na1\@: + lsr.l #1,d0 + bcc mmmr_na2\@ + move.\1 (a1)+,a2 +mmmr_na2\@: + lsr.l #1,d0 + bcc mmmr_na3\@ + move.\1 (a1)+,a3 +mmmr_na3\@: + lsr.l #1,d0 + bcc mmmr_na4\@ + move.\1 (a1)+,a4 +mmmr_na4\@: + lsr.l #1,d0 + bcc mmmr_na5\@ + move.\1 (a1)+,a5 +mmmr_na5\@: + lsr.l #1,d0 + bcc mmmr_na6\@ + move.\1 (a1)+,a6 +mmmr_na6\@: + lsr.l #1,d0 + bcc mmmr_na7\@ + move.\1 (a1)+,a1 // nach a0 + move.l a1,usp // war ja usp +mmmr_na7\@: + ii_end + .endm diff --git a/BaS_gcc/sources/ii_movep.h b/BaS_gcc/sources/ii_movep.h new file mode 100644 index 0000000..830fdf7 --- /dev/null +++ b/BaS_gcc/sources/ii_movep.h @@ -0,0 +1,179 @@ +//-------------------------------------------------------------------- +// movep +//-------------------------------------------------------------------- +.text +ii_movep_lset:.macro + ii_lset_opeau 01,0 //movep.w d(a0-7),d0 + ii_lset_opeau 03,0 //movep.w d(a0-7),d1 + ii_lset_opeau 05,0 //movep.w d(a0-7),d2 + ii_lset_opeau 07,0 //movep.w d(a0-7),d3 + ii_lset_opeau 09,0 //movep.w d(a0-7),d4 + ii_lset_opeau 0b,0 //movep.w d(a0-7),d5 + ii_lset_opeau 0d,0 //movep.w d(a0-7),d6 + ii_lset_opeau 0f,0 //movep.w d(a0-7),d7 + + ii_lset_opeau 01,4 //movep.w d0,d(a0-7) + ii_lset_opeau 03,4 //movep.w d1,d(a0-7) + ii_lset_opeau 05,4 //movep.w d2,d(a0-7) + ii_lset_opeau 07,4 //movep.w d3,d(a0-7) + ii_lset_opeau 09,4 //movep.w d4,d(a0-7) + ii_lset_opeau 0b,4 //movep.w d5,d(a0-7) + ii_lset_opeau 0d,4 //movep.w d6,d(a0-7) + ii_lset_opeau 0f,4 //movep.w d7,d(a0-7) + + ii_lset_opeau 01,8 //movep.l d(a0-7),d0 + ii_lset_opeau 03,8 //movep.l d(a0-7),d1 + ii_lset_opeau 05,8 //movep.l d(a0-7),d2 + ii_lset_opeau 07,8 //movep.l d(a0-7),d3 + ii_lset_opeau 09,8 //movep.l d(a0-7),d4 + ii_lset_opeau 0b,8 //movep.l d(a0-7),d5 + ii_lset_opeau 0d,8 //movep.l d(a0-7),d6 + ii_lset_opeau 0f,8 //movep.l d(a0-7),d7 + + ii_lset_opeau 01,c //movep.l d0,d(a0-7) + ii_lset_opeau 03,c //movep.l d1,d(a0-7) + ii_lset_opeau 05,c //movep.l d2,d(a0-7) + ii_lset_opeau 07,c //movep.l d3,d(a0-7) + ii_lset_opeau 09,c //movep.l d4,d(a0-7) + ii_lset_opeau 0b,c //movep.l d5,d(a0-7) + ii_lset_opeau 0d,c //movep.l d6,d(a0-7) + ii_lset_opeau 0f,c //movep.l d7,d(a0-7) +.endm +//--------------------------------------------------------------------------------------------- +ii_movep_func:.macro +//movep.w d(a0-7),d0-7 + ii_movep 010,d0_off(a7),wad + ii_movep 030,d1_off(a7),wad + ii_movep 050,d2,wad + ii_movep 070,d3,wad + ii_movep 090,d4,wad + ii_movep 0b0,d5,wad + ii_movep 0d0,d6,wad + ii_movep 0f0,d7,wad +//movep.w d0-7,d(a0-7) + ii_movep 014,d0_off(a7),wda + ii_movep 034,d1_off(a7),wda + ii_movep 054,d2,wda + ii_movep 074,d3,wda + ii_movep 094,d4,wda + ii_movep 0b4,d5,wda + ii_movep 0d4,d6,wda + ii_movep 0f4,d7,wda +//movep.l d(a0-7),d0-7 + ii_movep 018,d0_off(a7),lad + ii_movep 038,d1_off(a7),lad + ii_movep 058,d2,lad + ii_movep 078,d3,lad + ii_movep 098,d4,lad + ii_movep 0b8,d5,lad + ii_movep 0d8,d6,lad + ii_movep 0f8,d7,lad +//movep.l d0-7,d(a0-7) + ii_movep 01c,d0_off(a7),lda + ii_movep 03c,d1_off(a7),lda + ii_movep 05c,d2,lda + ii_movep 07c,d3,lda + ii_movep 09c,d4,lda + ii_movep 0bc,d5,lda + ii_movep 0dc,d6,lda + ii_movep 0fc,d7,lda +.endm +//--------------------------------------------------------------------------------------------- +ii_movep:.macro //1=code ziffer 1-3 2=register 3=art +ii_0x\18: +#ifdef halten_movep + halt +#endif + move.l a0_off(a7),a1 + ii_movep\3_up1 \2 +ii_0x\19: +#ifdef halten_movep + halt +#endif + move.l a1_off(a7),a1 + ii_movep\3_up1 \2 +ii_0x\1a: +#ifdef halten_movep + halt +#endif + move.l a2,a1 + ii_movep\3_up1 \2 +ii_0x\1b: +#ifdef halten_movep + halt +#endif + move.l a3,a1 + ii_movep\3_up1 \2 +ii_0x\1c: +#ifdef halten_movep + halt +#endif + move.l a4,a1 + ii_movep\3_up1 \2 +ii_0x\1d: +#ifdef halten_movep + halt +#endif + move.l a5,a1 + ii_movep\3_up1 \2 +ii_0x\1e: +#ifdef halten_movep + halt +#endif + move.l a6,a1 + ii_movep\3_up1 \2 +ii_0x\1f: +#ifdef halten_movep + halt +#endif + move.l usp,a1 + ii_movep\3_up1 \2 +.endm + +ii_movepwad_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.b (a1),d0 + lsl.l #8,d0 + move.b 2(a1,d1.l),d0 + move.w d0,\1 + ii_end +.endm + +ii_movepwda_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.w \1,d0 + move.b d0,2(a1) + lsr.l #8,d0 + move.b d0,(a1) + ii_end +.endm + +ii_moveplad_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.b (a1),d0 + lsl.l #8,d0 + move.b 2(a1),d0 + lsl.l #8,d0 + move.b 4(a1),d0 + lsl.l #8,d0 + move.b 6(a1),d0 + move.l d0,\1 + ii_end +.endm + +ii_moveplda_up1:.macro + mvs.w (a0)+,d1 + add.l d1,a1 + move.l \1,d0 + move.b d0,6(a1) + lsr.l #8,d0 + move.b d0,4(a1) + lsr.l #8,d0 + move.b d0,2(a1) + lsr.l #8,d0 + move.b d0,(a1) + ii_end +.endm diff --git a/BaS_gcc/sources/ii_op.h b/BaS_gcc/sources/ii_op.h new file mode 100644 index 0000000..a3fc0cf --- /dev/null +++ b/BaS_gcc/sources/ii_op.h @@ -0,0 +1,661 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_lset_op:.macro +//byt + ii_lset_opea \1,0 // dx,ax + ii_lset_opea \1,1 // (ax), (ax)+ + ii_lset_opea \1,2 // -(ax),d16(ax) + ii_lset_opeag \1,3 // d8(ax,dy) + lea table+0x\1\238*4,a0 + move.l #ii_0x\138,(a0)+ // xxx.w + move.l #ii_0x\139,(a0)+ // xxx.l +//word + ii_lset_opea \1,4 // dx,ax + ii_lset_opea \1,5 // (ax), (ax)+ + ii_lset_opea \1,6 // -(ax),d16(ax) + ii_lset_opeag \1,7 // d8(ax,dy) + lea table+0x\178*4,a0 + move.l #ii_0x\178,(a0)+ // xxx.w + move.l #ii_0x\179,(a0)+ // xxx.l +//long + ii_lset_opea \1,8 // dx,ax + ii_lset_opea \1,9 // (ax), (ax)+ + ii_lset_opea \1,a // -(ax),d16(ax) + ii_lset_opeag \1,b // d8(ax,dy) + lea table+0x\1b8*4,a0 + move.l #ii_0x\1b8,(a0)+ // xxx.w + move.l #ii_0x\1b9,(a0)+ // xxx.l + .endm + +ii_lset_opeag:.macro // 0x1120-0x1127 + lea table+0x\1\20*4,a0 + move.l #ii_0x\1\20,(a0)+ + move.l #ii_0x\1\21,(a0)+ + move.l #ii_0x\1\22,(a0)+ + move.l #ii_0x\1\23,(a0)+ + move.l #ii_0x\1\24,(a0)+ + move.l #ii_0x\1\25,(a0)+ + move.l #ii_0x\1\26,(a0)+ + move.l #ii_0x\1\27,(a0)+ + .endm; + +ii_lset_opeau:.macro // 0x1128-0x112f + lea table+0x\1\28*4,a0 + move.l #ii_0x\1\28,(a0)+ + move.l #ii_0x\1\29,(a0)+ + move.l #ii_0x\1\2a,(a0)+ + move.l #ii_0x\1\2b,(a0)+ + move.l #ii_0x\1\2c,(a0)+ + move.l #ii_0x\1\2d,(a0)+ + move.l #ii_0x\1\2e,(a0)+ + move.l #ii_0x\1\2f,(a0)+ + .endm; + +ii_lset_opea:.macro + ii_lset_opeag \1,\2 + ii_lset_opeau \1,\2 + .endm +/******************************************************/ +ii_op:.macro // 1=code 2=operation 3 = normal oder immediat/quick +// byt + opdx \1,\2,b,0,\3 // dx,ax + opia \1,\2,b,1,\3 // (ax),(ax)+ + opdia \1,\2,b,2,\3 // -(ax),d16(ax) + opd8a \1,\2,b,3,\3 // d8(ax),xxx +// word + opdx \1,\2,w,4,\3 // dx,ax + opia \1,\2,w,5,\3 // (ax),(ax)+ + opdia \1,\2,w,6,\3 // -(ax),d16(ax) + opd8a \1,\2,w,7,\3 // d8(ax),xxx +// long + opdx \1,\2,l,8,\3 // dx,ax + opia \1,\2,l,9,\3 // (ax),(ax)+ + opdia \1,\2,l,a,\3 // -(ax),d16(ax) + opd8a \1,\2,l,b,\3 // d8(ax),xxx + .endm +/******************************************************/ +// byt word long +/******************************************************/ +opdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + .ifc \3,b + op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 + .else + op\5smd \2,d0_off(a7),d0_off(a7),\3 + .endif + .endif +ii_0x\1\41: + .ifc \3,b + op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 + .else + op\5smd \2,d1_off(a7),d1_off(a7),\3 + .endif +.endif +ii_0x\1\42: + op\5smd \2,d2,d2,\3 +ii_0x\1\43: + op\5smd \2,d3,d3,\3 +ii_0x\1\44: + op\5smd \2,d4,d4,\3 +ii_0x\1\45: + op\5smd \2,d5,d5,\3 +ii_0x\1\46: + op\5smd \2,d6,d6,\3 +ii_0x\1\47: + op\5smd \2,d7,d7,\3 +//ax +ii_0x\1\48: + opa\5smd \2,a0_off(a7),a0_off(a7),\3 +ii_0x\1\49: + opa\5smd \2,a1_off(a7),a1_off(a7),\3 +ii_0x\1\4a: + opa\5smd \2,a2,a2,\3 +ii_0x\1\4b: + opa\5smd \2,a3,a3,\3 +ii_0x\1\4c: + opa\5smd \2,a4,a4,\3 +ii_0x\1\4d: + opa\5smd \2,a5,a5,\3 +ii_0x\1\4e: + opa\5smd \2,a6,a6,\3 +ii_0x\1\4f: + opa\5smd \2,usp,usp,\3 +.endm; +//----------------------------------------------- +opia: .macro // (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +//(ax) +ii_0x\1\40: + op\5sia \2,a0_off(a7),(a1),(a1),\3 +ii_0x\1\41: + op\5sia \2,a1_off(a7),(a1),(a1),\3 +ii_0x\1\42: + op\5smd \2,(a2),(a2),\3 +ii_0x\1\43: + op\5smd \2,(a3),(a3),\3 +ii_0x\1\44: + op\5smd \2,(a4),(a4),\3 +ii_0x\1\45: + op\5smd \2,(a5),(a5),\3 +ii_0x\1\46: + op\5smd \2,(a6),(a6),\3 +ii_0x\1\47: + op\5sia \2,usp,(a1),(a1),\3 +//(ax)+ +ii_0x\1\48: + op\5sia \2,a0_off(a7),(a1),(a1)+,\3 +ii_0x\1\49: + op\5sia \2,a1_off(a7),(a1),(a1)+,\3 +ii_0x\1\4a: + op\5smd \2,(a2),(a2)+,\3 +ii_0x\1\4b: + op\5smd \2,(a3),(a3)+,\3 +ii_0x\1\4c: + op\5smd \2,(a4),(a4)+,\3 +ii_0x\1\4d: + op\5smd \2,(a5),(a5)+,\3 +ii_0x\1\4e: + op\5smd \2,(a6),(a6)+,\3 +ii_0x\1\4f: + op\5sia \2,usp,(a1),(a1)+,\3 +.endm; +//----------------------------------------------- +opdia: .macro // -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + op\5sia \2,a0_off(a7),-(a1),(a1),\3 +ii_0x\1\41: + op\5sia \2,a1_off(a7),-(a1),(a1),\3 +ii_0x\1\42: + op\5smd \2,-(a2),(a2),\3 +ii_0x\1\43: + op\5smd \2,-(a3),(a3),\3 +ii_0x\1\44: + op\5smd \2,-(a4),(a4),\3 +ii_0x\1\45: + op\5smd \2,-(a5),(a5),\3 +ii_0x\1\46: + op\5smd \2,-(a6),(a6),\3 +ii_0x\1\47: + op\5sia \2,usp,-(a1),(a1),\3 + +ii_0x\1\48: + op\5sd16a \2,a0_off(a7),\3 +ii_0x\1\49: + op\5sd16a \2,a1_off(a7),\3 +ii_0x\1\4a: + op\5sd16a \2,a2,\3 +ii_0x\1\4b: + op\5sd16a \2,a3,\3 +ii_0x\1\4c: + op\5sd16a \2,a4,\3 +ii_0x\1\4d: + op\5sd16a \2,a5,\3 +ii_0x\1\4e: + op\5sd16a \2,a6,\3 +ii_0x\1\4f: + op\5sd16a \2,usp,\3 +.endm; +//----------------------------------------------- +opd8a: .macro // d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: + op\5sd8a \2,a0_off(a7),\3 +ii_0x\1\41: + op\5sd8a \2,a1_off(a7),\3 +ii_0x\1\42: + op\5sd8a \2,a2,\3 +ii_0x\1\43: + op\5sd8a \2,a3,\3 +ii_0x\1\44: + op\5sd8a \2,a4,\3 +ii_0x\1\45: + op\5sd8a \2,a5,\3 +ii_0x\1\46: + op\5sd8a \2,a6,\3 +ii_0x\1\47: + op\5sd8a \2,usp,\3 + +ii_0x\1\48: + op\5sxx \2,\3,w +ii_0x\1\49: + op\5sxx \2,\3,l +.endm; +//----------------------------------------------- +opnsmd:.macro // direct dx: 1=operation 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opansmd:.macro // direct ax: 1=operation 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d1 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end +.endm; + +opnsia:.macro // indirect: 1=operation 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opnsd16a:.macro // indirect: 1=operation 2=adress register 3=size +#ifdef halten_op + halt +#endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opnsd8a:.macro // indirect: 1=operation 2=adress register 3=size +#ifdef halten_op + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opnsxx:.macro // indirect: 1=operation 2=size 3=size adresse +#ifdef halten_op + halt +#endif + +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif + move.\3 (a0)+,a1 + .ifc \1,negx + move.b sr_off+1(a7),d1 //ccr holen + move d1,ccr //setzen + .endif + \1 d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; +//*******************************************************************************3 +opismd:.macro // immediate dx: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\4 d1,\3 +.endif + ii_end +.endm; + +opaismd:.macro // immediate ax: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_op + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d0,d1 +.ifnc \1,cmp.l +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif +.endif + ii_end +.endm; + +opisia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + +.ifc \5,l + move.l (a0)+,d0 +.else + .ifc \5,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\5 d1,\4 +.endif + ii_end +.endm; + +opisd16a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + +.ifc \3,l + move.l (a0)+,d0 +.else + .ifc \3,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\3 d1,(a1) +.endif + ii_end + .endm; + +opisd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + +.ifc \3,l + move.l (a0)+,d0 +.else + .ifc \3,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\3 d1,(a1) +.endif + ii_end + .endm; + +opisxx:.macro // immediate: 1=opieration 2=size 3=size adresse +.ifc \2,l + move.l (a0)+,d0 +.else + .ifc \2,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif + \1 d0,d1 + set_cc0 +.ifnc \1,cmp.l + move.\2 d1,(a1) +.endif + ii_end + .endm; +//*******************************************************************************3 +opqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opaqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 ,d1 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end + .endm; + +opqsia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_op + halt +#endif + + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opqsd16a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opqsd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_op + halt +#endif + + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opqsxx:.macro // quick: 1=opieration 2=size 3=size adresse +#ifdef halten_op + halt +#endif + + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d0 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 ,d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; diff --git a/BaS_gcc/sources/ii_opc.h b/BaS_gcc/sources/ii_opc.h new file mode 100644 index 0000000..8b887ce --- /dev/null +++ b/BaS_gcc/sources/ii_opc.h @@ -0,0 +1,263 @@ +/*****************************************************************************************/ +// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax +// zusammen mit op.h +/*****************************************************************************************/ +ii_lset_opc:.macro + ii_lset_opeag \1,c // dx,ax + ii_lset_opea \1,d // (ax), (ax)+ + ii_lset_opea \1,e // -(ax),d16(ax) + ii_lset_opeag \1,f // d8(ax,dy) + lea table+0x\1b8*4,a0 + move.l #ii_0x\1b8,(a0)+ // xxx.w + move.l #ii_0x\1b9,(a0)+ // xxx.l + .endm + +/******************************************************/ +ii_opc:.macro // 1=code 2=operation 3 = normal oder immediat + opcdx \1,\2,l,c,\3 // dx,ax + opia \1,\2,l,d,\3 // (ax),(ax)+ + opdia \1,\2,l,e,\3 // -(ax),d16(ax) + opd8a \1,\2,l,f,\3 // d8(ax),xxx + .endm +//*******************************************************************************3 +/******************************************************/ +// byt word long +/******************************************************/ +opcdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal +ii_0x\1\40: +#ifdef halten_opc + halt +#endif + .ifc \3,b + op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3 + .else + op\5smd \2,d0_off(a7),d0_off(a7),\3 + .endif + .endif +ii_0x\1\41: + .ifc \3,b + op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3 + .else + .ifc \3,w + op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3 + .else + op\5smd \2,d1_off(a7),d1_off(a7),\3 + .endif +.endif +ii_0x\1\42: + op\5smd \2,d2,d2,\3 +ii_0x\1\43: + op\5smd \2,d3,d3,\3 +ii_0x\1\44: + op\5smd \2,d4,d4,\3 +ii_0x\1\45: + op\5smd \2,d5,d5,\3 +ii_0x\1\46: + op\5smd \2,d6,d6,\3 +ii_0x\1\47: + op\5smd \2,d7,d7,\3 +.endm +//----------------------------------------------------- +opcsmd:.macro // dx: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \4,l + move.l \2,d1 +.else + mvs.\4 \2,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\4 d1,\3 + ii_end + .endm; + +opacsmd:.macro // ax: 1=opieration 2=ea src 3=ea dest 4=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif +.ifc \2,usp + move.l usp,a1 + move.l a1,d1 +.else + move.l \2,d1 +.endif + \1 d1 + set_cc0 +.ifc \3,usp + move.l d1,a1 + move.l a1,usp +.else + move.l d1,\3 +.endif + ii_end + .endm; + +opcsia:.macro // (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 +.ifc \5,l + move.l \3,d1 +.else + mvs.\5 \3,d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\5 d1,\4 + ii_end + .endm; + +opcsd16a:.macro // d16(ax): 1=opieration 2=adress register 3=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opcsd8a:.macro // indirect: 1=opieration 2=adress register 3=size +#ifdef halten_opc + halt +#endif + +.ifc \4,l + move.l (a0)+,d0 +.else + .ifc \4,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.l d0,_d0_save + move.l \2,a1 + jsr ewf + move.l _d0_save,d0 +.ifc \3,l + move.l (a1),d1 +.else + mvs.\3 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; + +opcsxx:.macro // indirect: 1=opieration 2=size 3=size adresse +#ifdef halten_opc + halt +#endif + +.ifc \2,l + move.l (a0)+,d0 +.else + .ifc \2,w + mvs.w (a0)+,d0 + .else + move.w (a0)+,d0 + extb.l d0 + .endif +.endif + move.\3 (a0)+,a1 +.ifc \2,l + move.l (a1),d1 +.else + mvs.\2 (a1),d1 +.endif +.ifc \1,eor.l d0 + move.l d0_off(a7),d1 +.endif +.ifc \1,eor.l d1 + move.l d1_off(a7),d1 +.endif + \1 d1 + set_cc0 + move.\2 d1,(a1) + ii_end + .endm; diff --git a/BaS_gcc/sources/ii_or.h b/BaS_gcc/sources/ii_or.h new file mode 100644 index 0000000..dfe4450 --- /dev/null +++ b/BaS_gcc/sources/ii_or.h @@ -0,0 +1,442 @@ +//-------------------------------------------------------------------- +// or +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// or.b #im,dx +//-------------------------------------------------------------------- +orbir_macro:.macro +#ifdef halten_or + halt +#endif + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + or.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea,dx +//-------------------------------------------------------------------- +ordd:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +orddd:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or (ea)->dy,dx +//-------------------------------------------------------------------- +ordda:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +orddai:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or ea->ay,-(ay),dx +//-------------------------------------------------------------------- +orddad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d16(ay),dx +//-------------------------------------------------------------------- +ord16ad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d8(ay,dy),dx +//-------------------------------------------------------------------- +ord8ad:.macro +#ifdef halten_or + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or xxx.w,dx +//-------------------------------------------------------------------- +orxwd:.macro +#ifdef halten_or + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or xxx.l,dx +//-------------------------------------------------------------------- +orxld:.macro +#ifdef halten_or + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d16(pc),dx +//-------------------------------------------------------------------- +ord16pcd:.macro + halt + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or d8(pc,dy),dx +//-------------------------------------------------------------------- +ord8pcd:.macro +#ifdef halten_or + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// or dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // or (ea)->dy,dx +//-------------------------------------------------------------------- +oreda:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +oredai:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +oredaid:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +oredad:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +oredadd:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + or.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,d16(ay) +//-------------------------------------------------------------------- +ore16ad:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or.w dx,d8(ay,dy) +//-------------------------------------------------------------------- +ore8ad:.macro +#ifdef halten_or + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,xxx.w +//-------------------------------------------------------------------- +orxwe:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // or dx,xxx.l +//-------------------------------------------------------------------- +orxle:.macro +#ifdef halten_or + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + or.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // ora.w ea,ax +//-------------------------------------------------------------------- +oraw:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// or.w ea,usp +//-------------------------------------------------------------------- +orawa7:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w usp?,ax +//-------------------------------------------------------------------- +orawu:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w usp?,usp +//-------------------------------------------------------------------- +orawua7:.macro + orawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // ora.w d16(ay),ax +//-------------------------------------------------------------------- +orawd16a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d8(ay,dy),ax +//-------------------------------------------------------------------- +orawd8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w xxx.w,ax +//-------------------------------------------------------------------- +orawxwax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w xxx.l,ax +//-------------------------------------------------------------------- +orawxlax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d16(pc),ax +//-------------------------------------------------------------------- +orawd16pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w d8(pc,dy),ax +//-------------------------------------------------------------------- +orawd8pcax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.w #im,ax +//-------------------------------------------------------------------- +orawim:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.l d8(ay,dy),ax +//-------------------------------------------------------------------- +orald8a:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // ora.l d8(pc,dy),ax +//-------------------------------------------------------------------- +orald8pcax:.macro + jmp ii_error + .endm; +//***************************************************************************************** +// spezial addx subx etc. +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // addx dy,dx +//-------------------------------------------------------------------- +ordx:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- +// // addx -(ay),-(ax) +//-------------------------------------------------------------------- +ordax:.macro + jmp ii_error + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_gcc/sources/ii_pea.h b/BaS_gcc/sources/ii_pea.h new file mode 100644 index 0000000..69f69d0 --- /dev/null +++ b/BaS_gcc/sources/ii_pea.h @@ -0,0 +1,74 @@ +//-------------------------------------------------------------------- +// pea +//-------------------------------------------------------------------- +.text +ii_pea_lset:.macro + ii_lset_opeag 48,7 + ii_lset 0x487b +.endm +//--------------------------------------------------------------------------------------------- +ii_pea_func:.macro +ii_0x4870: +#ifdef halten_pea + halt +#endif + move.l a0_off(a7),a1 + pea_macro +ii_0x4871: +#ifdef halten_pea + halt +#endif + move.l a1_off(a7),a1 + pea_macro +ii_0x4872: +#ifdef halten_pea + halt +#endif + move.l a2,a1 + pea_macro +ii_0x4873: +#ifdef halten_pea + halt +#endif + move.l a3,a1 + pea_macro +ii_0x4874: +#ifdef halten_pea + halt +#endif + move.l a4,a1 + pea_macro +ii_0x4875: +#ifdef halten_pea + halt +#endif + move.l a5,a1 + pea_macro +ii_0x4876: +#ifdef halten_pea + halt +#endif + move.l a6,a1 + pea_macro +ii_0x4877: +#ifdef halten_pea + halt +#endif + move.l usp,a1 + pea_macro +ii_0x487b: +#ifdef halten_pea + halt +#endif + move.l a0,a1 + pea_macro +.endm +//--------------------------------------------------------------------------------------------- +pea_macro:.macro + jsr ewf + move.l (a1),d0 + move.l usp,a1 + move.l d0,-(a1) + move.l a1,usp + ii_end +.endm \ No newline at end of file diff --git a/BaS_gcc/sources/ii_shd.h b/BaS_gcc/sources/ii_shd.h new file mode 100644 index 0000000..ecace29 --- /dev/null +++ b/BaS_gcc/sources/ii_shd.h @@ -0,0 +1,247 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_lset_shd:.macro + ii_lset_shdx e0 //r d0 + ii_lset_shdx e2 //r d1 + ii_lset_shdx e4 //r d2 + ii_lset_shdx e6 //r d3 + ii_lset_shdx e8 //r d4 + ii_lset_shdx ea //r d5 + ii_lset_shdx ec //r d6 + ii_lset_shdx ee //r d7 + + ii_lset_shdx e1 //l d0 + ii_lset_shdx e3 //l d1 + ii_lset_shdx e4 //l d2 + ii_lset_shdx e5 //l d3 + ii_lset_shdx e9 //l d4 + ii_lset_shdx eb //l d5 + ii_lset_shdx ed //l d6 + ii_lset_shdx ef //l d7 + .endm + +ii_lset_shdx:.macro +//byt + ii_lset_opea \1,0 // as,ls #im,dx + ii_lset_opea \1,1 // rox,ro #im,dx + ii_lset_opea \1,2 // as,ls dy,dx + ii_lset_opea \1,3 // rox,ro dy,dx +//word + ii_lset_opea \1,4 // as,ls #im,dx + ii_lset_opea \1,5 // rox,ro #im,dx + ii_lset_opea \1,6 // as,ls dy,dx + ii_lset_opea \1,7 // rox,ro dy,dx +//long +// ii_lset_opea \1,8 // as,ls #im,dx -> vorhanden + ii_lset_opea \1,9 // rox,ro #im,dx +// ii_lset_opea \1,a // as,ls dy,dx -> vorhanden + ii_lset_opea \1,b // rox,ro dy,dx + .endm +/******************************************************/ +ii_shd:.macro // 1=code 2=operation 3 = normal, direct oder immediat +// byt + opdx \1,\2,b,0,\3 // dx +// word + opdx \1,\2,w,4,\3 // dx +// long + opdx \1,\2,l,8,\3 // dx + .endm +/******************************************************/ +// byt word long routinen +/******************************************************/ +sh_asr: .macro // asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvs.\4 \2,d1 + sh_shal \1,\2,\3,\4 + .endm + +sh_lsr: .macro // asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvz.\4 \2,d1 + sh_shal \1,\2,\3,\4 + .endm + +sh_shal:.macro + move.w \3,d0 + \1.l d0,d1 + set_cc0 + move.\4 d1,\2 + .endm + +sh_all: .macro // asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w + mvz.\4 \2,d1 +.ifc \4,b + byterev.l d1 +.else + swap.w d1 +.endif + sh_asr \1,\2,\3,\4 + .endm + +sh_ror: .macro // ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + move.\4 \2,d1 / + move.w \3,d0 +.ifc \4,b + lsl.l #8,d1 + move.b \2,d1 + and.l #0x7,d0 + lsr.l d0,d1 +.else + .ifc \4,w + swap.w d1 + move.w \2,d1 + and.l #0xf,d0 + lsr.l d0,d1 + .else + and.l #0x1f,d0 + lsr.l d0,d1 + move.l d1,a1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsl.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + move.w ccr,d0 + and.l #1,d1 // ist auch carry bit + or.l d1,d0 + move.b d0,ccr_off(a7) + .endm + +sh_rol: .macro // rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + move.\4 \2,d1 + move.w \3,d0 +.ifc \4,b + lsl.l #8,d1 + move.b \2,d1 + and.l #0x7,d0 + lsl.l d0,d1 + lsr.l #8,d1 + moveq #7,d0 +.else + .ifc \4,w + swap.w d1 + move.w \2,d1 + and.l #0xf,d0 + lsr.l d0,d1 + swap.w d1 + moveq #15,d0 + .else + and.l #0x1f,d0 + lsl.l d0,d1 + move.l d1,a1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsr.l d0,d1 + add.l a1,d1 + moveq #31,d0 + .endif +.endif + move.\4 d1,\2 + lsr.l d0,d1 // carry bit schieben + move.w ccr,d0 + and.l #1,d1 + or.l d1,d0 + move.b d0,ccr_off(a7) + .endm + +sh_roxr: .macro // roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + clr.l d0 + addx.l d0,d0 +ifc \4,b + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + move.b \2,d1 + move.w \3,d0 + and.l #0x7,d0 + lsr.l d0,d1 + set_cc0 +else + .ifc \4,w + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + lsl.l #8,d1 + move.w \2,d1 + move.w \3,d0 + and.l #0xf,d0 + lsr.l d0,d1 + set_cc0 + .else + bitrev.l d0 + move.l \2,d1 + lsr.l #1,d1 + add.l d0,d1 + move.w \3,d0 + subq.l #1,d0 + and.l #0x1f,d0 + lsr.l d0,d1 + move.l d1,a1 + set_cc1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsl.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + .endm + +sh_roxl: .macro // roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l + clr.l d0 + addx.l d0,d0 +ifc \4,b + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + move.b \2,d1 + lsl.l #8,d1 + lsl.l #7,d1 + move.w \3,d0 + and.l #0x7,d0 + lsl.l d0,d1 + set_cc0 + byterev.l d1 +else + .ifc \4,w + mvz.b \2,d1 + lsl.l #1,d1 + add.l d0,d1 + lsl.l #8,d1 + lsl.l #7,d1 + mvz.w \2,d0 + lsr.l #1,d0 + add.l d0,d1 + move.w \3,d0 + and.l #0xf,d0 + lsl.l d0,d1 + set_cc0 + swap.w d1 + .else + move.l \2,d1 + lsl.l #1,d1 + add.l d0,d1 + move.w \3,d0 + subq.l #1,d0 + and.l #0x1f,d0 + lsl.l d0,d1 + move.l d1,a1 + set_cc1 + move.l \2,d1 + sub.l #32,d0 + neg.l d0 + lsr.l d0,d1 + add.l a1,d1 + .endif +.endif + move.\4 d1,\2 + .endm + + \ No newline at end of file diff --git a/BaS_gcc/sources/ii_shift.h b/BaS_gcc/sources/ii_shift.h new file mode 100644 index 0000000..f83bfcb --- /dev/null +++ b/BaS_gcc/sources/ii_shift.h @@ -0,0 +1,687 @@ +/*****************************************************************************************/ +// opertionen +/*****************************************************************************************/ +ii_shift_lset:.macro +/******************************************************/ +// byt +/******************************************************/ +// asx.b #,dx + ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,01 + ii_lset_dx \1,02 + ii_lset_dx \1,03 + ii_lset_dx \1,04 + ii_lset_dx \1,05 + ii_lset_dx \1,06 + ii_lset_dx \1,07 +// lsx.b #,dx + ii_lset_dxu \1,08 + ii_lset_dxu \1,09 + ii_lset_dxu \1,0a + ii_lset_dxu \1,0b + ii_lset_dxu \1,0c + ii_lset_dxu \1,0d + ii_lset_dxu \1,0e + ii_lset_dxu \1,0f +// roxx.b #,dx + ii_lset_dx \1,10 + ii_lset_dx \1,11 + ii_lset_dx \1,12 + ii_lset_dx \1,13 + ii_lset_dx \1,14 + ii_lset_dx \1,15 + ii_lset_dx \1,16 + ii_lset_dx \1,17 +// rox.b #,dx + ii_lset_dx \1,18 + ii_lset_dx \1,19 + ii_lset_dx \1,1a + ii_lset_dx \1,1b + ii_lset_dx \1,1c + ii_lset_dx \1,1d + ii_lset_dx \1,1e + ii_lset_dx \1,1f +// asx.b dy,dx + ii_lset_dx \1,20 + ii_lset_dx \1,21 + ii_lset_dx \1,22 + ii_lset_dx \1,23 + ii_lset_dx \1,24 + ii_lset_dx \1,25 + ii_lset_dx \1,26 + ii_lset_dx \1,27 +// lsx.b dy,dx + ii_lset_dx \1,28 + ii_lset_dx \1,29 + ii_lset_dx \1,2a + ii_lset_dx \1,2b + ii_lset_dx \1,2c + ii_lset_dx \1,2d + ii_lset_dx \1,2e + ii_lset_dx \1,2f +// roxx.dy,dx + ii_lset_dx \1,30 + ii_lset_dx \1,31 + ii_lset_dx \1,32 + ii_lset_dx \1,33 + ii_lset_dx \1,34 + ii_lset_dx \1,35 + ii_lset_dx \1,36 + ii_lset_dx \1,37 +// rox.b dy,dx + ii_lset_dx \1,38 + ii_lset_dx \1,39 + ii_lset_dx \1,3a + ii_lset_dx \1,3b + ii_lset_dx \1,3c + ii_lset_dx \1,3d + ii_lset_dx \1,3e + ii_lset_dx \1,3f +/******************************************************/ +// word +/******************************************************/ +// asx.w #x,dx + ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c + ii_lset_dx \1,41 + ii_lset_dx \1,42 + ii_lset_dx \1,43 + ii_lset_dx \1,44 + ii_lset_dx \1,45 + ii_lset_dx \1,46 + ii_lset_dx \1,47 +// lsx.w #,dx + ii_lset_dx \1,48 + ii_lset_dx \1,49 + ii_lset_dx \1,4a + ii_lset_dx \1,4b + ii_lset_dx \1,4c + ii_lset_dx \1,4d + ii_lset_dx \1,4e + ii_lset_dx \1,4f +// roxx.w #,dx + ii_lset_dx \1,50 + ii_lset_dx \1,51 + ii_lset_dx \1,52 + ii_lset_dx \1,53 + ii_lset_dx \1,54 + ii_lset_dx \1,55 + ii_lset_dx \1,56 + ii_lset_dx \1,57 +// rox.w #xdx + ii_lset_dx \1,58 + ii_lset_dx \1,59 + ii_lset_dx \1,5a + ii_lset_dx \1,5b + ii_lset_dx \1,5c + ii_lset_dx \1,5d + ii_lset_dx \1,5e + ii_lset_dx \1,5f +// asx.w dy,dx + ii_lset_dx \1,60 + ii_lset_dx \1,61 + ii_lset_dx \1,62 + ii_lset_dx \1,63 + ii_lset_dx \1,64 + ii_lset_dx \1,65 + ii_lset_dx \1,66 + ii_lset_dx \1,67 +// lsx.w dy,dx + ii_lset_dx \1,68 + ii_lset_dx \1,69 + ii_lset_dx \1,6a + ii_lset_dx \1,6b + ii_lset_dx \1,6c + ii_lset_dx \1,6d + ii_lset_dx \1,6e + ii_lset_dx \1,6f +// roxx.w dy,dx + ii_lset_dx \1,70 + ii_lset_dx \1,71 + ii_lset_dx \1,72 + ii_lset_dx \1,73 + ii_lset_dx \1,74 + ii_lset_dx \1,75 + ii_lset_dx \1,76 + ii_lset_dx \1,77 +// rox.w dy,dx + ii_lset_dx \1,78 + ii_lset_dx \1,79 + ii_lset_dx \1,7a + ii_lset_dx \1,7b + ii_lset_dx \1,7c + ii_lset_dx \1,7d + ii_lset_dx \1,7e + ii_lset_dx \1,7f +/******************************************************/ +// long +/******************************************************/ +// roxx.l #,dx + ii_lset_dx \1,90 + ii_lset_dx \1,91 + ii_lset_dx \1,92 + ii_lset_dx \1,93 + ii_lset_dx \1,94 + ii_lset_dx \1,95 + ii_lset_dx \1,96 + ii_lset_dx \1,97 +// rox.l #xdx + ii_lset_dx \1,98 + ii_lset_dx \1,99 + ii_lset_dx \1,9a + ii_lset_dx \1,9b + ii_lset_dx \1,9c + ii_lset_dx \1,9d + ii_lset_dx \1,9e + ii_lset_dx \1,9f +// roxx.l dy,dx + ii_lset_dx \1,b0 + ii_lset_dx \1,b1 + ii_lset_dx \1,b2 + ii_lset_dx \1,b3 + ii_lset_dx \1,b4 + ii_lset_dx \1,b5 + ii_lset_dx \1,b6 + ii_lset_dx \1,b7 +// rox.l dy,dx + ii_lset_dx \1,b8 + ii_lset_dx \1,b9 + ii_lset_dx \1,ba + ii_lset_dx \1,bb + ii_lset_dx \1,bc + ii_lset_dx \1,bd + ii_lset_dx \1,be + ii_lset_dx \1,bf +//-------------------------------------------------------------------- +// asr.w ea + ii_lset_opea \10,d // (ax), (ax)+ + ii_lset_opea \10,e // -(ax),d16(ax) + ii_lset_opeag \10,f // d8(ax,dy) + lea table+0x\10\2f8*4,a0 + move.l #ii_0x\10f8,(a0)+ // xxx.w + move.l #ii_0x\10f9,(a0)+ // xxx.l +// asl.w ea + ii_lset_opea \11,d // (ax), (ax)+ + ii_lset_opea \11,e // -(ax),d16(ax) + ii_lset_opeag \11,f // d8(ax,dy) + lea table+0x\11\2f8*4,a0 + move.l #ii_0x\11f8,(a0)+ // xxx.w + move.l #ii_0x\11f9,(a0)+ // xxx.l +// lsr.w ea + ii_lset_opea \12,d // (ax), (ax)+ + ii_lset_opea \12,e // -(ax),d16(ax) + ii_lset_opeag \12,f // d8(ax,dy) + lea table+0x\12\2f8*4,a0 + move.l #ii_0x\12f8,(a0)+ // xxx.w + move.l #ii_0x\12f9,(a0)+ // xxx.l +// lsr.w ea + ii_lset_opea \13,d // (ax), (ax)+ + ii_lset_opea \13,e // -(ax),d16(ax) + ii_lset_opeag \13,f // d8(ax,dy) + lea table+0x\13\2f8*4,a0 + move.l #ii_0x\13f8,(a0)+ // xxx.w + move.l #ii_0x\13f9,(a0)+ // xxx.l +// roxr.w ea + ii_lset_opea \14,d // (ax), (ax)+ + ii_lset_opea \14,e // -(ax),d16(ax) + ii_lset_opeag \14,f // d8(ax,dy) + lea table+0x\14\2f8*4,a0 + move.l #ii_0x\14f8,(a0)+ // xxx.w + move.l #ii_0x\14f9,(a0)+ // xxx.l +// roxl.w ea + ii_lset_opea \15,e // (ax), (ax)+ + ii_lset_opea \15,e // -(ax),d16(ax) + ii_lset_opeag \15,f // d8(ax,dy) + lea table+0x\15\2f8*4,a0 + move.l #ii_0x\15f8,(a0)+ // xxx.w + move.l #ii_0x\15f9,(a0)+ // xxx.l +// ror.w ea + ii_lset_opea \16,d // (ax), (ax)+ + ii_lset_opea \16,e // -(ax),d16(ax) + ii_lset_opeag \16,f // d8(ax,dy) + lea table+0x\16\2f8*4,a0 + move.l #ii_0x\16f8,(a0)+ // xxx.w + move.l #ii_0x\16f9,(a0)+ // xxx.l +// rol.w ea + ii_lset_opea \17,d // (ax), (ax)+ + ii_lset_opea \17,e // -(ax),d16(ax) + ii_lset_opeag \17,f // d8(ax,dy) + lea table+0x\17\2f8*4,a0 + move.l #ii_0x\17f8,(a0)+ // xxx.w + move.l #ii_0x\17f9,(a0)+ // xxx.l +// ende +.endm; +/******************************************************/ +ii_shift_op:.macro // 1=code +//byt------------------------------- +//asx.b #x,dx + ii_shift_op2agb 0,as,a +//lsx.b #x,dx + ii_shift_op2aub 0,ls,a +//roxx.b #x,dx + ii_shift_op2agb 1,rox,a +//rox.b #x,dx + ii_shift_op2aub 1,ro,a +//asx.b dy,dx + ii_shift_op2agb 2,as,b +//lsx.b dy,dx + ii_shift_op2aub 2,ls,b +//roxx.b dy,dx + ii_shift_op2agb 3,rox,b +//rox.b dy,dx + ii_shift_op2aub 3,ro,b +// word --------------------------------------- +//asx.w #x,dx + ii_shift_op2agw 4,as,a +//lsx.w #x,dx + ii_shift_op2auw 4,ls,a +//roxx.w #x,dx + ii_shift_op2agw 5,rox,a +//rox.w #x,dx + ii_shift_op2auw 5,ro,a +//asx.w dy,dx + ii_shift_op2agw 6,as,b +//lsx.w dy,dx + ii_shift_op2auw 6,ls,b +//roxx.w dy,dx + ii_shift_op2agw 7,rox,b +//rox.w dy,dx + ii_shift_op2auw 7,ro,b +// long --------------------------------------- +//roxx.l #x,dx + ii_shift_op2agw 9,rox,a +//rox.l #x,dx + ii_shift_op2auw 9,ro,a +//roxx.l dy,dx + ii_shift_op2agw b,rox,b +//rox.l dy,dx + ii_shift_op2auw b,ro,b +// ea --------------------------------------- +//asr.w #1,ea + ii_shift_op2ea 0,asr +//asl.w #1,ea + ii_shift_op2ea 1,asl +//lsr.w #1,ea + ii_shift_op2ea 2,lsr, +//lsl.w #1,ea + ii_shift_op2ea 3,lsl +//roxr.w #1,ea + ii_shift_op2ea 4,roxr +//roxl.w #1,ea + ii_shift_op2ea 5,roxl +//ror.w #1,ea + ii_shift_op2ea 6,ror +//rol.w #1,ea + ii_shift_op2ea 7,rol +.endm +//byt ============================================ +ii_shift_op2agb:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3b \1,0,\2,d0_off+3(a7) + ii_shift_op1\3b \1,1,\2,d1_off+3(a7) + ii_shift_op1\3b \1,2,\2,d2 + ii_shift_op1\3b \1,3,\2,d3 + ii_shift_op1\3b \1,4,\2,d4 + ii_shift_op1\3b \1,5,\2,d5 + ii_shift_op1\3b \1,6,\2,d6 + ii_shift_op1\3b \1,7,\2,d7 +.endm + +ii_shift_op2aub:.macro //byt: 1=code 2=operation + ii_shift_op1\3b \1,8,\2,d0_off+3(a7) + ii_shift_op1\3b \1,9,\2,d1_off+3(a7) + ii_shift_op1\3b \1,a,\2,d2 + ii_shift_op1\3b \1,b,\2,d3 + ii_shift_op1\3b \1,c,\2,d4 + ii_shift_op1\3b \1,d,\2,d5 + ii_shift_op1\3b \1,e,\2,d6 + ii_shift_op1\3b \1,f,\2,d7 +.endm + +ii_shift_op1ab:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,b,\3r,#8,\4 + ii_shift_op0 2\1\2,b,\3r,#1,\4 + ii_shift_op0 4\1\2,b,\3r,#2,\4 + ii_shift_op0 6\1\2,b,\3r,#3,\4 + ii_shift_op0 8\1\2,b,\3r,#4,\4 + ii_shift_op0 a\1\2,b,\3r,#5,\4 + ii_shift_op0 c\1\2,b,\3r,#6,\4 + ii_shift_op0 e\1\2,b,\3r,#7,\4 + ii_shift_op0 1\1\2,b,\3l,#8,\4 + ii_shift_op0 3\1\2,b,\3l,#1,\4 + ii_shift_op0 5\1\2,b,\3l,#2,\4 + ii_shift_op0 7\1\2,b,\3l,#3,\4 + ii_shift_op0 9\1\2,b,\3l,#4,\4 + ii_shift_op0 b\1\2,b,\3l,#5,\4 + ii_shift_op0 d\1\2,b,\3l,#6,\4 + ii_shift_op0 f\1\2,b,\3l,#7,\4 +.endm + +ii_shift_op1bb:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,b,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,b,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,b,\3r,d2,\4 + ii_shift_op0 6\1\2,b,\3r,d3,\4 + ii_shift_op0 8\1\2,b,\3r,d4,\4 + ii_shift_op0 a\1\2,b,\3r,d5,\4 + ii_shift_op0 c\1\2,b,\3r,d6,\4 + ii_shift_op0 e\1\2,b,\3r,d7,\4 + ii_shift_op0b 1\1\2,b,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,b,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,b,\3l,d2,\4 + ii_shift_op0 7\1\2,b,\3l,d3,\4 + ii_shift_op0 9\1\2,b,\3l,d4,\4 + ii_shift_op0 b\1\2,b,\3l,d5,\4 + ii_shift_op0 d\1\2,b,\3l,d6,\4 + ii_shift_op0 f\1\2,b,\3l,d7,\4 +.endm +// word --------------------------------------- +ii_shift_op2agw:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3w \1,0,\2,d0_off+2(a7) + ii_shift_op1\3w \1,1,\2,d1_off+2(a7) + ii_shift_op1\3w \1,2,\2,d2 + ii_shift_op1\3w \1,3,\2,d3 + ii_shift_op1\3w \1,4,\2,d4 + ii_shift_op1\3w \1,5,\2,d5 + ii_shift_op1\3w \1,6,\2,d6 + ii_shift_op1\3w \1,7,\2,d7 +.endm + +ii_shift_op2auw:.macro //byt: 1=code 2=operation + ii_shift_op1\3w \1,8,\2,d0_off+2(a7) + ii_shift_op1\3w \1,9,\2,d1_off+2(a7) + ii_shift_op1\3w \1,a,\2,d2 + ii_shift_op1\3w \1,b,\2,d3 + ii_shift_op1\3w \1,c,\2,d4 + ii_shift_op1\3w \1,d,\2,d5 + ii_shift_op1\3w \1,e,\2,d6 + ii_shift_op1\3w \1,f,\2,d7 +.endm + +ii_shift_op1aw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,w,\3r,#8,\4 + ii_shift_op0 2\1\2,w,\3r,#1,\4 + ii_shift_op0 4\1\2,w,\3r,#2,\4 + ii_shift_op0 6\1\2,w,\3r,#3,\4 + ii_shift_op0 8\1\2,w,\3r,#4,\4 + ii_shift_op0 a\1\2,w,\3r,#5,\4 + ii_shift_op0 c\1\2,w,\3r,#6,\4 + ii_shift_op0 e\1\2,w,\3r,#7,\4 + ii_shift_op0 1\1\2,w,\3l,#8,\4 + ii_shift_op0 3\1\2,w,\3l,#1,\4 + ii_shift_op0 5\1\2,w,\3l,#2,\4 + ii_shift_op0 7\1\2,w,\3l,#3,\4 + ii_shift_op0 9\1\2,w,\3l,#4,\4 + ii_shift_op0 b\1\2,w,\3l,#5,\4 + ii_shift_op0 d\1\2,w,\3l,#6,\4 + ii_shift_op0 f\1\2,w,\3l,#7,\4 +.endm + +ii_shift_op1bw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,w,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,w,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,w,\3r,d2,\4 + ii_shift_op0 6\1\2,w,\3r,d3,\4 + ii_shift_op0 8\1\2,w,\3r,d4,\4 + ii_shift_op0 a\1\2,w,\3r,d5,\4 + ii_shift_op0 c\1\2,w,\3r,d6,\4 + ii_shift_op0 e\1\2,w,\3r,d7,\4 + ii_shift_op0b 1\1\2,w,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,w,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,w,\3l,d2,\4 + ii_shift_op0 7\1\2,w,\3l,d3,\4 + ii_shift_op0 9\1\2,w,\3l,d4,\4 + ii_shift_op0 b\1\2,w,\3l,d5,\4 + ii_shift_op0 d\1\2,w,\3l,d6,\4 + ii_shift_op0 f\1\2,w,\3l,d7,\4 +.endm +// long --------------------------------------- +ii_shift_op2agl:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b) + ii_shift_op1\3l \1,0,\2,d0_off(a7) + ii_shift_op1\3l \1,1,\2,d1_off(a7) + ii_shift_op1\3l \1,2,\2,d2 + ii_shift_op1\3l \1,3,\2,d3 + ii_shift_op1\3l \1,4,\2,d4 + ii_shift_op1\3l \1,5,\2,d5 + ii_shift_op1\3l \1,6,\2,d6 + ii_shift_op1\3l \1,7,\2,d7 +.endm + +ii_shift_op2aul:.macro //byt: 1=code 2=operation + ii_shift_op1\3l \1,8,\2,d0_off(a7) + ii_shift_op1\3l \1,9,\2,d1_off(a7) + ii_shift_op1\3l \1,a,\2,d2 + ii_shift_op1\3l \1,b,\2,d3 + ii_shift_op1\3l \1,c,\2,d4 + ii_shift_op1\3l \1,d,\2,d5 + ii_shift_op1\3l \1,e,\2,d6 + ii_shift_op1\3l \1,f,\2,d7 +.endm + +ii_shift_op1al:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0 0\1\2,l,\3r,#8,\4 + ii_shift_op0 2\1\2,l,\3r,#1,\4 + ii_shift_op0 4\1\2,l,\3r,#2,\4 + ii_shift_op0 6\1\2,l,\3r,#3,\4 + ii_shift_op0 8\1\2,l,\3r,#4,\4 + ii_shift_op0 a\1\2,l,\3r,#5,\4 + ii_shift_op0 c\1\2,l,\3r,#6,\4 + ii_shift_op0 e\1\2,l,\3r,#7,\4 + ii_shift_op0 1\1\2,l,\3l,#8,\4 + ii_shift_op0 3\1\2,l,\3l,#1,\4 + ii_shift_op0 5\1\2,l,\3l,#2,\4 + ii_shift_op0 7\1\2,l,\3l,#3,\4 + ii_shift_op0 9\1\2,l,\3l,#4,\4 + ii_shift_op0 b\1\2,l,\3l,#5,\4 + ii_shift_op0 d\1\2,l,\3l,#6,\4 + ii_shift_op0 f\1\2,l,\3l,#7,\4 +.endm + +ii_shift_op1bl:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx + ii_shift_op0b 0\1\2,l,\3r,d0_off(a7),\4 + ii_shift_op0b 2\1\2,l,\3r,d1_off(a7),\4 + ii_shift_op0 4\1\2,l,\3r,d2,\4 + ii_shift_op0 6\1\2,l,\3r,d3,\4 + ii_shift_op0 8\1\2,l,\3r,d4,\4 + ii_shift_op0 a\1\2,l,\3r,d5,\4 + ii_shift_op0 c\1\2,l,\3r,d6,\4 + ii_shift_op0 e\1\2,l,\3r,d7,\4 + ii_shift_op0b 1\1\2,l,\3l,d0_off(a7),\4 + ii_shift_op0b 3\1\2,l,\3l,d1_off(a7),\4 + ii_shift_op0 5\1\2,l,\3l,d2,\4 + ii_shift_op0 7\1\2,l,\3l,d3,\4 + ii_shift_op0 9\1\2,l,\3l,d4,\4 + ii_shift_op0 b\1\2,l,\3l,d5,\4 + ii_shift_op0 d\1\2,l,\3l,d6,\4 + ii_shift_op0 f\1\2,l,\3l,d7,\4 +.endm +// .word ea ============================================ +ii_shift_op2ea:.macro //1=code 2.ziffer 2=shiftart +// (a0) bis (a7) ---------------------------- +ii_0xe\1d0: + move.l a0_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d1: + move.l a1_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d2: + ii_shift_typ w,\2,#1,(a2),(a2). +ii_0xe\1d3: + ii_shift_typ w,\2,#1,(a3),(a3). +ii_0xe\1d4: + ii_shift_typ w,\2,#1,(a4),(a4). +ii_0xe\1d5: + ii_shift_typ w,\2,#1,(a5),(a5). +ii_0xe\1d6: + ii_shift_typ w,\2,#1,(a6),(a6). +ii_0xe\1d7: + move.l usp,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// (a0)+ bis (a7)+ ----------------------------- +ii_0xe\1d8: + move.l a0_off(a7),a1 + addq.l #2,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1d9: + move.l a1_off(a7),a1 + addq.l #2,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1da: + ii_shift_typ w,\2,#1,(a2),(a2)+. +ii_0xe\1db: + ii_shift_typ w,\2,#1,(a3),(a3)+ +ii_0xe\1dc: + ii_shift_typ w,\2,#1,(a4),(a4)+ +ii_0xe\1dd: + ii_shift_typ w,\2,#1,(a5),(a5)+ +ii_0xe\1de: + ii_shift_typ w,\2,#1,(a6),(a6)+ +ii_0xe\1df: + move.l usp,a1 + addq.l #2,a1 + move.l a1,usp + subq.l #2,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// -(a0) bis -(a7) ----------------------------- +ii_0xe\1e0: + move.l a0_off(a7),a1 + subq.l #2,a1 + move.l a1,a0_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e1: + move.l a1_off(a7),a1 + subq.l #2,a1 + move.l a1,a1_off(a7) + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e2: + ii_shift_typ w,\2,#1,-(a2),(a2). +ii_0xe\1e3: + ii_shift_typ w,\2,#1,-(a3),(a3) +ii_0xe\1e4: + ii_shift_typ w,\2,#1,-(a4),(a4) +ii_0xe\1e5: + ii_shift_typ w,\2,#1,-(a5),(a5) +ii_0xe\1e6: + ii_shift_typ w,\2,#1,-(a6),(a6) +ii_0xe\1e7: + move.l usp,a1 + subq.l #2,a1 + move.l a1,usp + ii_shift_typ w,\2,#1,(a1),(a1). +// d16(a0) bis d16(a7) ----------------------------- +ii_0xe\1e8: + move.w (a0)+,a1 + add.l a0_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1e9: + move.w (a0)+,a1 + add.l a1_off(a7),a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1ea: + move.w (a0)+,a1 + add.l a2,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1eb: + move.w (a0)+,a1 + add.l a3,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ec: + move.w (a0)+,a1 + add.l a4,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ed: + move.w (a0)+,a1 + add.l a5,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ee: + move.w (a0)+,a1 + add.l a6,a1 + ii_shift_typ w,\2,#1,(a1),(a1) +ii_0xe\1ef: + mvs.w (a0)+,d0 + move.l usp,a1 + add.l d0,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +// d8(a0,dy) bis d8(a7,dy) ----------------------------- +ii_0xe\1f0: + move.l a0_off(a0),a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f1: + move.l a1_off(a0),a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f2: + move.l a2,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f3: + move.l a3,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f4: + move.l a4,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f5: + move.l a5,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f6: + move.l a6,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f7: + move.l usp,a1 + jsr ewf + ii_shift_typ w,\2,#1,(a1),(a1). +// xxx.w xxx.l +ii_0xe\1f8: + move.w (a0)+,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +ii_0xe\1f9: + move.l (a0)+,a1 + ii_shift_typ w,\2,#1,(a1),(a1). +.endm +//============================================================================ +//subroutine +//------------------------------ +ii_shift_op0:.macro // shift: 1=code 2=size 3=shift art 4=shift wert 5=ea +ii_0xe\1: + ii_shift_typ \2,\3,\4,\5,\5 +.endm + +ii_shift_op0b:.macro // shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea +ii_0xe\1: + move.l \4,d0 + ii_shift_typ \2,\3,d0,\5,\5 +.endm + +ii_shift_typ:.macro //1=size 2=shift art 3=shift wert 4=source 5=dest +#ifdef halten + halt +#endif +.ifc asr,\2 + mvs.\1 \4,d1 +.else + mvz.\1 \4,d1 +.endif +.ifc roxr,\2 + nop +.else + .ifc roxl,\2 + nop + .else + .ifc ror,\2 + nop + .else + .ifc rol,\2 + nop + .else + \2.l \3,d1 + .endif + .endif + .endif +.endif + set_cc0 + move.\1 d1,\5 + ii_end +.endm diff --git a/BaS_gcc/sources/ii_sub.h b/BaS_gcc/sources/ii_sub.h new file mode 100644 index 0000000..1405e1a --- /dev/null +++ b/BaS_gcc/sources/ii_sub.h @@ -0,0 +1,584 @@ +//-------------------------------------------------------------------- +// sub +//-------------------------------------------------------------------- +/*****************************************************************************************/ +//-------------------------------------------------------------------- +// byt +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// sub.b #im,dx +//-------------------------------------------------------------------- +subbir_macro:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,d0 + extb.l d0 + mvs.b \2,d1 + sub.l d0,d1 + set_cc0 + move.b d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea,dx +//-------------------------------------------------------------------- +subdd:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea(l)->dy(w),dx z.B. für USP +//-------------------------------------------------------------------- +subddd:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 a1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub (ea)->dy,dx +//-------------------------------------------------------------------- +subdda:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea->ay,(ay)+,dx +//-------------------------------------------------------------------- +subddai:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 (a1)+,d0 + move.l a1,\1 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub ea->ay,-(ay),dx +//-------------------------------------------------------------------- +subddad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.\3 -(a1),d0 + move.l a1,\1 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d16(ay),dx +//-------------------------------------------------------------------- +subd16ad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d8(ay,dy),dx +//-------------------------------------------------------------------- +subd8ad:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub xxx.w,dx +//-------------------------------------------------------------------- +subxwd:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub xxx.l,dx +//-------------------------------------------------------------------- +subxld:.macro +#ifdef halten_sub + halt +#endif + move.l (a0)+,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d16(pc),dx +//-------------------------------------------------------------------- +subd16pcd:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + mvs.w (a0)+,d0 + add.l d0,a1 + mvs.\3 (a1),d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub d8(pc,dy),dx +//-------------------------------------------------------------------- +subd8pcd:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf +.ifc \3,l + move.l (a1),d0 + move.l \2,d1 +.else + mvs.\3 (a1),d0 + mvs.\3 \2,d1 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// sub dy,ea +//-------------------------------------------------------------------- +//-------------------------------------------------------------------- +// // sub (ea)->dy,dx +//-------------------------------------------------------------------- +subeda:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +subedai:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1)+ + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,(ay)+ +//-------------------------------------------------------------------- +subedaid:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 \2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2+ + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +subedad:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.\3 -(a1),d1 + move.l a1,\2 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,ea->ay,-(ay) +//-------------------------------------------------------------------- +subedadd:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + mvs.\3 -\2,d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,d16(ay) +//-------------------------------------------------------------------- +sube16ad:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l \2,a1 + mvs.w (a0)+,d1 + add.l d1,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,d8(ay,dy) +//-------------------------------------------------------------------- +sube8ad:.macro +#ifdef halten_sub + halt +#endif + move.l \2,a1 + jsr ewf +.ifc \3,l + move.l (a1),d1 + move.l \1,d0 +.else + mvs.\3 (a1),d1 + mvs.\3 \1,d0 +.endif + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,xxx.w +//-------------------------------------------------------------------- +subxwe:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.w (a0)+,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- +// // sub dx,xxx.l +//-------------------------------------------------------------------- +subxle:.macro +#ifdef halten_sub + halt +#endif + mvs.\3 \1,d0 + move.l (a0)+,a1 + mvs.\3 (a1),d1 + sub.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +/******************************************************/ +// adress register +/******************************************************/ +//-------------------------------------------------------------------- +// // suba.w ea,ax +//-------------------------------------------------------------------- +subaw:.macro +#ifdef halten_sub + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + mvs.w \1,d0 + suba.l d0,\2 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// sub.w ea,usp +//-------------------------------------------------------------------- +subawa7:.macro +#ifdef halten_sub + halt +#endif + mvs.w \1,d0 + move.l usp,a1 + sub.l d0,a1 + move.l a1,usp + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w usp?,ax +//-------------------------------------------------------------------- +subawu:.macro +#ifdef halten_sub + halt +#endif + move.l a0,pc_off(a7) // pc auf next + movem.l (a7),d0/d1/a0/a1 // register zurpück + move.l a7,_a7_save + move.l usp,a7 + move.l \1,d0 + suba.l d0,\2 + move.l a7,usp + move.l _a7_save,a7 + move.l d0_off(a7),d0 + lea ii_ss(a7),a7 // stack erhöhen + rte + .endm; +//-------------------------------------------------------------------- +// // suba.w usp?,usp +//-------------------------------------------------------------------- +subawua7:.macro + subawu \1,\2 + .endm; +//-------------------------------------------------------------------- +// // suba.w d16(ay),ax +//-------------------------------------------------------------------- +subawd16a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + mvs.w (a0)+,d0 + adda.l d0,a1 + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d8(ay,dy),ax +//-------------------------------------------------------------------- +subawd8a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w xxx.w,ax +//-------------------------------------------------------------------- +subawxwax:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w xxx.l,ax +//-------------------------------------------------------------------- +subawxlax:.macro +#ifdef halten_sub + halt +#endif + move.l (a0)+,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d16(pc),ax +//-------------------------------------------------------------------- +subawd16pcax:.macro +#ifdef halten_sub + halt +#endif + move.w (a0)+,a1 + adda.l a0,a1 + mvs.w (a1),d0 + move.l \2,a1 + suba.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w d8(pc,dy),ax +//-------------------------------------------------------------------- +subawd8pcax:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf + mvs.w (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.w #im,ax +//-------------------------------------------------------------------- +subawim:.macro +#ifdef halten_sub + halt +#endif + mvs.w \1,d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.l d8(ay,dy),ax +//-------------------------------------------------------------------- +subald8a:.macro +#ifdef halten_sub + halt +#endif + move.l \1,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//-------------------------------------------------------------------- +// // suba.l d8(pc,dy),ax +//-------------------------------------------------------------------- +subakd8pcax:.macro +#ifdef halten_sub + halt +#endif + move.l a0,a1 + jsr ewf + move.l (a1),d0 + move.l \2,a1 + sub.l d0,a1 + move.l a1,\2 + ii_end + .endm; +//***************************************************************************************** +// subx +//***************************************************************************************** +//-------------------------------------------------------------------- +// // subx dy,dx +//-------------------------------------------------------------------- +subdx:.macro +#ifdef halten_sub + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + mvs.\3 \2,d0 + mvs.\3 \1,d1 + subx.l d0,d1 + set_cc0 + move.\3 d1,\1 + ii_end + .endm; +//-------------------------------------------------------------------- +// // subx -(ay),-(ax) +//-------------------------------------------------------------------- +subdax:.macro +#ifdef halten_sub + halt +#endif + move.b sr_off+1(a7),d0 //ccr holen + move d0,ccr //setzen + move.l \1,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d0 +.endif + move.l \2,a1 +.ifc \3,l + move.l -(a1),d0 +.else + mvs.\3 -(a1),d1 +.endif + subx.l d0,d1 + set_cc0 + move.\3 d1,(a1) + ii_end + .endm; +//-------------------------------------------------------------------- diff --git a/BaS_gcc/sources/illegal_instruction.S b/BaS_gcc/sources/illegal_instruction.S new file mode 100644 index 0000000..25b3f70 --- /dev/null +++ b/BaS_gcc/sources/illegal_instruction.S @@ -0,0 +1,328 @@ +.global _illegal_instruction +.global _illegal_table_make + +#include "startcf.h" +#include "ii_macro.h" +#include "ii_func.h" +#include "ii_op.h" +#include "ii_opc.h" +#include "ii_add.h" +#include "ii_sub.h" +#include "ii_or.h" +#include "ii_and.h" +#include "ii_dbcc.h" +#include "ii_shd.h" +#include "ii_movem.h" +#include "ii_lea.h" +#include "ii_shift.h" +#include "ii_exg.h" +#include "ii_movep.h" +#include "ii_ewf.h" +#include "ii_move.h" + +.extern _ii_shift_vec +.extern ewf + +/*******************************************************/ +.text +ii_error: + nop + halt + nop + nop + +_illegal_instruction: +#ifdef ii_on + move.w #0x2700,sr + lea -ii_ss(a7),a7 + movem.l d0/d1/a0/a1,(a7) + move.l pc_off(a7),a0 // pc + mvz.w (a0)+,d0 // code + lea table,a1 + move.l 0(a1,d0*4),a1 + jmp (a1) +/*************************************************************************************************/ +#endif +_illegal_table_make: +#ifdef ii_on + lea table,a0 + moveq #0,d0 +_itm_loop: + move.l #ii_error,(a0)+ + addq.l #1,d0 + cmp.l #0xF000,d0 + bne _itm_loop +//------------------------------------------------------------------------- + ii_ewf_lset // diverse fehlende adressierungn +//------------------------------------------------------------------------- +// 0x0000 +// ori + ii_lset_op 00 +// andi + ii_lset_op 02 +// subi + ii_lset_op 04 +// addi + ii_lset_op 06 +// eori + ii_lset_op 0a +// cmpi + ii_lset_op 0c +// movep + ii_movep_lset +//------------------------------------------------------------------------- +// 0x1000 move.b +// 0x2000 move.l +// 0x3000 move.w + ii_move_lset +//------------------------------------------------------------------------- +// 0x4000 +//------------------------------------------------------------------------- +// negx + ii_lset_op 40 +// neg + ii_lset_op 44 +// not + ii_lset_op 46 +//--------------------------------------------------------------------------------------------- +// lea d8(ax,dy.w),az; d8(pc,dy.w),az +//------------------------------------------------------------------- + ii_lea_lset +//------------------------------------------------------------------- +// movem +//------------------------------------------------------------------- + ii_movem_lset +//------------------------------------------------------------------------- +// 0x5000 +//------------------------------------------------------------------------- +// addq, subq + ii_lset_op 50 + ii_lset_op 51 + ii_lset_op 52 + ii_lset_op 53 + ii_lset_op 54 + ii_lset_op 55 + ii_lset_op 56 + ii_lset_op 57 + ii_lset_op 58 + ii_lset_op 59 + ii_lset_op 5a + ii_lset_op 5b + ii_lset_op 5c + ii_lset_op 5d + ii_lset_op 5e + ii_lset_op 5f +// dbcc + ii_lset_dbcc +// scc + ii_lset_opc 50 + ii_lset_opc 51 + ii_lset_opc 52 + ii_lset_opc 53 + ii_lset_opc 54 + ii_lset_opc 55 + ii_lset_opc 56 + ii_lset_opc 57 + ii_lset_opc 58 + ii_lset_opc 59 + ii_lset_opc 5a + ii_lset_opc 5b + ii_lset_opc 5c + ii_lset_opc 5d + ii_lset_opc 5e + ii_lset_opc 5f +//------------------------------------------------------------------------- +// 0x8000 or +//------------------------------------------------------------------------- + ii_lset_func 8 +//------------------------------------------------------------------------- +// 0x9000 sub +//------------------------------------------------------------------------- + ii_lset_func 9 +//------------------------------------------------------------------------- +// 0xb000 +//------------------------------------------------------------------------- +// eor + ii_lset_op b1 + ii_lset_op b3 + ii_lset_op b5 + ii_lset_op b7 + ii_lset_op b9 + ii_lset_op bb + ii_lset_op bd + ii_lset_op bf +//------------------------------------------------------------------------- +// 0xc000 +//------------------------------------------------------------------------- +// and + ii_lset_func c +// exg + ii_exg_lset +//------------------------------------------------------------------------- +// 0xd000 add +//------------------------------------------------------------------------- + ii_lset_func d +//------------------------------------------------------------------------- +// 0xe000 +//------------------------------------------------------------------------- +// shift register + ii_shift_lset e +//------------------------------------------------- +// differenz zwischen orginal und gemoved korrigieren + lea ii_error(pc),a1 + move.l a1,d1 + sub.l #ii_error,d1 + lea table,a0 + moveq #0,d0 +_itkorr_loop: + add.l d1,(a0)+ + addq.l #1,d0 + cmp.l #0xF000,d0 + bne _itkorr_loop +#endif + rts +#ifdef ii_on +//***********************************************************************************/ +//------------------------------------------------------------------------- + ii_ewf_func // diverse fehlende adressierungn +//------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x0000 +//-------------------------------------------------------------------- +// ori 00 + ii_op 00,or.l,i +//-------------------------------------------------------------------- +// andi 02 + ii_op 02,and.l,i +//-------------------------------------------------------------------- +// subi 04 + ii_op 04,and.l,i +//-------------------------------------------------------------------- +// addi 06 + ii_op 06,add.l,i +//-------------------------------------------------------------------- +// eori 0a + ii_op 0a,eor.l,i +//-------------------------------------------------------------------- +// cmpi 0c + ii_op 0c,cmp.l,i +//-------------------------------------------------------------------- +// movep + ii_movep_func +///--------------------------------------------------------------------------------------------- +// 0x1000 move.b +// 0x2000 move.l +// 0x3000 move.w + ii_move_op +//--------------------------------------------------------------------------------------------- +// 0x4000 +//--------------------------------------------------------------------------------------------- +// neg 0x40.. + ii_op 40,negx.l,n +//--------------------------------------------------------------------------------------------- +// neg 0x44.. + ii_op 44,neg.l,n +//--------------------------------------------------------------------------------------------- +// not 0x46.. + ii_op 46,not.l,n +//--------------------------------------------------------------------------------------------- +// lea d8(ax,dy.w),az; d8(pc,dy.w),az +//------------------------------------------------------------------- + ii_lea_func +//------------------------------------------------------------------- +// movem +//-------------------------------------------------------------------- +ii_movem_func +//--------------------------------------------------------------------------------------------- +// 0x5000 +//--------------------------------------------------------------------------------------------- +//dbcc + ii_dbcc_func +// addq 0x5... + ii_op 50,addq.l #8,q + ii_op 52,addq.l #1,q + ii_op 54,addq.l #2,q + ii_op 56,addq.l #3,q + ii_op 58,addq.l #4,q + ii_op 5a,addq.l #5,q + ii_op 5c,addq.l #6,q + ii_op 5e,addq.l #7,q +//--------------------------------------------------------------------------------------------- +// subq 0x5... + ii_op 51,subq.l #8,q + ii_op 53,subq.l #1,q + ii_op 55,subq.l #2,q + ii_op 57,subq.l #3,q + ii_op 59,subq.l #4,q + ii_op 5b,subq.l #5,q + ii_op 5d,subq.l #6,q + ii_op 5f,subq.l #7,q +//--------------------------------------------------------------------------------------------- +// 0x5... scc + ii_opc 50,st,c + ii_opc 51,sf,c + ii_opc 52,shi,c + ii_opc 53,sls,c + ii_opc 54,scc,c + ii_opc 55,scs,c + ii_opc 56,sne,c + ii_opc 57,seq,c + ii_opc 58,svc,c + ii_opc 59,svs,c + ii_opc 5a,spl,c + ii_opc 5b,smi,c + ii_opc 5c,sge,c + ii_opc 5d,slt,c + ii_opc 5e,sgt,c + ii_opc 5f,sle,c +//--------------------------------------------------------------------------------------------- +// 0x6000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x7000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0x8000 +//--------------------------------------------------------------------------------------------- +// or + ii_func 8,or +//--------------------------------------------------------------------------------------------- +// 0x9000 +//--------------------------------------------------------------------------------------------- +// sub + ii_func 9,sub +//--------------------------------------------------------------------------------------------- +// 0xa000 +//-------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------- +// 0xb000 +//--------------------------------------------------------------------------------------------- +// eor + ii_op b1,eor.l d0,q + ii_op b3,eor.l d1,q + ii_op b5,eor.l d2,q + ii_op b7,eor.l d3,q + ii_op b9,eor.l d4,q + ii_op bb,eor.l d5,q + ii_op bd,eor.l d6,q + ii_op bf,eor.l d7,q +//--------------------------------------------------------------------------------------------- +// 0xc000 +//--------------------------------------------------------------------------------------------- +// and + ii_func c,and +// exg + ii_exg_func +//--------------------------------------------------------------------------------------------- +// 0xd000 +//--------------------------------------------------------------------------------------------- +// add + ii_func d,add +//--------------------------------------------------------------------------------------------- +// 0xe000 shift +//-------------------------------------------------------------------- + ii_shift_op +//-------------------------------------------------------------------- +// 0xf000 +//-------------------------------------------------------------------- +#endif diff --git a/BaS_gcc/sources/init_fpga.c b/BaS_gcc/sources/init_fpga.c new file mode 100644 index 0000000..f0f0b43 --- /dev/null +++ b/BaS_gcc/sources/init_fpga.c @@ -0,0 +1,102 @@ +/* + * init_fpga.c + * + * Created on: 16.10.2012 + * Author: Markus Fröschle + */ +#include +#include "sysinit.h" + +#define FPGA_STATUS (1 << 0) +#define FPGA_CLOCK (1 << 1) +#define FPGA_CONFIG (1 << 2) +#define FPGA_DATA0 (1 << 3) +#define FPGA_CONF_DONE (1 << 5) + +extern void xprintf_before_copy(const char *fmt, ...); +extern void display_progress_before_copy(void); +extern void wait_10ms(); + +#define xprintf xprintf_before_copy +#define display_progress display_progress_before_copy +/* + * load FPGA + */ +void init_fpga(void) +{ + register uint8_t *fpga_data; + register int i; + + xprintf("FPGA load data...\r\n"); + + + MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */ + MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */ + + while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); + MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high */ + while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS)); /* wait until status becomes high */ + + /* + * excerpt from an Altera configuration manual: + * + * The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The + * configuration cycle consists of 3 stages�reset, configuration, and initialization. + * While nCONFIG is low, the device is in reset. When the device comes out of reset, + * nCONFIG must be at a logic high level in order for the device to release the open-drain + * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA + * is ready to receive configuration data. Before and during configuration, all user I/O pins + * are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors + * on the I/O pins which are on, before and during configuration. + * + * To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay + * configuration by holding the nCONFIG low. The device receives configuration data on its + * DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After + * the FPGA has received all configuration data successfully, it releases the CONF_DONE pin, + * which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates + * configuration is complete and initialization of the device can begin. + */ + fpga_data = (uint8_t *) FPGA_FLASH_DATA; + do + { + uint8_t value = *fpga_data++; + + if (((int) fpga_data % 0x100) == 0) { + xprintf("%08x ", fpga_data); + display_progress(); + } + + for (i = 0; i < 8; i++, value >>= 1) + { + + if (value & 1) + { + /* bit set -> toggle DATA0 to high */ + MCF_GPIO_PODR_FEC1L |= FPGA_DATA0; + } + else + { + /* bit is cleared -> toggle DATA0 to low */ + MCF_GPIO_PODR_FEC1L &= ~FPGA_DATA0; + } + /* toggle DCLK -> FPGA reads the bit */ + MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK; + MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; + } + } while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END)); + + if (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END) + { + for (i = 0; i < 4000; i++) + { + /* toggle a little more since it's fun ;) */ + MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK; + MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; + } + xprintf("finished\r\n"); + } + else + { + xprintf("FAILED!\r\n"); + } +} diff --git a/BaS_gcc/sources/macro.h b/BaS_gcc/sources/macro.h new file mode 100644 index 0000000..2afa44e --- /dev/null +++ b/BaS_gcc/sources/macro.h @@ -0,0 +1,10 @@ +/*******************************************************/ +// allgemeine macros +/*******************************************************/ +.text +wait_pll: .macro +wait1_pll\@: + tst.w (a1) + bmi wait1_pll\@ + rts +.endm diff --git a/BaS_gcc/sources/mmu.S b/BaS_gcc/sources/mmu.S new file mode 100644 index 0000000..6e0765c --- /dev/null +++ b/BaS_gcc/sources/mmu.S @@ -0,0 +1,195 @@ +/* + * INIT ACR and MMU + */ + +#include "startcf.h" + + .extern _rt_vbr + .extern _rt_cacr + .extern _rt_asid + .extern _rt_acr0 + .extern _rt_acr1 + .extern _rt_acr2 + .extern _rt_acr3 + .extern _rt_mmubar + .extern ___MMUBAR + .extern cpusha + .extern _video_tlb + .extern _video_sbt + .extern __TOS + +/* Register read/write macros */ +#define MCF_MMU_MMUCR __MMUBAR +#define MCF_MMU_MMUOR __MMUBAR+0x04 +#define MCF_MMU_MMUSR __MMUBAR+0x08 +#define MCF_MMU_MMUAR __MMUBAR+0x10 +#define MCF_MMU_MMUTR __MMUBAR+0x14 +#define MCF_MMU_MMUDR __MMUBAR+0x18 + + +/* Bit definitions and macros for MCF_MMU_MMUCR */ +#define MCF_MMU_MMUCR_EN (0x1) +#define MCF_MMU_MMUCR_ASM (0x2) + +/* Bit definitions and macros for MCF_MMU_MMUOR */ +#define MCF_MMU_MMUOR_UAA (0x1) +#define MCF_MMU_MMUOR_ACC (0x2) +#define MCF_MMU_MMUOR_RW (0x4) +#define MCF_MMU_MMUOR_ADR (0x8) +#define MCF_MMU_MMUOR_ITLB (0x10) +#define MCF_MMU_MMUOR_CAS (0x20) +#define MCF_MMU_MMUOR_CNL (0x40) +#define MCF_MMU_MMUOR_CA (0x80) +#define MCF_MMU_MMUOR_STLB (0x100) +#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10) + +/* Bit definitions and macros for MCF_MMU_MMUSR */ +#define MCF_MMU_MMUSR_HIT (0x2) +#define MCF_MMU_MMUSR_WF (0x8) +#define MCF_MMU_MMUSR_RF (0x10) +#define MCF_MMU_MMUSR_SPF (0x20) + +/* Bit definitions and macros for MCF_MMU_MMUAR */ +#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_MMU_MMUTR */ +#define MCF_MMU_MMUTR_V (0x1) +#define MCF_MMU_MMUTR_SG (0x2) +#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2) +#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA) + +/* Bit definitions and macros for MCF_MMU_MMUDR */ +#define MCF_MMU_MMUDR_LK (0x2) +#define MCF_MMU_MMUDR_X (0x4) +#define MCF_MMU_MMUDR_W (0x8) +#define MCF_MMU_MMUDR_R (0x10) +#define MCF_MMU_MMUDR_SP (0x20) +#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6) +#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8) +#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA) + +#define std_mmutr (MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V) +#define mmuord_d ( MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define mmuord_i (MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA) +#define wt_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define cb_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) +#define nc_mmudr (MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X) + + .global _mmu_init + .global _mmutr_miss + +.text +_mmu_init: + move.l d3,-(sp) // Backup registers + move.l d2,-(sp) + + clr.l d0 + movec d0,ASID // ASID allways 0 + move.l d0,_rt_asid // sichern + + move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff + movec d0,ACR0 + move.l d0,_rt_acr0 // sichern + + move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff + movec d0,ACR1 + move.l d0,_rt_acr1 // sichern + + move.l #0xe007C400,d0 // instruction r wt e000'0000-e07f'ffff + movec d0,ACR2 + move.l d0,_rt_acr2 // sichern + + clr.l d0 // acr3 aus + movec d0,ACR3 + move.l d0,_rt_acr3 // sichern + + move.l #__MMUBAR+1,d0 + movec d0,MMUBAR //mmubar setzen + move.l d0,_rt_mmubar // sichern + + nop + + move.l #MCF_MMU_MMUOR_CA,d0 // clear all entries, + move.l d0,MCF_MMU_MMUOR + nop +// 0000'0000 locked + moveq.l #0x00000000|std_mmutr,d0 + moveq.l #0x00000000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + moveq.l #mmuord_d,d2 // MMU update date + moveq.l #mmuord_i,d3 // MMU update instruction + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // MMU update date + move.l d3,MCF_MMU_MMUOR // MMU update instruction + +//--------------------------------------------------------------------------------------- +// 00d0'0000 locked ID=6 +// video ram: read write execute normal write true + move.l #0x00d00000|MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0 + move.l #0x60d00000|wt_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // MMU update date + move.l #0x00d00000|std_mmutr,d0 + move.l d3,MCF_MMU_MMUOR // MMU update instruction + + move.l #0x2000,d0 + move.l d0,_video_tlb // set page as video page + clr.l _video_sbt // clear time +//------------------------------------------------------------------------------------- +// Make the TOS (in SDRAM) read-only + move.l #__TOS+std_mmutr,d0 + move.l #__TOS+cb_mmudr+MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen read only ?????? noch nicht + move.l d3,MCF_MMU_MMUOR // setzen +// 00f0'0000 locked + move.l #0x00f00000|std_mmutr,d0 + move.l #0xfff00000|nc_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // maped to ffffxxx, precise, + move.l d3,MCF_MMU_MMUOR // maped to ffffxxx, precise, +// 1fe0'0000 locked + move.l #0x1FE00000|std_mmutr,d0 + move.l #0x1FE00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen data + move.l d3,MCF_MMU_MMUOR // setzen instr +// 1ff0'0000 locked + move.l #0x1FF00000|std_mmutr,d0 + move.l #0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d2,MCF_MMU_MMUOR // setzen data + move.l d3,MCF_MMU_MMUOR // setzen instr +// instr 0xFFF0'0000 nach 0x1FF0'0000 umleiten -->> short sprung +/* move.l #0xFFF00000|std_mmutr,d0 + move.l #0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1 + move.l d0,MCF_MMU_MMUTR + move.l d1,MCF_MMU_MMUDR + move.l d3,MCF_MMU_MMUOR // setzen instr +*/ + move.l (sp)+,d2 // Restore registers + move.l (sp)+,d3 + rts + +/* + * MMU table search + */ +_mmutr_miss: + bsr cpusha + and.l #0xFFF00000,d0 + or.l #std_mmutr,d0 + move.l d0,MCF_MMU_MMUTR + and.l #0xFFF00000,d0 + or.l #cb_mmudr,d0 + move.l d0,MCF_MMU_MMUDR + moveq.l #mmuord_d,d0 // MMU update data + move.l d0,MCF_MMU_MMUOR // setzen + moveq.l #mmuord_i,d0 // MMU update instruction + move.l d0,MCF_MMU_MMUOR // setzen + move.l (sp)+,d0 + rte diff --git a/BaS_gcc/sources/printf_helper.S b/BaS_gcc/sources/printf_helper.S new file mode 100644 index 0000000..7bb8a12 --- /dev/null +++ b/BaS_gcc/sources/printf_helper.S @@ -0,0 +1,12 @@ +// assembler trampoline to let printf (compiled -mpcrel) indirectly reference __MBAR + + .global printf_helper +printf_helper: + .extern __MBAR +.wait_txready: + move.w __MBAR+0x8604,d2 // PSCSCR0 status register + btst #10,d2 // space left in TX fifo? + beq.s .wait_txready // no, loop + lea __MBAR+0x860C,a0 // PSCSTB0 transmitter buffer register + move.b d0,(a0) // send byte + rts diff --git a/BaS_gcc/sources/sd_card.c b/BaS_gcc/sources/sd_card.c new file mode 100644 index 0000000..15a8c39 --- /dev/null +++ b/BaS_gcc/sources/sd_card.c @@ -0,0 +1,37 @@ +/* + * sd card + */ + +#include +#include + +void sd_card_idle(void) +{ + __asm__ __volatile__ ( + ".extern sd_idle\n\t" + "bsr sd_idle\n\t" + /* output */: + /* input */ : + /* clobber */: "a0","a1","a2","a3","a4","a5", + "d0","d1","d2","d3","d4","d5","d6","d7","memory" + ); +} + + + +int sd_card_init(void) +{ + register int ret __asm__("d0"); + + __asm__ __volatile__ ( + ".extern sd_init\n\t" + "bsr.l sd_init\n\t" + /* output */: "=r" (ret) + /* input */ : + /* clobber */: "a0","a1","a2","a3","a4","a5", + "d1","d2","d3","d4","d5","d6","d7","memory" + ); + + return ret; +} + diff --git a/BaS_gcc/sources/sd_card_asm.S b/BaS_gcc/sources/sd_card_asm.S new file mode 100644 index 0000000..fac7935 --- /dev/null +++ b/BaS_gcc/sources/sd_card_asm.S @@ -0,0 +1,439 @@ +/********************************************************************/ +// sd card +/********************************************************************/ +#define dspi_dtar0 0x0c +#define dspi_dsr 0x2c +#define dspi_dtfr 0x34 +#define dspi_drfr 0x38 + +#define LONGASC(a, b, c, d) ((a << 24) | (b << 16) | (c << 8) | (d)) + +#define MCF_PAD_PAR_DSPI (__MBAR+0xA50) +#define MCF_PSC0_PSCTB_8BIT (__MBAR+0x860C) +#define MCF_DSPI_DMCR (__MBAR+0x8A00) +#define MCF_SLT0_SCNT (__MBAR + 0x908) + + .text + +warte_10ms: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #1320000,d0 +warte_d6: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d6 + move.l (sp)+,d0 + rts + +warte_1ms: + move.l d0,-(sp) + move.l MCF_SLT0_SCNT,d0 + sub.l #132000,d0 +warte_d5: + cmp.l MCF_SLT0_SCNT,d0 + bcs warte_d5 + move.l (sp)+,d0 + rts + + .global sd_idle + .global sd_init + +sd_init: + lea MCF_PSC0_PSCTB_8BIT,a6 + move.l #LONGASC('S', 'D', '-', 'C'),(a6) + move.l #LONGASC('a', 'r', 'd', ' '),(a6) + + move.l buffer,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!) + move.l #0x1fffffff,d0 // normal dspi + move.l d0,MCF_PAD_PAR_DSPI + lea MCF_DSPI_DMCR,a0 + move.l #0x800d3c00,(a0) // 8 bit cs5 on + move.l #0x38558897,d0 + move.l d0,dspi_dtar0(a0) // 400kHz + move.l #0x082000ff,d4 // tx vorbesetzen + mov3q.l #-1,dspi_dsr(a0) + + bsr.l warte_1ms + move.l #0xc00d3c00,(a0) // 8 bit 4MHz clocken cs off + bsr.l warte_10ms + move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + bsr sd_com + move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off + clr.b d4 + bsr sd_com + bsr sd_com + move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on + move.b #0xff,d4 + bsr sd_com + bsr sd_com + move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off + bsr.l warte_10ms + +// sd idle + move.l #100,d6 // 100 versuche + move.l #10,d3 // 10 versuche +sd_idle: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x40,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + move.b #0xff,d4 // receive byt + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + bsr sd_com + cmp.b #0x01,d5 + beq idle_end + subq.l #1,d6 + beq sd_not + bra sd_idle +idle_end: +// cdm 8 +read_ic: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x48,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + move.b #0xaa,d4 + bsr sd_com + move.b #0x87,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #5,d5 + beq sd_v1 + cmp.b #1,d5 + bne read_ic + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com + cmp.b #0xaa,d5 + bne sd_testd3 + move.l #LONGASC('S', 'D', 'H', 'C'),(a6) + move.b #' ',(a6) +sd_v1: + +// cdm 58 +read_ocr: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x7a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + bsr sd_get_status + move.l #LONGASC('V', 'e', 'r', '1'),d6 + cmp.b #5,d5 + beq read_ocr + cmp.b #1,d5 + bne read_ocr + + move.b #0xff,d4 + bsr sd_com + move.b d5,d0 + bsr sd_com + move.b d5,d1 + bsr sd_com + move.b d5,d2 + bsr sd_com + +// acdm 41 + move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen +wait_of_aktiv: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x77,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + cmp.b #0x05,d5 + beq wait_of_aktiv + +wait_of_aktiv2: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x69,d4 + bsr sd_com + move.b #0x40,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + bsr sd_get_status + tst.b d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq wait_of_aktiv2 + subq.l #1,d6 + bne wait_of_aktiv +sd_testd3: + subq.l #1,d3 + bne sd_idle + bra sd_error + +sd_init_ok: +// cdm 10 +read_cid: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x4a,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x95,d4 + bsr sd_com + + move.l a5,a4 // adresse setzen + bsr sd_rcv_info + +// name ausgeben + lea 1(a5),a4 + moveq #7,d7 +sd_nam_loop: + move.b (a4)+,(a6) + subq.l #1,d7 + bne sd_nam_loop + move.b #' ',(a6) + +// cdm 9 +read_csd: + move.b #0xff,d4 // receive byt + bsr sd_com + move.b #0x49,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x00,d4 + bsr sd_com + move.b #0x01,d4 + bsr sd_com + + move.l a5,a4 // adresse setzen + bsr sd_rcv_info + + mvz.b (a5),d0 + lsr.l #6,d0 + + bne sd_csd2 // format v2 + move.l 6(a5),d1 + moveq #14,d0 // bit 73..62 c_size + lsr.l d0,d1 // bits extrahieren + and.l #0xfff,d1 // 12 bits + addq.l #1,d1 + mvz.w 9(a5),d0 + lsr.l #7,d0 // bits 49..47 + and.l #0x7,d0 // 3 bits + moveq.l #8,d2 // x256 (dif v1 v2) + sub.l d0,d2 + lsr.l d2,d1 + bra sd_print_size +sd_csd2: + mvz.w 8(a5),d1 + addq.l #1,d1 +sd_print_size: + swap d1 + lsl.l #1,d1 + bcc sd_16G + move.l #LONGASC('3', '2', 'G', 'B'),(a6) + bra sd_ok +sd_16G: + lsl.l #1,d1 + bcc sd_8G + move.l #LONGASC('1', '6', 'G', 'B'),(a6) + bra sd_ok +sd_8G: + lsl.l #1,d1 + bcc sd_4G + move.l #LONGASC(' ', '4', 'G', 'B'),(a6) + bra sd_ok +sd_4G: + lsl.l #1,d1 + bcc sd_2G + move.l #LONGASC(' ', '4', 'G', 'B'),(a6) + bra sd_ok +sd_2G: + lsl.l #1,d1 + bcc sd_1G + move.l #LONGASC(' ', '2', 'G', 'B'),(a6) + bra sd_ok +sd_1G: + lsl.l #1,d1 + bcc sd_512M + move.l #LONGASC(' ', '1', 'G', 'B'),(a6) + bra sd_ok +sd_512M: + lsl.l #1,d1 + bcc sd_256M + move.b #'5',(a6) + move.l #LONGASC('1', '2', 'M', 'B'),(a6) + bra sd_ok +sd_256M: + lsl.l #1,d1 + bcc sd_128M + move.b #'2',(a6) + move.l #LONGASC('5', '6', 'M', 'B'),(a6) + bra sd_ok +sd_128M: + lsl.l #1,d1 + bcc sd_64M + move.b #'1',(a6) + move.l #LONGASC('2', '8', 'M', 'B'),(a6) + bra sd_ok +sd_64M: + lsl.l #1,d1 + bcc sd_32M + move.l #LONGASC('6', '4', 'M', 'B'),(a6) + bra sd_ok +sd_32M: + lsl.l #1,d1 + bcc sd_16M + move.l #LONGASC('3', '2', 'M', 'B'),(a6) + bra sd_ok +sd_16M: + lsl.l #1,d1 + bcc sd_8M + move.l #LONGASC('1', '6', 'M', 'B'),(a6) + bra sd_ok +sd_8M: + move.l #LONGASC('<', '9', 'M', 'B'),(a6) +sd_ok: + move.l #LONGASC(' ', 'O', 'K', '!'),(a6) + move.l #0x0a0d,(a6) + //halt + //halt + rts +// subs ende ------------------------------- +sd_V1: + move.l #LONGASC('n', 'o', 'n', '!'),(a6) + move.l #0x0a0d,(a6) + //halt + //halt + rts +sd_error: + move.l #LONGASC('E', 'r', 'r', 'o'),(a0) + move.l #LONGASC('r', '!', '', ''), (a0) + move.l #0x0a0d,(a6) + halt + halt + rts +sd_not: + move.l #LONGASC('n', 'o', 'n', '!'),(a0) + move.l #0x0a0d,(a6) + halt + halt + rts + +// status holen ------------------------------- +sd_get_status: + move.b #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_get_status + rts +// byt senden und holen --------------------- +sd_com: + move.l d4,dspi_dtfr(a0) +wait_auf_complett: + btst.b #7,dspi_dsr(a0) + beq wait_auf_complett + move.l dspi_drfr(a0),d5 + mov3q.l #-1,dspi_dsr(a0) // clr status register + rts + +// daten holen ---------------------------- +sd_rcv_info: + moveq #18,d3 // 16 byts + 2 byts crc + move.b #0xff,d4 +sd_rcv_rb_w: + bsr sd_get_status + cmp.b #0xfe,d5 // daten bereit? + bne sd_rcv_rb_w // nein-> +sd_rcv_rd_rb: + bsr sd_com + move.b d5,(a4)+ + subq.l #1,d3 + bne sd_rcv_rd_rb + rts +/******************************************/ + + .data +buffer: dc.l 0, 0, 0, 0, 0, 0, 0, 0 diff --git a/BaS_gcc/sources/sd_ide.c b/BaS_gcc/sources/sd_ide.c new file mode 100644 index 0000000..ffbde9d --- /dev/null +++ b/BaS_gcc/sources/sd_ide.c @@ -0,0 +1,540 @@ +#include "MCF5475.h" +#include "startcf.h" + + + +/* imported routines */ +//extern int warten_20ms(); +//extern int warten_200us(); +//extern int warten_10us(); + +/********************************************************************/ +void asm sd_test(void) +{ + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgr�sse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} + + +/**************************************************/ +void asm ide_test(void) +{ + lea MCF_PAD_PAR_DSPI,a0 + move.w #0x1fff,(a0) + lea MCF_DSPI_DCTAR0,a0 + move.l #0x38a644e4,(a0) + lea MCF_DSPI_DMCR,a0 + move.l #0x802d3c00,(a0) + clr.l MCF_DSPI_DTCR + bsr warten_20ms + lea MCF_DSPI_DTFR,a0 + lea MCF_DSPI_DRFR,a1 + + moveq #10,d0 +sd_reset: + move.l #0x000100ff,(a0) + bsr warten_20ms + and.l (a1),d0 + subq.l #1,d0 + bne sd_reset + + moveq #10,d1 +sd_loop1: + bsr warten_20ms + moveq #-1,d0 +// cmd 0 set to idle + move.l #0x00200040,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200095,(a0) + bsr warten_20ms + and.l (a1),d0 + cmp.w #0x0001,d0 + beq sd_loop2 + subq.l #1,d1 + bne sd_loop1 + moveq #10,d1 + bra sd_test +sd_loop2: + moveq #-1,d0 +// cmd 41 + move.l #0x00200069,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200000,(a0) + bsr warten_20ms + and.l (a1),d0 + move.l #0x00200001,(a0) + bsr warten_20ms + and.l (a1),d0 + tst.w d0 + bne sd_loop2 + + nop + nop +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zur�ck + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst.b #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +} +/********************************************************************/ diff --git a/BaS_gcc/sources/sd_ide.s b/BaS_gcc/sources/sd_ide.s new file mode 100644 index 0000000..4d31184 --- /dev/null +++ b/BaS_gcc/sources/sd_ide.s @@ -0,0 +1,458 @@ + + +//.include "startcf.h" + +//.extern ___MBAR +//#define MCF_SLT0_SCNT ___MBAR+0x908 + +//.global ide_test + +.text +/* +sd_test: + clr.w MCF_PAD_PAR_DSPI + lea MCF_GPIO_PPDSDR_DSPI,a2 // data in + lea MCF_GPIO_PODR_DSPI,a1 // data out + move.b #0x00,(a1) // alle auf 0 + lea MCF_GPIO_PDDR_DSPI,a0 + move.b #0x7d,(a0) // din = input rest output + + bsr warten_20ms + + move.b #0x7f,(a1) // alle auf 1 + + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk + bsr sd_16clk +// sd idle +sd_idle: + bsr sd_16clk + moveq #0x40,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x95,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x05,d5 + beq sd_test + cmp.b #0x01,d5 + beq wait_of_aktiv + cmp.b #0x04,d5 + beq sd_init_ok + cmp.b #0x00,d5 + beq sd_init_ok + bra sd_idle + +// acdm 41 +wait_of_aktiv: + bsr sd_16clk + + moveq #0x77,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + bsr sd_16clk + + move.l #0xff,d6 + moveq #0x69,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x02,d4 + bsr sd_com + and d5,d6 + moveq #00,d4 + bsr sd_com + and d5,d6 + moveq #0x01,d4 + bsr sd_com + and d5,d6 + + bsr sd_receive + + cmp.b #0x00,d5 + beq sd_init_ok + cmp.b #0x05,d5 + beq sd_test + bra wait_of_aktiv + +sd_init_ok: + +// blockgrösse 512byt +sd_bg: + bsr sd_16clk + moveq #0x50,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #02,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_bg + +// read block +sd_rb: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb + + lea 0xc00000,a4 + move.l #513,d7 +rd_rb: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb + +// write block +sd_wb: + bsr sd_16clk + moveq #0x58,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_wb + + lea 0xc00000,a4 + move.l #513,d7 + moveq.l #0x66,d4 +wr_wb: + bsr sd_com +// subq.l #1,d4 + moveq #0x66,d4 + subq.l #1,d7 + bne wr_wb + + bsr sd_receive + +wr_wb_el: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + bne wr_wb_el + + +// read block 2 +sd_rb2: + bsr sd_16clk + moveq #0x51,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x08,d4 + bsr sd_com + moveq #00,d4 + bsr sd_com + moveq #0x01,d4 + bsr sd_com + + bsr sd_receive + + cmp.b #0x00,d5 + bne sd_rb2 + + lea 0xc00400,a4 + move.l #513,d7 +rd_rb2: + bsr sd_receive + move.b d5,(a4)+ + subq.l #1,d7 + bne rd_rb2 + + + nop + nop + + rts + +sd_receive: + moveq #0xff,d4 + bsr sd_com + cmp.b #0xff,d5 + beq sd_receive + rts + +sd_com: + bclr.b #6,(a1) +sd_comb: + bsr warten_10us + moveq #7,d2 + clr.l d5 +sd_com_loop: + btst d2,d4 + beq sd_com2 + bset.b #0,(a1) + bra sd_com2_1 +sd_com2: + bclr.b #0,(a1) +sd_com2_1: + bsr sd_clk + and.l #0x02,d3 + beq sd_com3 + bset.b d2,d5 +sd_com3: + subq.l #1,d2 + bge sd_com_loop + bsr warten_10us + bset.b #6,(a1) + bset.b #0,(a1) + bsr warten_200us + rts +sd_clk: + tst.b 0xfffff700 + tst.b 0xfffff700 + bset.b #2,(a1) + tst.b 0xfffff700 + tst.b 0xfffff700 + move.b (a2),d3 + tst.b 0xfffff700 + bclr.b #2,(a1) + rts + +sd_15clk: + move #15,d0 + bra sd_16clk +sd_16clk: + moveq #16,d0 +sd_16clk1: + bsr sd_clk + subq.l #1,d0 + bne sd_16clk1 + bsr warten_10us + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +/********************************************************************/ +#define cmd_reg (0x1d) +#define status_reg (0x1d) +#define seccnt (0x09) + +ide_test: + lea 0xfff00040,a0 + lea 0xc00000,a1 + move.b #0xec,cmd_reg(a0) //identify devcie cmd + bsr wait_int + bsr ds_rx +// read sector normal + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read cmd + bsr wait_int + bsr ds_rx + +// write testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write cmd + bsr drq_wait +// write pattern + move.l #256,d0 +ide_test_loop3: + move.w #0xa55a,(a0) + subq.l #1,d0 + bne ide_test_loop3 + bsr wait_int +// read testpattern sector + move.b #1,seccnt(a0) // 1 sector + move.b #0x20,cmd_reg(a0) // read + bsr wait_int + bsr ds_rx +// sector restauriern + move.b #1,seccnt(a0) // 1 sector + move.b #0x30,cmd_reg(a0) // write + lea -0x400(a1),a1 // vorletzer + bsr drq_wait + bsr ds_tx + bsr wait_int +// fertig und zurück + nop + rts +// wait auf int +wait_int: + move.b 0xfffffa01,d0 + btst #5,d0 + bne wait_int + move.b status_reg(a0),d0 + rts +// wait auf drq +drq_wait: + move.b status_reg(a0),d0 + btst #3,d0 + beq drq_wait + rts + +// 1 sector lesen word +ds_rx: + move.l #256,d0 +ds_rx_loop: + move.w (a0),(a1)+ + subq.l #1,d0 + bne ds_rx_loop + rts +// 1 sector lesen long +ds_rxl: + move.l #128,d0 +ds_rxl_loop: + move.l (a0),(a1)+ + subq.l #1,d0 + bne ds_rxl_loop + rts +// 1 sector schreiben word +ds_tx: + move.l #256,d0 +ds_tx_loop: + move.w (a1)+,(a0) + subq.l #1,d0 + bne ds_tx_loop + rts +// 1 sector schreiben word +ds_txl: + move.l #128,d0 +ds_txl_loop: + move.l (a1)+,(a0) + subq.l #1,d0 + bne ds_txl_loop + rts +// warteschleife ca. 20ms +warten_20ms: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #700000,d6 + bra warten_loop +// warteschleife ca. 200us +warten_200us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #7000,d6 + bra warten_loop +// warteschleife ca. 10us +warten_10us: + move.l a0,-(sp) + move.l d6,-(sp) + move.l d1,-(sp) + move.l d0,-(sp) + lea MCF_SLT0_SCNT,a0 + move.l (a0),d0 + move.l #333,d6 +warten_loop: + move.l (a0),d1 + sub.l d0,d1 + add.l d6,d1 + bpl warten_loop + move.l (sp)+,d0 + move.l (sp)+,d1 + move.l (sp)+,d6 + move.l (sp)+,a0 + rts; +/********************************************************************/ diff --git a/BaS_gcc/sources/startcf.S b/BaS_gcc/sources/startcf.S new file mode 100644 index 0000000..118acd9 --- /dev/null +++ b/BaS_gcc/sources/startcf.S @@ -0,0 +1,63 @@ +/* This object file must be the first to be linked, + * so it will be placed at the very beginning of the ROM. + */ + + .equ MCF_MMU_MMUCR, __MMUBAR + 0 + + .global _rom_header + .global _rom_entry + + .extern _initialize_hardware + .extern _rt_mbar + +/* ROM header */ +_rom_header: + /* The first long is supposed to be the initial SP. + * We replace it by bra.s to allow running the ROM from the first byte. + * Then we add a fake jmp instruction for pretty disassembly. + */ + bra.s _rom_entry // Short jump to the real entry point + .short 0x4ef9 // Fake jmp instruction + + /* The second long is the initial PC */ + .long _rom_entry // Real entry point + +/* ROM entry point */ +_rom_entry: + /* disable interrupts */ + move.w #0x2700,SR + + /* Initialize MBAR */ + move.l #__MBAR,d0 + movec d0,MBAR + move.l d0,_rt_mbar + + /* mmu off */ + move.l #__MMUBAR+1,d0 + movec d0,MMUBAR + + clr.l d0 + move.l d0,MCF_MMU_MMUCR + + /* Initialize RAMBARs: locate SRAM and validate it */ + move.l #__RAMBAR0 + 0x7,%d0 /* supervisor only */ + movec d0,RAMBAR0 + move.l #__RAMBAR1 + 0x1,d0 + movec d0,RAMBAR1 + + /* set stack pointer to end of SRAM1 */ + lea __SUP_SP,a7 + + /* Initialize the processor caches. + * The instruction cache is fully enabled. + * The data cache is enabled, but cache-inhibited by default. + * Later, the MMU will fully activate the data cache for specific areas. + * It is important to enable both caches now, otherwise cpushl would hang. + */ + move.l #0xa50c8120,d0 + movec d0,cacr + andi.l #0xfefbfeff,d0 // Clear invalidate bits + move.l d0,_rt_cacr + + /* initialize any hardware specific issues */ + bra _initialize_hardware diff --git a/BaS_gcc/sources/startcf.h b/BaS_gcc/sources/startcf.h new file mode 100644 index 0000000..67a9d9d --- /dev/null +++ b/BaS_gcc/sources/startcf.h @@ -0,0 +1,25 @@ + +#define cf_stack + +//#define ii_on +#define halten +#define halten_dbcc +#define halten_and +#define halten_add +#define halten_sub +#define halten_or +#define halten_op +#define halten_opc +#define halten_movem +#define halten_lea +#define halten_shift +#define halten_move +#define halten_exg +#define halten_movep +#define halten_ewf + +#define DIP_SWITCH (*(volatile uint8_t *)(&_MBAR[0xA2C])) +#define DIP_SWITCHa __MBAR + 0xA2C + +#define sca_page_ID 6 + diff --git a/BaS_gcc/sources/supervisor.S b/BaS_gcc/sources/supervisor.S new file mode 100644 index 0000000..b637348 --- /dev/null +++ b/BaS_gcc/sources/supervisor.S @@ -0,0 +1,565 @@ +/* + * user/supervisor handler + */ + +#include "startcf.h" +#define cf_stack + +.extern _rt_cacr; +.extern _rt_mod; +.extern _rt_ssp; +.extern _rt_usp; +.extern ___MMUBAR +.extern _flush_and_invalidate_caches + +/* Register read/write macros */ +#define MCF_MMU_MMUCR __MMUBAR +#define MCF_MMU_MMUOR __MMUBAR+0x04 +#define MCF_MMU_MMUSR __MMUBAR+0x08 +#define MCF_MMU_MMUAR __MMUBAR+0x10 +#define MCF_MMU_MMUTR __MMUBAR+0x14 +#define MCF_MMU_MMUDR __MMUBAR+0x18 + +.global _privileg_violation +.global cpusha + +.text +_privileg_violation: + move.w #0x2700,sr + lea -12(a7),a7 + movem.l d0/a0/a5,(a7) +#ifndef cf_stack + lea 0x52f0,a0 + move.l #0x20,(a0) // set auf 68030 +#endif + lea _rt_mod,a0 // zugriff setzen + tst.b (a0) // vom rt_supervisormodus? + bne pv_work // ja-> +// tats�chlich privileg violation + mov3q.l #-1,(a0) // sr_mod setzen + move.l usp,a5 // usp holen + move.l a5,8(a0) // sichern + move.l 4(a0),a5 // rt_ssp holen +#ifdef cf_stack + move.l 16(a7),-(a5) // pc verschieben + move.l 12(a7),-(a5) // sr verschieben + bset #5,2(a5) // auf super setzen +#else + move.w 12(a7),-(a5) // vector nr. + move.l 16(a7),-(a5) // pc verschieben + move.w 14(a7),-(a5) // sr verschieben + bset #5,(a5) // auf super +#endif + move.l a5,usp + move.l 12(a0),a5 // rt_vbr + lea 0x18(a5),a5 // vector + move.l (a5),16(a7) // vector privileg violation + movem.l (a7),d0/a0/a5 // register zur�ck + lea 12(a7),a7 + rte +// privileg violation +pv_work: + move.l 16(a7),a5 // fault pc + move.b (a5),d0 // fault code + cmp.b #0x4e,d0 // 1.byt 0x4e + beq pv_4e // ja-> + cmp.b #0x46,d0 // 1.byt 0x46 + beq pv_46 // ja-> + cmp.b #0x40,d0 // 1.byt 0x40 + beq pv_40 // ja-> + cmp.b #0xf4,d0 // 0xf4? + beq pv_f4 + cmp.b #0xf3,d0 // 0xf3? + beq pv_f3 +// hierher sollt man nicht kommen + nop + halt + nop +// code 0x4exx ******************************************** +pv_4e: + move.b 1(a5),d0 + cmp.b #0x73,d0 //rte? + beq pv_rte //ja-> + cmp.b #0x72,d0 //stop? + beq pv_stop //ja-> + cmp.b #0x7B,d0 //movec? + beq pv_movec //ja-> +// move usp + btst #3,d0 // to or from + bne pv_usp_to_ax // usp -> ax +// move ax->usp + cmp.b #0x60,d0 //movec? + beq pv_a0_usp //ja-> + cmp.b #0x61,d0 //movec? + beq pv_a1_usp //ja-> + cmp.b #0x62,d0 //movec? + beq pv_a2_usp //ja-> + cmp.b #0x63,d0 //movec? + beq pv_a3_usp //ja-> + cmp.b #0x64,d0 //movec? + beq pv_a4_usp //ja-> + cmp.b #0x65,d0 //movec? + beq pv_a5_usp //ja-> + cmp.b #0x66,d0 //movec? + beq pv_a6_usp //ja-> + halt + bra pv_a7_usp //ja-> +// move usp->ax +pv_usp_to_ax: + move.l 8(a0),a5 //rt_usp holen + cmp.b #0x68,d0 //movec? + beq pv_usp_a0 //ja-> + cmp.b #0x69,d0 //movec? + beq pv_usp_a1 //ja-> + cmp.b #0x6a,d0 //movec? + beq pv_usp_a2 //ja-> + cmp.b #0x6b,d0 //movec? + beq pv_usp_a3 //ja-> + cmp.b #0x6c,d0 //movec? + beq pv_usp_a4 //ja-> + cmp.b #0x6d,d0 //movec? + beq pv_usp_a5 //ja-> + cmp.b #0x6e,d0 //movec? + beq pv_usp_a6 //ja-> +// usp->a7 + move.l a5,4(a0) // rt usp -> rt ssp + move.l a5,usp // und setzen + bra pv_usp_ax +// a0->usp +pv_a0_usp: move.l 4(a7),a5 + bra pv_ax_usp +// a1->usp +pv_a1_usp: move.l a1,a5 + bra pv_ax_usp +// a2->usp +pv_a2_usp: move.l a2,a5 + bra pv_ax_usp +// a3->usp +pv_a3_usp: move.l a3,a5 + bra pv_ax_usp +// a4->usp +pv_a4_usp: move.l a4,a5 + bra pv_ax_usp +// a5->usp +pv_a5_usp: move.l 8(a7),a5 + bra pv_ax_usp +// a6->usp +pv_a6_usp: move.l a6,a5 + bra pv_ax_usp +// a7->usp +pv_a7_usp: move.l 4(a0),a5 // rt_ssp -> a5 +pv_ax_usp: + move.l a5,8(a0) // usp -> rt_usp + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zur�ck + lea 12(a7),a7 + rte +// usp->a0 +pv_usp_a0: + move.l a5,4(a7) + bra pv_usp_ax +pv_usp_a1: + move.l a5,a1 + bra pv_usp_ax +pv_usp_a2: + move.l a5,a2 + bra pv_usp_ax +pv_usp_a3: + move.l a5,a3 + bra pv_usp_ax +pv_usp_a4: + move.l a5,a4 + bra pv_usp_ax +pv_usp_a5: + move.l a5,8(a7) + bra pv_usp_ax +pv_usp_a6: + move.l a5,a6 +pv_usp_ax: + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zur�ck + lea 12(a7),a7 + rte +// rte +pv_rte: + move.l usp,a5 +#ifdef cf_stack + move.l (a5)+,12(a7) // sr verschieben + move.l (a5)+,16(a7) // pc verschieben +#else + move.w (a5)+,14(a7) // sr verschieben + move.l (a5)+,16(a7) // pc verschieben + move.w (a5)+,12(a7) // vector +#endif + bclr #5,14(a7) // war es von super? + bne pv_rte_sup // ja-> + clr.l (a0) // rt_mod auf user + move.l a5,4(a0) // rt_ssp sichern + move.l 8(a0),a5 // rt_usp holen +pv_rte_sup: + move.l a5,usp // usp setzen + movem.l (a7),d0/a0/a5 // register zur�ck + lea 12(a7),a7 + rte +// stop +pv_stop: + move.b 2(a5),d0 // sr wert + and.l #0x0700,d0 // int mask + cmp.w #0x700,d0 + beq stop7 + cmp.w #0x600,d0 + beq stop6 + cmp.w #0x500,d0 + beq stop5 + cmp.w #0x400,d0 + beq stop4 + cmp.w #0x300,d0 + beq stop3 + cmp.w #0x200,d0 + beq stop2 + cmp.w #0x100,d0 + beq stop1 + stop #0x2000 + bra stop_weiter +stop1: + stop #0x2100 + bra stop_weiter +stop2: + stop #0x2200 + bra stop_weiter +stop3: + stop #0x2300 + bra stop_weiter +stop4: + stop #0x2400 + bra stop_weiter +stop5: + stop #0x2500 + bra stop_weiter +stop6: + stop #0x2600 + bra stop_weiter +stop7: + stop #0x2700 +stop_weiter: + addq.l #4,16(a7) // next + movem.l (a7),d0/a0/a5 // register zur�ck + lea 12(a7),a7 + rte +// movec ??????? +pv_movec: + move.w 2(a5),d0 // 2.word holen + and.l #0xf000,d0 + btst #15,d0 // addressregister? + bne pv_movec_ax // ja-> + tst.w d0 // d0? + bne pvm_d1 // nein-> + move.l (a7),-(a7) // d0 holen und sichern + bra pvm_me +pvm_d1: + cmp.w #0x1000,d0 // d1? + bne pvm_d2 // nein-> + move.l d1,-(a7) // d1 holen und sichern + bra pvm_me // fertig machen +pvm_d2: + cmp.w #0x2000,d0 // d1? + bne pvm_d3 // nein-> + move.l d2,-(a7) // d2 holen und sichern + bra pvm_me // fertig machen +pvm_d3: + cmp.w #0x3000,d0 // d1? + bne pvm_d4 // nein-> + move.l d3,-(a7) // d3 holen und sichern + bra pvm_me // fertig machen +pvm_d4: + cmp.w #0x4000,d0 // d1? + bne pvm_d5 // nein-> + move.l d4,-(a7) // d4 holen und sichern + bra pvm_me // fertig machen +pvm_d5: + cmp.w #0x5000,d0 // d1? + bne pvm_d6 // nein-> + move.l d5,-(a7) // d5 holen und sichern + bra pvm_me // fertig machen +pvm_d6: + cmp.w #0x6000,d0 // d1? + bne pvm_d7 // nein-> + move.l d6,-(a7) // d6 holen und sichern + bra pvm_me // fertig machen +pvm_d7: + move.l d7,-(a7) // d7 holen und sichern + bra pvm_me // fertig machen +pv_movec_ax: + cmp.w #0x8000,d0 // a0? + bne pvm_a1 // nein-> + move.l 4(a7),-(a7) // a0 holen und sichern + bra pvm_me // fertig machen +pvm_a1: + cmp.w #0x9000,d0 // a0? + bne pvm_a2 // nein-> + move.l a1,-(a7) // a1 holen und sichern + bra pvm_me // fertig machen +pvm_a2: + cmp.w #0xa000,d0 // a0? + bne pvm_a3 // nein-> + move.l a2,-(a7) // a2 holen und sichern + bra pvm_me // fertig machen +pvm_a3: + cmp.w #0xb000,d0 // a0? + bne pvm_a4 // nein-> + move.l a3,-(a7) // a3 holen und sichern + bra pvm_me // fertig machen +pvm_a4: + cmp.w #0xc000,d0 // a0? + bne pvm_a5 // nein-> + move.l a4,-(a7) // a4 holen und sichern + bra pvm_me // fertig machen +pvm_a5: + cmp.w #0xd000,d0 // a0? + bne pvm_a6 // nein-> + move.l 8(a7),-(a7) // a5 holen und sichern + bra pvm_me // fertig machen +pvm_a6: + cmp.w #0xe000,d0 // a0? + bne pvm_a7 // nein-> + move.l a6,-(a7) // a6 holen und sichern + bra pvm_me // fertig machen +pvm_a7: + move.l 4(a7),-(a7) // a7 holen und sichern +pvm_me: + move.w 2(a5),d0 // 2.word holen + andi.l #0xf,d0 // nur letzte 4 bits + move.l (a7)+,8(a0,d0*4) // start bei +8, *4 weil long + jsr cpusha // gesammten cache flushen + rte +// code 0x46xx ***************************************** +pv_46: + move.b 1(a5),d0 + cmp.b #0xfc,d0 //#d16->sr + beq im_sr //ja-> +//move dx->sr (sr und rt_mod ist supervisor sonst w�re es privileg violation + cmp.b #0xc0,d0 //d0->sr? + bne d1_sr //nein-> + move.w 2(a7),d0 //hier ist d0 gesichert + bra d0_sr +d1_sr: + cmp.b #0xc1,d0 //d1->sr? + bne d2_sr //nein-> + move.w d1,d0 + bra d0_sr +d2_sr: + cmp.b #0xc2,d0 //d2->sr? + bne d3_sr + move.w d2,d0 + bra d0_sr +d3_sr: + cmp.b #0xc3,d0 //d3->sr? + bne d4_sr + move.w d3,d0 + bra d0_sr +d4_sr: + cmp.b #0xc4,d0 //d4->sr? + bne d5_sr + move.w d4,d0 + bra d0_sr +d5_sr: + cmp.b #0xc5,d0 //d5->sr? + bne d6_sr + move.w d5,d0 + bra d0_sr +d6_sr: + cmp.b #0xc6,d0 //d6->sr? + bne d7_sr + move.w d6,d0 + bra d0_sr +d7_sr: + move.w d7,d0 // sonst d7->sr +d0_sr: + addq.l #2,16(a7) // next + bra pv_set_sr_end // fertig machen +// move #xxxx,sr +im_sr: + addq.l #4,16(a7) // next + move.w 2(a5),d0 // data +pv_set_sr_end: + bclr #13,d0 // war super? + bne pv_sre2 // ja -> + clr.l (a0) + move.l usp,a5 // usp + move.l a5,4(a0) // rt_ssp speichern + move.l 8(a0),a5 // rt_usp holen + move.l a5,usp // setzen +pv_sre2: + move.w d0,14(a7) // sr setzen + movem.l (a7),d0/a0/a5 // register zur�ck + lea 12(a7),a7 + rte +// code 0x40xx ***************************************** +pv_40: + move.b 1(a5),d0 // 2.byt + cmp.b #0xe7,d0 + beq pv_strldsr +// move sr->dx + move.l 12(a7),a5 // sr holen + tst.b (a0) // super? + beq pv_40_user // nein? + lea 0x2000(a5),a5 // super zuaddieren +pv_40_user: + cmp.b #0xc0,d0 + bne nsr_d1 + move.w a5,2(a7) + bra sr_dx_end +nsr_d1: + cmp.b #0xc1,d0 + bne nsr_d2 + move.w a5,d1 + bra sr_dx_end +nsr_d2: + cmp.b #0xc2,d0 + bne nsr_d3 + move.w a5,d2 + bra sr_dx_end +nsr_d3: + cmp.b #0xc3,d0 + bne nsr_d4 + move.w a5,d3 + bra sr_dx_end +nsr_d4: + cmp.b #0xc4,d0 + bne nsr_d5 + move.w a5,d4 + bra sr_dx_end +nsr_d5: + cmp.b #0xc5,d0 + bne nsr_d6 + move.w a5,d5 + bra sr_dx_end +nsr_d6: + cmp.b #0xc6,d0 + bne nsr_d7 + move.w a5,d6 + bra sr_dx_end +nsr_d7: + move.w a5,d7 + halt +sr_dx_end: + addq.l #2,16(a7) // next + movem.l (a7),d0/a0/a5 // register zur�ck + lea 12(a7),a7 + rte +// strldsr +pv_strldsr: + nop + halt + nop +// code 0xf4xx *********************************** +pv_f4: + addq.l #2,16(a7) // next instr + move.b 1(a5),d0 // 2.byt + bsr pv_ax_a0 // richtiges register + move.b 1(a5),d0 // 2.byt + cmp.b #0x30,d0 // >0xf430 + blo pv_intouch +// cpushl + cpushl bc,(a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +pv_intouch: + intouch a0 + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +// subroutine register ax->a0 +pv_ax_a0: + and.l #0x7,d0 // nur register nummer + subq.l #1,d0 + bmi pv_a0_a0 + subq.l #1,d0 + bmi pv_a1_a0 + subq.l #1,d0 + bmi pv_a2_a0 + subq.l #1,d0 + bmi pv_a3_a0 + subq.l #1,d0 + bmi pv_a4_a0 + subq.l #1,d0 + bmi pv_a5_a0 + subq.l #1,d0 + bmi pv_a6_a0 + move.l a7,a0 + rts +pv_a0_a0: + move.l 8(a7),a0 + rts +pv_a1_a0: + move.l a1,a0 + rts +pv_a2_a0: + move.l a2,a0 + rts +pv_a3_a0: + move.l a3,a0 + rts +pv_a4_a0: + move.l a4,a0 + rts +pv_a5_a0: + move.l 12(a7),a0 + rts +pv_a6_a0: + move.l a6,a0 + rts +// code 0xf4xx *********************************** +pv_f3: + addq.l #2,16(a7) // next instr + move.b 1(a5),d0 // 2. byt + cmp.b #0x40,d0 + bgt pv_frestore +//fsave (ax) oder d16(ax) + jsr pv_ax_a0 // richtiges register holen + move.b 1(a5),d0 + cmp.b #0x20,d0 +// +d16 + blt pv_f3_ax + addq.l #2,16(a7) // next instr + clr.l d0 + move.w 2(a0),d0 // d16 + add.l d0,a0 +pv_f3_ax: + fsave (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +pv_frestore: + cmp.b #0x7a,d0 + beq pv_f_d16pc +// frestore (ax) oder d16(ax) + jsr pv_ax_a0 // richtiges register holen + move.b 1(a5),d0 + cmp.b #0x60,d0 + blt pv_frestore_ax +pv_fend: + addq.l #2,16(a7) // next instr + clr.l d0 + move.w 2(a0),d0 // d16 + add.l d0,a0 +pv_frestore_ax: + frestore (a0) + movem.l (a7),d0/a0/a5 + lea 12(a7),a7 + rte +// frestore d16(pc) +pv_f_d16pc: + move.l 16(a7),a0 // pc holen + bra pv_fend +//***************************************************** +cpusha: + lea -16(a7),a7 + movem.l d0-d1/a0-a1,(a7) // backup C trash registers + jsr _flush_and_invalidate_caches + movem.l (a7),d0-d1/a0-a1 // restore C trash registers + lea 16(a7),a7 + rts +//*******************************************************33 + diff --git a/BaS_gcc/sources/sysinit.c b/BaS_gcc/sources/sysinit.c new file mode 100644 index 0000000..515be71 --- /dev/null +++ b/BaS_gcc/sources/sysinit.c @@ -0,0 +1,796 @@ +/* + * File: sysinit.c + * Purpose: Power-on Reset configuration of the Firebee board. + * + * Notes: + * + */ + +#include "MCF5475.h" +#include "startcf.h" +#include "cache.h" +#include "sysinit.h" +#include "bas_printf.h" + +extern void xprintf_before_copy(const char *fmt, ...); +#define xprintf xprintf_before_copy +extern void flush_and_invalidate_caches_before_copy(void); +#define flush_and_invalidate_caches flush_and_invalidate_caches_before_copy + +#define UNUSED(x) (void)(x) /* Unused variable */ + +extern volatile long _VRAM; /* start address of video ram from linker script */ + +/* + * wait for the specified number of us on slice timer 0. Replaces the original routines that had + * the number of useconds to wait for hardcoded in their name. + */ +void wait(uint32_t us) +{ + uint32_t target = MCF_SLT_SCNT(0) - (us * 132); + + while (MCF_SLT_SCNT(0) > target); +} + + +/* + * init SLICE TIMER 0 + * all = 32.538 sec = 30.736mHz + * BYT0 = 127.1ms/tick = 7.876Hz offset 0 + * BYT1 = 496.5us/tick = 2.014kHz offset 1 + * BYT2 = 1.939us/tick = 515.6kHz offset 2 + * BYT3 = 7.576ns/tick = 132.00MHz offset 3 + * count down!!! 132MHz!!! + */ +void init_slt(void) +{ + xprintf("slice timer initialization: "); + MCF_SLT0_STCNT = 0xffffffff; + MCF_SLT0_SCR = MCF_SLT_SCR_TEN | MCF_SLT_SCR_RUN; /* enable and run continuously */ + xprintf("finished\r\n"); +} + +/* + * init GPIO general purpose I/O module + */ +void init_gpio(void) +{ + /* + * pad register P.S.:FBCTL and FBCS set correctly at reset + */ + + /* + * configure all four 547x GPIO module DMA pins: + * + * /DACK1 - DMA acknowledge 1 + * /DACK0 - DMA acknowledge 0 + * /DREQ1 - DMA request 1 + * /DREQ0 - DMA request 0 + * + * for DMA operation + */ + MCF_PAD_PAR_DMA = MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 | + MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 | + MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 | + MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0; + + /* + * configure FEC0 pin assignment on GPIO module as FEC0 + * configure FEC1 pin assignment (PAR_E17, PAR_E1MII) as GPIO, + * /IRQ5 and /IRQ6 from GPIO (needs to be disabled on EPORT module, which also can + * use those INTs). + */ + MCF_PAD_PAR_FECI2CIRQ = MCF_PAD_PAR_FECI2CIRQ_PAR_E07 | + MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII | + MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO | + MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC | + MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO | + MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC | + MCF_PAD_PAR_FECI2CIRQ_PAR_SDA | + MCF_PAD_PAR_FECI2CIRQ_PAR_SCL | + MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 | + MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5; + + /* + * configure PCI Grant pin assignment on GPIO module: + * + * /PCIBG4 used as FlexBus /TBST + * /PCIBG3 used as general purpose I/O + * /PCIBG2 used as /PCIBG2 + * /PCIBG1 used as /PCIBG1 + * /PCIBG0 used as /PCIBG0 + */ + MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST | + MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO | + MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0; + + /* + * configure PCI request pin assignment on GPIO module: + * /PCIBR4 as /IRQ4 + * /PCIBR3 as GPIO (PIC) + * /PCIBR2 as /PCIBR2 + * /PCIBR1 as /PCIBR1 + * /PCIBR0 as /PCIBR0 + */ + MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO | + MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0; + + /* + * configure PSC3 pin assignment on GPIO module: + * /PSC3CTS as /PSC3PTS + * /PSC3RTS as /PSC3RTS + * PSC3RXD as PSC3RXD + * PSC3TXD as PSC3TXD + */ + + MCF_PAD_PAR_PSC3 = MCF_PAD_PAR_PSC3_PAR_TXD3 | MCF_PAD_PAR_PSC3_PAR_RXD3; + + /* + * Configure PSC1 pin assignment on GPIO module: + * - all pins configured for serial interface operation + */ + + MCF_PAD_PAR_PSC1 = MCF_PAD_PAR_PSC1_PAR_CTS1_CTS | + MCF_PAD_PAR_PSC1_PAR_RTS1_RTS | + MCF_PAD_PAR_PSC1_PAR_RXD1 | + MCF_PAD_PAR_PSC1_PAR_TXD1; + + /* + * Configure PSC0 Pin Assignment on GPIO module: + * - all pins configured for serial interface operation + */ + + MCF_PAD_PAR_PSC0 = MCF_PAD_PAR_PSC0_PAR_CTS0_CTS | + MCF_PAD_PAR_PSC0_PAR_RTS0_RTS | + MCF_PAD_PAR_PSC0_PAR_RXD0 | + MCF_PAD_PAR_PSC0_PAR_TXD0; + + MCF_PAD_PAR_DSPI = 0b0001111111111111; /* DSPI NORMAL */ + + MCF_PAD_PAR_TIMER = 0b00101101; /* TIN3..2=#IRQ3..2;TOUT3..2=NORMAL */ + + // ALLE OUTPUTS NORMAL LOW + + + // ALLE DIR NORMAL INPUT = 0 + MCF_GPIO_PDDR_FEC1L = 0b00011110; /* OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA) */ +} + +/* + * init serial + */ +void init_serial(void) +{ + /* PSC0: SER1 */ + MCF_PSC0_PSCSICR = 0; /* PSC control register: select UART mode */ + MCF_PSC0_PSCCSR = 0xDD; /* use TX and RX baud rate from PSC timer */ + MCF_PSC0_PSCCTUR = 0x00; /* =\ */ + MCF_PSC0_PSCCTLR = 36; /* divide sys_clk by 36 => BAUD RATE = 115200 bps */ + MCF_PSC0_PSCCR = 0x20; /* reset receiver and RxFIFO */ + MCF_PSC0_PSCCR = 0x30; /* reset transmitter and TxFIFO */ + MCF_PSC0_PSCCR = 0x40; /* reset all error status */ + MCF_PSC0_PSCCR = 0x50; /* reset break change interrupt */ + MCF_PSC0_PSCCR = 0x10; /* reset MR pointer */ + MCF_PSC0_PSCIMR = 0x8700; /* enable input port change interrupt, enable delta break interrupt, */ + /* enable receiver interrupt/request, enable transceiver interrupt/request */ + + MCF_PSC0_PSCACR = 0x03; /* enable state change of CTS */ + MCF_PSC0_PSCMR1 = 0xb3; /* 8 bit, no parity */ + MCF_PSC0_PSCMR2 = 0x07; /* 1 stop bit */ + MCF_PSC0_PSCRFCR = 0x0F; + MCF_PSC0_PSCTFCR = 0x0F; + MCF_PSC0_PSCRFAR = 0x00F0; + MCF_PSC0_PSCTFAR = 0x00F0; + MCF_PSC0_PSCOPSET = 0x01; + MCF_PSC0_PSCCR = 0x05; + + /* PSC3: PIC */ + MCF_PSC3_PSCSICR = 0; // UART + MCF_PSC3_PSCCSR = 0xDD; + MCF_PSC3_PSCCTUR = 0x00; + MCF_PSC3_PSCCTLR = 36; // BAUD RATE = 115200 + MCF_PSC3_PSCCR = 0x20; + MCF_PSC3_PSCCR = 0x30; + MCF_PSC3_PSCCR = 0x40; + MCF_PSC3_PSCCR = 0x50; + MCF_PSC3_PSCCR = 0x10; + MCF_PSC3_PSCIMR = 0x0200; // receiver interrupt enable + MCF_PSC3_PSCACR = 0x03; + MCF_PSC3_PSCMR1 = 0xb3; + MCF_PSC3_PSCMR2 = 0x07; + MCF_PSC3_PSCRFCR = 0x0F; + MCF_PSC3_PSCTFCR = 0x0F; + MCF_PSC3_PSCRFAR = 0x00F0; + MCF_PSC3_PSCTFAR = 0x00F0; + MCF_PSC3_PSCOPSET = 0x01; + MCF_PSC3_PSCCR = 0x05; + MCF_INTC_ICR32 = 0x3F; //MAXIMALE PRIORITY/**********/ + + xprintf("serial interfaces initialization: finished\r\n"); +} + +/********************************************************************/ +/* Initialize DDR DIMMs on the EVB board */ +/********************************************************************/ +void init_ddram(void) +{ + xprintf("SDRAM controller initialization: "); + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) { + /* Basic configuration and initialization */ + MCF_SDRAMC_SDRAMDS = 0x000002AA;/* SDRAMDS configuration */ + MCF_SDRAMC_CS0CFG = 0x0000001A; /* SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) */ + MCF_SDRAMC_CS1CFG = 0x0800001A; /* SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) */ + MCF_SDRAMC_CS2CFG = 0x1000001A; /* SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF) */ + MCF_SDRAMC_CS3CFG = 0x1800001A; /* SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) */ + MCF_SDRAMC_SDCFG1 = 0x73622830; /* SDCFG1 */ + MCF_SDRAMC_SDCFG2 = 0x46770000; /* SDCFG2 */ + MCF_SDRAMC_SDCR = 0xE10D0002; /* SDCR + IPALL */ + MCF_SDRAMC_SDMR = 0x40010000; /* SDMR (write to LEMR) */ + MCF_SDRAMC_SDMR = 0x048D0000; /* SDRM (write to LMR) */ + MCF_SDRAMC_SDCR = 0xE10D0002; /* SDCR + IPALL */ + MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (first refresh) */ + MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (second refresh) */ + MCF_SDRAMC_SDMR = 0x008D0000; /* SDMR (write to LMR) */ + MCF_SDRAMC_SDCR = 0x710D0F00; /* SDCR (lock SDMR and enable refresh) */ + + xprintf("finished\r\n"); + } + else + { + xprintf("skipped. Already initialized (running from RAM)\r\n"); + } +} + +/* + * initialize FlexBus chip select registers + */ +void init_fbcs() +{ + xprintf("FlexBus chip select registers initialization: "); + + /* Flash */ + MCF_FBCS0_CSAR = 0xE0000000; /* flash base address */ + MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 | + MCF_FBCS_CSCR_WS(4)| + MCF_FBCS_CSCR_AA; + MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM_8M | + MCF_FBCS_CSMR_V; /* 8 MByte on */ + + MCF_FBCS1_CSAR = 0xFFF00000; /* ATARI I/O ADRESS */ + MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */ + | MCF_FBCS_CSCR_WS(8) /* DEFAULT 8WS */ + | MCF_FBCS_CSCR_AA; /* AA */ + MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V; + + MCF_FBCS2_CSAR = 0xF0000000; // NEUER I/O ADRESS-BEREICH + MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT + | MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS + | MCF_FBCS_CSCR_AA; // AA + MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M // F000'0000-F7FF'FFFF + | MCF_FBCS_CSMR_V); + + MCF_FBCS3_CSAR = 0xF8000000; // NEUER I/O ADRESS-BEREICH + MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT + | MCF_FBCS_CSCR_AA; // AA + MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M // F800'0000-FBFF'FFFF + | MCF_FBCS_CSMR_V); + + MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BENÃœTZT, DECODE DIREKT AUF DEM FPGA + MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT + | MCF_FBCS_CSCR_BSTR // BURST READ ENABLE + | MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE + MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF + | MCF_FBCS_CSMR_V; + + xprintf("finished\r\n"); +} + + +void wait_pll(void) +{ + uint32_t trgt = MCF_SLT0_SCNT - 100000; + do + { + ; + } while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt); +} + +static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600; + +void init_pll(void) +{ + xprintf("FPGA PLL initialization: "); + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x48) = 27; /* loopfilter r */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */ + + wait_pll(); + * (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */ + + wait_pll(); + + * (volatile uint8_t *) 0xf0000800 = 0; /* set */ + + xprintf("finished\r\n"); +} + + + +/* + * INIT VIDEO DDR RAM + */ + +#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") + +void init_video_ddr(void) { + xprintf("init video RAM: "); + + * (volatile uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */ + NOP(); + + _VRAM = 0x00050400; /* IPALL */ + NOP(); + + _VRAM = 0x00072000; /* load EMR pll on */ + NOP(); + + _VRAM = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */ + NOP(); + + _VRAM = 0x00050400; /* IPALL */ + NOP(); + + _VRAM = 0x00060000; /* auto refresh */ + NOP(); + + _VRAM = 0x00060000; /* auto refresh */ + NOP(); + + _VRAM = 0000070022; /* load MR dll on */ + NOP(); + + * (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */ + + xprintf("finished\r\n"); +} + + +#define PCI_MEMORY_OFFSET (0x80000000) +#define PCI_MEMORY_SIZE (0x40000000) +#define PCI_IO_OFFSET (0xD0000000) +#define PCI_IO_SIZE (0x10000000) + +/* + * INIT PCI + */ +void init_PCI(void) { + xprintf("PCI BUS controller initialization: "); + + MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI + + MCF_PCIARB_PACR_EXTMPRI(0x1F) + + MCF_PCIARB_PACR_INTMINTEN + + MCF_PCIARB_PACR_EXTMINTEN(0x1F); + + // Setup burst parameters + MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32); + MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16); + + // Turn on error signaling + MCF_PCI_PCIICR = MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_REE + 32; + MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE; + + /* Configure Initiator Windows */ + /* initiator window 0 base / translation adress register */ + MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE -1) >> 8)) & 0xffff0000; + + /* initiator window 1 base / translation adress register */ + MCF_PCI_PCIIW1BTAR = (PCI_IO_OFFSET + ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000; + + /* initiator window 2 base / translation address register */ + MCF_PCI_PCIIW2BTAR = 0L; /* not used */ + + /* initiator window configuration register */ + MCF_PCI_PCIIWCR = MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE + MCF_PCI_PCIIWCR_WINCTRL1_IO; + + /* reset PCI devices */ + MCF_PCI_PCIGSCR &= ~MCF_PCI_PCIGSCR_PR; + + xprintf("finished\r\n"); +} + + +/* + * probe for UPC720101 (USB) + */ +void test_upd720101(void) +{ + xprintf("UDP720101 USB controller initialization: "); + + /* select UPD720101 AD17 */ + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E + + MCF_PCI_PCICAR_DEVNUM(17) + + MCF_PCI_PCICAR_FUNCNUM(0) + + MCF_PCI_PCICAR_DWORD(0); + + if (* (uint32_t *) PCI_IO_OFFSET == 0x33103500) + { + MCF_PCI_PCICAR = MCF_PCI_PCICAR_E + + MCF_PCI_PCICAR_DEVNUM(17) + + MCF_PCI_PCICAR_FUNCNUM(0) + + MCF_PCI_PCICAR_DWORD(57); + + * (uint8_t *) PCI_IO_OFFSET = 0x20; + } + else + { + MCF_PSC0_PSCTB_8BIT = 'NOT '; + + MCF_PCI_PCICAR = MCF_PCI_PCICAR_DEVNUM(17) + + MCF_PCI_PCICAR_FUNCNUM(0) + + MCF_PCI_PCICAR_DWORD(57); + } + xprintf("finished\r\n"); +} + +static void wait_i2c_transfer_finished(void) +{ + while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)); /* wait until interrupt bit has been set */ + MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF; /* clear interrupt bit (byte transfer finished */ +} + +/* + * TFP410 (DVI) on + */ +void dvi_on(void) { + uint8_t receivedByte; + uint8_t dummyByte; /* only used for a dummy read */ + int num_tries = 0; + + xprintf("DVI digital video output initialization: "); + + MCF_I2C_I2FDR = 0x3c; /* divide system clock by 1280: 100kHz standard */ + + do { + /* disable all i2c interrupt routing targets */ + MCF_I2C_I2ICR = 0x0; //~(MCF_I2C_I2ICR_IE | MCF_I2C_I2ICR_RE | MCF_I2C_I2ICR_TE | MCF_I2C_I2ICR_BNBE); + + /* disable i2c, disable i2c interrupts, slave, receive, i2c = acknowledge, no repeat start */ + MCF_I2C_I2CR = 0x0; + + /* repeat start, transmit acknowledge */ + MCF_I2C_I2CR = MCF_I2C_I2CR_RSTA | MCF_I2C_I2CR_TXAK; + + receivedByte = MCF_I2C_I2DR; /* read a byte */ + MCF_I2C_I2SR = 0x0; /* clear status register */ + MCF_I2C_I2CR = 0x0; /* disable i2c */ + + MCF_I2C_I2ICR = MCF_I2C_I2ICR_IE; /* route i2c interrupts to cpu */ + /* i2c enable, master mode, transmit acknowledge */ + MCF_I2C_I2CR = MCF_I2C_I2CR_IEN | MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_MTX; + + MCF_I2C_I2DR = 0x7a; /* send data: address of TFP410 */ + wait_i2c_transfer_finished(); + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) /* next try if no acknowledge */ + continue; + + MCF_I2C_I2DR = 0x00; /* send data: SUB ADRESS 0 */ + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR |= MCF_I2C_I2CR_RSTA; /* repeat start */ + MCF_I2C_I2DR = 0x7b; /* begin read */ + + wait_i2c_transfer_finished(); + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) /* next try if no acknowledge */ + continue; + + MCF_I2C_I2CR &= 0xef; //~MCF_I2C_I2CR_MTX; /* switch to receive mode */ + dummyByte = MCF_I2C_I2DR; /* dummy read */ + + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR |= MCF_I2C_I2CR_TXAK; /* transmit acknowledge enable */ + receivedByte = MCF_I2C_I2DR; /* read a byte */ + + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR = MCF_I2C_I2CR_IEN; /* stop */ + + dummyByte = MCF_I2C_I2DR; // dummy read + + if (receivedByte != 0x4c) + continue; + + MCF_I2C_I2CR = 0x0; // stop + MCF_I2C_I2SR = 0x0; // clear sr + + while ((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)); /* wait for bus free */ + + MCF_I2C_I2CR = 0xb0; // on tx master + MCF_I2C_I2DR = 0x7A; + + wait_i2c_transfer_finished(); + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + continue; + + MCF_I2C_I2DR = 0x08; // SUB ADRESS 8 + + wait_i2c_transfer_finished(); + + MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable + + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR = 0x80; // stop + dummyByte = MCF_I2C_I2DR; // dummy read + MCF_I2C_I2SR = 0x0; // clear sr + + while ((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)); /* wait until bus free */ + + MCF_I2C_I2CR = 0xb0; + MCF_I2C_I2DR = 0x7A; + + wait_i2c_transfer_finished(); + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + continue; + + MCF_I2C_I2DR = 0x08; // SUB ADRESS 8 + + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR |= 0x4; // repeat start + MCF_I2C_I2DR = 0x7b; // beginn read + + wait_i2c_transfer_finished(); + + if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) + continue; + + MCF_I2C_I2CR &= 0xef; // switch to rx + dummyByte = MCF_I2C_I2DR; // dummy read + + wait_i2c_transfer_finished(); + MCF_I2C_I2CR |= 0x08; // txak=1 + + wait(50); + + receivedByte = MCF_I2C_I2DR; + + wait_i2c_transfer_finished(); + + MCF_I2C_I2CR = 0x80; // stop + + dummyByte = MCF_I2C_I2DR; // dummy read + num_tries++; + } while ((receivedByte != 0xbf) && (num_tries < 10)); + + if (num_tries >= 10) { + xprintf("FAILED!\r\n"); + } else { + xprintf("finished\r\n"); + } + UNUSED(dummyByte); + // Avoid warning +} + + +/* + * AC97 + */ +void init_ac97(void) { + // PSC2: AC97 ---------- + int i; + int zm; + int va; + int vb; + int vc; + + xprintf("AC97 sound chip initialization: "); + MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS // PSC2=TX,RX BCLK,CTS->AC'97 + | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK + | MCF_PAD_PAR_PSC2_PAR_TXD2 + | MCF_PAD_PAR_PSC2_PAR_RXD2; + MCF_PSC2_PSCMR1 = 0x0; + MCF_PSC2_PSCMR2 = 0x0; + MCF_PSC2_PSCIMR = 0x0300; + MCF_PSC2_PSCSICR = 0x03; //AC97 + MCF_PSC2_PSCRFCR = 0x0f000000; + MCF_PSC2_PSCTFCR = 0x0f000000; + MCF_PSC2_PSCRFAR = 0x00F0; + MCF_PSC2_PSCTFAR = 0x00F0; + + for (zm = 0; zm < 100000; zm++) // wiederholen bis synchron + { + MCF_PSC2_PSCCR = 0x20; + MCF_PSC2_PSCCR = 0x30; + MCF_PSC2_PSCCR = 0x40; + MCF_PSC2_PSCCR = 0x05; + + // MASTER VOLUME -0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x02000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + + for (i = 2; i < 13; i++) + { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + + // read register + MCF_PSC2_PSCTB_AC97 = 0xc0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x82000000; //SLOT1:master volume + + for (i = 2; i < 13; i++) + { + MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0 + } + wait(50); + + va = MCF_PSC2_PSCTB_AC97; + if ((va & 0x80000fff) == 0x80000800) { + vb = MCF_PSC2_PSCTB_AC97; + vc = MCF_PSC2_PSCTB_AC97; + + /* FIXME: that looks more than suspicious (Fredi?) */ + if ((va & 0xE0000fff) == 0xE0000800 & vb == 0x02000000 & vc == 0x00000000) { + goto livo; + } + } + } + uart_out_word(' NOT'); +livo: + // AUX VOLUME ->-0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16 + MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME + for (i = 3; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + + // line in VOLUME +12dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 2; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + // cd in VOLUME 0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 2; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + // mono out VOLUME 0dB + MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME + MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 + for (i = 3; i < 13; i++) { + MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 + } + MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF + MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data + xprintf(" finished\r\n"); +} + +/* Symbols from the linker script */ + +extern uint8_t _STRAM_END[]; +#define STRAM_END ((uint32_t)_STRAM_END) + +extern uint8_t _FIRETOS[]; +#define FIRETOS ((uint32_t)_FIRETOS) /* where FireTOS is stored in flash */ + +extern uint8_t _BAS_LMA[]; +#define BAS_LMA ((uint32_t)_BAS_LMA) /* where the BaS is stored in flash */ + +extern uint8_t _BAS_IN_RAM[]; +#define BAS_IN_RAM ((uint32_t)_BAS_IN_RAM) /* where the BaS is run in RAM */ + +extern uint8_t _BAS_SIZE[]; +#define BAS_SIZE ((uint32_t)_BAS_SIZE) /* size of the BaS, in bytes */ + +void initialize_hardware(void) { + /* used in copy loop */ + uint32_t *src; /* src address to read from flash */ + uint32_t *end; /* end address to read from flash */ + uint32_t *dst; /* destination address to copy to */ + + /* Test for FireTOS switch: DIP switch #5 up */ + if (!(DIP_SWITCH & (1 << 6))) { + /* Minimal hardware initialization */ + init_gpio(); + init_fbcs(); + init_ddram(); + init_fpga(); + + /* FireTOS seems to have trouble to initialize the ST-RAM by itself, so... */ + /* Validate ST RAM */ + * (volatile uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */ + * (volatile uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */ + * (volatile uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */ + * (volatile uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */ + + /* Jump into FireTOS */ + typedef void void_func(void); + void_func* FireTOS = (void_func*)FIRETOS; + FireTOS(); // Should never return + return; + } + + init_gpio(); + init_serial(); + init_slt(); + init_fbcs(); + init_ddram(); + init_PCI(); + init_fpga(); + init_pll(); + init_video_ddr(); + dvi_on(); + test_upd720101(); + //video_1280_1024(); + init_ac97(); + + /* copy the BaS code contained in flash to its final location */ + src = (uint32_t *)BAS_LMA; + end = (uint32_t *)(BAS_LMA + BAS_SIZE); + dst = (uint32_t *)BAS_IN_RAM; + + /* The linker script will ensure that the Bas size + * is a multiple of the following. + */ + while (src < end) + { + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + } + + /* we have copied a code area, so flush the caches */ + flush_and_invalidate_caches(); + + /* jump into the BaS in RAM */ + extern void BaS(void); + BaS(); +} diff --git a/BaS_gcc/sources/sysinit.h b/BaS_gcc/sources/sysinit.h new file mode 100644 index 0000000..a8df15e --- /dev/null +++ b/BaS_gcc/sources/sysinit.h @@ -0,0 +1,26 @@ +/* + * File: sysinit.h + * Purpose: Firebee Power-on Reset configuration + * + * Notes: + * + */ + +#ifndef __SYSINIT_H__ +#define __SYSINIT_H__ + +extern void wait_10us(void); + +/* send a 16-bit word out on the serial port */ +#define uart_out_word(a) MCF_PSC0_PSCTB_8BIT = (a) + +/* adresses where FPGA data lives in flash */ +#define FPGA_FLASH_DATA ((uint8_t *) 0xe0700000L) +#define FPGA_FLASH_DATA_END ((uint8_t *) 0xe0800000L) + +/* function(s) from init_fpga.c */ +extern void init_fpga(void); + +#endif /* __SYSINIT_H__ */ + +