deciphered SDRAM initialization values (SDCR and SDMR) with Coldfire preprocessor macros
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@@ -284,9 +284,25 @@ void init_ddram(void)
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MCF_SDRAMC_SDCFG2 = 0x46770000; /* SDCFG2 */
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MCF_SDRAMC_SDCFG2 = 0x46770000; /* SDCFG2 */
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#endif /* _NOT_USED_ */
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#endif /* _NOT_USED_ */
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MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_IPALL /* initiate Precharge All command */
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| MCF_SDRAMC_SDCR_RCNT(13) /* Refresh Count (= (x + 1) * 64 */
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| MCF_SDRAMC_SDCR_MUX(1) /* Muxing control */
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| MCF_SDRAMC_SDCR_DDR
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| MCF_SDRAMC_SDCR_CKE
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| MCF_SDRAMC_SDCR_MODE_EN;
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MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_CMD /* Generate an LMR/LEMR command */
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| MCF_SDRAMC_SDMR_AD(0) /* Address */
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| MCF_SDRAMC_SDMR_BNKAD(1); /* LEMR */
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MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_CMD /* Generate an LMR/LEMR command */
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| MCF_SDRAMC_SDMR_AD(0x123)
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| MCF_SDRAMC_SDMR_BNKAD(0); /* LMR */
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#ifdef _NOT_USED_
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MCF_SDRAMC_SDCR = 0xE10D0002; /* SDCR + IPALL */
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MCF_SDRAMC_SDCR = 0xE10D0002; /* SDCR + IPALL */
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MCF_SDRAMC_SDMR = 0x40010000; /* SDMR (write to LEMR) */
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MCF_SDRAMC_SDMR = 0x40010000; /* SDMR (write to LEMR) */
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MCF_SDRAMC_SDMR = 0x048D0000; /* SDRM (write to LMR) */
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MCF_SDRAMC_SDMR = 0x048D0000; /* SDRM (write to LMR) */
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#endif /* _NOT_USED_ */
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MCF_SDRAMC_SDCR = 0xE10D0002; /* SDCR + IPALL */
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MCF_SDRAMC_SDCR = 0xE10D0002; /* SDCR + IPALL */
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MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (first refresh) */
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MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (first refresh) */
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MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (second refresh) */
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MCF_SDRAMC_SDCR = 0xE10D0004; /* SDCR + IREF (second refresh) */
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