diff --git a/BaS_gcc/sys/mmu.c b/BaS_gcc/sys/mmu.c index abe2b9a..34d2849 100644 --- a/BaS_gcc/sys/mmu.c +++ b/BaS_gcc/sys/mmu.c @@ -229,8 +229,6 @@ static struct virt_to_phys translation[] = { 0x00000000, 0x00e00000, 0x00000000 }, /* map first 14 MByte to first 14 Mb of SD ram */ { 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */ { 0x01000000, 0x04000000, 0x00000000 }, /* map rest of ram virt = phys */ - { 0x60000000, 0x10000000, 0x00000000 }, /* map CPLD CF card I/O area */ - }; #elif defined(MACHINE_M54455) /* FIXME: this is not determined yet! */ @@ -528,17 +526,15 @@ void mmu_init(void) if (addr >= 0x60000000UL && addr < 0x70000000UL) /* Compact Flash on the m5484lite */ { pages[i].cache_mode = CACHE_NOCACHE_PRECISE; - pages[i].execute = 0; + pages[i].supervisor_protect = 0; pages[i].read = 1; pages[i].write = 1; - pages[i].execute = 0; + pages[i].execute = 1; pages[i].global = 1; - pages[i].supervisor_protect = 1; } else if (addr >= 0x0UL && addr < 0x00e00000UL) /* ST-RAM, potential video memory */ { pages[i].cache_mode = CACHE_WRITETHROUGH; - pages[i].execute = 1; pages[i].supervisor_protect = 0; pages[i].read = 1; pages[i].write = 1; @@ -694,23 +690,6 @@ void mmu_init(void) /* 0x00000000 - 0x00100000 (first MB of physical memory) locked virt = phys */ mmu_map_page(0x0, 0x0, MMU_PAGE_SIZE_1M, 0, &flags); -#ifdef _NOT_USED_ -#if defined(MACHINE_FIREBEE) - /* - * 0x00d00000 - 0x00e00000 (last megabyte of ST RAM = Falcon video memory) locked ID = 6 - * mapped to physical address 0x60d0'0000 (FPGA video memory) - * video RAM: read write execute normal write true - */ - flags.cache_mode = CACHE_WRITETHROUGH; - flags.supervisor_protect = 0; - flags.read = 1; - flags.write = 1; - flags.execute = 1; - flags.locked = true; - mmu_map_page(0x00d00000, 0x60d00000, MMU_PAGE_SIZE_1M, SCA_PAGE_ID, &flags); -#endif /* MACHINE_FIREBEE */ -#endif - /* * Make the TOS (in SDRAM) read-only * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address @@ -735,6 +714,17 @@ void mmu_init(void) flags.execute = 0; flags.locked = 1; mmu_map_page(0x00f00000, 0xfff00000, MMU_PAGE_SIZE_1M, 0, &flags); +#elif defined(MACHINE_M5484LITE) + /* + * Map m5484LITE CPLD access + */ + flags.cache_mode = CACHE_NOCACHE_PRECISE; + flags.supervisor_protect = 1; + flags.read = 1; + flags.write = 1; + flags.execute = 0; + flags.locked = 1; + mmu_map_page(0x6a000000, 0x6a000000, MMU_PAGE_SIZE_1M, 0, &flags); #endif /* MACHINE_FIREBEE */ /* @@ -767,7 +757,7 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, uint32 { uint32_t fault = format_status & 0xc030000; - dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", fault_address, format_status, pc); + //dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", fault_address, format_status, pc); // flush_and_invalidate_caches(); switch (fault) diff --git a/BaS_gcc/sys/sysinit.c b/BaS_gcc/sys/sysinit.c index db7f01b..5f09984 100644 --- a/BaS_gcc/sys/sysinit.c +++ b/BaS_gcc/sys/sysinit.c @@ -406,60 +406,44 @@ void init_fbcs() xprintf("FlexBus chip select registers initialization: "); /* Flash */ - MCF_FBCS0_CSAR = BOOTFLASH_BASE_ADDRESS; /* flash base address */ - MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 | /* 16 bit word access */ + MCF_FBCS0_CSAR = MCF_FBCS_CSAR_BA(BOOTFLASH_BASE_ADDRESS); /* flash base address */ + MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 | /* 16 bit word access */ MCF_FBCS_CSCR_WS(6)| /* 6 Waitstates */ MCF_FBCS_CSCR_AA | MCF_FBCS_CSCR_ASET(1) | - MCF_FBCS_CSCR_RDAH(1); /* chip errata SECF077 */ + MCF_FBCS_CSCR_RDAH(1); /* chip errata SECF077 */ MCF_FBCS0_CSMR = BOOTFLASH_BAM | MCF_FBCS_CSMR_V; /* enable */ -#if MACHINE_FIREBEE /* FBC setup for FireBee */ - MCF_FBCS1_CSAR = 0xFFF00000; /* ATARI I/O ADRESS */ +#if defined(MACHINE_FIREBEE) /* FBC setup for FireBee */ + MCF_FBCS1_CSAR = MCF_FBCS_CSAR_BA(0xFFF00000); /* ATARI I/O ADRESS */ MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */ | MCF_FBCS_CSCR_WS(8) /* DEFAULT 8WS */ | MCF_FBCS_CSCR_AA; /* AA */ MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V; - MCF_FBCS2_CSAR = 0xF0000000; /* Firebee new I/O address range */ + MCF_FBCS2_CSAR = MCF_FBCS_CSAR_BA(0xF0000000); /* Firebee new I/O address range */ MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 /* 32BIT PORT */ | MCF_FBCS_CSCR_WS(8) /* DEFAULT 4WS */ | MCF_FBCS_CSCR_AA; /* AA */ MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M /* F000'0000-F7FF'FFFF */ | MCF_FBCS_CSMR_V); - MCF_FBCS3_CSAR = 0xF8000000; /* Firebee new I/O address range */ + MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xF8000000); /* Firebee new I/O address range */ MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */ | MCF_FBCS_CSCR_AA; // AA MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M /* F800'0000-FBFF'FFFF */ | MCF_FBCS_CSMR_V); - MCF_FBCS4_CSAR = 0x40000000; /* video ram area, FB_CS3 not used, decoded on FPGA */ + MCF_FBCS4_CSAR = MCF_FBCS_CSAR_BA(0x40000000); /* video ram area, FB_CS3 not used, decoded on FPGA */ MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 /* 32BIT PORT */ | MCF_FBCS_CSCR_BSTR /* burst read enable */ | MCF_FBCS_CSCR_BSTW; /* burst write enable */ MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G /* 4000'0000-7FFF'FFFF */ | MCF_FBCS_CSMR_V; -#elif MACHINE_M5484LITE - /* disable other FBCS for now */ - MCF_FBCS1_CSMR = 0; - MCF_FBCS2_CSMR = 0; - MCF_FBCS3_CSMR = 0; - MCF_FBCS4_CSMR = 0; - MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000); - MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 | /* CPLD access */ - MCF_FBCS_CSCR_WS(32) | - MCF_FBCS_CSCR_ASET(1) | - MCF_FBCS_CSCR_AA; - MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_1G | - MCF_FBCS_CSMR_V; -#endif /* MACHINE_FIREBEE */ - - -#ifndef MACHINE_M5484LITE + /* disable FBCS5 on Firebee */ MCF_FBCS5_CSAR = 0x0; MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_8 | MCF_FBCS_CSCR_BSTR @@ -467,7 +451,21 @@ void init_fbcs() | MCF_FBCS_CSCR_RDAH(1); /* chip errata SECF077 */ MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_1G; //| MCF_FBCS_CSMR_V; -#endif /* MACHINE_M5484LITE */ +#elif defined(MACHINE_M5484LITE) + /* disable other FBCS for now */ + MCF_FBCS1_CSMR = 0; + MCF_FBCS2_CSMR = 0; + MCF_FBCS3_CSMR = 0; + MCF_FBCS4_CSMR = 0; + + MCF_FBCS5_CSAR = MCF_FBCS_CSAR_BA(0x60000000); + MCF_FBCS5_CSCR = MCF_FBCS_CSCR_PS_16 | /* CPLD access 16 bit wide */ + MCF_FBCS_CSCR_WS(32) | /* 32 wait states */ + MCF_FBCS_CSCR_ASET(1) | /* chip select on rising clock edge */ + MCF_FBCS_CSCR_AA; /* auto acknowledge */ + MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M | /* maps 0x60000000 to 0x68000000 */ + MCF_FBCS_CSMR_V; +#endif /* MACHINE_FIREBEE */ xprintf("finished\r\n"); } @@ -1047,19 +1045,34 @@ void initialize_hardware(void) break; } - /* make sure MMU is disabled */ - MCF_MMU_MMUCR = 0; /* MMU off */ - NOP(); /* force pipeline sync */ - /* * Determine the processor revision */ xprintf(" (revision %d)\r\n", ((MCF_SIU_JTAGID & MCF_SIU_JTAGID_REV) >> 28)); + /* make sure MMU is disabled */ + MCF_MMU_MMUCR = 0; /* MMU off */ + NOP(); /* force pipeline sync */ + init_slt(); init_fbcs(); coldboot = init_ddram(); +#if defined(MACHINE_M5484LITE) + xprintf("Fire Engine Control register: %02x\r\n", * (uint8_t *) 0x61000000); + xprintf("Fire Engine interrupt register: %02x\r\n", * (uint8_t *) 0x62000000); + xprintf("Fire Engine interrupt mask register: %02x\r\n", * (uint8_t *) 0x63000000); + xprintf("Fire Engine power management register: %02x\r\n", * (uint8_t *) 0x64000000); + xprintf("Fire Engine EEPROM SPI register: %02x\r\n", * (uint8_t *) 0x65000000); + xprintf("Fire Engine Flash register: %02x\r\n", * (uint8_t *) 0x66000000); + xprintf("Fire Engine CPLD revision register: %02x\r\n", * (uint8_t *) 0x67000000); + xprintf("Fire Engine Hardware revision register:%02x\r\n", * (uint8_t *) 0x68000000); + + xprintf("write control register 0x%02x\r\n", 1 << 7); + * (uint8_t *) 0x61000000 = 1 << 7; + xprintf("Fire Engine Control register: %02x\r\n", * (uint8_t *) 0x61000000); +#endif /* MACHINE_M5484LITE */ + /* * install (preliminary) exception vectors */