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fixed formatting

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This commit is contained in:
Markus Fröschle
2014-08-09 19:17:09 +00:00
parent e9f5ee1ed3
commit cf659204c8
3 changed files with 264 additions and 266 deletions
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1
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -723,7 +723,6 @@ set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd
set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip
set_global_assignment -name VHDL_FILE ../../../testbenches/ddr_ram_model.vhd
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to CLK_DDR_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to CLK_DDR_OUTn
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLK_DDR_OUTn

380
vhdl/rtl/vhdl/Interrupt/interrupt.vhd
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@@ -83,88 +83,88 @@ entity INTHANDLER is
end entity INTHANDLER;
architecture BEHAVIOUR of INTHANDLER is
type INT_LA_TYPE is array(9 downto 0) of std_logic_vector(3 downto 0);
signal INT_LA : INT_LA_TYPE;
signal FB_B : std_logic_vector(3 downto 0);
signal INT_CTR : std_logic_vector(31 downto 0);
signal INT_CTR_CS : std_logic;
signal INT_LATCH : std_logic_vector(31 downto 0);
signal INT_LATCH_CS : std_logic;
signal INT_CLEAR : std_logic_vector(31 downto 0);
signal INT_CLEAR_CS : std_logic;
signal INT_IN : std_logic_vector(31 downto 0);
signal INT_ENA : std_logic_vector(31 downto 0);
signal INT_ENA_CS : std_logic;
signal INT_L : std_logic_vector(9 downto 0);
signal FBEE_CONF_REG : std_logic_vector(31 downto 0);
signal FBEE_CONF_CS : std_logic;
signal PSEUDO_BUS_ERROR : std_logic;
type INT_LA_TYPE is array(9 downto 0) of std_logic_vector(3 downto 0);
signal INT_LA : INT_LA_TYPE;
signal FB_B : std_logic_vector(3 downto 0);
signal INT_CTR : std_logic_vector(31 downto 0);
signal INT_CTR_CS : std_logic;
signal INT_LATCH : std_logic_vector(31 downto 0);
signal INT_LATCH_CS : std_logic;
signal INT_CLEAR : std_logic_vector(31 downto 0);
signal INT_CLEAR_CS : std_logic;
signal INT_IN : std_logic_vector(31 downto 0);
signal INT_ENA : std_logic_vector(31 downto 0);
signal INT_ENA_CS : std_logic;
signal INT_L : std_logic_vector(9 downto 0);
signal FBEE_CONF_REG : std_logic_vector(31 downto 0);
signal FBEE_CONF_CS : std_logic;
signal PSEUDO_BUS_ERROR : std_logic;
begin
-- Byte selectors:
FB_B(0) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "00" else -- HH Byte.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
-- Byte selectors:
FB_B(0) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "00" else -- HH Byte.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
FB_B(1) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "01" else -- HL Byte.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
FB_B(1) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "01" else -- HL Byte.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
FB_B(2) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "10" else -- LH Byte.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
FB_B(2) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "10" else -- LH Byte.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
FB_B(3) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "11" else -- LL Byte.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
FB_B(3) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '1' else -- Low word.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' and FB_ADR(1 downto 0) = "11" else -- LL Byte.
'1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else -- Long.
'1' when FB_SIZE1 = '1' and FB_SIZE0 = '1' else '0';-- Line.
INT_CTR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000000" else '0'; -- $10000/4;
INT_ENA_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000001" else '0'; -- $10004/4;
INT_CLEAR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000010" else '0'; -- $10008/4;
INT_LATCH_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000011" else '0'; -- $1000C/4;
INT_CTR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000000" else '0'; -- $10000/4;
INT_ENA_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000001" else '0'; -- $10004/4;
INT_CLEAR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000010" else '0'; -- $10008/4;
INT_LATCH_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000000000100000000000011" else '0'; -- $1000C/4;
P_INT_CTRL : process
-- Interrupt control register:
--BIT0 = INT5, Bit1 = INT7.
-- Interrupt enabe register:
-- BIT31 = INT7, Bit30 = INT6, Bit29 = INT5, Bit28 = INT4, Bit27 = INT3, Bit26 = INT2
-- The interrupt clear register is write only; 1 = interrupt clear.
begin
wait until CLK_MAIN = '1' and CLK_MAIN' event;
if INT_CTR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
INT_CTR(31 downto 24) <= FB_AD_IN(31 downto 24);
elsif INT_CTR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
INT_CTR(23 downto 16) <= FB_AD_IN(23 downto 16);
elsif INT_CTR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
INT_CTR(15 downto 8) <= FB_AD_IN(15 downto 8);
elsif INT_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
INT_CTR(7 downto 0) <= FB_AD_IN(7 downto 0);
end if;
--
if RESETn = '0' then
INT_ENA <= (others => '0');
elsif INT_ENA_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
INT_ENA(31 downto 24) <= FB_AD_IN(31 downto 24);
elsif INT_ENA_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
INT_ENA(23 downto 16) <= FB_AD_IN(23 downto 16);
elsif INT_ENA_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
INT_ENA(15 downto 8) <= FB_AD_IN(15 downto 8);
elsif INT_ENA_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
INT_ENA(7 downto 0) <= FB_AD_IN(7 downto 0);
end if;
--
if INT_CLEAR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
INT_CLEAR(31 downto 24) <= FB_AD_IN(31 downto 24);
elsif INT_CLEAR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
INT_CLEAR(23 downto 16) <= FB_AD_IN(23 downto 16);
elsif INT_CLEAR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
INT_CLEAR(15 downto 8) <= FB_AD_IN(15 downto 8);
elsif INT_CLEAR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
INT_CLEAR(7 downto 0) <= FB_AD_IN(7 downto 0);
end if;
P_INT_CTRL : process
-- Interrupt control register:
-- BIT0 = INT5, Bit1 = INT7.
-- Interrupt enabe register:
-- BIT31 = INT7, Bit30 = INT6, Bit29 = INT5, Bit28 = INT4, Bit27 = INT3, Bit26 = INT2
-- The interrupt clear register is write only; 1 = interrupt clear.
begin
wait until rising_edge(CLK_MAIN);
if INT_CTR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
INT_CTR(31 downto 24) <= FB_AD_IN(31 downto 24);
elsif INT_CTR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
INT_CTR(23 downto 16) <= FB_AD_IN(23 downto 16);
elsif INT_CTR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
INT_CTR(15 downto 8) <= FB_AD_IN(15 downto 8);
elsif INT_CTR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
INT_CTR(7 downto 0) <= FB_AD_IN(7 downto 0);
end if;
--
if RESETn = '0' then
INT_ENA <= (others => '0');
elsif INT_ENA_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
INT_ENA(31 downto 24) <= FB_AD_IN(31 downto 24);
elsif INT_ENA_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
INT_ENA(23 downto 16) <= FB_AD_IN(23 downto 16);
elsif INT_ENA_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
INT_ENA(15 downto 8) <= FB_AD_IN(15 downto 8);
elsif INT_ENA_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
INT_ENA(7 downto 0) <= FB_AD_IN(7 downto 0);
end if;
--
if INT_CLEAR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
INT_CLEAR(31 downto 24) <= FB_AD_IN(31 downto 24);
elsif INT_CLEAR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
INT_CLEAR(23 downto 16) <= FB_AD_IN(23 downto 16);
elsif INT_CLEAR_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
INT_CLEAR(15 downto 8) <= FB_AD_IN(15 downto 8);
elsif INT_CLEAR_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
INT_CLEAR(7 downto 0) <= FB_AD_IN(7 downto 0);
end if;
end process P_INT_CTRL;
-- Interrupt latch register: read only.
@@ -176,131 +176,131 @@ begin
IRQn(7) <= '0' when PSEUDO_BUS_ERROR = '1' and INT_ENA(31) = '1' else '1';
PSEUDO_BUS_ERROR <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F8C8" else -- SCC
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F8E0" else -- VME
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F920" else -- PADDLE
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F921" else -- PADDLE
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F922" else -- PADDLE
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA9" else -- MFP2
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFAA" else -- MFP2
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 8) = x"F87" else -- TT SCSI
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFC2" else -- ST UHR
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFC3" else '0'; -- ST UHR
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F890" else -- DMA SOUND
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F891" else -- DMA SOUND
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F892" else '0'; -- DMA SOUND
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F8E0" else -- VME
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F920" else -- PADDLE
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F921" else -- PADDLE
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F922" else -- PADDLE
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA9" else -- MFP2
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFAA" else -- MFP2
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFA8" else -- MFP2
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 8) = x"F87" else -- TT SCSI
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFC2" else -- ST UHR
'1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"FFC3" else '0'; -- ST UHR
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F890" else -- DMA SOUND
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F891" else -- DMA SOUND
-- '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 4) = x"F892" else '0'; -- DMA SOUND
-- IF video ADR changes:
TIN0 <= '1' when FB_CSn(1) = '0' and FB_WRn = '0' and FB_ADR(19 downto 1) = x"7C100" else '0'; -- Write video base address high 0xFFFF8201/2.
-- IF video ADR changes:
TIN0 <= '1' when FB_CSn(1) = '0' and FB_WRn = '0' and FB_ADR(19 downto 1) = x"7C100" else '0'; -- Write video base address high 0xFFFF8201/2.
P_INT_LATCH : process
begin
wait until CLK_MAIN = '1' and CLK_MAIN' event;
if RESETn = '0' then
INT_L <= (others => '0');
else
INT_L(0) <= PIC_INT and INT_ENA(0);
INT_L(1) <= E0_INT and INT_ENA(1);
INT_L(2) <= DVI_INT and INT_ENA(2);
INT_L(3) <= not PCI_INTAn and INT_ENA(3);
INT_L(4) <= not PCI_INTBn and INT_ENA(4);
INT_L(5) <= not PCI_INTCn and INT_ENA(5);
INT_L(6) <= not PCI_INTDn and INT_ENA(6);
INT_L(7) <= DSP_INT and INT_ENA(7);
INT_L(8) <= VSYNC and INT_ENA(8);
INT_L(9) <= HSYNC and INT_ENA(9);
end if;
P_INT_LATCH : process
begin
wait until rising_edge(CLK_MAIN);
if RESETn = '0' then
INT_L <= (others => '0');
else
INT_L(0) <= PIC_INT and INT_ENA(0);
INT_L(1) <= E0_INT and INT_ENA(1);
INT_L(2) <= DVI_INT and INT_ENA(2);
INT_L(3) <= not PCI_INTAn and INT_ENA(3);
INT_L(4) <= not PCI_INTBn and INT_ENA(4);
INT_L(5) <= not PCI_INTCn and INT_ENA(5);
INT_L(6) <= not PCI_INTDn and INT_ENA(6);
INT_L(7) <= DSP_INT and INT_ENA(7);
INT_L(8) <= VSYNC and INT_ENA(8);
INT_L(9) <= HSYNC and INT_ENA(9);
end if;
for i in 0 to 9 loop
if INT_ENA(i) = '1' and RESETn = '1' then
INT_LA(i) <= x"0";
elsif INT_L(i) = '1' and INT_LA(i) < x"7" then
INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) + 1);
elsif INT_L(i) = '0' and INT_LA(i) > x"8" then
INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) - 1);
elsif INT_L(i) = '1' and INT_LA(i) > x"6" then
INT_LA(i) <= x"F";
elsif INT_L(i) = '0' and INT_LA(i) > x"9" then
INT_LA(i) <= x"0";
end if;
end loop;
for i in 0 to 9 loop
if INT_ENA(i) = '1' and RESETn = '1' then
INT_LA(i) <= x"0";
elsif INT_L(i) = '1' and INT_LA(i) < x"7" then
INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) + 1);
elsif INT_L(i) = '0' and INT_LA(i) > x"8" then
INT_LA(i) <= std_logic_vector(unsigned(INT_LA(i)) - 1);
elsif INT_L(i) = '1' and INT_LA(i) > x"6" then
INT_LA(i) <= x"F";
elsif INT_L(i) = '0' and INT_LA(i) > x"9" then
INT_LA(i) <= x"0";
end if;
end loop;
for i in 0 to 31 loop
if INT_CLEAR(i) = '0' and RESETn = '1' then
INT_LATCH(i) <= '0';
end if;
end loop;
for i in 0 to 31 loop
if INT_CLEAR(i) = '0' and RESETn = '1' then
INT_LATCH(i) <= '0';
end if;
end loop;
for i in 0 to 9 loop
if INT_LA(i)(3) = '1' then
INT_LATCH(i) <= '1';
end if;
end loop;
end process P_INT_LATCH;
for i in 0 to 9 loop
if INT_LA(i)(3) = '1' then
INT_LATCH(i) <= '1';
end if;
end loop;
end process P_INT_LATCH;
-- INT_IN:
INT_IN(0) <= PIC_INT;
INT_IN(1) <= E0_INT;
INT_IN(2) <= DVI_INT;
INT_IN(3) <= not PCI_INTAn;
INT_IN(4) <= not PCI_INTBn;
INT_IN(5) <= not PCI_INTCn;
INT_IN(6) <= not PCI_INTDn;
INT_IN(7) <= DSP_INT;
INT_IN(8) <= VSYNC;
INT_IN(9) <= HSYNC;
INT_IN(25 downto 10) <= x"0000";
INT_IN(26) <= HSYNC;
INT_IN(27) <= INT_CTR(0);
INT_IN(28) <= VSYNC;
INT_IN(29) <= '1' when INT_LATCH /= x"00000000";
INT_IN(30) <= not MFP_INTn;
INT_IN(31) <= DRQ_DMA;
-- INT_IN:
INT_IN(0) <= PIC_INT;
INT_IN(1) <= E0_INT;
INT_IN(2) <= DVI_INT;
INT_IN(3) <= not PCI_INTAn;
INT_IN(4) <= not PCI_INTBn;
INT_IN(5) <= not PCI_INTCn;
INT_IN(6) <= not PCI_INTDn;
INT_IN(7) <= DSP_INT;
INT_IN(8) <= VSYNC;
INT_IN(9) <= HSYNC;
INT_IN(25 downto 10) <= x"0000";
INT_IN(26) <= HSYNC;
INT_IN(27) <= INT_CTR(0);
INT_IN(28) <= VSYNC;
INT_IN(29) <= '1' when INT_LATCH /= x"00000000";
INT_IN(30) <= not MFP_INTn;
INT_IN(31) <= DRQ_DMA;
FBEE_CONF_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000001000000000000000000" else '0'; -- $40000/4.
FBEE_CONF_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(27 downto 2) = "00000001000000000000000000" else '0'; -- $40000/4.
P_FBEE_CONFIG : process
-- Firebee configuration register: BIT 31 -> 0 = CF 1 = IDE
begin
wait until rising_edge(CLK_MAIN);
if FBEE_CONF_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
FBEE_CONF_REG(31 downto 24) <= FB_AD_IN(31 downto 24);
elsif FBEE_CONF_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
FBEE_CONF_REG(23 downto 16) <= FB_AD_IN(23 downto 16);
elsif FBEE_CONF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
FBEE_CONF_REG(15 downto 8) <= FB_AD_IN(15 downto 8);
elsif FBEE_CONF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
FBEE_CONF_REG(7 downto 0) <= FB_AD_IN(7 downto 0);
end if;
FBEE_CONF <= FBEE_CONF_REG;
end process P_FBEE_CONFIG;
P_FBEE_CONFIG : process
-- Firebee configuration register: BIT 31 -> 0 = CF 1 = IDE
begin
wait until CLK_MAIN = '1' and CLK_MAIN' event;
if FBEE_CONF_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
FBEE_CONF_REG(31 downto 24) <= FB_AD_IN(31 downto 24);
elsif FBEE_CONF_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
FBEE_CONF_REG(23 downto 16) <= FB_AD_IN(23 downto 16);
elsif FBEE_CONF_CS = '1' and FB_B(2) = '1' and FB_WRn = '0' then
FBEE_CONF_REG(15 downto 8) <= FB_AD_IN(15 downto 8);
elsif FBEE_CONF_CS = '1' and FB_B(3) = '1' and FB_WRn = '0' then
FBEE_CONF_REG(7 downto 0) <= FB_AD_IN(7 downto 0);
end if;
FBEE_CONF <= FBEE_CONF_REG;
end process P_FBEE_CONFIG;
-- Data out multiplexers:
FB_AD_EN_31_24 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
FB_AD_EN_23_16 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
FB_AD_EN_15_8 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
FB_AD_EN_7_0 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
-- Data out multiplexers:
FB_AD_EN_31_24 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
FB_AD_EN_23_16 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
FB_AD_EN_15_8 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
FB_AD_EN_7_0 <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or FBEE_CONF_CS) and not FB_OEn;
FB_AD_OUT(31 downto 24) <= INT_CTR(31 downto 24) when INT_CTR_CS = '1' else
INT_ENA(31 downto 24) when INT_ENA_CS = '1' else
INT_LATCH(31 downto 24) when INT_LATCH_CS = '1' else
INT_IN(31 downto 24) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(31 downto 24);
FB_AD_OUT(31 downto 24) <= INT_CTR(31 downto 24) when INT_CTR_CS = '1' else
INT_ENA(31 downto 24) when INT_ENA_CS = '1' else
INT_LATCH(31 downto 24) when INT_LATCH_CS = '1' else
INT_IN(31 downto 24) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(31 downto 24);
FB_AD_OUT(23 downto 16) <= INT_CTR(23 downto 16) when INT_CTR_CS = '1' else
INT_ENA(23 downto 16) when INT_ENA_CS = '1' else
INT_LATCH(23 downto 16) when INT_LATCH_CS = '1' else
INT_IN(23 downto 16) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(23 downto 16);
FB_AD_OUT(23 downto 16) <= INT_CTR(23 downto 16) when INT_CTR_CS = '1' else
INT_ENA(23 downto 16) when INT_ENA_CS = '1' else
INT_LATCH(23 downto 16) when INT_LATCH_CS = '1' else
INT_IN(23 downto 16) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(23 downto 16);
FB_AD_OUT(15 downto 8) <= INT_CTR(15 downto 8) when INT_CTR_CS = '1' else
INT_ENA(15 downto 8) when INT_ENA_CS = '1' else
INT_LATCH(15 downto 8) when INT_LATCH_CS = '1' else
INT_CLEAR(15 downto 8) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(15 downto 8);
FB_AD_OUT(15 downto 8) <= INT_CTR(15 downto 8) when INT_CTR_CS = '1' else
INT_ENA(15 downto 8) when INT_ENA_CS = '1' else
INT_LATCH(15 downto 8) when INT_LATCH_CS = '1' else
INT_CLEAR(15 downto 8) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(15 downto 8);
FB_AD_OUT(7 downto 0) <= INT_CTR(7 downto 0) when INT_CTR_CS = '1' else
INT_ENA(7 downto 0) when INT_ENA_CS = '1' else
INT_LATCH(7 downto 0) when INT_LATCH_CS = '1' else
INT_CLEAR(7 downto 0) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(7 downto 0);
FB_AD_OUT(7 downto 0) <= INT_CTR(7 downto 0) when INT_CTR_CS = '1' else
INT_ENA(7 downto 0) when INT_ENA_CS = '1' else
INT_LATCH(7 downto 0) when INT_LATCH_CS = '1' else
INT_CLEAR(7 downto 0) when INT_CLEAR_CS = '1' else FBEE_CONF_REG(7 downto 0);
INT_HANDLER_TA <= INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS;
INT_HANDLER_TA <= INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS;
end architecture BEHAVIOUR;

149
vhdl/rtl/vhdl/Video/Video_Top.vhd
View File

@@ -129,7 +129,7 @@ architecture BEHAVIOUR of VIDEO_SYSTEM is
data : in std_logic_vector (127 downto 0);
rdreq : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (127 downto 0)
q : out std_logic_vector (127 downto 0)
);
end component;
@@ -209,12 +209,11 @@ architecture BEHAVIOUR of VIDEO_SYSTEM is
signal ZR_C8 : std_logic_vector(7 downto 0);
begin
CLK_PIXEL <= CLK_PIXEL_I;
FIFO_CLR <= FIFO_CLR_I;
CLK_PIXEL <= CLK_PIXEL_I;
FIFO_CLR <= FIFO_CLR_I;
P_CLUT_ST_MC: process
-- This is the dual ported ram for the ST colour lookup tables.
P_CLUT_ST_MC: process
-- This is the dual ported ram for the ST colour lookup tables.
variable clut_fa_index : integer;
variable clut_st_index : integer;
variable clut_fi_index : integer;
@@ -223,7 +222,7 @@ begin
clut_fa_index := to_integer(unsigned(FB_ADR(9 downto 2)));
clut_fi_index := to_integer(unsigned(FB_ADR(9 downto 2)));
wait until CLK_MAIN = '1' and CLK_MAIN' event;
wait until rising_edge(CLK_MAIN);
if CLUT_ST_WR(0) = '1' then
CLUT_ST(clut_st_index)(11 downto 8) <= FB_AD_IN(27 downto 24);
end if;
@@ -254,14 +253,14 @@ begin
CLUT_ST_OUT <= CLUT_ST(clut_st_index);
CLUT_FA_OUT <= CLUT_FA(clut_fa_index);
CLUT_FBEE_OUT <= CLUT_FI(clut_fi_index);
end process P_CLUT_ST_MC;
end process P_CLUT_ST_MC;
P_CLUT_ST_PX: process
variable clut_fa_index : integer;
P_CLUT_ST_PX: process
variable clut_fa_index : integer;
variable clut_st_index : integer;
variable clut_fi_index : integer;
-- This is the dual ported ram for the ST colour lookup tables.
begin
-- This is the dual ported ram for the ST colour lookup tables.
begin
clut_st_index := to_integer(unsigned(CLUT_ADR(3 downto 0)));
clut_fa_index := to_integer(unsigned(CLUT_ADR));
clut_fi_index := to_integer(unsigned(ZR_C8));
@@ -282,7 +281,7 @@ begin
end process P_CLUT_ST_PX;
P_VIDEO_OUT: process
variable VIDEO_OUT : std_logic_vector(23 downto 0);
variable VIDEO_OUT : std_logic_vector(23 downto 0);
begin
wait until rising_edge(CLK_PIXEL_I);
case CC_SEL is
@@ -436,7 +435,7 @@ begin
DFF_CLK2: process
begin
wait until CLK_DDR2 = '1' and CLK_DDR2' event;
wait until rising_edge(CLK_DDR2);
VDMP <= SR_VDMP;
end process DFF_CLK2;
@@ -488,66 +487,66 @@ begin
wrusedw => FIFO_MW
);
I_FIFO_DZ: lpm_fifoDZ
port map(
aclr => DOP_FIFO_CLR,
clock => CLK_PIXEL_I,
data => FIFO_D_OUT_512,
rdreq => FIFO_RD_REQ_128,
wrreq => FIFO_RD_REQ_512,
q => FIFO_D_OUT_128
);
I_FIFO_DZ: lpm_fifoDZ
port map(
aclr => DOP_FIFO_CLR,
clock => CLK_PIXEL_I,
data => FIFO_D_OUT_512,
rdreq => FIFO_RD_REQ_128,
wrreq => FIFO_RD_REQ_512,
q => FIFO_D_OUT_128
);
I_VIDEO_CTRL: VIDEO_CTRL
port map(
CLK_MAIN => CLK_MAIN,
FB_CSn(1) => FB_CSn(1),
FB_CSn(2) => FB_CSn(2),
FB_WRn => FB_WRn,
FB_OEn => FB_OEn,
FB_SIZE(0) => FB_SIZE0,
FB_SIZE(1) => FB_SIZE1,
FB_ADR => FB_ADR,
CLK33M => CLK_33M,
CLK25M => CLK_25M,
BLITTER_RUN => BLITTER_RUN,
CLK_VIDEO => CLK_VIDEO,
VR_D => VR_D,
VR_BUSY => VR_BUSY,
COLOR8 => COLOR8,
FBEE_CLUT_RD => CLUT_FBEE_RD,
COLOR1 => COLOR1,
FALCON_CLUT_RDH => CLUT_FA_RDH,
FALCON_CLUT_RDL => CLUT_FA_RDL,
FALCON_CLUT_WR => CLUT_FA_WR,
CLUT_ST_RD => CLUT_ST_RD,
CLUT_ST_WR => CLUT_ST_WR,
CLUT_MUX_ADR => CLUT_ADR_MUX,
HSYNC => HSYNC,
VSYNC => VSYNC,
BLANKn => BLANKn,
SYNCn => SYNCn,
PD_VGAn => PD_VGAn,
FIFO_RDE => FIFO_RDE,
COLOR2 => COLOR2,
COLOR4 => COLOR4,
CLK_PIXEL => CLK_PIXEL_I,
CLUT_OFF => CLUT_OFF,
BLITTER_ON => BLITTER_ON,
VIDEO_RAM_CTR => VIDEO_RAM_CTR,
VIDEO_MOD_TA => VIDEO_MOD_TA,
CCR => CCR,
CCSEL => CC_SEL,
FBEE_CLUT_WR => CLUT_FBEE_WR,
INTER_ZEI => INTER_ZEI,
DOP_FIFO_CLR => DOP_FIFO_CLR,
VIDEO_RECONFIG => VIDEO_RECONFIG,
VR_WR => VR_WR,
VR_RD => VR_RD,
FIFO_CLR => FIFO_CLR_I,
DATA_IN => FB_AD_IN,
DATA_OUT => DATA_OUT_VIDEO_CTRL,
DATA_EN_H => DATA_EN_H_VIDEO_CTRL,
DATA_EN_L => DATA_EN_L_VIDEO_CTRL
);
I_VIDEO_CTRL: VIDEO_CTRL
port map(
CLK_MAIN => CLK_MAIN,
FB_CSn(1) => FB_CSn(1),
FB_CSn(2) => FB_CSn(2),
FB_WRn => FB_WRn,
FB_OEn => FB_OEn,
FB_SIZE(0) => FB_SIZE0,
FB_SIZE(1) => FB_SIZE1,
FB_ADR => FB_ADR,
CLK33M => CLK_33M,
CLK25M => CLK_25M,
BLITTER_RUN => BLITTER_RUN,
CLK_VIDEO => CLK_VIDEO,
VR_D => VR_D,
VR_BUSY => VR_BUSY,
COLOR8 => COLOR8,
FBEE_CLUT_RD => CLUT_FBEE_RD,
COLOR1 => COLOR1,
FALCON_CLUT_RDH => CLUT_FA_RDH,
FALCON_CLUT_RDL => CLUT_FA_RDL,
FALCON_CLUT_WR => CLUT_FA_WR,
CLUT_ST_RD => CLUT_ST_RD,
CLUT_ST_WR => CLUT_ST_WR,
CLUT_MUX_ADR => CLUT_ADR_MUX,
HSYNC => HSYNC,
VSYNC => VSYNC,
BLANKn => BLANKn,
SYNCn => SYNCn,
PD_VGAn => PD_VGAn,
FIFO_RDE => FIFO_RDE,
COLOR2 => COLOR2,
COLOR4 => COLOR4,
CLK_PIXEL => CLK_PIXEL_I,
CLUT_OFF => CLUT_OFF,
BLITTER_ON => BLITTER_ON,
VIDEO_RAM_CTR => VIDEO_RAM_CTR,
VIDEO_MOD_TA => VIDEO_MOD_TA,
CCR => CCR,
CCSEL => CC_SEL,
FBEE_CLUT_WR => CLUT_FBEE_WR,
INTER_ZEI => INTER_ZEI,
DOP_FIFO_CLR => DOP_FIFO_CLR,
VIDEO_RECONFIG => VIDEO_RECONFIG,
VR_WR => VR_WR,
VR_RD => VR_RD,
FIFO_CLR => FIFO_CLR_I,
DATA_IN => FB_AD_IN,
DATA_OUT => DATA_OUT_VIDEO_CTRL,
DATA_EN_H => DATA_EN_H_VIDEO_CTRL,
DATA_EN_L => DATA_EN_L_VIDEO_CTRL
);
end architecture;