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fixed formatting

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This commit is contained in:
Markus Fröschle
2014-08-09 19:17:09 +00:00
parent e9f5ee1ed3
commit cf659204c8
3 changed files with 264 additions and 266 deletions
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1
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -723,7 +723,6 @@ set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd
set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip
set_global_assignment -name VHDL_FILE ../../../testbenches/ddr_ram_model.vhd
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to CLK_DDR_OUT
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to CLK_DDR_OUTn
set_instance_assignment -name IO_STANDARD "2.5 V" -to CLK_DDR_OUTn

40
vhdl/rtl/vhdl/Interrupt/interrupt.vhd
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@@ -83,22 +83,22 @@ entity INTHANDLER is
end entity INTHANDLER;
architecture BEHAVIOUR of INTHANDLER is
type INT_LA_TYPE is array(9 downto 0) of std_logic_vector(3 downto 0);
signal INT_LA : INT_LA_TYPE;
signal FB_B : std_logic_vector(3 downto 0);
signal INT_CTR : std_logic_vector(31 downto 0);
signal INT_CTR_CS : std_logic;
signal INT_LATCH : std_logic_vector(31 downto 0);
signal INT_LATCH_CS : std_logic;
signal INT_CLEAR : std_logic_vector(31 downto 0);
signal INT_CLEAR_CS : std_logic;
signal INT_IN : std_logic_vector(31 downto 0);
signal INT_ENA : std_logic_vector(31 downto 0);
signal INT_ENA_CS : std_logic;
signal INT_L : std_logic_vector(9 downto 0);
signal FBEE_CONF_REG : std_logic_vector(31 downto 0);
signal FBEE_CONF_CS : std_logic;
signal PSEUDO_BUS_ERROR : std_logic;
type INT_LA_TYPE is array(9 downto 0) of std_logic_vector(3 downto 0);
signal INT_LA : INT_LA_TYPE;
signal FB_B : std_logic_vector(3 downto 0);
signal INT_CTR : std_logic_vector(31 downto 0);
signal INT_CTR_CS : std_logic;
signal INT_LATCH : std_logic_vector(31 downto 0);
signal INT_LATCH_CS : std_logic;
signal INT_CLEAR : std_logic_vector(31 downto 0);
signal INT_CLEAR_CS : std_logic;
signal INT_IN : std_logic_vector(31 downto 0);
signal INT_ENA : std_logic_vector(31 downto 0);
signal INT_ENA_CS : std_logic;
signal INT_L : std_logic_vector(9 downto 0);
signal FBEE_CONF_REG : std_logic_vector(31 downto 0);
signal FBEE_CONF_CS : std_logic;
signal PSEUDO_BUS_ERROR : std_logic;
begin
-- Byte selectors:
FB_B(0) <= '1' when FB_SIZE1 = '1' and FB_SIZE0 = '0' and FB_ADR(1) = '0' else -- High word.
@@ -128,12 +128,12 @@ begin
P_INT_CTRL : process
-- Interrupt control register:
--BIT0 = INT5, Bit1 = INT7.
-- BIT0 = INT5, Bit1 = INT7.
-- Interrupt enabe register:
-- BIT31 = INT7, Bit30 = INT6, Bit29 = INT5, Bit28 = INT4, Bit27 = INT3, Bit26 = INT2
-- The interrupt clear register is write only; 1 = interrupt clear.
begin
wait until CLK_MAIN = '1' and CLK_MAIN' event;
wait until rising_edge(CLK_MAIN);
if INT_CTR_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
INT_CTR(31 downto 24) <= FB_AD_IN(31 downto 24);
elsif INT_CTR_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then
@@ -196,7 +196,7 @@ begin
P_INT_LATCH : process
begin
wait until CLK_MAIN = '1' and CLK_MAIN' event;
wait until rising_edge(CLK_MAIN);
if RESETn = '0' then
INT_L <= (others => '0');
else
@@ -263,7 +263,7 @@ begin
P_FBEE_CONFIG : process
-- Firebee configuration register: BIT 31 -> 0 = CF 1 = IDE
begin
wait until CLK_MAIN = '1' and CLK_MAIN' event;
wait until rising_edge(CLK_MAIN);
if FBEE_CONF_CS = '1' and FB_B(0) = '1' and FB_WRn = '0' then
FBEE_CONF_REG(31 downto 24) <= FB_AD_IN(31 downto 24);
elsif FBEE_CONF_CS = '1' and FB_B(1) = '1' and FB_WRn = '0' then

5
vhdl/rtl/vhdl/Video/Video_Top.vhd
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@@ -210,7 +210,6 @@ architecture BEHAVIOUR of VIDEO_SYSTEM is
begin
CLK_PIXEL <= CLK_PIXEL_I;
FIFO_CLR <= FIFO_CLR_I;
P_CLUT_ST_MC: process
@@ -223,7 +222,7 @@ begin
clut_fa_index := to_integer(unsigned(FB_ADR(9 downto 2)));
clut_fi_index := to_integer(unsigned(FB_ADR(9 downto 2)));
wait until CLK_MAIN = '1' and CLK_MAIN' event;
wait until rising_edge(CLK_MAIN);
if CLUT_ST_WR(0) = '1' then
CLUT_ST(clut_st_index)(11 downto 8) <= FB_AD_IN(27 downto 24);
end if;
@@ -436,7 +435,7 @@ begin
DFF_CLK2: process
begin
wait until CLK_DDR2 = '1' and CLK_DDR2' event;
wait until rising_edge(CLK_DDR2);
VDMP <= SR_VDMP;
end process DFF_CLK2;