Firebee/FireBee_SVN
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

released 0.8.7 (new MMU layout, m5484LITE board working again)

Browse Source
This commit is contained in:
Markus Fröschle
2015-01-24 10:24:33 +00:00
parent f72b551170
commit ce6e8d58fd
284 changed files with 126529 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

478
BaS_gcc/sys/BaS.c Normal file
View File

@@ -0,0 +1,478 @@
/*
* BaS
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2011 - 2012 V. Riviere
* Copyright 2012 M. Froeschle
*/
#include <bas_types.h>
#include "MCF5475.h"
#include "startcf.h"
#include "sysinit.h"
#include "util.h"
#include "cache.h"
#include "bas_printf.h"
#include "bas_string.h"
#include "bas_types.h"
#include "sd_card.h"
#include "wait.h"
#include "diskio.h"
#include "ff.h"
#include "s19reader.h"
#include "mmu.h"
#include "dma.h"
#include "net.h"
#include "eth.h"
#include "nbuf.h"
#include "nif.h"
#include "fec.h"
#include "bootp.h"
#include "interrupts.h"
#include "exceptions.h"
#include "net_timer.h"
#include "pci.h"
#include "video.h"
//#define BAS_DEBUG
#if defined(BAS_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0)
/* imported routines */
extern int vec_init();
/* Symbols from the linker script */
extern uint8_t _STRAM_END[];
#define STRAM_END ((uint32_t)_STRAM_END)
extern uint8_t _TOS[];
#define TOS ((uint32_t)_TOS) /* final TOS location */
extern uint8_t _FASTRAM_END[];
#define FASTRAM_END ((uint32_t)_FASTRAM_END)
extern uint8_t _EMUTOS[];
#define EMUTOS ((uint32_t)_EMUTOS) /* where EmuTOS is stored in flash */
extern uint8_t _EMUTOS_SIZE[];
#define EMUTOS_SIZE ((uint32_t)_EMUTOS_SIZE) /* size of EmuTOS, in bytes */
/*
* check if it is possible to transfer data to PIC
*/
static inline bool pic_txready(void)
{
if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
{
return true;
}
return false;
}
/*
* check if it is possible to receive data from PIC
*/
static inline bool pic_rxready(void)
{
if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
{
return true;
}
return false;
}
void write_pic_byte(uint8_t value)
{
/*
* Wait until the transmitter is ready or 1000us are passed
*/
waitfor(1000, pic_txready);
/*
* Transmit the byte
*/
*(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
}
uint8_t read_pic_byte(void)
{
/*
* Wait until a byte has been received or 1000us are passed
*/
waitfor(1000, pic_rxready);
/*
* Return the received byte
*/
return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
}
void pic_init(void)
{
char answer[4] = "OLD";
xprintf("initialize the PIC: ");
/*
* Send the PIC initialization string
*/
write_pic_byte('A');
write_pic_byte('C');
write_pic_byte('P');
write_pic_byte('F');
/*
* Read the 3-char answer string. Should be "OK!".
*/
answer[0] = read_pic_byte();
answer[1] = read_pic_byte();
answer[2] = read_pic_byte();
answer[3] = '\0';
if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
{
dbg("PIC initialization failed. Already initialized?\r\n");
}
else
{
xprintf("%s\r\n", answer);
}
}
void nvram_init(void)
{
int i;
xprintf("Restore the NVRAM data: ");
/* Request for NVRAM backup data */
write_pic_byte(0x01);
/* Check answer type */
if (read_pic_byte() != 0x81)
{
// FIXME: PIC protocol error
xprintf("FAILED\r\n");
return;
}
/* Restore the NVRAM backup to the FPGA */
for (i = 0; i < 64; i++)
{
uint8_t data = read_pic_byte();
*(volatile uint8_t*)0xffff8961 = i;
*(volatile uint8_t*)0xffff8963 = data;
}
xprintf("finished\r\n");
}
#define KBD_ACIA_CONTROL * ((uint8_t *) 0xfffffc00)
#define MIDI_ACIA_CONTROL * ((uint8_t *) 0xfffffc04)
#define MFP_INTR_IN_SERVICE_A * ((uint8_t *) 0xfffffa0f)
#define MFP_INTR_IN_SERVICE_B * ((uint8_t *) 0xfffffa11)
void acia_init()
{
xprintf("init ACIA: ");
/* init ACIA */
KBD_ACIA_CONTROL = 3; /* master reset */
NOP();
MIDI_ACIA_CONTROL = 3; /* master reset */
NOP();
KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
NOP();
MFP_INTR_IN_SERVICE_A = 0xff;
NOP();
MFP_INTR_IN_SERVICE_B = 0xff;
NOP();
xprintf("finished\r\n");
}
void enable_coldfire_interrupts()
{
xprintf("enable interrupts: ");
#if defined(MACHINE_FIREBEE)
FBEE_INTR_CONTROL = 0L; /* disable all interrupts */
#endif /* MACHINE_FIREBEE */
MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */
#if defined(MACHINE_FIREBEE)
/*
* TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
* access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
*/
MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */
MCF_GPT_GMS_IEN |
MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */
MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 7 */
MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
//MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
MCF_INTC_IMRH = 0;
FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */
FBEE_INTR_INT_MFP_IRQ6 | /* enable MFP interrupts */
FBEE_INTR_INT_FPGA_IRQ5 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
FBEE_INTR_INT_VSYNC_IRQ4 | /* enable vsync interrupts */
FBEE_INTR_PCI_INTA | /* enable PCI interrupts */
FBEE_INTR_PCI_INTB |
FBEE_INTR_PCI_INTC |
FBEE_INTR_PCI_INTD;
#endif
xprintf("finished\r\n");
}
void disable_coldfire_interrupts()
{
#if defined(MACHINE_FIREBEE)
FBEE_INTR_ENABLE = 0; /* disable all interrupts */
#endif /* MACHINE_FIREBEE */
MCF_EPORT_EPIER = 0x0;
MCF_INTC_IMRL = 0xfffffffe;
MCF_INTC_IMRH = 0xffffffff;
}
NIF nif1;
#if defined(MACHINE_M5484LITE)
NIF nif2;
#endif
bool spurious_interrupt_handler(void *arg1, void *arg2)
{
dbg("IMRH=%lx, IMRL=%lx\r\n", MCF_INTC_IMRH, MCF_INTC_IMRL);
dbg("IPRH=%lx, IPRL=%lx\r\n", MCF_INTC_IPRH, MCF_INTC_IPRL);
dbg("IRLR=%x\r\n", MCF_INTC_IRLR);
return true;
}
/*
* initialize the interrupt handler tables to dispatch interrupt requests from Coldfire devices
*/
void init_isr(void)
{
isr_init(); /* need to call that explicitely, otherwise isr table might be full */
/*
* register spurious interrupt handler
*/
if (!isr_register_handler(24, 6, 6, spurious_interrupt_handler, NULL, NULL))
{
dbg("unable to register spurious interrupt handler\r\n");
}
/*
* register the FEC interrupt handler
*/
if (!isr_register_handler(64 + INT_SOURCE_FEC0, 5, 1, fec0_interrupt_handler, NULL, (void *) &nif1))
{
dbg("unable to register isr for FEC0\r\n");
}
/*
* Register the DMA interrupt handler
*/
if (!isr_register_handler(64 + INT_SOURCE_DMA, 5, 3, dma_interrupt_handler, NULL, NULL))
{
dbg("unable to register isr for DMA\r\n");
}
#ifdef MACHINE_FIREBEE
/*
* register GPT0 timer interrupt vector
*/
if (!isr_register_handler(64 + INT_SOURCE_GPT0, 5, 2, gpt0_interrupt_handler, NULL, NULL))
{
dbg("unable to register isr for GPT0 timer\r\n");
}
/*
* register the PIC interrupt handler
*/
if (!isr_register_handler(64 + INT_SOURCE_PSC3, 5, 5, pic_interrupt_handler, NULL, NULL))
{
dbg("Error: unable to register ISR for PSC3\r\n");
}
#endif /* MACHINE_FIREBEE */
/*
* register the XLB PCI interrupt handler
*/
if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, 7, 0, xlbpci_interrupt_handler, NULL, NULL))
{
dbg("Error: unable to register isr for XLB PCI interrupts\r\n");
}
MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */
MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */
MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */
MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */
MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */
MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */
if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 7, 1, pciarb_interrupt_handler, NULL, NULL))
{
dbg("Error: unable to register isr for PCIARB interrupts\r\n");
return;
}
MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */
}
void BaS(void)
{
uint8_t *src;
uint8_t *dst = (uint8_t *) TOS;
#if defined(MACHINE_FIREBEE) /* LITE board has no pic and (currently) no nvram */
pic_init();
nvram_init();
#endif /* MACHINE_FIREBEE */
xprintf("initialize MMU: ");
mmu_init();
xprintf("finished\r\n");
xprintf("copy EmuTOS: ");
dma_init();
/* copy EMUTOS */
src = (uint8_t *) EMUTOS;
dma_memcpy(dst, src, EMUTOS_SIZE);
xprintf("finished\r\n");
xprintf("initialize exception vector table: ");
vec_init();
xprintf("finished\r\n");
xprintf("flush caches: ");
flush_and_invalidate_caches();
xprintf("finished\r\n");
xprintf("enable MMU: ");
MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */
NOP(); /* force pipeline sync */
xprintf("finished\r\n");
#ifdef MACHINE_FIREBEE
xprintf("IDE reset: ");
/* IDE reset */
* (volatile uint8_t *) (0xffff8802 - 2) = 14;
* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
wait(1);
* (volatile uint8_t *) (0xffff8802 - 0) = 0;
xprintf("finished\r\n");
xprintf("enable video: ");
/*
* video setup (25MHz)
*/
* (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba; /* horizontal 640x480 */
* (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a; /* vertical 640x480 */
* (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d; /* horizontal 320x240 */
* (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */
/* fifo on, refresh on, ddrcs and cke on, video dac on */
* (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
xprintf("finished\r\n");
#endif /* MACHINE_FIREBEE */
sd_card_init();
/*
* memory setup
*/
memset((void *) 0x400, 0, 0x400);
#if defined(MACHINE_FIREBEE)
/* set Falcon bus control register */
/* sets bit 3 and 6. Both are undefined on an original Falcon? */
* (volatile uint8_t *) 0xffff8007 = 0x48;
#endif /* MACHINE_FIREBEE */
/* ST RAM */
* (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */
* (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */
* (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
* (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
/* TT-RAM */
* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
#if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */
acia_init();
#endif /* MACHINE_FIREBEE */
srec_execute("BASFLASH.S19");
/* Jump into the OS */
typedef void void_func(void);
struct rom_header
{
void *initial_sp;
void_func *initial_pc;
};
xprintf("BaS initialization finished, enable interrupts\r\n");
init_isr();
enable_coldfire_interrupts();
MCF_INTC_IMRH = 0;
MCF_INTC_IMRL = 0;
dma_irq_enable();
fec_irq_enable(0, 5, 1);
init_pci();
// video_init();
/* initialize USB devices */
//init_usb();
set_ipl(7); /* disable interrupts */
xprintf("call EmuTOS\r\n");
struct rom_header *os_header = (struct rom_header *) TOS;
os_header->initial_pc();
}

239
BaS_gcc/sys/cache.c Normal file
View File

@@ -0,0 +1,239 @@
/*
* cache handling
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2011 - 2012 V. Riviere
* Copyright 2012 M. Froeschle
*
*/
#include "cache.h"
void cacr_set(uint32_t value)
{
extern uint32_t rt_cacr;
rt_cacr = value;
__asm__ __volatile__("movec %0, cacr\n\t"
: /* output */
: "r" (rt_cacr)
: "memory" /* clobbers */);
}
uint32_t cacr_get(void)
{
extern uint32_t rt_cacr;
return rt_cacr;
}
void disable_data_cache(void)
{
flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
}
void disable_instruction_cache(void)
{
flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
}
void enable_data_cache(void)
{
cacr_set(cacr_get() & ~CF_CACR_DCINVA);
}
void flush_and_invalidate_caches(void)
{
__asm__ __volatile__(
" clr.l d0 \n\t"
" clr.l d1 \n\t"
" move.l d0,a0 \n\t"
"cfa_setloop: \n\t"
" cpushl bc,(a0) | flush\n\t"
" lea 0x10(a0),a0 | index+1\n\t"
" addq.l #1,d1 | index+1\n\t"
" cmpi.w #512,d1 | all sets?\n\t"
" bne.s cfa_setloop | no->\n\t"
" clr.l d1 \n\t"
" addq.l #1,d0 \n\t"
" move.l d0,a0 \n\t"
" cmpi.w #4,d0 | all ways?\n\t"
" bne.s cfa_setloop | no->\n\t"
/* input */ :
/* output */ :
/* clobber */ : "cc", "d0", "d1", "a0"
);
}
/*
* flush and invalidate a specific memory region from the instruction cache
*/
void flush_icache_range(void *address, size_t size)
{
uint32_t set;
uint32_t start_set;
uint32_t end_set;
void *endaddr = address + size;
start_set = (uint32_t) address & _ICACHE_SET_MASK;
end_set = (uint32_t) endaddr & _ICACHE_SET_MASK;
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set) /* input parameters */
: "cc" /* clobbered registers */
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_ICACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3)) {
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set])"
: /* output parameters */
: [set] "a" (set)
: "cc"
);
}
}
/*
* flush and invalidate a specific region from the data cache
*/
void flush_dcache_range(void *address, size_t size)
{
unsigned long set;
unsigned long start_set;
unsigned long end_set;
void *endaddr;
endaddr = address + size;
start_set = (uint32_t) address & _DCACHE_SET_MASK;
end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_DCACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq%.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
}
/*
* flush and invalidate a specific region from the both caches. We do not know if the area is cached
* at all, we do not know in which of the four ways it is cached, but we know the index where they
* would be cached if they are, so we only need to flush and invalidate only a subset of the 512 index
* entries, but all four ways.
*/
void flush_cache_range(void *address, size_t size)
{
unsigned long set;
unsigned long start_set;
unsigned long end_set;
void *endaddr;
endaddr = address + size;
start_set = (uint32_t) address & _DCACHE_SET_MASK;
end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_DCACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" addq%.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
}

341
BaS_gcc/sys/driver_mem.c Normal file
View File

@@ -0,0 +1,341 @@
/*
* driver_mem.c
*
* based from Emutos / BDOS
*
* Copyright (c) 2001 Lineo, Inc.
*
* Authors: Karl T. Braun, Martin Doering, Laurent Vogel
*
* This file is distributed under the GPL, version 2 or at your
* option any later version.
*/
#include <bas_types.h>
#include "bas_string.h"
#include "bas_printf.h"
#include "usb.h"
#include "exceptions.h" /* set_ipl() */
#if defined(MACHINE_FIREBEE)
#include "firebee.h"
#elif defined(MACHINE_M5484LITE)
#include "m5484l.h"
#elif defined(MACHINE_M54455)
#include "m54455.h"
#else
#error "unknown machine!"
#endif
//#define DBG_DM
#ifdef DBG_DM
#define dbg(fmt, args...) xprintf(fmt, ##args)
#else
#define dbg(fmt, args...)
#endif
extern long offscren_reserved(void);
extern uint8_t driver_mem_buffer[DRIVER_MEM_BUFFER_SIZE]; /* defined in linker control file */
/* MD - Memory Descriptor */
#define MD struct _md_
MD
{
MD *m_link;
long m_start;
long m_length;
void *m_own;
};
/* MPB - Memory Partition Block */
#define MPB struct _mpb
MPB
{
MD *mp_mfl;
MD *mp_mal;
MD *mp_rover;
};
#define MAXMD 256
static MD tab_md[MAXMD];
static MPB pmd;
static void *xmgetblk(void)
{
int i;
for (i = 0; i < MAXMD; i++)
{
if (tab_md[i].m_own == NULL)
{
tab_md[i].m_own = (void*)1L;
return(&tab_md[i]);
}
}
return NULL;
}
static void xmfreblk(void *m)
{
int i = (int)(((long) m - (long) tab_md) / sizeof(MD));
if ((i > 0) && (i < MAXMD))
{
tab_md[i].m_own = NULL;
}
}
static MD *ffit(long amount, MPB *mp)
{
MD *p, *q, *p1; /* free list is composed of MD's */
int maxflg;
long maxval;
if (amount != -1)
{
amount += 15; /* 16 bytes alignment */
amount &= 0xFFFFFFF0;
}
if ((q = mp->mp_rover) == 0) /* get rotating pointer */
{
return 0;
}
maxval = 0;
maxflg = ((amount == -1) ? true : false) ;
p = q->m_link; /* start with next MD */
do /* search the list for an MD with enough space */
{
if (p == 0)
{
/* at end of list, wrap back to start */
q = (MD *) &mp->mp_mfl; /* q => mfl field */
p = q->m_link; /* p => 1st MD */
}
if ((!maxflg) && (p->m_length >= amount))
{
/* big enough */
if (p->m_length == amount)
{
q->m_link = p->m_link; /* take the whole thing */
}
else
{
/*
* break it up - 1st allocate a new
* MD to describe the remainder
*/
p1 = xmgetblk();
if (p1 == NULL)
{
return(NULL);
}
/* init new MD */
p1->m_length = p->m_length - amount;
p1->m_start = p->m_start + amount;
p1->m_link = p->m_link;
p->m_length = amount; /* adjust allocated block */
q->m_link = p1;
}
/* link allocate block into allocated list,
mark owner of block, & adjust rover */
p->m_link = mp->mp_mal;
mp->mp_mal = p;
mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
return(p); /* got some */
}
else if (p->m_length > maxval)
maxval = p->m_length;
p = ( q=p )->m_link;
} while(q != mp->mp_rover);
/*
* return either the max, or 0 (error)
*/
if (maxflg)
{
maxval -= 15; /* 16 bytes alignment */
if (maxval < 0)
{
maxval = 0;
}
else
{
maxval &= 0xFFFFFFF0;
}
}
return(maxflg ? (MD *) maxval : 0);
}
static void freeit(MD *m, MPB *mp)
{
MD *p, *q;
q = 0;
for (p = mp->mp_mfl; p ; p = (q = p) -> m_link)
{
if (m->m_start <= p->m_start)
{
break;
}
}
m->m_link = p;
if (q)
{
q->m_link = m;
}
else
{
mp->mp_mfl = m;
}
if (!mp->mp_rover)
{
mp->mp_rover = m;
}
if (p)
{
if (m->m_start + m->m_length == p->m_start)
{
/* join to higher neighbor */
m->m_length += p->m_length;
m->m_link = p->m_link;
if (p == mp->mp_rover)
{
mp->mp_rover = m;
}
xmfreblk(p);
}
}
if (q)
{
if (q->m_start + q->m_length == m->m_start)
{
/* join to lower neighbor */
q->m_length += m->m_length;
q->m_link = m->m_link;
if (m == mp->mp_rover)
{
mp->mp_rover = q;
}
xmfreblk(m);
}
}
}
int32_t driver_mem_free(void *addr)
{
int level;
MD *p, **q;
MPB *mpb;
mpb = &pmd;
level = set_ipl(7);
for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
{
if ((long) addr == p->m_start)
{
break;
}
}
if (!p)
{
set_ipl(level);
return(-1);
}
*q = p->m_link;
freeit(p, mpb);
set_ipl(level);
dbg("%s: driver_mem_free(0x%08X)\r\n", __FUNCTION__, addr);
return(0);
}
void *driver_mem_alloc(uint32_t amount)
{
void *ret = NULL;
int level;
MD *m;
if (amount == -1L)
{
return (void *) ffit(-1L, &pmd);
}
if (amount <= 0 )
{
return(0);
}
if ((amount & 1))
{
amount++;
}
level = set_ipl(7);
m = ffit(amount, &pmd);
if (m != NULL)
{
ret = (void *) m->m_start;
}
set_ipl(level);
dbg("%s: driver_mem_alloc(%d) = 0x%08X\r\n", __FUNCTION__, amount, ret);
return ret;
}
static int use_count = 0;
int driver_mem_init(void)
{
if (use_count == 0)
{
dbg("%s: initialise driver_mem_buffer[] at %p, size 0x%x\r\n", __FUNCTION__, driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE);
pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
tab_md[0].m_link = (MD *) NULL;
tab_md[0].m_start = ((long) driver_mem_buffer + 15) & ~15;
tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;
tab_md[0].m_own = (void *) 1L;
pmd.mp_mal = (MD *) NULL;
memset(driver_mem_buffer, 0, tab_md[0].m_length);
dbg("%s: uncached driver memory buffer at 0x%08X size %d\r\n", __FUNCTION__, tab_md[0].m_start, tab_md[0].m_length);
}
use_count++;
dbg("%s: driver_mem now has a use count of %d\r\n", __FUNCTION__, use_count);
return 0;
}
void driver_mem_release(void)
{
if (use_count-- == 0)
{
#ifndef CONFIG_USB_MEM_NO_CACHE
#ifdef USE_RADEON_MEMORY
if (driver_mem_buffer == (void *) offscren_reserved())
return;
#endif
#endif
}
dbg("%s: driver_mem use count now %d\r\n", __FUNCTION__, use_count);
}

600
BaS_gcc/sys/exceptions.S Normal file
View File

@@ -0,0 +1,600 @@
/*
* initialize exception vectors
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 26.02.2013
* Author: Markus Fröschle
*/
#include "startcf.h"
#if MACHINE_FIREBEE
#include "firebee.h"
#elif MACHINE_M5484LITE
#include "m5484l.h"
#endif /* MACHINE_FIREBEE */
.extern __SUP_SP
.extern _rom_entry
.extern __RAMBAR0
.extern _rt_mod
.extern _rt_ssp
.extern _rt_usp
.extern _rt_vbr
.extern _mmutr_miss
.extern __MBAR
.extern __MMUBAR
.extern _video_tlb
.extern _video_sbt
.extern _flush_and_invalidate_caches
.extern _get_bas_drivers
/* PCI interrupt handlers */
.extern _irq5_handler
.extern _irq6_handler
.extern _irq7_handler
.global _vec_init
.global _std_exc_vec /* needed by driver_vec.c */
/* Register read/write equates */
/* MMU */
.equ MCF_MMU_MMUCR, __MMUBAR
.equ MCF_MMU_MMUOR, __MMUBAR+0x04
.equ MCF_MMU_MMUSR, __MMUBAR+0x08
.equ MCF_MMU_MMUAR, __MMUBAR+0x10
.equ MCF_MMU_MMUTR, __MMUBAR+0x14
.equ MCF_MMU_MMUDR, __MMUBAR+0x18
/* EPORT flag register */
.equ MCF_EPORT_EPFR, __MBAR+0xf0c
/* FEC1 port output data direction register */
.equ MCF_GPIO_PODR_FEC1L, __MBAR+0xa07
/* PSC0 transmit buffer register */
.equ MCF_PSC0_PSCTB_8BIT, __MBAR+0x860c
/* GPT mode select register */
.equ MCF_GPT0_GMS, __MBAR+0x800
/* Slice timer 0 count register */
.equ MCF_SLT0_SCNT, __MBAR+0x908
// interrupt sources
.equ INT_SOURCE_EPORT_EPF1,1 // edge port flag 1
.equ INT_SOURCE_EPORT_EPF2,2 // edge port flag 2
.equ INT_SOURCE_EPORT_EPF3,3 // edge port flag 3
.equ INT_SOURCE_EPORT_EPF4,4 // edge port flag 4
.equ INT_SOURCE_EPORT_EPF5,5 // edge port flag 5
.equ INT_SOURCE_EPORT_EPF6,6 // edge port flag 6
.equ INT_SOURCE_EPORT_EPF7,7 // edge port flag 7
.equ INT_SOURCE_USB_EP0ISR,15 // USB endpoint 0 interrupt
.equ INT_SOURCE_USB_EP1ISR,16 // USB endpoint 1 interrupt
.equ INT_SOURCE_USB_EP2ISR,17 // USB endpoint 2 interrupt
.equ INT_SOURCE_USB_EP3ISR,18 // USB endpoint 3 interrupt
.equ INT_SOURCE_USB_EP4ISR,19 // USB endpoint 4 interrupt
.equ INT_SOURCE_USB_EP5ISR,20 // USB endpoint 5 interrupt
.equ INT_SOURCE_USB_EP6ISR,21 // USB endpoint 6 interrupt
.equ INT_SOURCE_USB_USBISR,22 // USB general interrupt
.equ INT_SOURCE_USB_USBAISR,23 // USB core interrupt
.equ INT_SOURCE_USB_ANY,24 // OR of all USB interrupts
.equ INT_SOURCE_USB_DSPI_OVF,25 // DSPI overflow or underflow
.equ INT_SOURCE_USB_DSPI_RFOF,26 // receive FIFO overflow interrupt
.equ INT_SOURCE_USB_DSPI_RFDF,27 // receive FIFO drain interrupt
.equ INT_SOURCE_USB_DSPI_TFUF,28 // transmit FIFO underflow interrupt
.equ INT_SOURCE_USB_DSPI_TCF,29 // transfer complete interrupt
.equ INT_SOURCE_USB_DSPI_TFFF,30 // transfer FIFO fill interrupt
.equ INT_SOURCE_USB_DSPI_EOQF,31 // end of queue interrupt
.equ INT_SOURCE_PSC3,32 // PSC3 interrupt
.equ INT_SOURCE_PSC2,33 // PSC2 interrupt
.equ INT_SOURCE_PSC1,34 // PSC1 interrupt
.equ INT_SOURCE_PSC0,35 // PSC0 interrupt
.equ INT_SOURCE_CTIMERS,36 // combined source for comm timers
.equ INT_SOURCE_SEC,37 // SEC interrupt
.equ INT_SOURCE_FEC1,38 // FEC1 interrupt
.equ INT_SOURCE_FEC0,39 // FEC0 interrupt
.equ INT_SOURCE_I2C,40 // I2C interrupt
.equ INT_SOURCE_PCIARB,41 // PCI arbiter interrupt
.equ INT_SOURCE_CBPCI,42 // COMM bus PCI interrupt
.equ INT_SOURCE_XLBPCI,43 // XLB PCI interrupt
.equ INT_SOURCE_XLBARB,47 // XLBARB to PCI interrupt
.equ INT_SOURCE_DMA,48 // multichannel DMA interrupt
.equ INT_SOURCE_CAN0_ERROR,49 // FlexCAN error interrupt
.equ INT_SOURCE_CAN0_BUSOFF,50 // FlexCAN bus off interrupt
.equ INT_SOURCE_CAN0_MBOR,51 // message buffer ORed interrupt
.equ INT_SOURCE_SLT1,53 // slice timer 1 interrupt
.equ INT_SOURCE_SLT0,54 // slice timer 0 interrupt
.equ INT_SOURCE_CAN1_ERROR,55 // FlexCAN error interrupt
.equ INT_SOURCE_CAN1_BUSOFF,56 // FlexCAN bus off interrupt
.equ INT_SOURCE_CAN1_MBOR,57 // message buffer ORed interrupt
.equ INT_SOURCE_GPT3,59 // GPT3 timer interrupt
.equ INT_SOURCE_GPT2,60 // GPT2 timer interrupt
.equ INT_SOURCE_GPT1,61 // GPT1 timer interrupt
.equ INT_SOURCE_GPT0,62 // GPT0 timer interrupt
// Atari register equates (provided by FPGA)
.equ vbasehi, 0xffff8201
/*
* macros
*/
/*
* used for "forwarding" interrupt handlers. This just clears the "pending interrupt"
* flag from the EDGE PORT flag register, set the status register to the appropriate interrupt
* mask an jump through the corresponging vector
*/
.macro irq vector,int_mask,clr_int
move.w #0x2700,sr // disable interrupt
subq.l #8,sp
movem.l d0/a5,(sp) // save registers
lea MCF_EPORT_EPFR,a5
move.b #\clr_int,(a5) // clear int pending
movem.l (sp),d0/a5 // restore registers
addq.l #8,sp
move.l \vector,-(sp)
move #0x2\int_mask\()00,sr
rts
.endm
.text
_vec_init:
move.l a2,-(sp) // Backup registers
mov3q.l #-1,_rt_mod // rt_mod auf super
clr.l _rt_ssp
clr.l _rt_usp
clr.l _rt_vbr
move.l #__RAMBAR0,d0 // exception vectors reside in rambar0
movec d0,VBR
move.l d0,a0
move.l a0,a2
/*
* first, set standard vector for all exceptions
*/
init_vec:
move.l #256,d0
lea std_exc_vec(pc),a1 // standard vector
init_vec_loop:
move.l a1,(a2)+ // set standard vector for all exceptions
subq.l #1,d0
bne init_vec_loop
// set individual interrupt handler assignments
move.l #__SUP_SP,(a0) // set initial stack pointer at start of exception vector table
lea reset_vector(pc),a1 // set reset vector
move.l a1,0x04(a0)
lea access(pc),a1 // set illegal access exception handler
move.l a1,0x08(a0)
// install spurious interrupt handler
lea _lowlevel_isr_handler,a1
move.l a1,0x60(a0)
// trap #0 (without any parameters for now) is used to provide BaS' driver addresses to the OS
lea _get_bas_drivers(pc),a1
move.l a1,0x80(a0) // trap #0 exception vector
// MFP non-autovector interrupt handlers. Those are just rerouted to their autovector counterparts
lea irq1(pc),a1
move.l a1,0x104(a0)
lea irq2(pc),a1
move.l a1,0x108(a0)
lea irq3(pc),a1
move.l a1,0x10c(a0)
lea irq4(pc),a1
move.l a1,0x110(a0)
lea irq5(pc),a1
move.l a1,0x114(a0)
lea irq6(pc),a1
move.l a1,0x118(a0)
lea irq7(pc),a1
move.l a1,0x11c(a0)
// install lowlevel_isr_handler for the three GPT timers
lea _lowlevel_isr_handler(pc),a1
move.l a1,(INT_SOURCE_GPT1 + 64) * 4(a0)
move.l a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
// install lowlevel_isr_handler for the PSC3 interrupt
move.l a1,(INT_SOURCE_PSC3 + 64) * 4(a0)
// install lowlevel_isr_handler for Coldfire DMA interrupts
move.l a1,(INT_SOURCE_DMA + 64) * 4(a0)
// install lowlevel_isr_handler for the XLBPCI interrupt
move.l a1,(INT_SOURCE_XLBPCI + 64) * 4(a0)
// install lowlevel_isr_handler for the FEC0 interrupt
move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
#ifndef MACHINE_FIREBEE
// FEC1 not wired on the FireBee (used for FPGA as GPIO), but available on other machines
move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
#endif
#ifdef MACHINE_FIREBEE
// timer vectors (triggers when vbashi gets changed, used for video page copy)
move.l a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
#endif /* MACHINE_FIREBEE */
move.l (sp)+,a2 // Restore registers
rts
/*
* exception vector routines
*/
vector_table_start:
std_exc_vec:
_std_exc_vec:
//move.w #0x2700,sr // disable interrupt
subq.l #8,sp
movem.l d0/a5,(sp) // save registers
move.w 8(sp),d0 // fetch vector
and.l #0x3fc,d0 // mask out vector number
//#define DBG_EXC
#ifdef DBG_EXC
// printout vector number of exception
lea -4 * 4(sp),sp // reserve stack space
movem.l d0-d1/a0-a1,(sp) // save gcc scratch registers
lsr.l #2,d0 // shift vector number in place
cmp.l #33,d0
beq noprint
cmp.l #34,d0
beq noprint
cmp.l #45,d0
beq noprint
cmp.l #46,d0
beq noprint
move.l 4 * 4 + 8 + 4(sp),-(sp) // pc at exception
move.l d0,-(sp) // provide it to xprintf()
pea exception_text
jsr _xprintf // call xprintf()
add.l #3*4,sp // adjust stack
noprint:
movem.l (sp),d0-d1/a0-a1 // restore registers
lea 4 * 4(sp),sp
#endif /* DBG_EXC */
add.l _rt_vbr,d0 // + VBR
move.l d0,a5
move.l (a5),d0 // fetch exception routine address
move.l 4(sp),a5 // restore a5
move.l d0,4(sp) // store exception routine address
// FIXME: not clear why we would need the following?
//move.w 10(sp),d0 // restore original SR
//bset #13,d0 // set supervisor bit
//move.w d0,sr //
move.l (sp)+,d0 // restore d0
rts // jump to exception handler
exception_text:
.ascii "DEBUG: EXCEPTION %d caught at %p"
.byte 13, 10, 0
.align 4
reset_vector:
move.w #0x2700,sr // disable interrupts
move.l #0x31415926,d0
cmp.l 0x426,d0 // _resvalid: reset vector valid?
beq std_exc_vec // yes->
jmp _rom_entry // no, cold start machine
access:
move.w #0x2700,sr // disable interrupts
link a6,#-4 * 4 // make room for gcc scratch registers
movem.l d0-d1/a0-a1,(sp) // save them
move.l 4(a6),-(sp) // push format_status
move.l 8(a6),-(sp) // pc at exception
move.l MCF_MMU_MMUAR,-(sp) // MMU fault address
move.l MCF_MMU_MMUSR,-(sp) // MMU status regisrter
move.w #0x2300,sr // can lower interrupt mask now that MMU status is safe
jsr _mmutr_miss // call C routine
lea 4 * 4(sp),sp // adjust stack
tst.l d0 // exception handler signals bus error
bne bus_error
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6
rte
bus_error:
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6
bra std_exc_vec // FIXME: this seems to be bogous...
zero_divide:
move.w #0x2700,sr // disable interrupt
move.l a0,-(sp)
move.l d0,-(sp)
move.l 12(sp),a0 // pc
move.w (a0)+,d0 // command word
btst #7,d0 // long?
beq zd_word // nein->
addq.l #2,a0
zd_word:
and.l 0x3f,d0 // mask out ea field
cmp.w #0x08,d0 // -(ax) or less?
ble zd_end
addq.l #2,a0
cmp.w #0x39,d0 // xxx.L
bne zd_nal
addq.l #2,a0
bra zd_end
zd_nal: cmp.w #0x3c,d0 // immediate?
bne zd_end // no->
btst #7,d0 // long?
beq zd_end // no
addq.l #2,a0
zd_end:
move.l a0,12(sp)
move.l (sp)+,d0
move.l (sp)+,a0
rte
#ifdef _NOT_USED_
linea:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
linef:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
format:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
//floating point
flpoow:
move.w #0x2700,sr // disable interrupt
halt
nop
nop
#endif /* _NOT_USED */
irq1: irq 0x64, 1, 0x02 // Level 1 autovector interrupt (unused)
irq2: irq 0x68, 2, 0x04 // Level 2 autovector interrupt (horizontal blank)
irq3: irq 0x6c, 3, 0x08 // Level 3 autovector interrupt (unused)
irq4: irq 0x70, 4, 0x10 // Level 4 autovector interrupt (vertical blank)
#if defined(MACHINE_FIREBEE) /* these handlers are only meaningful for the Firebee */
irq5: //move.w #0x2700,sr // disable interrupts
subq.l #4,sp // extra space
link a6,#-4 * 4 // save gcc scratch registers
movem.l d0-d1/a0-a1,(sp)
jsr _irq5_handler // call C handler routine
tst.b d0 // handled?
beq irq5_forward
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6
addq.l #4,sp
rte // return from exception
irq5_forward: move.l 0x74,a0 // fetch OS irq5 vector
add.l _rt_vbr,a0 // add runtime vbr
move.l a0,4(a6) // put on stack
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6 //
move.w #0x2500,sr // set interrupt level
rts // jump through vector
/*
* irq6 needs special treatment since - because the Coldfire only supports autovector interrupts
* - the exception vector is provided by the simulated MFP from the FPGA
*/
irq6: //move.w #0x2700,sr // disable interrupt
subq.l #4,sp // extra space
link a6,#-4 * 4 // save gcc scratch registers
movem.l d0-d1/a0-a1,(sp)
move.l 8(a6),-(sp) // format status word
move.l 12(a6),-(sp) // pc at exception
jsr _irq6_handler // call C handler
lea 8(sp),sp // fix stack
tst.b d0 // interrupt handled?
beq irq6_forward // no, forward to TOS
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6
addq.l #4,sp // "extra space" not needed in this case
rte
irq6_forward:
move.l 0xf0020000,a0 // fetch "MFP interrupt vector" from FPGA
add.l _rt_vbr,a0 // add runtime VBR
move.l (a0),4(a6) // fetch handler address and put it on "extra space"
movem.l (sp),d0-d1/a0-a1
unlk a6
move.w #0x2600,sr // set interrupt mask to MFP level
rts // jump through vector
/*
* irq 7 = pseudo bus error
*/
irq7:
lea -12(sp),sp
movem.l d0/a0,(sp)
move.l __RAMBAR0+0x008,a0 // real access error handler
move.l a0,8(sp) // this will be the return address for rts
move.w 12(sp),d0 // format/vector word
andi.l #0xf000,d0 // keep only the format
ori.l #2*4,d0 // simulate vector #2, no fault
move.w d0,12(sp)
// TODO: Inside an interrupt handler, 16(sp) is the return address.
// For an Access Error, it should be the address of the fault instruction instead
lea MCF_EPORT_EPFR,a0
bset #7,(a0) // clear int 7
move.l (sp)+,d0 // restore registers
move.l (sp)+,a0
rts // Forward to the Access Error handler
#else // handlers for M5484LITE
irq5: //move.w #0x2700,sr // disable interrupts
subq.l #4,sp // extra space
link a6,#-4 * 4 // save gcc scratch registers
movem.l d0-d1/a0-a1,(sp)
jsr _irq5_handler // call C handler routine
tst.b d0 // handled?
beq irq5_forward
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6
addq.l #4,sp
rte // return from exception
irq5_forward: move.l 0x74,a0 // fetch OS irq5 vector
add.l _rt_vbr,a0 // add runtime vbr
move.l a0,4(a6) // put on stack
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6 //
move.w #0x2500,sr // set interrupt level
rts // jump through vector
irq6:
irq 0x74,5,0x20
irq7: // irq7 is tied to PCI INTA# and PCI INTB# on the M5484LITE
//move.w #0x2700,sr // disable interrupts
lea -4*4(sp),sp // save gcc scratch registers
movem.l d0-d1/a0-a1,(sp)
jsr _irq7_handler // call C handler routine
movem.l (sp),d0-d1/a0-a1 // restore registers
lea 4*4(sp),sp
rte // return from exception
irq7text:
.data
.ascii "IRQ7!"
.dc.b 13,10,0
.text
#endif /* MACHINE_FIREBEE */
/*
* low-level interrupt service routine for routines registered with
* isr_register_handler(int vector). If the higlevel routine (isr_execute_handler())
* returns != true, the call is forwarded to the OS (through its own vector base).
*/
.global _lowlevel_isr_handler
.extern _isr_execute_handler
/*
* stack format (after link instruction) is like this:
*
* +12 program counter (return address)
* +8 format_status
* +4 save area for rts (if we need to jump through the OS vector)
* (a6) -> saved a6 (from link)
* -4
* -8
* -12
* (sp) -> gcc scratch registers save area
*/
_lowlevel_isr_handler:
subq.l #4,sp // extra space
link a6,#-4 * 4 // make room for
movem.l d0-d1/a0-a1,(sp) // gcc scratch registers and save them,
// other registers will be taken care of by gcc itself
move.w 8(a6),d0 // fetch vector number from stack
lsr.l #2,d0 // move it in place
andi.l #0xff,d0 // mask it out
move.l d0,-(sp) // push it
jsr _isr_execute_handler // call the C handler
addq.l #4,sp // adjust stack
tst.b d0 // handled?
beq lowlevel_forward // no, forward it to TOS
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6
addq.l #4,sp // eliminate extra space
rte
lowlevel_forward:
move.l 8(a6),d0 // fetch OS irq vector
lsr.l #2,d0 // move it in place
andi.l #0xff,d0 // mask out vector number
add.l _rt_vbr,d0 // add runtime vbr
move.l d0,4(a6) // put on stack as return address
movem.l (sp),d0-d1/a0-a1 // restore registers
unlk a6 //
rts // jump through vector

235
BaS_gcc/sys/fault_vectors.c Normal file
View File

@@ -0,0 +1,235 @@
/*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* provide an early exception vector branch table to catch exceptions _before_ VBR has been setup eventually
* (to RAMBAR0, in exceptions.S)
*/
#include "MCF5475.h"
#include "bas_types.h"
#include "bas_printf.h"
typedef void (*exception_handler)(void);
extern exception_handler SDRAM_VECTOR_TABLE[];
/*
* decipher Coldfire exception stack frame and print it out in cleartext
*/
void fault_handler(uint32_t pc, uint32_t format_status)
{
int format;
int fault_status;
int vector;
int sr;
xprintf("\007\007exception! Processor halted.\r\n");
xprintf("format_status: %lx\r\n", format_status);
xprintf("pc: %lx\r\n", pc);
/*
* extract info from format-/status word
*/
format = (format_status & 0b11110000000000000000000000000000) >> 28;
fault_status = ((format_status & 0b00001100000000000000000000000000) >> 26) |
((format_status & 0b00000000000000110000000000000000) >> 16);
vector = (format_status & 0b00000011111111000000000000000000) >> 18;
sr = (format_status & 0b00000000000000001111111111111111);
xprintf("format: %x\r\n", format);
xprintf("fault_status: %x (", fault_status);
switch (fault_status)
{
case 0:
xprintf("not an access or address error nor an interrupted debug service routine");
break;
case 1:
case 3:
case 11:
xprintf("reserved");
break;
case 2:
xprintf("interrupt during a debug service routine for faults other than access errors");
break;
case 4:
xprintf("error (for example, protection fault) on instruction fetch");
break;
case 5:
xprintf("TLB miss on opword or instruction fetch");
break;
case 6:
xprintf("TLB miss on extension word of instruction fetch");
break;
case 7:
xprintf("IFP access error while executing in emulator mode");
break;
case 8:
xprintf("error on data write");
break;
case 9:
xprintf("error on attempted write to write-protected space");
break;
case 10:
xprintf("TLB miss on data write");
break;
case 12:
xprintf("error on data read");
break;
case 13:
xprintf("attempted read, read-modify-write of protected space");
break;
case 14:
xprintf("TLB miss on data read or read-modify-write");
break;
case 15:
xprintf("OEP access error while executing in emulator mode");
}
xprintf(")\r\n");
xprintf("vector = %d (", vector);
switch (vector)
{
case 2:
xprintf("access error");
break;
case 3:
xprintf("address error");
break;
case 4:
xprintf("illegal instruction");
break;
case 5:
xprintf("divide by zero");
break;
case 8:
xprintf("privilege violation");
break;
case 9:
xprintf("trace");
break;
case 10:
xprintf("unimplemented line-a opcode");
break;
case 11:
xprintf("unimplemented line-f opcode");
break;
case 12:
xprintf("non-PC breakpoint debug interrupt");
break;
case 13:
xprintf("PC breakpoint debug interrupt");
break;
case 14:
xprintf("format error");
break;
case 24:
xprintf("spurious interrupt");
break;
default:
if ( ((vector >= 6) && (vector <= 7)) ||
((vector >= 16) && (vector <= 23)))
{
xprintf("reserved");
}
else if ((vector >= 25) && (vector <= 31))
{
xprintf("level %d autovectored interrupt", fault_status - 24);
}
else if ((vector >= 32) && (vector <= 47))
{
xprintf("trap #%d", vector - 32);
}
else
{
xprintf("unknown vector\r\n");
}
}
xprintf(")\r\n");
xprintf("sr=%4x\r\n", sr);
__asm__ __volatile__(
" move.w 0x2700,d0 \r\n" // disable interrupts
" move.w d0,sr \r\n"
" halt \r\n" // stop processor
: /* no output */
: /* no input */
: "memory");
}
void __attribute__((interrupt)) handler(void)
{
/*
* Prepare exception stack contents so it can be handled by a C routine.
*
* For standard routines, we'd have to save registers here.
* Since we do not intend to return anyway, we just ignore that requirement.
*/
__asm__ __volatile__("move.l (sp),-(sp)\n\t"\
"move.l 8(sp),-(sp)\n\t"\
"bsr _fault_handler\n\t"\
"halt\n\t"\
: : : "memory");
}
void setup_vectors(void)
{
int i;
xprintf("\r\ninstall early exception vector table:");
for (i = 8; i < 256; i++)
{
SDRAM_VECTOR_TABLE[i] = &handler;
}
/*
* make sure VBR points to our table
*/
__asm__ __volatile__("clr.l d0\n\t"\
"movec.l d0,VBR\n\t"\
"nop\n\t"\
"move.l d0,_rt_vbr"
: /* outputs */
: /* inputs */
: "d0", "memory", "cc" /* clobbered registers */
);
xprintf("finished.\r\n");
}

189
BaS_gcc/sys/init_fpga.c Normal file
View File

@@ -0,0 +1,189 @@
/*
* init_fpga.c
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2011 - 2012 V. Riviere
* Copyright 2012 M. Froeschle
*
*/
#include "MCF5475.h"
#include "sysinit.h"
#include "bas_printf.h"
#include "wait.h"
// #define FPGA_DEBUG
#if defined(FPGA_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
#define FPGA_STATUS (1 << 0)
#define FPGA_CLOCK (1 << 1)
#define FPGA_CONFIG (1 << 2)
#define FPGA_DATA0 (1 << 3)
#define FPGA_CONF_DONE (1 << 5)
extern uint8_t _FPGA_CONFIG[];
#define FPGA_FLASH_DATA &_FPGA_CONFIG[0]
extern uint8_t _FPGA_CONFIG_SIZE[];
#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_CONFIG_SIZE[0])
/*
* flag located in processor SRAM1 that indicates that the FPGA configuration has
* been loaded through the onboard JTAG interface.
* init_fpga() will honour this and not overwrite config.
*/
extern bool _FPGA_JTAG_LOADED;
extern int32_t _FPGA_JTAG_VALID;
#define VALID_JTAG 0xaffeaffe
void config_gpio_for_fpga_config(void)
{
#if defined(MACHINE_FIREBEE)
/*
* Configure GPIO FEC1L port directions (needed to load FPGA configuration)
*/
MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */
0 | /* bit 6 = input */
0 | /* bit 5 = input */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 | /* bit 2 = FPGA_CONFIG => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 | /* bit 1 = PRG_CLK (FPGA) => output */
0; /* bit 0 => input */
#endif /* MACHINE_FIREBEE */
}
void config_gpio_for_jtag_config(void)
{
/*
* configure FEC1L port directions to enable external JTAG configuration download to FPGA
*/
MCF_GPIO_PDDR_FEC1L = 0 |
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */
/*
* unfortunately, the GPIO module cannot trigger interrupts. That means CONF_DONE needs to be polled to detect
* external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
*/
}
/*
* load FPGA
*/
bool init_fpga(void)
{
uint8_t *fpga_data;
volatile int32_t time, start, end;
int i;
dbg("FPGA load config\r\n(_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
if (_FPGA_JTAG_LOADED == true && _FPGA_JTAG_VALID == VALID_JTAG)
{
dbg("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
/* reset the flag so that next boot will load config again from flash */
_FPGA_JTAG_LOADED = 0;
_FPGA_JTAG_VALID = 0;
return true;
}
start = MCF_SLT0_SCNT;
config_gpio_for_fpga_config();
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */
/* pulling FPGA_CONFIG to low resets the FPGA */
MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */
wait(10); /* give it some time to do its reset stuff */
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS))
; /* wait until status becomes high */
/*
* excerpt from an Altera configuration manual:
*
* The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The
* configuration cycle consists of 3 stages<65>reset, configuration, and initialization.
* While nCONFIG is low, the device is in reset. When the device comes out of reset,
* nCONFIG must be at a logic high level in order for the device to release the open-drain
* nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
* is ready to receive configuration data. Before and during configuration, all user I/O pins
* are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors
* on the I/O pins which are on, before and during configuration.
*
* To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay
* configuration by holding the nCONFIG low. The device receives configuration data on its
* DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After
* the FPGA has received all configuration data successfully, it releases the CONF_DONE pin,
* which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates
* configuration is complete and initialization of the device can begin.
*/
const uint8_t *fpga_flash_data_end = FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE;
fpga_data = (uint8_t *) FPGA_FLASH_DATA;
do
{
uint8_t value = *fpga_data++;
for (i = 0; i < 8; i++, value >>= 1)
{
if (value & 1)
{
/* bit set -> toggle DATA0 to high */
MCF_GPIO_PODR_FEC1L |= FPGA_DATA0;
}
else
{
/* bit is cleared -> toggle DATA0 to low */
MCF_GPIO_PODR_FEC1L &= ~FPGA_DATA0;
}
/* toggle DCLK -> FPGA reads the bit */
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
}
} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < fpga_flash_data_end));
if (fpga_data < fpga_flash_data_end)
{
#ifdef _NOT_USED_
while (fpga_data++ < fpga_flash_data_end)
{
/* toggle a little more since it's fun ;) */
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
}
#endif /* _NOT_USED_ */
end = MCF_SLT0_SCNT;
time = (start - end) / (SYSCLK / 1000) / 1000;
xprintf("finished (took %f seconds).\r\n", time / 1000.0);
config_gpio_for_jtag_config();
return true;
}
xprintf("FAILED!\r\n");
config_gpio_for_jtag_config();
return false;
}

477
BaS_gcc/sys/interrupts.c Normal file
View File

@@ -0,0 +1,477 @@
/*
* Interrupts
*
* Handle interrupts, the levels.
*
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 26.02.2013
* Author: Markus Fröschle
*/
#include <bas_types.h>
#include "MCF5475.h"
#include "bas_utils.h"
#include "bas_printf.h"
#include "bas_string.h"
#include "exceptions.h"
#include "interrupts.h"
#include "bas_printf.h"
#include "startcf.h"
#include "cache.h"
#include "util.h"
#include "dma.h"
#include "pci.h"
//#define IRQ_DEBUG
#if defined(IRQ_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
#define err(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
#ifndef MAX_ISR_ENTRY
#define MAX_ISR_ENTRY (20)
#endif
struct isrentry
{
int vector;
bool (*handler)(void *, void *);
void *hdev;
void *harg;
};
static struct isrentry isrtab[MAX_ISR_ENTRY]; /* list of interrupt service routines */
/*
* clear the table of interrupt service handlers
*/
void isr_init(void)
{
memset(isrtab, 0, sizeof(isrtab));
}
bool isr_set_prio_and_level(int int_source, int priority, int level)
{
if (int_source > 8 && int_source <= 62)
{
/*
* preset interrupt control registers with level and priority
*/
dbg("set MCF_INTC_ICR(%d) to priority %d, level %d\r\n",
int_source, priority, level);
MCF_INTC_ICR(int_source) = MCF_INTC_ICR_IP(priority) |
MCF_INTC_ICR_IL(level);
}
else if (int_source >= 1 && int_source <= 8)
{
dbg("interrrupt control register for vector %d is read only!\r\n");
}
else
{
err("invalid vector - interrupt control register not set.\r\n");
return false;
}
return true;
}
/*
* enable internal int source in interrupt controller
*/
bool isr_enable_int_source(int int_source)
{
dbg("anding int_source %d, MCF_INTC_IMR%c = 0x%08x, now 0x%08x\r\n",
int_source,
int_source < 32 && int_source > 0 ? 'L' :
int_source >= 32 && int_source <= 62 ? 'H' : 'U',
int_source < 32 && int_source > 0 ? ~(1 << int_source) :
int_source >= 32 && int_source <= 62 ? ~(1 << (int_source - 32)) : 0,
MCF_INTC_IMRH);
if (int_source < 32 && int_source > 0)
{
MCF_INTC_IMRL &= ~(1 << int_source);
}
else if (int_source >= 32 && int_source <= 62)
{
MCF_INTC_IMRH &= ~(1 << (int_source - 32));
}
else
{
dbg("vector %d does not correspond to an internal interrupt source\r\n");
return false;
}
return true;
}
/*
* This function places an interrupt handler in the ISR table,
* thereby registering it so that the low-level handler may call it.
*
* The two parameters are intended for the first arg to be a
* pointer to the device itself, and the second a pointer to a data
* structure used by the device driver for that particular device.
*/
bool isr_register_handler(int vector, int level, int priority, bool (*handler)(void *, void *), void *hdev, void *harg)
{
int index;
int int_source;
if ((vector == 0) || (handler == NULL))
{
dbg("illegal vector or handler!\r\n");
return false;
}
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].vector == vector)
{
/* one cross each, only! */
dbg("already set handler with this vector (%d, %d)\r\n", vector);
return false;
}
if (isrtab[index].vector == 0)
{
isrtab[index].vector = vector;
isrtab[index].handler = handler;
isrtab[index].hdev = hdev;
isrtab[index].harg = harg;
int_source = vector - 64;
if (!isr_enable_int_source(int_source))
{
dbg("failed to enable internal interrupt souce %d in IMRL/IMRH\r\n", int_source);
return false;
}
if (!isr_set_prio_and_level(int_source, priority, level))
{
dbg("failed to set priority and level for interrupt source %d\r\n", int_source);
return false;
}
return true;
}
}
dbg("no available slots to register handler for vector %d\n\r", vector);
return false; /* no available slots */
}
void isr_remove_handler(bool (*handler)(void *, void *))
{
/*
* This routine removes from the ISR table all
* entries that matches 'handler'.
*/
int index;
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].handler == handler)
{
memset(&isrtab[index], 0, sizeof(struct isrentry));
return;
}
}
dbg("no such handler registered (handler=%p\r\n", handler);
}
/*
* This routine searches the ISR table for an entry that matches
* 'vector'. If one is found, then 'handler' is executed.
*
* This routine returns either true or false where
* true = interrupt has been handled, return to caller
* false= interrupt has been handled or hasn't, but needs to be forwarded to TOS
*/
bool isr_execute_handler(int vector)
{
int index;
dbg("vector = %d\r\n", vector);
/*
* locate an interrupt service routine handler.
*/
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].vector == vector)
{
isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg);
return true;
}
}
err("no isr handler for vector %d found. Spurious?\r\n", vector);
return true;
}
/*
* PIC interrupt handler for Firebee
*
* Handles PIC requests that come in from PSC3 serial interface. Currently, that
* is RTC/NVRAM requests only
*/
bool pic_interrupt_handler(void *arg1, void *arg2)
{
uint8_t rcv_byte;
rcv_byte = MCF_PSC3_PSCRB_8BIT;
if (rcv_byte == 2) /* PIC requests RTC data */
{
uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
uint8_t *rtc_data = (uint8_t *) 0xffff8963;
int index = 0;
err("PIC interrupt: requesting RTC data\r\n");
MCF_PSC3_PSCTB_8BIT = 0x82; // header byte to PIC
do
{
*rtc_reg = 0;
MCF_PSC3_PSCTB_8BIT = *rtc_data;
} while (index++ < 64);
}
return true;
}
bool xlbpci_interrupt_handler(void *arg1, void *arg2)
{
uint32_t reason;
dbg("XLB PCI interrupt\r\n");
reason = MCF_PCI_PCIISR;
if (reason & MCF_PCI_PCIISR_RE)
{
dbg("Retry error. Retry terminated or max retries reached. Cleared\r\n");
MCF_PCI_PCIISR |= MCF_PCI_PCIISR_RE;
}
if (reason & MCF_PCI_PCIISR_IA)
{
dbg("Initiator abort. No target answered in time. Cleared.\r\n");
MCF_PCI_PCIISR |= MCF_PCI_PCIISR_IA;
}
if (reason & MCF_PCI_PCIISR_TA)
{
dbg("Target abort. Cleared.\r\n");
MCF_PCI_PCIISR |= MCF_PCI_PCIISR_TA;
}
return true;
}
bool pciarb_interrupt_handler(void *arg1, void *arg2)
{
dbg("PCI ARB interrupt\r\n");
return true;
}
#if defined(MACHINE_FIREBEE)
/*
* This gets called from irq5 in exceptions.S
*
* IRQ5 are the "FBEE" (PIC, ETH PHY, PCI, DVI monitor sense and DSP) interrupts multiplexed by the FPGA interrupt handler
*/
bool irq5_handler(void *arg1, void *arg2)
{
uint32_t pending_interrupts = FBEE_INTR_PENDING;
dbg("IRQ5!\r\n");
if (pending_interrupts & FBEE_INTR_PIC)
{
dbg("PIC interrupt\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_PIC;
}
if (pending_interrupts & FBEE_INTR_ETHERNET)
{
dbg("ethernet 0 PHY interrupt\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_ETHERNET;
}
if (pending_interrupts & FBEE_INTR_DVI)
{
dbg("DVI monitor sense interrupt\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_DVI;
}
if (pending_interrupts & FBEE_INTR_PCI_INTA ||
pending_interrupts & FBEE_INTR_PCI_INTB ||
pending_interrupts & FBEE_INTR_PCI_INTC ||
pending_interrupts & FBEE_INTR_PCI_INTD)
{
dbg("PCI interrupt IRQ5\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_PCI_INTA |
FBEE_INTR_PCI_INTB |
FBEE_INTR_PCI_INTC |
FBEE_INTR_PCI_INTD;
}
if (pending_interrupts & FBEE_INTR_DSP)
{
dbg("DSP interrupt\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_DSP;
}
MCF_EPORT_EPFR |= (1 << 5); /* clear interrupt from edge port */
return true;
}
/*
* blink the Firebee's LED to show we are still alive
*/
void blink_led(void)
{
static uint16_t blinker = 0;
if ((blinker++ & 0x80) > 0)
{
MCF_GPIO_PODR_FEC1L |= (1 << 4); /* LED off */
}
else
{
MCF_GPIO_PODR_FEC1L &= ~(1 << 4); /* LED on */
}
}
/*
* Atari MFP interrupt registers.
*
* TODO: should go into a header file
*/
#define FALCON_MFP_IERA *((volatile uint8_t *) 0xfffffa07)
#define FALCON_MFP_IERB *((volatile uint8_t *) 0xfffffa09)
#define FALCON_MFP_IPRA *((volatile uint8_t *) 0xfffffa0b)
#define FALCON_MFP_IPRB *((volatile uint8_t *) 0xfffffa0d)
#define FALCON_MFP_IMRA *((volatile uint8_t *) 0xfffffa13)
#define FALCON_MFP_IMRB *((volatile uint8_t *) 0xfffffa15)
bool irq6_acsi_dma_interrupt(void)
{
dbg("ACSI DMA interrupt\r\n");
/*
* TODO: implement handler
*/
return false;
}
bool irq6_handler(uint32_t sf1, uint32_t sf2)
{
//err("IRQ6!\r\n");
if (FALCON_MFP_IPRA || FALCON_MFP_IPRB)
{
blink_led();
}
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
return false; /* always forward IRQ6 to TOS */
}
#else /* MACHINE_FIREBEE */
bool irq5_handler(void *arg1, void *arg2)
{
MCF_EPORT_EPFR |= (1 << 5); /* clear int5 from edge port */
return true;
}
bool irq6_handler(void *arg1, void *arg2)
{
err("IRQ6!\r\n");
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
return false; /* always forward IRQ6 to TOS */
}
/*
* This gets called from irq7 in exceptions.S
* Once we arrive here, the SR has been set to disable interrupts and the gcc scratch registers have been saved
*/
bool irq7_handler(void)
{
int32_t handle;
int32_t value = 0;
int32_t newvalue;
MCF_EPORT_EPFR |= (1 << 7);
dbg("IRQ7!\r\n");
if ((handle = pci_get_interrupt_cause()) > 0)
{
newvalue = pci_call_interrupt_chain(handle, value);
if (newvalue == value)
{
dbg("interrupt not handled!\r\n");
}
}
MCF_EPORT_EPFR |= (1 << 7); /* clear int7 from edge port */
return true;
}
#endif /* MACHINE_M548X */
#if defined(MACHINE_FIREBEE)
/*
* this is the higlevel interrupt service routine for gpt0 timer interrupts.
*
* It is called from handler_gpt0 in exceptions.S
*
* The gpt0 timer is not used as a timer, but as interrupt trigger by the FPGA which fires
* everytime the video base address high byte (0xffff8201) gets written by user code (i.e.
* everytime the video base address is set).
* The interrupt service routine checks if that page was already set as a video page (in that
* case it does nothing), if not (if we have a newly set page), it sets up an MMU mapping for
* that page (effectively rerouting any further access to Falcon video RAM to Firebee FPGA
* video RAM starting at 0x60000000) and copies SDRAM contents of that page to the video
* RAM page.
*/
bool gpt0_interrupt_handler(void *arg0, void *arg1)
{
dbg("handler called\n\r");
MCF_GPT0_GMS &= ~1; /* rearm trigger */
NOP();
MCF_GPT0_GMS |= 1;
return true;
}
#endif /* MACHINE_FIREBEE */

972
BaS_gcc/sys/mmu.c Normal file
View File

@@ -0,0 +1,972 @@
#include "mmu.h"
#include "acia.h"
#include "exceptions.h"
#if defined(MACHINE_FIREBEE)
#include "firebee.h"
#elif defined(MACHINE_M5484LITE)
#include "m5484l.h"
#elif defined(MACHINE_M54455)
#include "m54455.h"
#else
#error "unknown machine!"
#endif
/*
* mmu.c
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* derived from original assembler sources:
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2013 M. Froeschle
*/
#define ACR_BA(x) ((x) & 0xffff0000)
#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
#define ACR_E(x) (((x) & 1) << 15)
#define ACR_S(x) (((x) & 3) << 13)
#define ACR_S_USERMODE 0
#define ACR_S_SUPERVISOR_MODE 1
#define ACR_S_ALL 2
#define ACR_AMM(x) (((x) & 1) << 10)
#define ACR_CM(x) (((x) & 3) << 5)
#define ACR_CM_CACHEABLE_WT 0x0
#define ACR_CM_CACHEABLE_CB 0x1
#define ACR_CM_CACHE_INH_PRECISE 0x2
#define ACR_CM_CACHE_INH_IMPRECISE 0x3
#define ACR_SP(x) (((x) & 1) << 3)
#define ACR_W(x) (((x) & 1) << 2)
#include <stdint.h>
#include "bas_printf.h"
#include "bas_types.h"
#include "MCF5475.h"
#include "pci.h"
#include "cache.h"
#include "util.h"
#if defined(MACHINE_FIREBEE)
#include "firebee.h"
#elif defined(MACHINE_M5484LITE)
#include "m5484l.h"
#elif defined(MACHINE_M54455)
#include "m54455.h"
#else
#error "unknown machine!"x
#endif /* MACHINE_FIREBEE */
//#define DBG_MMU
#ifdef DBG_MMU
#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
#else
#define dbg(format, arg...) do {;} while (0)
#endif /* DBG_MMU */
#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0);
/*
* set ASID register
* saves new value to rt_asid and returns former value
*/
inline uint32_t set_asid(uint32_t value)
{
extern long rt_asid;
uint32_t ret = rt_asid;
__asm__ __volatile__(
"movec %[value],ASID\n\t"
: /* no output */
: [value] "r" (value)
:
);
rt_asid = value;
return ret;
}
/*
* set ACRx register
* saves new value to rt_acrx and returns former value
*/
inline uint32_t set_acr0(uint32_t value)
{
extern uint32_t rt_acr0;
uint32_t ret = rt_acr0;
__asm__ __volatile__(
"movec %[value],ACR0\n\t"
: /* not output */
: [value] "r" (value)
:
);
rt_acr0 = value;
return ret;
}
/*
* set ACRx register
* saves new value to rt_acrx and returns former value
*/
inline uint32_t set_acr1(uint32_t value)
{
extern uint32_t rt_acr1;
uint32_t ret = rt_acr1;
__asm__ __volatile__(
"movec %[value],ACR1\n\t"
: /* not output */
: [value] "r" (value)
:
);
rt_acr1 = value;
return ret;
}
/*
* set ACRx register
* saves new value to rt_acrx and returns former value
*/
inline uint32_t set_acr2(uint32_t value)
{
extern uint32_t rt_acr2;
uint32_t ret = rt_acr2;
__asm__ __volatile__(
"movec %[value],ACR2\n\t"
: /* not output */
: [value] "r" (value)
:
);
rt_acr2 = value;
return ret;
}
/*
* set ACRx register
* saves new value to rt_acrx and returns former value
*/
inline uint32_t set_acr3(uint32_t value)
{
extern uint32_t rt_acr3;
uint32_t ret = rt_acr3;
__asm__ __volatile__(
"movec %[value],ACR3\n\t"
: /* not output */
: [value] "r" (value)
:
);
rt_acr3 = value;
return ret;
}
inline uint32_t set_mmubar(uint32_t value)
{
extern uint32_t rt_mmubar;
uint32_t ret = rt_mmubar;
__asm__ __volatile__(
"movec %[value],MMUBAR\n\t"
: /* no output */
: [value] "r" (value)
: /* no clobber */
);
rt_mmubar = value;
NOP();
return ret;
}
/*
* translation table for virtual address ranges. Holds the physical_offset (which must be added to a virtual
* address to get its physical counterpart) for memory ranges.
*/
struct virt_to_phys
{
uint32_t start_address;
uint32_t length;
uint32_t physical_offset;
};
#if defined(MACHINE_FIREBEE)
static struct virt_to_phys translation[] =
{
/* virtual , length , offset */
{ 0x00000000, 0x00e00000, 0x60000000 }, /* map first 14 MByte to first 14 Mb of video ram */
{ 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */
{ 0x00f00000, 0x00100000, 0xff000000 }, /* map Falcon I/O area to FPGA */
{ 0x01000000, 0x1f000000, 0x00000000 }, /* map rest of ram virt = phys */
};
#elif defined(MACHINE_M5484LITE)
static struct virt_to_phys translation[] =
{
/* virtual , length , offset */
{ 0x00000000, 0x00e00000, 0x00000000 }, /* map first 14 MByte to first 14 Mb of SD ram */
{ 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */
{ 0x01000000, 0x04000000, 0x00000000 }, /* map rest of ram virt = phys */
};
#elif defined(MACHINE_M54455)
/* FIXME: this is not determined yet! */
static struct virt_to_phys translation[] =
{
/* virtual , length , offset */
{ 0x00000000, 0x00e00000, 0x60000000 }, /* map first 14 MByte to first 14 Mb of video ram */
{ 0x00e00000, 0x00100000, 0x00000000 }, /* map TOS to SDRAM */
{ 0x00f00000, 0x00100000, 0xff000000 }, /* map Falcon I/O area to FPGA */
{ 0x01000000, 0x1f000000, 0x00000000 }, /* map rest of ram virt = phys */
};
#else
#error unknown machine!
#endif
static int num_translations = sizeof(translation) / sizeof(struct virt_to_phys);
static inline int32_t lookup_phys(int32_t virt)
{
int i;
for (i = 0; i < num_translations; i++)
{
if (virt >= translation[i].start_address && virt < translation[i].start_address + translation[i].length)
{
return virt + translation[i].physical_offset;
}
}
err("virtual address 0x%lx not found in translation table!\r\n", virt);
return -1;
}
struct mmu_page_descriptor
{
uint8_t cache_mode : 2;
uint8_t supervisor_protect : 1;
uint8_t read : 1;
uint8_t write : 1;
uint8_t execute : 1;
uint8_t global : 1;
uint8_t locked : 1;
};
/*
* page descriptors. Size depending on DEFAULT_PAGE_SIZE, either 1M (resulting in 512
* bytes size) or 8k pages (64k descriptor array size)
*/
static struct mmu_page_descriptor pages[SDRAM_SIZE / DEFAULT_PAGE_SIZE];
int mmu_map_instruction_page(int32_t virt, uint8_t asid)
{
const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1); /* pagesize */
int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE; /* index into page_descriptor array */
struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
int ipl;
int32_t phys = lookup_phys(virt); /* virtual to physical translation of page */
if (phys == -1)
{
/* no valid mapping found, caller will issue a bus error in return */
return 0;
}
#ifdef DBG_MMU
register int sp asm("sp");
dbg("page_descriptor: 0x%02x, ssp = 0x%08x\r\n", * (uint8_t *) page, sp);
#endif /* DBG_MMU */
/*
* add page to TLB
*/
ipl = set_ipl(7); /* do not disturb */
MCF_MMU_MMUAR = (virt & size_mask);
MCF_MMU_MMUTR = (virt & size_mask) | /* virtual address */
MCF_MMU_MMUTR_ID(asid) | /* address space id (ASID) */
(page->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */
MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) | /* page size */
MCF_MMU_MMUDR_CM(page->cache_mode) | /* cache mode */
(page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) | /* supervisor protect */
(page->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
(page->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
(page->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */
(page->locked ? MCF_MMU_MMUDR_LK : 0);
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
MCF_MMU_MMUOR_ACC | /* access TLB */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
set_ipl(ipl);
dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask);
dbg("ITLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
return 1;
}
int mmu_map_data_page(int32_t virt, uint8_t asid)
{
uint16_t ipl;
const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1); /* pagesize */
int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE; /* index into page_descriptor array */
struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
int32_t phys = lookup_phys(virt); /* virtual to physical translation of page */
if (phys == -1)
{
/* no valid mapping found, caller will issue a bus error in return */
return 0;
}
#ifdef DBG_MMU
register int sp asm("sp");
dbg("page_descriptor: 0x%02x, ssp = 0x%08x\r\n", * (uint8_t *) page, sp);
#endif /* DBG_MMU */
/*
* add page to TLB
*/
ipl = set_ipl(7); /* do not disturb */
MCF_MMU_MMUTR = (virt & size_mask) | /* virtual address */
MCF_MMU_MMUTR_ID(asid) | /* address space id (ASID) */
(page->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
MCF_MMU_MMUDR = (phys & size_mask) | /* physical address */
MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) | /* page size */
MCF_MMU_MMUDR_CM(page->cache_mode) | /* cache mode */
(page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) | /* supervisor protect */
(page->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
(page->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
(page->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */
(page->locked ? MCF_MMU_MMUDR_LK : 0);
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
set_ipl(ipl);
dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask);
dbg("DTLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
return 1;
}
/*
* map a page of memory using virt and phys as addresses with the Coldfire MMU.
*
* Theory of operation: the Coldfire MMU in the Firebee has 64 TLB entries, 32 for data (DTLB), 32 for
* instructions (ITLB). Mappings can either be done locked (normal MMU TLB misses will not consider them
* for replacement) or unlocked (mappings will reallocate using a LRU scheme when the MMU runs out of
* TLB entries). For proper operation, the MMU needs at least two ITLBs and/or four free/allocatable DTLBs
* per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
* LRU algorithm) should be used sparsingly.
*/
int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags)
{
int size_mask;
int ipl;
switch (sz)
{
case MMU_PAGE_SIZE_1M:
size_mask = ~ (SIZE_1M - 1);
break;
case MMU_PAGE_SIZE_8K:
size_mask = ~ (SIZE_8K - 1);
break;
case MMU_PAGE_SIZE_4K:
size_mask = ~ (SIZE_4K - 1);
break;
case MMU_PAGE_SIZE_1K:
size_mask = ~ (SIZE_1K - 1);
break;
default:
dbg("illegal map size %d\r\n", sz);
return 0;
}
/*
* add page to TLB
*/
ipl = set_ipl(7); /* do not disturb */
MCF_MMU_MMUTR = ((int) virt & size_mask) | /* virtual address */
MCF_MMU_MMUTR_ID(page_id) | /* address space id (ASID) */
(flags->global ? MCF_MMU_MMUTR_SG : 0) | /* shared global */
MCF_MMU_MMUTR_V; /* valid */
MCF_MMU_MMUDR = ((int) phys & size_mask) | /* physical address */
MCF_MMU_MMUDR_SZ(sz) | /* page size */
MCF_MMU_MMUDR_CM(flags->cache_mode) |
(flags->read ? MCF_MMU_MMUDR_R : 0) | /* read access enable */
(flags->write ? MCF_MMU_MMUDR_W : 0) | /* write access enable */
(flags->execute ? MCF_MMU_MMUDR_X : 0) | /* execute access enable */
(flags->locked ? MCF_MMU_MMUDR_LK : 0);
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC | /* access TLB, data */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
NOP();
MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | /* instruction */
MCF_MMU_MMUOR_ACC | /* access TLB */
MCF_MMU_MMUOR_UAA; /* update allocation address field */
set_ipl(ipl);
dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys);
return 1;
}
void mmu_init(void)
{
extern uint8_t _MMUBAR[];
uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
struct mmu_page_descriptor flags;
int i;
/*
* clear all MMU TLB entries first
*/
MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA; /* clears _all_ TLBs (including locked ones) */
NOP();
/*
* prelaminary initialization of page descriptor 0 (root) table
*/
for (i = 0; i < sizeof(pages) / sizeof(struct mmu_page_descriptor); i++)
{
uint32_t addr = i * DEFAULT_PAGE_SIZE;
#if defined(MACHINE_FIREBEE)
if (addr >= 0x00f00000UL && addr < 0x00ffffffUL) /* Falcon I/O area on the Firebee */
{
pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
pages[i].execute = 0;
pages[i].read = 1;
pages[i].write = 1;
pages[i].execute = 0;
pages[i].global = 1;
pages[i].supervisor_protect = 1;
}
else if (addr >= 0x0UL && addr < 0x00e00000UL) /* ST-RAM, potential video memory */
{
pages[i].cache_mode = CACHE_WRITETHROUGH;
pages[i].execute = 1;
pages[i].supervisor_protect = 0;
pages[i].read = 1;
pages[i].write = 1;
pages[i].execute = 1;
pages[i].global = 1;
}
else if (addr >= 0x00e00000UL && addr < 0x00f00000UL) /* EmuTOS */
{
pages[i].cache_mode = CACHE_COPYBACK;
pages[i].execute = 1;
pages[i].supervisor_protect = 1;
pages[i].read = 1;
pages[i].write = 0;
pages[i].execute = 1;
pages[i].global = 1;
}
else
{
pages[i].cache_mode = CACHE_COPYBACK;
pages[i].execute = 1;
pages[i].read = 1;
pages[i].write = 1;
pages[i].supervisor_protect = 0;
pages[i].global = 1;
}
pages[i].locked = 0; /* not locked */
pages[0].supervisor_protect = 0; /* protect system vectors */
#elif defined(MACHINE_M5484LITE)
if (addr >= 0x60000000UL && addr < 0x70000000UL) /* Compact Flash on the m5484lite */
{
pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
pages[i].supervisor_protect = 0;
pages[i].read = 1;
pages[i].write = 1;
pages[i].execute = 1;
pages[i].global = 1;
}
else if (addr >= 0x0UL && addr < 0x00e00000UL) /* ST-RAM, potential video memory */
{
pages[i].cache_mode = CACHE_WRITETHROUGH;
pages[i].supervisor_protect = 0;
pages[i].read = 1;
pages[i].write = 1;
pages[i].execute = 1;
pages[i].global = 1;
}
else if (addr >= 0x00e00000UL && addr < 0x00f00000UL) /* EmuTOS */
{
pages[i].cache_mode = CACHE_COPYBACK;
pages[i].execute = 1;
pages[i].supervisor_protect = 1;
pages[i].read = 1;
pages[i].write = 0;
pages[i].execute = 1;
pages[i].global = 1;
}
else
{
pages[i].cache_mode = CACHE_COPYBACK; /* rest of RAM */
pages[i].execute = 1;
pages[i].read = 1;
pages[i].write = 1;
pages[i].supervisor_protect = 0;
pages[i].global = 1;
}
pages[i].locked = 0; /* not locked */
pages[0].supervisor_protect = 0; /* protect system vectors */
#elif defined(MACHINE_M54455)
if (addr >= 0x60000000UL && addr < 0x70000000UL) /* Compact Flash on the m5484lite */
{
pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
pages[i].execute = 0;
pages[i].read = 1;
pages[i].write = 1;
pages[i].execute = 0;
pages[i].global = 1;
pages[i].supervisor_protect = 1;
}
else if (addr >= 0x0UL && addr < 0x00e00000UL) /* ST-RAM, potential video memory */
{
pages[i].cache_mode = CACHE_WRITETHROUGH;
pages[i].execute = 1;
pages[i].supervisor_protect = 0;
pages[i].read = 1;
pages[i].write = 1;
pages[i].execute = 1;
pages[i].global = 1;
}
else if (addr >= 0x00e00000UL && addr < 0x00f00000UL) /* EmuTOS */
{
pages[i].cache_mode = CACHE_COPYBACK;
pages[i].execute = 1;
pages[i].supervisor_protect = 1;
pages[i].read = 1;
pages[i].write = 0;
pages[i].execute = 1;
pages[i].global = 1;
}
else
{
pages[i].cache_mode = CACHE_COPYBACK; /* rest of RAM */
pages[i].execute = 1;
pages[i].read = 1;
pages[i].write = 1;
pages[i].supervisor_protect = 0;
pages[i].global = 1;
}
pages[i].locked = 0; /* not locked */
pages[0].supervisor_protect = 0; /* protect system vectors */
#else
#error Unknown machine!
#endif /* MACHINE_FIREBEE */
}
set_asid(0); /* do not use address extension (ASID provides virtual 48 bit addresses */
/* set data access attributes in ACR0 and ACR1 */
/* map PCI address space */
set_acr0(ACR_W(0) | /* read and write accesses permitted */
ACR_SP(1) | /* supervisor and user mode access permitted */
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */
ACR_AMM(0) | /* control region > 16 MB */
ACR_S(ACR_S_SUPERVISOR_MODE) | /* match addresses in supervisor mode only */
ACR_E(1) | /* enable ACR */
#if defined(MACHINE_FIREBEE)
ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */
ACR_BA(0x80000000)); /* (equals area from 3 to 4 GB */
#elif defined(MACHINE_M5484LITE)
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
ACR_BA(0x80000000));
#elif defined(MACHINE_M54455)
ACR_ADMSK(0x7f) |
ACR_BA(0x80000000)); /* FIXME: not determined yet */
#else
#error unknown machine!
#endif /* MACHINE_FIREBEE */
// set_acr1(0x601fc000);
/* data access attributes for BaS in flash */
set_acr1(ACR_W(0) |
ACR_SP(0) |
ACR_CM(0) |
#if defined(MACHINE_FIREBEE)
ACR_CM(ACR_CM_CACHEABLE_WT) |
#elif defined(MACHINE_M5484LITE)
ACR_CM(ACR_CM_CACHEABLE_WT) |
#elif defined(MACHINE_M54455)
ACR_CM(ACR_CM_CACHEABLE_WT) |
#else
#error unknown machine!
#endif /* MACHINE_FIREBEE */
ACR_AMM(0) |
ACR_S(ACR_S_ALL) |
ACR_E(1) |
ACR_ADMSK(0x1f) |
ACR_BA(0xe0000000));
/* set instruction access attributes in ACR2 and ACR3 */
//set_acr2(0xe007c400);
/* instruction access attribute for BaS in flash */
set_acr2(ACR_W(0) |
ACR_SP(0) |
ACR_CM(0) |
ACR_CM(ACR_CM_CACHEABLE_WT) |
ACR_AMM(1) |
ACR_S(ACR_S_ALL) |
ACR_E(1) |
ACR_ADMSK(0x7) |
ACR_BA(0xe0000000));
/* disable ACR1 - 3, essentially disabling all of the above */
set_acr3(0x0);
set_mmubar(MMUBAR + 1); /* set and enable MMUBAR */
/* create locked TLB entries */
flags.cache_mode = CACHE_COPYBACK;
flags.supervisor_protect = 0;
flags.read = 1;
flags.write = 1;
flags.execute = 1;
flags.locked = true;
/* 0x00000000 - 0x00100000 (first MB of physical memory) locked virt = phys */
mmu_map_page(0x0, 0x0, MMU_PAGE_SIZE_1M, 0, &flags);
/*
* Make the TOS (in SDRAM) read-only
* This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
*/
flags.cache_mode = CACHE_COPYBACK;
flags.supervisor_protect = 0;
flags.read = 1;
flags.write = 0;
flags.execute = 1;
flags.locked = 1;
mmu_map_page(0xe00000, 0xe00000, MMU_PAGE_SIZE_1M, 0, &flags);
#if defined(MACHINE_FIREBEE)
/*
* Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O
* area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee
*/
flags.cache_mode = CACHE_NOCACHE_PRECISE;
flags.supervisor_protect = 1;
flags.read = 1;
flags.write = 1;
flags.execute = 0;
flags.locked = 1;
mmu_map_page(0x00f00000, 0xfff00000, MMU_PAGE_SIZE_1M, 0, &flags);
#elif defined(MACHINE_M5484LITE)
/*
* Map m5484LITE CPLD access
*/
flags.cache_mode = CACHE_NOCACHE_PRECISE;
flags.supervisor_protect = 1;
flags.read = 1;
flags.write = 1;
flags.execute = 0;
flags.locked = 1;
mmu_map_page(0x6a000000, 0x6a000000, MMU_PAGE_SIZE_1M, 0, &flags);
#endif /* MACHINE_FIREBEE */
/*
* Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
* virtual address. This is also used (completely) when BaS is in RAM
*/
flags.cache_mode = CACHE_COPYBACK;
flags.supervisor_protect = 1;
flags.read = 1;
flags.write = 1;
flags.execute = 1;
flags.locked = 1;
mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00200000, SDRAM_START + SDRAM_SIZE - 0x00200000, MMU_PAGE_SIZE_1M, 0, &flags);
/*
* Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same
* virtual address. Used uncached for drivers.
*/
flags.cache_mode = CACHE_NOCACHE_PRECISE;
flags.supervisor_protect = 1;
flags.read = 1;
flags.write = 1;
flags.execute = 0;
flags.locked = 1;
mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00100000, SDRAM_START + SDRAM_SIZE - 0x00100000, MMU_PAGE_SIZE_1M, 0, &flags);
}
uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, uint32_t format_status)
{
uint32_t fault = format_status & 0xc030000;
//dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", fault_address, format_status, pc);
// flush_and_invalidate_caches();
switch (fault)
{
/* if we have a real TLB miss, map the offending page */
case 0x04010000: /* TLB miss on opword of instruction fetch */
case 0x04020000: /* TLB miss on extension word of instruction fetch */
dbg("MMU ITLB MISS accessing 0x%08x\r\n"
"FS = 0x%08x\r\n"
"MMUSR = 0x%08x\r\n"
"PC = 0x%08x\r\n",
fault_address, format_status, mmu_sr, pc);
dbg("fault = 0x%08x\r\n", fault);
if (!mmu_map_instruction_page(pc, 0))
{
dbg("bus error\r\n");
return 1; /* bus error */
}
/* due to prefetch, it makes sense to map the next adjacent page also for ITLBs */
if (pc + DEFAULT_PAGE_SIZE < TARGET_ADDRESS)
{
/*
* only do this if the next page is still valid RAM
*/
if (!mmu_map_instruction_page(pc + DEFAULT_PAGE_SIZE, 0))
{
dbg("bus error\r\n");
return 1; /* bus error */
}
}
break;
case 0x08020000: /* TLB miss on data write */
case 0x0c020000: /* TLB miss on data read or read-modify-write */
dbg("MMU DTLB MISS accessing 0x%08x\r\n"
"FS = 0x%08x\r\n"
"MMUSR = 0x%08x\r\n"
"PC = 0x%08x\r\n",
fault_address, format_status, mmu_sr, pc);
dbg("fault = 0x%08x\r\n", fault);
if (!mmu_map_data_page(fault_address, 0))
{
dbg("bus error\r\n");
return 1; /* bus error */
}
break;
/* else issue a bus error */
default:
dbg("bus error\r\n");
return 1; /* signal bus error to caller */
}
#ifdef DBG_MMU
xprintf("\r\n");
#endif /* DBG_MMU */
return 0; /* signal TLB miss handled to caller */
}
/* TODO: implement */
/*
* API-exposed, externally callable MMU functions
*/
/*
* lock data page(s) with address space id asid from address virt to virt + size.
*
* ASID probably needs an explanation - this is the "address space id" managed by
* the MMU.
* If its value range would be large enough, this could directly map to a PID
* in MiNT. Unfortunately, the Coldfire MMU only allows an 8 bit value for ASID
* (with 0 already occupied for the super user/root process and the Firebee video
* subsystem occupying another one), so we are left with 253 distinct values.
* MMU software needs to implement some kind of mapping and LRU scheme which will
* lead to a throwaway of all mappings for processes not seen for a while (and thus
* to undeterministic response/task switching times when such processes are activated
* again).
*
* FIXME: There is no check for "too many locked pages", currently.
*
* return: 0 if failed (page not in translation table), 1 otherwise
*/
int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
{
const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1); /* pagesize */
int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE; /* index into page_descriptor array */
struct mmu_page_descriptor *page = &pages[page_index]; /* attributes of page to map */
int i = 0;
while (page_index * DEFAULT_PAGE_SIZE < virt + size)
{
if (page->locked)
{
dbg("page at %p is already locked. Nothing to do\r\n", virt);
}
else
{
page->locked = 1;
mmu_map_data_page(virt, 0);
i++;
}
virt += DEFAULT_PAGE_SIZE;
}
dbg("%d pages locked\r\n", i);
return 1; /* success */
}
/*
* the opposite: unlock data page(s) with address space id asid from address virt to virt + size_t
*
* return: 0 if failed (page not found), 1 otherwise
*/
int32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
{
int curr_asid;
const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);
int page_index = (address & size_mask) / DEFAULT_PAGE_SIZE; /* index into page descriptor array */
struct mmu_page_descriptor *page = &pages[page_index];
curr_asid = set_asid(asid); /* set asid to the one to search for */
/* TODO: check for pages[] array bounds */
while (page_index * DEFAULT_PAGE_SIZE < address + size)
{
MCF_MMU_MMUAR = address + page->supervisor_protect;
MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB | /* search TLB */
MCF_MMU_MMUOR_ADR |
MCF_MMU_MMUOR_RW;
if (MCF_MMU_MMUSR & MCF_MMU_MMUSR_HIT) /* found */
{
#ifdef DBG_MMU
uint32_t tlb_aa = MCF_MMU_MMUOR >> 16; /* MMU internal allocation address for TLB */
#endif /* DBG_MMU */
MCF_MMU_MMUDR &= ~MCF_MMU_MMUDR_LK; /* clear lock bit */
MCF_MMU_MMUOR = MCF_MMU_MMUOR_UAA |
MCF_MMU_MMUOR_ACC; /* update TLB */
dbg("DTLB %d unlocked\r\n", tlb_aa);
}
else
{
dbg("%p doesn't seem to be locked??\r\n");
}
page_index++;
}
set_asid(curr_asid);
return 1; /* success */
}
int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)
{
int i;
int li = 0;
int ld = 0;
/* Coldfire V4e allocation addresses run from 0 to 63 */
for (i = 0; i < 31; i++) /* 0-31 = ITLB AA */
{
MCF_MMU_MMUAR = i;
MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB |
MCF_MMU_MMUOR_ITLB |
MCF_MMU_MMUOR_RW; /* search ITLB */
if (MCF_MMU_MMUTR & MCF_MMU_MMUTR_V)
{
/* entry is valid */
if (MCF_MMU_MMUDR & MCF_MMU_MMUDR_LK)
{
li++;
}
}
}
for (i = 32; i < 64; i++) /* 32-63 = DTLB AA */
{
MCF_MMU_MMUAR = i;
MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB |
MCF_MMU_MMUOR_RW; /* search ITLB */
if (MCF_MMU_MMUTR & MCF_MMU_MMUTR_V)
{
/* entry is valid */
if (MCF_MMU_MMUDR & MCF_MMU_MMUDR_LK)
{
ld++;
}
}
}
*num_itlb = li;
*num_dtlb = ld;
return 1; /* success */
}
uint32_t mmu_report_pagesize(void)
{
return DEFAULT_PAGE_SIZE;
}

67
BaS_gcc/sys/startcf.S Normal file
View File

@@ -0,0 +1,67 @@
/*
* This object file must be the first to be linked,
* so it will be placed at the very beginning of the ROM.
*/
.equ MCF_MMU_MMUCR, __MMUBAR + 0
.global _rom_header
.global _rom_entry
.extern _initialize_hardware
.extern _rt_mbar
/* ROM header */
_rom_header:
/* The first long is supposed to be the initial SP.
* We replace it by bra.s to allow running the ROM from the first byte.
* Then we add a fake jmp instruction for pretty disassembly.
*/
bra.s _rom_entry // Short jump to the real entry point
.short 0x4ef9 // Fake jmp instruction
/* The second long is the initial PC */
.long _rom_entry // Real entry point
/* ROM entry point */
_rom_entry:
/* disable interrupts */
move.w #0x2700,SR
/* Initialize MBAR */
move.l #__MBAR,d0
movec d0,MBAR
move.l d0,_rt_mbar
/* mmu off */
move.l #__MMUBAR+1,d0
movec d0,MMUBAR
clr.l d0
move.l d0,MCF_MMU_MMUCR
/* Initialize RAMBARs: locate SRAM and validate it */
move.l #__RAMBAR0 + 0x7,d0 /* supervisor only */
movec d0,RAMBAR0
move.l #__RAMBAR1 + 0x1,d0
movec d0,RAMBAR1
/* set stack pointer to end of SRAM */
lea __SUP_SP,a7
move.l #0,(sp)
/*
* Initialize the processor caches.
* The instruction cache is fully enabled.
* The data cache is enabled, but cache-inhibited by default.
* Later, the MMU will fully activate the data cache for specific areas.
* It is important to enable both caches now, otherwise cpushl would hang.
*/
move.l #0xa50c8120,d0
movec d0,cacr
andi.l #0xfefbfeff,d0 // Clear invalidate bits
move.l d0,_rt_cacr
/* initialize any hardware specific issues */
bra _initialize_hardware

1138
BaS_gcc/sys/sysinit.c Normal file
View File

File diff suppressed because it is too large Load Diff