diff --git a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd b/vhdl/rtl/vhdl/Firebee_V1/Firebee_Top.vhd
similarity index 99%
rename from vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
rename to vhdl/rtl/vhdl/Firebee_V1/Firebee_Top.vhd
index 9686523..65c2849 100644
--- a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
+++ b/vhdl/rtl/vhdl/Firebee_V1/Firebee_Top.vhd
@@ -788,7 +788,7 @@ BEGIN
END IF;
END PROCESS VDP_Q_BUFFER;
- I_DDR_CTRL: DDR_CTRL_V1
+ I_DDR_CTRL: DDR_CTRL
PORT MAP(
CLK_MAIN => CLK_MAIN,
ddr_sync_66m => ddr_sync_66m,
diff --git a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1.sdc b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1.sdc
deleted file mode 100644
index ffe6d02..0000000
--- a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1.sdc
+++ /dev/null
@@ -1,30 +0,0 @@
-#**************************************************************
-# Time Information
-#**************************************************************
-
- set_time_format -unit ps
-
-
-
-#**************************************************************
-# Create Clock
-#**************************************************************
-
-# create_clock -name CLK -period 100.000 -waveform {0.000 50.000} [get_ports {CLK}]
-
-create_clock -period 30.303 -name CLK_MAIN [get_ports {CLK_MAIN}]
-create_clock -period 30.303 -name CLK_33M [get_ports {CLK_33M}]
-
-derive_pll_clocks -use_net_name
-derive_clock_uncertainty
-
-#set_clock_groups -exclusive -group {CLK_2M0}
-#set_clock_groups -exclusive -group {CLK_500K}
-#set_clock_groups -exclusive -group {CLK_2M4576}
-#set_clock_groups -exclusive -group {CLK_24M576}
-#set_clock_groups -exclusive -group {CLK_FDC}
-#set_clock_groups -exclusive -group {CLK_VIDEO}
-#set_clock_groups -exclusive -group {CLK_25M}
-#set_clock_groups -exclusive -group {CLK_48M}
-#set_clock_groups -exclusive -group {CLK_PIXEL}
-
diff --git a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd b/vhdl/rtl/vhdl/Firebee_V1/Firebee_pkg.vhd
similarity index 97%
rename from vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd
rename to vhdl/rtl/vhdl/Firebee_V1/Firebee_pkg.vhd
index 9cbd579..c106214 100644
--- a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd
+++ b/vhdl/rtl/vhdl/Firebee_V1/Firebee_pkg.vhd
@@ -154,7 +154,7 @@ package firebee_pkg is
);
end component;
- component DDR_CTRL_V1 is
+ component DDR_CTRL is
port(
CLK_MAIN : in std_logic;
DDR_SYNC_66M : in std_logic;
diff --git a/vhdl/rtl/vhdl/Firebee_V1/altpll1_waveforms.html b/vhdl/rtl/vhdl/Firebee_V1/altpll1_waveforms.html
deleted file mode 100644
index 1382a12..0000000
--- a/vhdl/rtl/vhdl/Firebee_V1/altpll1_waveforms.html
+++ /dev/null
@@ -1,10 +0,0 @@
-
-
-Sample Waveforms for "altpll1.vhd"
-
-
-Sample behavioral waveforms for design file "altpll1.vhd"
-
-
-
-
diff --git a/vhdl/rtl/vhdl/Firebee_V1/altpll2_waveforms.html b/vhdl/rtl/vhdl/Firebee_V1/altpll2_waveforms.html
deleted file mode 100644
index 1932527..0000000
--- a/vhdl/rtl/vhdl/Firebee_V1/altpll2_waveforms.html
+++ /dev/null
@@ -1,10 +0,0 @@
-
-
-Sample Waveforms for "altpll2.vhd"
-
-
-Sample behavioral waveforms for design file "altpll2.vhd"
-
-
-
-