diff --git a/BaS_gcc.files b/BaS_gcc.files index 677b349..31af8f8 100644 --- a/BaS_gcc.files +++ b/BaS_gcc.files @@ -893,3 +893,4 @@ tos/vmem_test/sources/printf_helper.S tos/vmem_test/sources/vmem_test.c tos/vmem_test/Makefile tos/Makefile +radeon/radeon_i2c.c diff --git a/Makefile b/Makefile index 5413dc2..025ec34 100644 --- a/Makefile +++ b/Makefile @@ -138,6 +138,7 @@ CSRCS= \ radeon_accel.c \ radeon_cursor.c \ radeon_monitor.c \ + radeon_i2c.c \ fnt_st_8x16.c \ \ x86emu.c \ diff --git a/flash_scripts/run_m548x_dbug.bdm b/flash_scripts/run_m548x_dbug.bdm index b216035..f0eb3c1 100755 --- a/flash_scripts/run_m548x_dbug.bdm +++ b/flash_scripts/run_m548x_dbug.bdm @@ -8,7 +8,9 @@ sleep 1 wait - +# set VBR +write-ctrl 0x0801 0x00000000 +dump-register VBR # Turn on MBAR at 0x1000_0000 write-ctrl 0x0C0F 0x10000000 @@ -20,8 +22,8 @@ write-ctrl 0x0C04 0x20000021 # Turn on RAMBAR1 at address 20001000 write-ctrl 0x0C05 0x20001021 -# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 8Mbytes) -write 0x10000500 0xE0000000 4 +# Init CS0 (BootFLASH @ ff80_0000 - ff8F_FFFF 8Mbytes) +write 0x10000500 0xff800000 4 write 0x10000508 0x00041180 4 write 0x10000504 0x003F0001 4 wait @@ -47,11 +49,7 @@ write 0x10000100 0x018D0000 4 # SDMR (write to LMR) write 0x10000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh) sleep 100 -load m548xlite_dbug_ram.elf .sec1 .sec2 .sec3 - -# set VBR -write-ctrl 0x0801 0x00000000 -dump-register VBR +load m548xlite_dbug_ram.elf execute wait diff --git a/include/fb.h b/include/fb.h index 57cef1d..8083c2b 100644 --- a/include/fb.h +++ b/include/fb.h @@ -12,7 +12,7 @@ #define FBIOPUT_VSCREENINFO 0x4601 #define FBIOGET_FSCREENINFO 0x4602 #define FBIOPAN_DISPLAY 0x4606 -#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ +#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ #define FBIO_ALLOC 0x4613 #define FBIO_FREE 0x4614 @@ -77,103 +77,104 @@ struct mode_option { extern struct mode_option resolution; /* fVDI */ -#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ -#define FB_TYPE_PLANES 1 /* Non interleaved planes */ -#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */ -#define FB_TYPE_TEXT 3 /* Text/attributes */ -#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */ +#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ +#define FB_TYPE_PLANES 1 /* Non interleaved planes */ +#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */ +#define FB_TYPE_TEXT 3 /* Text/attributes */ +#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */ -#define FB_AUX_TEXT_MDA 0 /* Monochrome text */ -#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */ -#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */ -#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */ -#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */ +#define FB_AUX_TEXT_MDA 0 /* Monochrome text */ +#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */ +#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */ +#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */ +#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */ -#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */ -#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */ -#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */ +#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */ +#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */ +#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */ -#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */ -#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */ -#define FB_VISUAL_TRUECOLOR 2 /* True color */ -#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */ -#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */ -#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */ +#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */ +#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */ +#define FB_VISUAL_TRUECOLOR 2 /* True color */ +#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */ +#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */ +#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */ -#define FB_ACCEL_NONE 0 /* no hardware accelerator */ -#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */ -#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */ -#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */ -#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */ -#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */ -#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */ -#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */ -#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */ -#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */ -#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */ -#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */ -#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */ -#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */ -#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */ -#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */ -#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */ -#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */ -#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */ -#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */ -#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */ -#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */ -#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */ -#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */ -#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */ -#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */ -#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */ -#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */ -#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */ -#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */ -#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */ -#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */ -#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */ -#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */ -#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */ -#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */ -#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */ -#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */ -#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */ -#define FB_ACCEL_I810 39 /* Intel 810/815 */ -#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */ -#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */ -#define FB_ACCEL_I830 42 /* Intel 830M/845G/85x/865G */ -#define FB_ACCEL_NV_10 43 /* nVidia Arch 10 */ -#define FB_ACCEL_NV_20 44 /* nVidia Arch 20 */ -#define FB_ACCEL_NV_30 45 /* nVidia Arch 30 */ -#define FB_ACCEL_NV_40 46 /* nVidia Arch 40 */ -#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */ -#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */ -#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */ -#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */ -#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */ -#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */ -#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */ -#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */ -#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */ +#define FB_ACCEL_NONE 0 /* no hardware accelerator */ +#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */ +#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */ +#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */ +#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */ +#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */ +#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */ +#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */ +#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */ +#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */ +#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */ +#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */ +#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */ +#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */ +#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */ +#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */ +#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */ +#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */ +#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */ +#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */ +#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */ +#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */ +#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */ +#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */ +#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */ +#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */ +#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */ +#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */ +#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */ +#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */ +#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */ +#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */ +#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */ +#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */ +#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */ +#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */ +#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */ +#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */ +#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */ +#define FB_ACCEL_I810 39 /* Intel 810/815 */ +#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */ +#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */ +#define FB_ACCEL_I830 42 /* Intel 830M/845G/85x/865G */ +#define FB_ACCEL_NV_10 43 /* nVidia Arch 10 */ +#define FB_ACCEL_NV_20 44 /* nVidia Arch 20 */ +#define FB_ACCEL_NV_30 45 /* nVidia Arch 30 */ +#define FB_ACCEL_NV_40 46 /* nVidia Arch 40 */ +#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */ +#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */ +#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */ +#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */ +#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */ +#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */ +#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */ +#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */ +#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */ -#define FB_ACCEL_SAVAGE4 0x80 /* S3 Savage4 */ -#define FB_ACCEL_SAVAGE3D 0x81 /* S3 Savage3D */ -#define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */ -#define FB_ACCEL_SAVAGE2000 0x83 /* S3 Savage2000 */ -#define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */ -#define FB_ACCEL_SAVAGE_MX 0x85 /* S3 Savage/MX */ -#define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */ -#define FB_ACCEL_SAVAGE_IX 0x87 /* S3 Savage/IX */ -#define FB_ACCEL_PROSAVAGE_PM 0x88 /* S3 ProSavage PM133 */ -#define FB_ACCEL_PROSAVAGE_KM 0x89 /* S3 ProSavage KM133 */ -#define FB_ACCEL_S3TWISTER_P 0x8a /* S3 Twister */ -#define FB_ACCEL_S3TWISTER_K 0x8b /* S3 TwisterK */ -#define FB_ACCEL_SUPERSAVAGE 0x8c /* S3 Supersavage */ -#define FB_ACCEL_PROSAVAGE_DDR 0x8d /* S3 ProSavage DDR */ -#define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */ +#define FB_ACCEL_SAVAGE4 0x80 /* S3 Savage4 */ +#define FB_ACCEL_SAVAGE3D 0x81 /* S3 Savage3D */ +#define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */ +#define FB_ACCEL_SAVAGE2000 0x83 /* S3 Savage2000 */ +#define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */ +#define FB_ACCEL_SAVAGE_MX 0x85 /* S3 Savage/MX */ +#define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */ +#define FB_ACCEL_SAVAGE_IX 0x87 /* S3 Savage/IX */ +#define FB_ACCEL_PROSAVAGE_PM 0x88 /* S3 ProSavage PM133 */ +#define FB_ACCEL_PROSAVAGE_KM 0x89 /* S3 ProSavage KM133 */ +#define FB_ACCEL_S3TWISTER_P 0x8a /* S3 Twister */ +#define FB_ACCEL_S3TWISTER_K 0x8b /* S3 TwisterK */ +#define FB_ACCEL_SUPERSAVAGE 0x8c /* S3 Supersavage */ +#define FB_ACCEL_PROSAVAGE_DDR 0x8d /* S3 ProSavage DDR */ +#define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */ -struct fb_fix_screeninfo { +struct fb_fix_screeninfo +{ char id[16]; /* identification string eg "TT Builtin" */ unsigned long smem_start; /* Start of frame buffer mem */ /* (physical address) */ @@ -199,18 +200,19 @@ struct fb_fix_screeninfo { * stream and is written to video memory as that unmodified. This implies * big-endian byte order if bits_per_pixel is greater than 8. */ -struct fb_bitfield { +struct fb_bitfield +{ unsigned long offset; /* beginning of bitfield */ unsigned long length; /* length of bitfield */ unsigned long msb_right; /* != 0 : Most significant bit is */ /* right */ }; -#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ +#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ -#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/ -#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */ -#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */ +#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/ +#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */ +#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */ #define FB_ACTIVATE_MASK 15 /* values */ #define FB_ACTIVATE_VBL 16 /* activate values on next vbl */ @@ -219,30 +221,31 @@ struct fb_bitfield { #define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/ #define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */ -#define FB_ACCELF_TEXT 1 /* (OBSOLETE) see fb_info.flags and vc_mode */ +#define FB_ACCELF_TEXT 1 /* (OBSOLETE) see fb_info.flags and vc_mode */ -#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ -#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ -#define FB_SYNC_EXT 4 /* external sync */ -#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ -#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ +#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_EXT 4 /* external sync */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ /* vtotal = 144d/288n/576i => PAL */ /* vtotal = 121d/242n/484i => NTSC */ -#define FB_SYNC_ON_GREEN 32 /* sync on green */ +#define FB_SYNC_ON_GREEN 32 /* sync on green */ #define FB_VMODE_NONINTERLACED 0 /* non interlaced */ -#define FB_VMODE_INTERLACED 1 /* interlaced */ -#define FB_VMODE_DOUBLE 2 /* double scan */ -#define FB_VMODE_MASK 255 +#define FB_VMODE_INTERLACED 1 /* interlaced */ +#define FB_VMODE_DOUBLE 2 /* double scan */ +#define FB_VMODE_MASK 255 -#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ -#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ -#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ +#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ -#define PICOS2KHZ(a) (1000000000UL/(a)) -#define KHZ2PICOS(a) (1000000000UL/(a)) +#define PICOS2KHZ(a) (1000000000UL/(a)) +#define KHZ2PICOS(a) (1000000000UL/(a)) -struct fb_var_screeninfo { +struct fb_var_screeninfo +{ unsigned long xres; /* visible resolution */ unsigned long yres; unsigned long xres_virtual; /* virtual resolution */ @@ -311,7 +314,8 @@ enum { #define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */ #define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */ -struct fb_vblank { +struct fb_vblank +{ unsigned long flags; /* FB_VBLANK flags */ unsigned long count; /* counter of retraces since boot */ unsigned long vcount; /* current scanline position */ @@ -349,7 +353,8 @@ struct file; #define FB_MISC_PRIM_COLOR 1 #define FB_MISC_1ST_DETAIL 2 /* First Detailed Timing is preferred */ -struct fb_chroma { +struct fb_chroma +{ unsigned long redx; /* in fraction of 1024 */ unsigned long greenx; unsigned long bluex; @@ -360,7 +365,8 @@ struct fb_chroma { unsigned long whitey; }; -struct fb_monspecs { +struct fb_monspecs +{ struct fb_chroma chroma; struct fb_videomode *modedb; /* mode database */ unsigned char manufacturer[4]; /* Manufacturer */ @@ -390,7 +396,8 @@ struct fb_monspecs { unsigned char max_y; /* Maximum vertical size (cm) */ }; -struct fb_ops { +struct fb_ops +{ /* checks var and eventually tweaks if to soomething supported, * DO NOT MODIFY PAR */ int (*fb_check_var)(struct fb_var_screeninfo *var, struct fb_info *info); @@ -449,7 +456,8 @@ struct fb_ops { void (*WaitVbl)(struct fb_info *info); }; -struct fb_info { +struct fb_info +{ struct fb_var_screeninfo var; /* Current var */ struct fb_fix_screeninfo fix; /* Current fix */ struct fb_monspecs monspecs; /* Current Monitor specs */ diff --git a/include/radeonfb.h b/include/radeonfb.h index 10e7191..5de0923 100644 --- a/include/radeonfb.h +++ b/include/radeonfb.h @@ -1,6 +1,10 @@ #ifndef __RADEONFB_H__ #define __RADEONFB_H__ +#ifdef CONFIG_FB_RADEON_I2C +#undef CONFIG_FB_RADEON_I2C +#endif + #include #include "pci.h" #include "mod_devicetable.h" @@ -39,50 +43,50 @@ */ enum radeon_family { - CHIP_FAMILY_UNKNOW, - CHIP_FAMILY_LEGACY, - CHIP_FAMILY_RADEON, - CHIP_FAMILY_RV100, - CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ - CHIP_FAMILY_RV200, - CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ - CHIP_FAMILY_R200, - CHIP_FAMILY_RV250, - CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ - CHIP_FAMILY_RV280, - CHIP_FAMILY_R300, - CHIP_FAMILY_R350, - CHIP_FAMILY_RV350, - CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ - CHIP_FAMILY_R420, /* R420/R423/M18 */ - CHIP_FAMILY_LAST, + CHIP_FAMILY_UNKNOW, + CHIP_FAMILY_LEGACY, + CHIP_FAMILY_RADEON, + CHIP_FAMILY_RV100, + CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ + CHIP_FAMILY_RV200, + CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ + CHIP_FAMILY_R200, + CHIP_FAMILY_RV250, + CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ + CHIP_FAMILY_RV280, + CHIP_FAMILY_R300, + CHIP_FAMILY_R350, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ + CHIP_FAMILY_R420, /* R420/R423/M18 */ + CHIP_FAMILY_LAST, }; #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ - ((rinfo)->family == CHIP_FAMILY_RV200) || \ - ((rinfo)->family == CHIP_FAMILY_RS100) || \ - ((rinfo)->family == CHIP_FAMILY_RS200) || \ - ((rinfo)->family == CHIP_FAMILY_RV250) || \ - ((rinfo)->family == CHIP_FAMILY_RV280) || \ - ((rinfo)->family == CHIP_FAMILY_RS300)) + ((rinfo)->family == CHIP_FAMILY_RV200) || \ + ((rinfo)->family == CHIP_FAMILY_RS100) || \ + ((rinfo)->family == CHIP_FAMILY_RS200) || \ + ((rinfo)->family == CHIP_FAMILY_RV250) || \ + ((rinfo)->family == CHIP_FAMILY_RV280) || \ + ((rinfo)->family == CHIP_FAMILY_RS300)) #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ - ((rinfo)->family == CHIP_FAMILY_RV350) || \ - ((rinfo)->family == CHIP_FAMILY_R350) || \ - ((rinfo)->family == CHIP_FAMILY_RV380) || \ - ((rinfo)->family == CHIP_FAMILY_R420)) + ((rinfo)->family == CHIP_FAMILY_RV350) || \ + ((rinfo)->family == CHIP_FAMILY_R350) || \ + ((rinfo)->family == CHIP_FAMILY_RV380) || \ + ((rinfo)->family == CHIP_FAMILY_R420)) /* * Chip flags */ enum radeon_chip_flags { - CHIP_FAMILY_MASK = 0x0000ffffUL, - CHIP_FLAGS_MASK = 0xffff0000UL, - CHIP_IS_MOBILITY = 0x00010000UL, - CHIP_IS_IGP = 0x00020000UL, - CHIP_HAS_CRTC2 = 0x00040000UL, + CHIP_FAMILY_MASK = 0x0000ffffUL, + CHIP_FLAGS_MASK = 0xffff0000UL, + CHIP_IS_MOBILITY = 0x00010000UL, + CHIP_IS_IGP = 0x00020000UL, + CHIP_HAS_CRTC2 = 0x00040000UL, }; /* @@ -90,9 +94,9 @@ enum radeon_chip_flags */ enum radeon_errata { - CHIP_ERRATA_R300_CG = 0x00000001, - CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, - CHIP_ERRATA_PLL_DELAY = 0x00000004, + CHIP_ERRATA_R300_CG = 0x00000001, + CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, + CHIP_ERRATA_PLL_DELAY = 0x00000004, }; @@ -101,12 +105,12 @@ enum radeon_errata */ enum radeon_montype { - MT_NONE = 0, - MT_CRT, /* CRT */ - MT_LCD, /* LCD */ - MT_DFP, /* DVI */ - MT_CTV, /* composite TV */ - MT_STV /* S-Video out */ + MT_NONE = 0, + MT_CRT, /* CRT */ + MT_LCD, /* LCD */ + MT_DFP, /* DVI */ + MT_CTV, /* composite TV */ + MT_STV /* S-Video out */ }; /* @@ -114,11 +118,11 @@ enum radeon_montype */ enum ddc_type { - ddc_none, - ddc_monid, - ddc_dvi, - ddc_vga, - ddc_crt2, + ddc_none, + ddc_monid, + ddc_dvi, + ddc_vga, + ddc_crt2, }; /* @@ -126,11 +130,11 @@ enum ddc_type */ enum conn_type { - conn_none, - conn_proprietary, - conn_crt, - conn_DVI_I, - conn_DVI_D, + conn_none, + conn_proprietary, + conn_crt, + conn_DVI_I, + conn_DVI_D, }; @@ -139,11 +143,11 @@ enum conn_type */ struct pll_info { - int32_t ppll_max; - int32_t ppll_min; - int32_t sclk, mclk; - int32_t ref_div; - int32_t ref_clk; + int32_t ppll_max; + int32_t ppll_min; + int32_t sclk, mclk; + int32_t ref_div; + int32_t ref_clk; }; @@ -155,120 +159,120 @@ struct pll_info */ struct radeon_regs { - /* Common registers */ - uint32_t ovr_clr; - uint32_t ovr_wid_left_right; - uint32_t ovr_wid_top_bottom; - uint32_t ov0_scale_cntl; - uint32_t mpp_tb_config; - uint32_t mpp_gp_config; - uint32_t subpic_cntl; - uint32_t viph_control; - uint32_t i2c_cntl_1; - uint32_t gen_int32_t_cntl; - uint32_t cap0_trig_cntl; - uint32_t cap1_trig_cntl; - uint32_t bus_cntl; - uint32_t surface_cntl; - uint32_t bios_5_scratch; + /* Common registers */ + uint32_t ovr_clr; + uint32_t ovr_wid_left_right; + uint32_t ovr_wid_top_bottom; + uint32_t ov0_scale_cntl; + uint32_t mpp_tb_config; + uint32_t mpp_gp_config; + uint32_t subpic_cntl; + uint32_t viph_control; + uint32_t i2c_cntl_1; + uint32_t gen_int32_t_cntl; + uint32_t cap0_trig_cntl; + uint32_t cap1_trig_cntl; + uint32_t bus_cntl; + uint32_t surface_cntl; + uint32_t bios_5_scratch; - /* Other registers to save for VT switches or driver load/unload */ - uint32_t dp_datatype; - uint32_t rbbm_soft_reset; - uint32_t clock_cntl_index; - uint32_t amcgpio_en_reg; - uint32_t amcgpio_mask; + /* Other registers to save for VT switches or driver load/unload */ + uint32_t dp_datatype; + uint32_t rbbm_soft_reset; + uint32_t clock_cntl_index; + uint32_t amcgpio_en_reg; + uint32_t amcgpio_mask; - /* Surface/tiling registers */ - uint32_t surf_lower_bound[8]; - uint32_t surf_upper_bound[8]; - uint32_t surf_info[8]; + /* Surface/tiling registers */ + uint32_t surf_lower_bound[8]; + uint32_t surf_upper_bound[8]; + uint32_t surf_info[8]; - /* CRTC registers */ - uint32_t crtc_gen_cntl; - uint32_t crtc_ext_cntl; - uint32_t dac_cntl; - uint32_t crtc_h_total_disp; - uint32_t crtc_h_sync_strt_wid; - uint32_t crtc_v_total_disp; - uint32_t crtc_v_sync_strt_wid; - uint32_t crtc_offset; - uint32_t crtc_offset_cntl; - uint32_t crtc_pitch; - uint32_t disp_merge_cntl; - uint32_t grph_buffer_cntl; - uint32_t crtc_more_cntl; + /* CRTC registers */ + uint32_t crtc_gen_cntl; + uint32_t crtc_ext_cntl; + uint32_t dac_cntl; + uint32_t crtc_h_total_disp; + uint32_t crtc_h_sync_strt_wid; + uint32_t crtc_v_total_disp; + uint32_t crtc_v_sync_strt_wid; + uint32_t crtc_offset; + uint32_t crtc_offset_cntl; + uint32_t crtc_pitch; + uint32_t disp_merge_cntl; + uint32_t grph_buffer_cntl; + uint32_t crtc_more_cntl; - /* CRTC2 registers */ - uint32_t crtc2_gen_cntl; - uint32_t dac2_cntl; - uint32_t disp_output_cntl; - uint32_t disp_hw_debug; - uint32_t disp2_merge_cntl; - uint32_t grph2_buffer_cntl; - uint32_t crtc2_h_total_disp; - uint32_t crtc2_h_sync_strt_wid; - uint32_t crtc2_v_total_disp; - uint32_t crtc2_v_sync_strt_wid; - uint32_t crtc2_offset; - uint32_t crtc2_offset_cntl; - uint32_t crtc2_pitch; + /* CRTC2 registers */ + uint32_t crtc2_gen_cntl; + uint32_t dac2_cntl; + uint32_t disp_output_cntl; + uint32_t disp_hw_debug; + uint32_t disp2_merge_cntl; + uint32_t grph2_buffer_cntl; + uint32_t crtc2_h_total_disp; + uint32_t crtc2_h_sync_strt_wid; + uint32_t crtc2_v_total_disp; + uint32_t crtc2_v_sync_strt_wid; + uint32_t crtc2_offset; + uint32_t crtc2_offset_cntl; + uint32_t crtc2_pitch; - /* Flat panel regs */ - uint32_t fp_crtc_h_total_disp; - uint32_t fp_crtc_v_total_disp; - uint32_t fp_gen_cntl; - uint32_t fp2_gen_cntl; - uint32_t fp_h_sync_strt_wid; - uint32_t fp2_h_sync_strt_wid; - uint32_t fp_horz_stretch; - uint32_t fp_panel_cntl; - uint32_t fp_v_sync_strt_wid; - uint32_t fp2_v_sync_strt_wid; - uint32_t fp_vert_stretch; - uint32_t lvds_gen_cntl; - uint32_t lvds_pll_cntl; - uint32_t tmds_crc; - uint32_t tmds_transmitter_cntl; + /* Flat panel regs */ + uint32_t fp_crtc_h_total_disp; + uint32_t fp_crtc_v_total_disp; + uint32_t fp_gen_cntl; + uint32_t fp2_gen_cntl; + uint32_t fp_h_sync_strt_wid; + uint32_t fp2_h_sync_strt_wid; + uint32_t fp_horz_stretch; + uint32_t fp_panel_cntl; + uint32_t fp_v_sync_strt_wid; + uint32_t fp2_v_sync_strt_wid; + uint32_t fp_vert_stretch; + uint32_t lvds_gen_cntl; + uint32_t lvds_pll_cntl; + uint32_t tmds_crc; + uint32_t tmds_transmitter_cntl; - /* Computed values for PLL */ - uint32_t dot_clock_freq; - uint32_t pll_output_freq; - int32_t feedback_div; - int32_t post_div; + /* Computed values for PLL */ + uint32_t dot_clock_freq; + uint32_t pll_output_freq; + int32_t feedback_div; + int32_t post_div; - /* PLL registers */ - uint32_t ppll_div_3; - uint32_t ppll_ref_div; - uint32_t vclk_ecp_cntl; - uint32_t clk_cntl_index; - uint32_t htotal_cntl; + /* PLL registers */ + uint32_t ppll_div_3; + uint32_t ppll_ref_div; + uint32_t vclk_ecp_cntl; + uint32_t clk_cntl_index; + uint32_t htotal_cntl; - /* Computed values for PLL2 */ - uint32_t dot_clock_freq_2; - uint32_t pll_output_freq_2; - int32_t feedback_div_2; - int32_t post_div_2; + /* Computed values for PLL2 */ + uint32_t dot_clock_freq_2; + uint32_t pll_output_freq_2; + int32_t feedback_div_2; + int32_t post_div_2; - /* PLL2 registers */ - uint32_t p2pll_ref_div; - uint32_t p2pll_div_0; - uint32_t htotal_cntl2; + /* PLL2 registers */ + uint32_t p2pll_ref_div; + uint32_t p2pll_div_0; + uint32_t htotal_cntl2; }; struct panel_info { - int32_t xres, yres; - int32_t valid; - int32_t clock; - int32_t hOver_plus, hSync_width, hblank; - int32_t vOver_plus, vSync_width, vblank; - int32_t hAct_high, vAct_high, int32_terlaced; - int32_t pwr_delay; - int32_t use_bios_dividers; - int32_t ref_divider; - int32_t post_divider; - int32_t fbk_divider; + int32_t xres, yres; + int32_t valid; + int32_t clock; + int32_t hOver_plus, hSync_width, hblank; + int32_t vOver_plus, vSync_width, vblank; + int32_t hAct_high, vAct_high, int32_terlaced; + int32_t pwr_delay; + int32_t use_bios_dividers; + int32_t ref_divider; + int32_t post_divider; + int32_t fbk_divider; }; struct radeonfb_info; @@ -276,186 +280,186 @@ struct radeonfb_info; #ifdef CONFIG_FB_RADEON_I2C struct radeon_i2c_chan { - struct radeonfb_info *rinfo; - uint32_t ddc_reg; - struct i2c_adapter adapter; - struct i2c_algo_bit_data algo; + struct radeonfb_info *rinfo; + uint32_t ddc_reg; + struct i2c_adapter adapter; + struct i2c_algo_bit_data algo; }; #endif enum radeon_pm_mode { - radeon_pm_none = 0, /* Nothing supported */ - radeon_pm_d2 = 0x00000001, /* Can do D2 state */ - radeon_pm_off = 0x00000002, /* Can resume from D3 cold */ + radeon_pm_none = 0, /* Nothing supported */ + radeon_pm_d2 = 0x00000001, /* Can do D2 state */ + radeon_pm_off = 0x00000002, /* Can resume from D3 cold */ }; typedef struct { - uint8_t table_revision; - uint8_t table_size; - uint8_t tuner_type; - uint8_t audio_chip; - uint8_t product_id; - uint8_t tuner_voltage_teletext_fm; - uint8_t i2s_config; /* configuration of the sound chip */ - uint8_t video_decoder_type; - uint8_t video_decoder_host_config; - uint8_t input[5]; + uint8_t table_revision; + uint8_t table_size; + uint8_t tuner_type; + uint8_t audio_chip; + uint8_t product_id; + uint8_t tuner_voltage_teletext_fm; + uint8_t i2s_config; /* configuration of the sound chip */ + uint8_t video_decoder_type; + uint8_t video_decoder_host_config; + uint8_t input[5]; } _MM_TABLE; struct radeonfb_info { - int32_t handle; /* PCI BIOS, must be 1st place */ - int32_t big_endian; /* PCI BIOS */ + int32_t handle; /* PCI BIOS, must be 1st place */ + int32_t big_endian; /* PCI BIOS */ - uint32_t cursor_x; - uint32_t cursor_y; - int32_t cursor_show; - uint32_t cursor_start; - uint32_t cursor_end; - int32_t cursor_fg; - int32_t cursor_bg; + uint32_t cursor_x; + uint32_t cursor_y; + int32_t cursor_show; + uint32_t cursor_start; + uint32_t cursor_end; + int32_t cursor_fg; + int32_t cursor_bg; - int32_t fifo_slots; /* Free slots in the FIFO (64 max) */ + int32_t fifo_slots; /* Free slots in the FIFO (64 max) */ - /* Computed values for Radeon */ - uint32_t dp_gui_master_cntl_clip; - uint32_t trans_color; + /* Computed values for Radeon */ + uint32_t dp_gui_master_cntl_clip; + uint32_t trans_color; - /* Saved values for ScreenToScreenCopy */ - int32_t xdir; - int32_t ydir; + /* Saved values for ScreenToScreenCopy */ + int32_t xdir; + int32_t ydir; - /* ScanlineScreenToScreenColorExpand support */ - int32_t scanline_h; - int32_t scanline_words; - int32_t scanline_bpp; /* Only used for ImageWrite */ + /* ScanlineScreenToScreenColorExpand support */ + int32_t scanline_h; + int32_t scanline_words; + int32_t scanline_bpp; /* Only used for ImageWrite */ - /* Saved values for DashedTwoPoint32_tLine */ - int32_t dashLen; - uint32_t dashPattern; - int32_t dash_fg; - int32_t dash_bg; + /* Saved values for DashedTwoPoint32_tLine */ + int32_t dashLen; + uint32_t dashPattern; + int32_t dash_fg; + int32_t dash_bg; - struct fb_info *info; + struct fb_info *info; - struct radeon_regs state; - struct radeon_regs init_state; + struct radeon_regs state; + struct radeon_regs init_state; - uint8_t name[50]; + uint8_t name[50]; - uint32_t io_base_phys; - uint32_t mmio_base_phys; - uint32_t fb_base_phys; + uint32_t io_base_phys; + uint32_t mmio_base_phys; + uint32_t fb_base_phys; - void *io_base; - void *mmio_base; - void *fb_base; + void *io_base; + void *mmio_base; + void *fb_base; - uint32_t fb_local_base; - uint32_t fb_offset; + uint32_t fb_local_base; + uint32_t fb_offset; - uint32_t bios_seg_phys; - void *bios_seg; - int32_t fp_bios_start; + uint32_t bios_seg_phys; + void *bios_seg; + int32_t fp_bios_start; - struct - { - uint8_t red; - uint8_t green; - uint8_t blue; - uint8_t pad; - } palette[256]; + struct + { + uint8_t red; + uint8_t green; + uint8_t blue; + uint8_t pad; + } palette[256]; - int32_t chipset; - uint8_t family; - uint8_t rev; - int32_t errata; - uint32_t video_ram; - uint32_t mapped_vram; - int32_t vram_width; - int32_t vram_ddr; + int32_t chipset; + uint8_t family; + uint8_t rev; + int32_t errata; + uint32_t video_ram; + uint32_t mapped_vram; + int32_t vram_width; + int32_t vram_ddr; - int32_t pitch, bpp, depth; + int32_t pitch, bpp, depth; - int32_t has_CRTC2; - int32_t is_mobility; - int32_t is_IGP; - int32_t reversed_DAC; - int32_t reversed_TMDS; - struct panel_info panel_info; - int32_t mon1_type; - uint8_t *mon1_EDID; - struct fb_videomode *mon1_modedb; - int32_t mon1_dbsize; - int32_t mon2_type; - uint8_t *mon2_EDID; + int32_t has_CRTC2; + int32_t is_mobility; + int32_t is_IGP; + int32_t reversed_DAC; + int32_t reversed_TMDS; + struct panel_info panel_info; + int32_t mon1_type; + uint8_t *mon1_EDID; + struct fb_videomode *mon1_modedb; + int32_t mon1_dbsize; + int32_t mon2_type; + uint8_t *mon2_EDID; - uint32_t dp_gui_master_cntl; + uint32_t dp_gui_master_cntl; - struct pll_info bios_pll; - struct pll_info pll; + struct pll_info bios_pll; + struct pll_info pll; - uint32_t save_regs[100]; - int32_t asleep; - int32_t lock_blank; - int32_t dynclk; - int32_t no_schedule; - enum radeon_pm_mode pm_mode; + uint32_t save_regs[100]; + int32_t asleep; + int32_t lock_blank; + int32_t dynclk; + int32_t no_schedule; + enum radeon_pm_mode pm_mode; - /* Timer used for delayed LVDS operations */ - int32_t lvds_timer; - uint32_t pending_lvds_gen_cntl; + /* Timer used for delayed LVDS operations */ + int32_t lvds_timer; + uint32_t pending_lvds_gen_cntl; #ifdef CONFIG_FB_RADEON_I2C - struct radeon_i2c_chan i2c[4]; + struct radeon_i2c_chan i2c[4]; #endif - /* Texture */ + /* Texture */ - int32_t RenderInited3D; - int32_t tilingEnabled; - void *RenderTex; - uint32_t RenderTexOffset; - int32_t RenderTexSize; - void (*RenderCallback)(struct radeonfb_info *rinfo); - uint32_t RenderTimeout; - uint32_t dst_pitch_offset; + int32_t RenderInited3D; + int32_t tilingEnabled; + void *RenderTex; + uint32_t RenderTexOffset; + int32_t RenderTexSize; + void (*RenderCallback)(struct radeonfb_info *rinfo); + uint32_t RenderTimeout; + uint32_t dst_pitch_offset; #ifdef _NOT_USED_ - /* Video & theatre */ + /* Video & theatre */ - TheatrePtr theatre; + TheatrePtr theatre; - int32_t MM_TABLE_valid; - _MM_TABLE MM_TABLE; + int32_t MM_TABLE_valid; + _MM_TABLE MM_TABLE; - int32_t RageTheatreCrystal; - int32_t RageTheatreTunerPort; - int32_t RageTheatreCompositePort; - int32_t RageTheatreSVideoPort; - int32_t tunerType; + int32_t RageTheatreCrystal; + int32_t RageTheatreTunerPort; + int32_t RageTheatreCompositePort; + int32_t RageTheatreSVideoPort; + int32_t tunerType; - int32_t videoStatus; - int32_t encoding; - int32_t overlay_deint32_terlacing_method; - int32_t video_stream_active; - int32_t capture_vbi_data; - int32_t v; - void *videoLinear; - int32_t videoLinearSize; - struct - { - uint32_t y,u,v; - } videoLinearOffset; + int32_t videoStatus; + int32_t encoding; + int32_t overlay_deint32_terlacing_method; + int32_t video_stream_active; + int32_t capture_vbi_data; + int32_t v; + void *videoLinear; + int32_t videoLinearSize; + struct + { + uint32_t y,u,v; + } videoLinearOffset; #endif /* _NOT_USED_ */ - int32_t dec_hue; - int32_t dec_saturation; - int32_t dec_contrast; - int32_t dec_brightness; + int32_t dec_hue; + int32_t dec_saturation; + int32_t dec_contrast; + int32_t dec_brightness; }; #define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type) @@ -473,7 +477,7 @@ struct radeonfb_info */ static inline void _radeon_msleep(struct radeonfb_info *rinfo, uint32_t ms) { - wait_ms(ms); + wait_ms(ms); } #define radeon_msleep(ms) _radeon_msleep(rinfo,ms) @@ -509,14 +513,14 @@ extern int32_t *tab_funcs_pci; static inline uint32_t radeon_get_dstbpp(uint16_t depth) { - switch(depth) - { - case 8: return DST_8BPP; - case 15: return DST_15BPP; - case 16: return DST_16BPP; - case 32: return DST_32BPP; - default: return 0; - } + switch(depth) + { + case 8: return DST_8BPP; + case 15: return DST_15BPP; + case 16: return DST_16BPP; + case 32: return DST_32BPP; + default: return 0; + } } /* I2C Functions */ @@ -532,11 +536,11 @@ extern void radeonfb_pm_exit(struct radeonfb_info *rinfo); /* Monitor probe functions */ extern void radeon_probe_screens(struct radeonfb_info *rinfo, - const char *monitor_layout, int ignore_edid); + const char *monitor_layout, int ignore_edid); extern void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolution); extern int radeon_match_mode(struct radeonfb_info *rinfo, - struct fb_var_screeninfo *dest, - const struct fb_var_screeninfo *src); + struct fb_var_screeninfo *dest, + const struct fb_var_screeninfo *src); /* Video functions */ void RADEONResetVideo(struct radeonfb_info *rinfo); @@ -549,7 +553,7 @@ void RADEONVIP_reset(struct radeonfb_info *rinfo); void RADEONInitVideo(struct radeonfb_info *rinfo); void RADEONShutdownVideo(struct radeonfb_info *rinfo); int32_t RADEONPutVideo(struct radeonfb_info *rinfo, int32_t src_x, int32_t src_y, int32_t src_w, int32_t src_h, - int32_t drw_x, int32_t drw_y, int32_t drw_w, int32_t drw_h); + int32_t drw_x, int32_t drw_y, int32_t drw_w, int32_t drw_h); void RADEONStopVideo(struct radeonfb_info *rinfo, int32_t cleanup); /* Theatre functions */ @@ -582,18 +586,18 @@ extern void radeon_wait_for_idle_mmio(struct radeonfb_info *rinfo); #define radeon_engine_idle() radeon_wait_for_idle_mmio(rinfo) #define radeon_wait_for_fifo(rinfo, entries) \ -do \ -{ \ - if (rinfo->fifo_slots < entries) \ - radeon_wait_for_fifo_function(rinfo, entries); \ - rinfo->fifo_slots -= entries; \ -} while (0) + do \ + { \ + if (rinfo->fifo_slots < entries) \ + radeon_wait_for_fifo_function(rinfo, entries); \ + rinfo->fifo_slots -= entries; \ + } while (0) static inline int radeonfb_sync(struct fb_info *info) { - struct radeonfb_info *rinfo = info->par; - radeon_engine_idle(); - return 0; + struct radeonfb_info *rinfo = info->par; + radeon_engine_idle(); + return 0; } extern void radeon_restore_accel_state_mmio(struct fb_info *info); @@ -602,47 +606,47 @@ extern void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int x, extern void radeon_setup_for_solid_line_mmio(struct fb_info *info, int color, int rop, unsigned int planemask); extern void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int x, int y, int len, int dir); extern void radeon_subsequent_solid_two_point_line_mmio(struct fb_info *info, int xa, int ya, int xb, - int yb, int flags); + int yb, int flags); extern void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int fg, int bg, - int rop, unsigned int planemask, int length, unsigned char *pattern); + int rop, unsigned int planemask, int length, unsigned char *pattern); extern void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info, - int xa, int ya, int xb, int yb, int flags, int phase); + int xa, int ya, int xb, int yb, int flags, int phase); extern void radeon_setup_for_screen_to_screen_copy_mmio(struct fb_info *info, - int xdir, int ydir, int rop, unsigned int planemask, int trans_color); + int xdir, int ydir, int rop, unsigned int planemask, int trans_color); extern void radeon_subsequent_screen_to_screen_copy_mmio(struct fb_info *info, - int xa, int ya, int xb, int yb, int w, int h); + int xa, int ya, int xb, int yb, int w, int h); extern void radeon_screen_to_screen_copy_mmio(struct fb_info *info, - int xa, int ya, int xb, int yb, int w, int h, int rop); + int xa, int ya, int xb, int yb, int w, int h, int rop); extern void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info, - int patternx, int patterny, int fg, int bg, int rop, unsigned int planemask); + int patternx, int patterny, int fg, int bg, int rop, unsigned int planemask); extern void radeon_subsequent_mono_8x8_pattern_fill_rect_mmio(struct fb_info *info, - int patternx, int patterny, int x, int y, int w, int h); + int patternx, int patterny, int x, int y, int w, int h); extern void radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info, - int fg, int bg, int rop, unsigned int planemask); + int fg, int bg, int rop, unsigned int planemask); extern void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info, - int x, int y, int w, int h, int skipleft); + int x, int y, int w, int h, int skipleft); extern void radeon_subsequent_scanline_mmio(struct fb_info *info, unsigned long *buf); extern void radeon_setup_for_scanline_image_write_mmio(struct fb_info *info, - int rop, unsigned int planemask, int trans_color, int bpp); + int rop, unsigned int planemask, int trans_color, int bpp); extern void radeon_subsequent_scanline_image_write_rect_mmio(struct fb_info *info, - int x, int y, int w, int h, int skipleft); + int x, int y, int w, int h, int skipleft); extern void radeon_set_clipping_rectangle_mmio(struct fb_info *info, - int xa, int ya, int xb, int yb); + int xa, int ya, int xb, int yb); extern void radeon_disable_clipping_mmio(struct fb_info *info); extern int32_t radeon_setup_for_cpu_to_screen_alpha_texture_mmio(struct fb_info *info, - int op, int red, int green, int blue, - int alpha, int maskFormat, int dstFormat, - uint8_t *alphaPtr, int alphaPitch, - int width, int height, int32_t flags); + int op, int red, int green, int blue, + int alpha, int maskFormat, int dstFormat, + uint8_t *alphaPtr, int alphaPitch, + int width, int height, int32_t flags); extern int32_t radeon_setup_for_cpu_to_screen_texture_mmio(struct fb_info *info, int32_t op, - uint32_t srcFormat, uint32_t dstFormat, - uint8_t *texPtr, int32_t texPitch, - int32_t width, int32_t height, int32_t flags); + uint32_t srcFormat, uint32_t dstFormat, + uint8_t *texPtr, int32_t texPitch, + int32_t width, int32_t height, int32_t flags); extern void radeon_subsequent_cpu_to_screen_texture_mmio(struct fb_info *info, - int32_t dstx, int32_t dsty, - int32_t srcx, int32_t srcy, - int32_t width, int32_t height); + int32_t dstx, int32_t dsty, + int32_t srcx, int32_t srcy, + int32_t width, int32_t height); /* Cursor functions */ extern void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg); extern void radeon_set_cursor_position(struct fb_info *info, int x, int y); @@ -655,7 +659,7 @@ extern long radeon_cursor_init(struct fb_info *info); extern int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t mode_switch); extern void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t reg_only); int radeonfb_setcolreg(unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, struct fb_info *info); + unsigned blue, unsigned transp, struct fb_info *info); extern int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent); extern void radeonfb_pci_unregister(void); diff --git a/pci/pci.c b/pci/pci.c index 5dc0e78..153ef13 100644 --- a/pci/pci.c +++ b/pci/pci.c @@ -34,7 +34,7 @@ #include "interrupts.h" #include "wait.h" -#define DEBUG +// #define DEBUG #include "debug.h" #define pci_config_wait() do { __asm__ __volatile("tpf" ::: "memory"); } while (0) @@ -862,7 +862,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function) if (IS_PCI_MEM_BAR(address)) { /* adjust base address to card's alignment requirements */ - long size = ~(address & 0xfffffff0) + 1; + size_t size = ~(address & 0xfffffff0) + 1; dbg("device 0x%02x: BAR[%d] requests %ld kBytes of memory\r\n", handle, i / 4, size / 1024); /* calculate a valid map adress with alignment requirements */ diff --git a/radeon/radeon_base.c b/radeon/radeon_base.c index f63be71..c73bba9 100644 --- a/radeon/radeon_base.c +++ b/radeon/radeon_base.c @@ -79,7 +79,7 @@ extern void run_bios(struct radeonfb_info *rinfo); 0, \ 0, \ (flags) | (CHIP_FAMILY_##family) \ - } +} struct pci_device_id radeonfb_pci_table[] = { @@ -236,8 +236,6 @@ extern struct fb_info *info_fb; #define rinfo ((struct radeonfb_info *) info_fb->par) static uint32_t inreg(uint32_t addr) { - dbg("info_fb = %p, info_fb->par = %p\r\n", info_fb, info_fb->par); - dbg("retrieve from addr %p\r\n", rinfo->mmio_base + addr); return INREG(addr); } @@ -282,8 +280,8 @@ void radeon_pll_errata_after_index(struct radeonfb_info *rinfo) { if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS)) return; - (void)INREG(CLOCK_CNTL_DATA); - (void)INREG(CRTC_GEN_CNTL); + (void) INREG(CLOCK_CNTL_DATA); + (void) INREG(CRTC_GEN_CNTL); } void radeon_pll_errata_after_data(struct radeonfb_info *rinfo) @@ -363,9 +361,7 @@ static int radeon_map_ROM(struct radeonfb_info *rinfo) dbg("bios_seg=%p\r\n", rinfo->bios_seg); dbg("bios_seg_phys=%p\r\n", rinfo->bios_seg_phys); - dbg("before inreg\r\n"); temp = inreg(MPP_TB_CONFIG); - dbg("after inreg\r\n"); dbg("temp=%d\r\n", temp); temp &= 0x00ffffffu; @@ -445,12 +441,12 @@ anyway: uint16_t pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); dbg("BIOS PLL info block offset: %p\r\n", BIOS_IN16(rinfo->fp_bios_start + 0x30)); - rinfo->bios_pll.sclk = BIOS_IN16(pll_info_block + 0x08); - rinfo->bios_pll.mclk = BIOS_IN16(pll_info_block + 0x0a); + rinfo->bios_pll.sclk = BIOS_IN16(pll_info_block + 0x08); + rinfo->bios_pll.mclk = BIOS_IN16(pll_info_block + 0x0a); rinfo->bios_pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); rinfo->bios_pll.ref_div = BIOS_IN16(pll_info_block + 0x10); - rinfo->bios_pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); - rinfo->bios_pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); + rinfo->bios_pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); + rinfo->bios_pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); } return 0; @@ -490,7 +486,8 @@ static int radeon_probe_pll_params(struct radeonfb_info *rinfo) { if ((get_timer() - start_tv) > US_TO_TIMER(10000000UL)) /* 10 sec */ { - timeout=1; + timeout = 1; + dbg("timeout\r\n"); break; } } @@ -502,7 +499,8 @@ static int radeon_probe_pll_params(struct radeonfb_info *rinfo) { if ((get_timer() - start_tv) > US_TO_TIMER(1000000UL)) /* 1 sec */ { - timeout=1; + timeout = 1; + dbg("timeout2\r\n"); break; } } @@ -512,7 +510,8 @@ static int radeon_probe_pll_params(struct radeonfb_info *rinfo) { if ((get_timer() - start_tv) > US_TO_TIMER(10000000UL)) /* 10 sec */ { - timeout=1; + timeout = 1; + dbg("timeout3\r\n"); break; } } @@ -773,7 +772,10 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) } if (radeon_match_mode(rinfo, &v, var)) + { + dbg("invalid mode\r\n"); return -1; //-EINVAL; + } switch (v.bits_per_pixel) { @@ -795,6 +797,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) break; default: + dbg("invalid bits per pixel\r\n"); return -1; //-EINVAL; } @@ -2128,7 +2131,7 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent) info = framebuffer_alloc(sizeof(struct radeonfb_info)); if (!info) { - dbg("could not allocate frame buffer\r\n"); + dbg("could not allocate frame buffer info\r\n"); return -1; // -ENOMEM; } @@ -2376,7 +2379,7 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent) #endif //rinfo->RageTheatreCrystal = rinfo->RageTheatreTunerPort=rinfo->RageTheatreCompositePort = rinfo->RageTheatreSVideoPort = -1; //rinfo->tunerType = -1; - return(0); + return 0; } #if 0 diff --git a/radeon/radeon_i2c.c b/radeon/radeon_i2c.c new file mode 100644 index 0000000..c049ea6 --- /dev/null +++ b/radeon/radeon_i2c.c @@ -0,0 +1,216 @@ +#include "radeonfb.h" +// #include "relocate.h" +#include "edid.h" +#include "driver_mem.h" + +#ifdef CONFIG_FB_RADEON_I2C + +#define RADEON_DDC 0x50 + +extern void mdelay(long msec); +extern void udelay(long usec); + +static void radeon_gpio_setscl(void* data, int state) +{ + struct radeon_i2c_chan *chan = data; + struct radeonfb_info *rinfo = chan->rinfo; + unsigned long val; + val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN); + if(!state) + val |= VGA_DDC_CLK_OUT_EN; + OUTREG(chan->ddc_reg, val); + (void)INREG(chan->ddc_reg); +} + +static void radeon_gpio_setsda(void* data, int state) +{ + struct radeon_i2c_chan *chan = data; + struct radeonfb_info *rinfo = chan->rinfo; + unsigned long val; + val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN); + if(!state) + val |= VGA_DDC_DATA_OUT_EN; + OUTREG(chan->ddc_reg, val); + (void)INREG(chan->ddc_reg); +} + +static int radeon_gpio_getscl(void* data) +{ + struct radeon_i2c_chan *chan = data; + struct radeonfb_info *rinfo = chan->rinfo; + unsigned long val; + val = INREG(chan->ddc_reg); + return(val & VGA_DDC_CLK_INPUT) ? 1 : 0; +} + +static int radeon_gpio_getsda(void* data) +{ + struct radeon_i2c_chan *chan = data; + struct radeonfb_info *rinfo = chan->rinfo; + unsigned long val; + val = INREG(chan->ddc_reg); + return(val & VGA_DDC_DATA_INPUT) ? 1 : 0; +} + +static int radeon_setup_i2c_bus(struct radeon_i2c_chan *chan) +{ + int rc; + chan->adapter.algo_data = &chan->algo; + chan->algo.setsda = radeon_gpio_setsda; + chan->algo.setscl = radeon_gpio_setscl; + chan->algo.getsda = radeon_gpio_getsda; + chan->algo.getscl = radeon_gpio_getscl; + chan->algo.udelay = 40; + chan->algo.timeout = 20; + chan->algo.data = chan; + /* Raise SCL and SDA */ + radeon_gpio_setsda(chan, 1); + radeon_gpio_setscl(chan, 1); + udelay(20); + rc = i2c_bit_add_bus(&chan->adapter); + return rc; +} + +void radeon_create_i2c_busses(struct radeonfb_info *rinfo) +{ + rinfo->i2c[0].rinfo = rinfo; + rinfo->i2c[0].ddc_reg = GPIO_MONID; + radeon_setup_i2c_bus(&rinfo->i2c[0]); + rinfo->i2c[1].rinfo = rinfo; + rinfo->i2c[1].ddc_reg = GPIO_DVI_DDC; + radeon_setup_i2c_bus(&rinfo->i2c[1]); + rinfo->i2c[2].rinfo = rinfo; + rinfo->i2c[2].ddc_reg = GPIO_VGA_DDC; + radeon_setup_i2c_bus(&rinfo->i2c[2]); + rinfo->i2c[3].rinfo = rinfo; + rinfo->i2c[3].ddc_reg = GPIO_CRT2_DDC; + radeon_setup_i2c_bus(&rinfo->i2c[3]); +} + +#if 0 +void radeon_delete_i2c_busses(struct radeonfb_info *rinfo) +{ + if(rinfo->i2c[0].rinfo) + i2c_bit_del_bus(&rinfo->i2c[0].adapter); + rinfo->i2c[0].rinfo = NULL; + if(rinfo->i2c[1].rinfo) + i2c_bit_del_bus(&rinfo->i2c[1].adapter); + rinfo->i2c[1].rinfo = NULL; + if(rinfo->i2c[2].rinfo) + i2c_bit_del_bus(&rinfo->i2c[2].adapter); + rinfo->i2c[2].rinfo = NULL; + if(rinfo->i2c[3].rinfo) + i2c_bit_del_bus(&rinfo->i2c[3].adapter); + rinfo->i2c[3].rinfo = NULL; +} +#endif + +static unsigned char *radeon_do_probe_i2c_edid(struct radeon_i2c_chan *chan) +{ + unsigned char start = 0x0; + struct i2c_msg msgs[] = + { + { + .addr = RADEON_DDC, + .len = 1, + .buf = &start, + }, + { + .addr = RADEON_DDC, + .flags = I2C_M_RD, + .len = EDID_LENGTH, + }, + }; + + unsigned char *buf; + + buf = driver_mem_alloc(EDID_LENGTH * 3); + if (!buf) + return NULL; + + msgs[1].buf = buf; + if(i2c_transfer(&chan->adapter, msgs, 2) == 2) + return buf; + + driver_mem_free(buf); + return NULL; +} + +int32_t radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int32_t conn, uint8_t **out_edid) +{ + unsigned long reg = rinfo->i2c[conn-1].ddc_reg; + unsigned char *edid = NULL; + int i, j; + // DPRINTVAL("radeonfb: radeon_probe_i2c_connector ", conn); + // DPRINT("\r\n"); + OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUTPUT | VGA_DDC_CLK_OUTPUT)); + OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN)); + (void)INREG(reg); + for(i = 0; i < 3; i++) + { + /* For some old monitors we need the + * following process to initialize/stop DDC + */ + OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN)); + (void)INREG(reg); + mdelay(13); + OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN)); + (void)INREG(reg); + for(j = 0; j < 5; j++) + { + mdelay(10); + if(INREG(reg) & VGA_DDC_CLK_INPUT) + break; + } + if(j == 5) + continue; + OUTREG(reg, INREG(reg) | VGA_DDC_DATA_OUT_EN); + (void)INREG(reg); + mdelay(15); + OUTREG(reg, INREG(reg) | VGA_DDC_CLK_OUT_EN); + (void)INREG(reg); + mdelay(15); + OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN)); + (void)INREG(reg); + mdelay(15); + /* Do the real work */ + edid = radeon_do_probe_i2c_edid(&rinfo->i2c[conn-1]); + OUTREG(reg, INREG(reg) | (VGA_DDC_DATA_OUT_EN | VGA_DDC_CLK_OUT_EN)); + (void)INREG(reg); + mdelay(15); + OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN)); + (void)INREG(reg); + for(j = 0; j < 10; j++) + { + mdelay(10); + if(INREG(reg) & VGA_DDC_CLK_INPUT) + break; + } + OUTREG(reg, INREG(reg) & ~(VGA_DDC_DATA_OUT_EN)); + (void)INREG(reg); + mdelay(15); + OUTREG(reg, INREG(reg) | (VGA_DDC_DATA_OUT_EN | VGA_DDC_CLK_OUT_EN)); + (void)INREG(reg); + if(edid) + break; + } + /* Release the DDC lines when done or the Apple Cinema HD display + * will switch off */ + OUTREG(reg, INREG(reg) & ~(VGA_DDC_CLK_OUT_EN | VGA_DDC_DATA_OUT_EN)); + (void)INREG(reg); + if(out_edid) + *out_edid = edid; + if(!edid) + return MT_NONE; + if(edid[0x14] & 0x80) + { + /* Fix detection using BIOS tables */ + if(rinfo->is_mobility /*&& conn == ddc_dvi*/ && (INREG(LVDS_GEN_CNTL) & LVDS_ON)) + return MT_LCD; + else + return MT_DFP; + } + return MT_CRT; +} + +#endif /* CONFIG_FB_RADEON_I2C */ diff --git a/radeon/radeon_monitor.c b/radeon/radeon_monitor.c index 09e706c..731b2b9 100644 --- a/radeon/radeon_monitor.c +++ b/radeon/radeon_monitor.c @@ -5,12 +5,8 @@ #include "bas_printf.h" #include "bas_string.h" -//#define DBG_MONITOR -#ifdef DBG_MONITOR -#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0) -#else -#define dbg(format, arg...) do { ; } while (0) -#endif /* DBG_MONITOR */ +// #define DEBUG +#include "debug.h" #ifndef INT_MAX #define INT_MAX ((int) (~0U >> 1)) @@ -136,7 +132,7 @@ static int radeon_parse_monitor_layout(struct radeonfb_info *rinfo, const char * if ((monitor_layout == NULL) || (*monitor_layout == '\0')) { - dbg("%s: monitor_layout missing\r\n"); + dbg("monitor_layout missing\r\n"); return 0; } @@ -178,33 +174,33 @@ static int radeon_parse_monitor_layout(struct radeonfb_info *rinfo, const char * if (strcmp(s1, "CRT")) { rinfo->mon1_type = MT_CRT; - dbg("%s: monitor 1 set to CRT\r\n", __FUNCTION__); + dbg("monitor 1 set to CRT\r\n"); } else if (strcmp(s1, "TMDS")) { rinfo->mon1_type = MT_DFP; - dbg("%s: monitor 1 set to TMDS\r\n", __FUNCTION__); + dbg("monitor 1 set to TMDS\r\n"); } else if (strcmp(s1, "LVDS")) { rinfo->mon1_type = MT_LCD; - dbg("%s: monitor 1 set to LVDS\r\n", __FUNCTION__); + dbg("monitor 1 set to LVDS\r\n"); } if (strcmp(s2, "CRT")) { rinfo->mon2_type = MT_CRT; - dbg("%s: monitor 2 set to CRT\r\n", __FUNCTION__); + dbg("monitor 2 set to CRT\r\n"); } else if (strcmp(s2, "TMDS")) { rinfo->mon2_type = MT_DFP; - dbg("%s: monitor 2 set to TMDS\r\n", __FUNCTION__); + dbg("monitor 2 set to TMDS\r\n"); } else if (strcmp(s2, "LVDS")) { rinfo->mon2_type = MT_LCD; - dbg("%s: monitor 2 set to LVDS\r\n", __FUNCTION__); + dbg("monitor 2 set to LVDS\r\n"); } return 1; } @@ -227,25 +223,25 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou * a layout for each card ? */ #ifdef CONFIG_FB_RADEON_I2C - dbg("%s: use monitor layout\r\n", __FUNCTION__); + dbg("use monitor layout\r\n"); if (!ignore_edid) { if (rinfo->mon1_type != MT_NONE) { - dbg("%s: probe ddc_dvi on MON1\r\n", __FUNCTION__); + dbg("probe ddc_dvi on MON1\r\n"); if (!radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID)) { - dbg("%s: probe ddc_crt2 on MON1\r\n", __FUNCTION__); + dbg("probe ddc_crt2 on MON1\r\n"); radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID); ddc_crt2_used = 1; } } if (rinfo->mon2_type != MT_NONE) { - dbg("%s: probe ddc_vga on MON2\r\n", __FUNCTION__); + dbg("probe ddc_vga on MON2\r\n"); if (!radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon2_EDID) && !ddc_crt2_used) { - dbg("%s: probe ddc_crt2 on MON2\r\n", __FUNCTION__); + dbg("probe ddc_crt2 on MON2\r\n"); radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon2_EDID); } } @@ -261,7 +257,7 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou else { rinfo->mon1_type = MT_CRT; - dbg("%s: No valid monitor, assuming CRT on first port\r\n", __FUNCTION__); + dbg("No valid monitor, assuming CRT on first port\r\n"); } rinfo->mon2_type = MT_NONE; rinfo->mon2_EDID = NULL; @@ -273,7 +269,7 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou * Auto-detecting display type (well... trying to ...) */ #ifdef CONFIG_FB_RADEON_I2C - dbg("%s: Auto-detecting\r\n", __FUNCTION__); + dbg("Auto-detecting\r\n"); #endif #if 0 //#if DEBUG && defined(CONFIG_FB_RADEON_I2C) { @@ -292,17 +288,17 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou #ifdef CONFIG_FB_RADEON_I2C if (rinfo->mon1_type == MT_NONE) { - dbg("%s: probe ddc_dvi on MON1\r\n", __FUNCTION__); + dbg("probe ddc_dvi on MON1\r\n"); rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID); } if (rinfo->mon1_type == MT_NONE) { - dbg("%s: probe ddc_vga on MON1\r\n", __FUNCTION__); + dbg("probe ddc_vga on MON1\r\n"); rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon1_EDID); } if (rinfo->mon1_type == MT_NONE) { - dbg("%s: probe ddc_crt2 on MON1\r\n", __FUNCTION__); + dbg("probe ddc_crt2 on MON1\r\n"); rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID); } #endif /* CONFIG_FB_RADEON_I2C */ @@ -316,12 +312,12 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou #ifdef CONFIG_FB_RADEON_I2C if (rinfo->mon1_type == MT_NONE) { - dbg("%s: probe ddc_dvi on MON1\r\n", __FUNCTION__); + dbg("probe ddc_dvi on MON1\r\n"); rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID); } if (rinfo->mon1_type == MT_NONE) { - dbg("%s: probe ddc_crt2 on MON1\r\n", __FUNCTION__); + dbg("probe ddc_crt2 on MON1\r\n"); rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID); if (rinfo->mon1_type != MT_NONE) ddc_crt2_used = 1; @@ -331,7 +327,7 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou && (INREG(LVDS_GEN_CNTL) & LVDS_ON)) { rinfo->mon1_type = MT_LCD; - dbg("%s: Non-DDC laptop panel detected\r\n", __FUNCTION__); + dbg("Non-DDC laptop panel detected\r\n"); } if (rinfo->mon1_type == MT_NONE) rinfo->mon1_type = radeon_crt_is_connected(rinfo, rinfo->reversed_DAC); @@ -341,12 +337,12 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou #ifdef CONFIG_FB_RADEON_I2C if (rinfo->mon2_type == MT_NONE) { - dbg("%s: probe ddc_vga on MON2\r\n", __FUNCTION__); + dbg("probe ddc_vga on MON2\r\n"); rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon2_EDID); } if (rinfo->mon2_type == MT_NONE && !ddc_crt2_used) { - dbg("%s: probe ddc_crt2 on MON2\r\n", __FUNCTION__); + dbg("probe ddc_crt2 on MON2\r\n"); rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon2_EDID); } #endif /* CONFIG_FB_RADEON_I2C */ @@ -399,18 +395,18 @@ void radeon_probe_screens(struct radeonfb_info *rinfo, const char *monitor_layou } bail: - dbg("%s: Monitor 1 type %s found\r\n", __FUNCTION__, radeon_get_mon_name(rinfo->mon1_type)); + dbg("Monitor 1 type %s found\r\n", radeon_get_mon_name(rinfo->mon1_type)); if (rinfo->mon1_EDID) { - dbg("%s: EDID probed\r\n", __FUNCTION__); + dbg("EDID probed\r\n"); } if (!rinfo->has_CRTC2) return; - dbg("%s: Monitor 2 type %s\r\n", __FUNCTION__, radeon_get_mon_name(rinfo->mon2_type)); + dbg("Monitor 2 type %s\r\n", radeon_get_mon_name(rinfo->mon2_type)); if (rinfo->mon2_EDID) { - dbg("%s: EDID probed\r\n", __FUNCTION__); + dbg("EDID probed\r\n"); } } @@ -470,7 +466,7 @@ void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolut struct fb_info *info = rinfo->info; int has_default_mode = 0; struct mode_option xres_yres; - dbg("%s: radeon_check_modes\r\n", __FUNCTION__); + dbg("\r\n"); /* * Fill default var first @@ -487,7 +483,7 @@ void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolut { struct fb_var_screeninfo var; - dbg("%s: fb_parse_edid\r\n", __FUNCTION__); + dbg("fb_parse_edid\r\n"); if (fb_parse_edid(rinfo->mon1_EDID, &var) == 0) { if ((var.xres >= rinfo->panel_info.xres) && (var.yres >= rinfo->panel_info.yres)) @@ -495,7 +491,7 @@ void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolut } else { - dbg("%s: no data to parse\r\n", __FUNCTION__); + dbg("no data to parse\r\n"); } } /* @@ -505,7 +501,8 @@ void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolut if (rinfo->mon1_type != MT_CRT && rinfo->panel_info.valid) { struct fb_var_screeninfo *var = &info->var; - dbg("%s: setup the default mode based on panel info\r\n", __FUNCTION__); + + dbg("setup the default mode based on panel info\r\n"); var->xres = rinfo->panel_info.xres; var->yres = rinfo->panel_info.yres; var->xres_virtual = rinfo->panel_info.xres; @@ -664,7 +661,7 @@ int radeon_match_mode(struct radeonfb_info *rinfo, int distance = INT_MAX; const struct fb_videomode *candidate = NULL; - dbg("%s:\r\n", __FUNCTION__); + dbg("\r\n"); /* Start with a copy of the requested mode */ memcpy(dest, src, sizeof(struct fb_var_screeninfo)); @@ -698,7 +695,7 @@ int radeon_match_mode(struct radeonfb_info *rinfo, } return 0; } - dbg("%s:look for a mode in the database\r\n", __FUNCTION__); + dbg("look for a mode in the database\r\n"); /* Now look for a mode in the database */ while(db) diff --git a/sys/sysinit.c b/sys/sysinit.c index a525f1a..47e70f4 100644 --- a/sys/sysinit.c +++ b/sys/sysinit.c @@ -53,7 +53,7 @@ #include "usb.h" #include "video.h" -#define DEBUG +// #define DEBUG #include "debug.h" #define UNUSED(x) (void)(x) /* Unused variable */ diff --git a/usb/usb.c b/usb/usb.c index fce1923..acb8834 100644 --- a/usb/usb.c +++ b/usb/usb.c @@ -54,7 +54,7 @@ #include "usb.h" #include "usb_hub.h" -#define DEBUG +// #define DEBUG #include "debug.h" struct hci diff --git a/usb/usb_hub.c b/usb/usb_hub.c index 03b774f..5c1cf25 100644 --- a/usb/usb_hub.c +++ b/usb/usb_hub.c @@ -12,14 +12,8 @@ #include "usb.h" #include "usb_hub.h" -#define DEBUG_HUB -#ifdef DEBUG_HUB -#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) -#else -#define dbg(format, arg...) do { ; } while (0) -#endif /* DEBUG_HUB */ -#define err(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) -#define info(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) +// #define DEBUG +#include "debug.h" static struct usb_hub_device hub_dev[USB_MAX_BUS][USB_MAX_HUB]; static int usb_hub_index[USB_MAX_BUS]; diff --git a/usb/usb_mouse.c b/usb/usb_mouse.c index d5f9e4b..5763255 100644 --- a/usb/usb_mouse.c +++ b/usb/usb_mouse.c @@ -26,13 +26,8 @@ #include "exceptions.h" #include "driver_mem.h" -#define DEBUG_USBMOUSE -#ifdef DEBUG_USBMOUSE -#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) -#else -#define dbg(format, arg...) do { ; } while (0) -#endif /* DEBUG_USBMOUSE */ -#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0) +// #define DEBUG +#include "debug.h" extern void ltoa(char *buf, long n, unsigned long base); extern void call_mousevec(unsigned char *data, void (**mousevec)(void *)); diff --git a/video/fbmodedb.c b/video/fbmodedb.c index 4b26fe5..66c2e1f 100644 --- a/video/fbmodedb.c +++ b/video/fbmodedb.c @@ -16,12 +16,8 @@ #include "bas_printf.h" #include "bas_string.h" -#define DBG_MODES -#ifdef DBG_MODES -#define dbg(format, arg...) do { xprintf("DEBUG: " format, __FUNCTION__, ##arg); } while (0) -#else -#define dbg(format, arg...) do { ; } while (0) -#endif /* DBG_MODES */ +// #define DEBUG +#include "debug.h" #define name_matches(v, s, l) \ ((v).name && !strncmp((s), (v).name, (l)) && strlen((v).name) == (l)) @@ -29,8 +25,8 @@ ((v).xres == (x) && (v).yres == (y)) /* - * Standard video mode definitions (taken from XFree86) - */ + * Standard video mode definitions (taken from XFree86) + */ #define DEFAULT_MODEDB_INDEX 0 diff --git a/video/video.c b/video/video.c index 3c0f712..419f2ca 100644 --- a/video/video.c +++ b/video/video.c @@ -286,12 +286,12 @@ int16_t ignore_edid; struct mode_option resolution = { - .used = 0, + .used = 1, .width = 640, .height = 480, .bpp = 8, .freq = 60, - .flags = 0 + .flags = MODE_VESA_FLAG }; int16_t force_measure_pll; diff --git a/x86emu/x86biosemu.c b/x86emu/x86biosemu.c index c79f364..985222a 100644 --- a/x86emu/x86biosemu.c +++ b/x86emu/x86biosemu.c @@ -10,7 +10,7 @@ #include "pci_ids.h" #include "x86pcibios.h" -#define DEBUG +// #define DEBUG #include "debug.h" #define USE_SDRAM diff --git a/x86emu/x86pcibios.c b/x86emu/x86pcibios.c index afa8110..624ac79 100644 --- a/x86emu/x86pcibios.c +++ b/x86emu/x86pcibios.c @@ -6,7 +6,7 @@ #include "bas_printf.h" extern unsigned short offset_port; -#define DEBUG +// #define DEBUG #include "debug.h" int x86_pcibios_handler(struct X86EMU *emu)