From c69f2487e3225f64decee85040d79b60a297c968 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 16 Oct 2012 06:13:48 +0000 Subject: [PATCH] bit checks to wait for FPGA ready were the wrong way round. Allowed the compiler to use m68k bitfield instructions (-mbitfield). Now produces nearly the same code than Fredi's assembler sources. --- Makefile | 2 +- sources/sysinit.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 237bd24..dc9007a 100644 --- a/Makefile +++ b/Makefile @@ -18,7 +18,7 @@ CC=$(TCPREFIX)gcc LD=$(TCPREFIX)ld INCLUDE=-Iinclude -CFLAGS=-mcpu=5474 -Wall -Wno-multichar -Os -fomit-frame-pointer +CFLAGS=-mcpu=5474 -mbitfield -Wall -Wno-multichar -Os -fomit-frame-pointer SRCDIR=sources OBJDIR=objs diff --git a/sources/sysinit.c b/sources/sysinit.c index caaeb2a..db5ccf5 100644 --- a/sources/sysinit.c +++ b/sources/sysinit.c @@ -219,7 +219,7 @@ void init_fpga(void) MCF_GPIO_PODR_FEC1L &= ~(1 << 1); /* FPGA clock => low */ MCF_GPIO_PODR_FEC1L &= ~(1 << 2); /* FPGA config => low */ - while ((! (MCF_GPIO_PPDSDR_FEC1L & (1 << 0))) && (! (MCF_GPIO_PPDSDR_FEC1L & (1 << 5)))); + while (((MCF_GPIO_PPDSDR_FEC1L & (1 << 0))) || ((MCF_GPIO_PPDSDR_FEC1L & (1 << 5)))); wait_10us(); MCF_GPIO_PODR_FEC1L |= (1 << 2);