From c5ba3c4174fcc1dfac40fc10b83e174c5b6e78f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 18 Oct 2015 19:33:25 +0000 Subject: [PATCH] formatting --- FPGA_quartus_ori/Video/BLITTER/BLITTER.vhd | 58 ++++++++++------------ 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/FPGA_quartus_ori/Video/BLITTER/BLITTER.vhd b/FPGA_quartus_ori/Video/BLITTER/BLITTER.vhd index 63cc93f..04aeb66 100644 --- a/FPGA_quartus_ori/Video/BLITTER/BLITTER.vhd +++ b/FPGA_quartus_ori/Video/BLITTER/BLITTER.vhd @@ -21,47 +21,43 @@ -- Created on Fri Oct 16 15:40:59 2009 LIBRARY ieee; -USE ieee.std_logic_1164.all; - - --- Entity Declaration + USE ieee.std_logic_1164.ALL; + USE ieee.numeric_std.ALL; ENTITY blitter IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( - nRSTO : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); - BLITTER_ON : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - DDRCLK0 : IN STD_LOGIC; - BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); - BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); - BLITTER_RUN : OUT STD_LOGIC; - BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); - BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); - BLITTER_SIG : OUT STD_LOGIC; - BLITTER_WR : OUT STD_LOGIC; - BLITTER_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) + nRSTO : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); + BLITTER_ON : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + DDRCLK0 : IN STD_LOGIC; + BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); + BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); + BLITTER_RUN : OUT STD_LOGIC; + BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); + BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); + BLITTER_SIG : OUT STD_LOGIC; + BLITTER_WR : OUT STD_LOGIC; + BLITTER_TA : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END BLITTER; --- Architecture Body - -ARCHITECTURE BLITTER_architecture OF blitter IS +ARCHITECTURE rtl OF blitter IS BEGIN @@ -72,4 +68,4 @@ BEGIN BLITTER_WR <= '0'; BLITTER_TA <= '0'; -END BLITTER_architecture; +END rtl;