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modified to make RAM version run again

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This commit is contained in:
Markus Fröschle
2013-08-05 19:36:40 +00:00
parent 085cab10e4
commit c48c04004e
1 changed files with 14 additions and 7 deletions
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21
BaS_gcc/sources/mmu.S
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@@ -157,8 +157,8 @@ _mmu_init:
move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
// 1fe0'0000 locked
move.l #0x1FE00000|std_mmutr,d0
move.l #0x1FE00000|copyback_mmudr|MCF_MMU_MMUDR_LK,d1
move.l #0x1E000000|std_mmutr,d0
move.l #0x1E000000|copyback_mmudr|MCF_MMU_MMUDR_LK,d1
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // setzen data
@@ -186,13 +186,19 @@ _mmu_init:
* MMU table add on miss
*/
_mmutr_miss:
lea -8 * 4(sp),sp
movem.l d0-d3/a0-a3,(sp)
move.l d0,-(sp)
pea MISS_text
jsr _xprintf
addq.l #8,sp
movem.l (sp),d0-d3/a0-a3
lea 8 * 4(sp),sp
bsr cpusha // clear caches
pea MISS_text
move.l d0,-(sp)
bsr _xprintf
and.l #0xFFF00000,d0 // d0 is the address not found (MMUAR at the time of the exception)
or.l #std_mmutr,d0 // mark shared and valid
move.l d0,MCF_MMU_MMUTR // add to TLB
@@ -206,7 +212,8 @@ _mmutr_miss:
move.l (sp)+,d0 // restore register saved in acess
rte
.data
MISS_text:
.asciz "MMU TLB MISS at %p"
.ascii "MMU TLB MISS at %p"
.byte 13, 10, 0