implemented initial version of XLB PCI interrupt handler. For now it
just reports and clears errors.
This commit is contained in:
@@ -321,12 +321,12 @@ void init_isr(void)
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}
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}
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MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */
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MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */
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MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
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MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
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MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */
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MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */
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MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */
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MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */
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MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */
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MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */
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MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */
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MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */
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MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */
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MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */
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if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 7, 1, pciarb_interrupt_handler, NULL, NULL))
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if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 7, 1, pciarb_interrupt_handler, NULL, NULL))
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{
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{
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@@ -263,8 +263,29 @@ bool pic_interrupt_handler(void *arg1, void *arg2)
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bool xlbpci_interrupt_handler(void *arg1, void *arg2)
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bool xlbpci_interrupt_handler(void *arg1, void *arg2)
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{
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{
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uint32_t reason;
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dbg("XLB PCI interrupt\r\n");
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dbg("XLB PCI interrupt\r\n");
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reason = MCF_PCI_PCIISR;
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if (reason & MCF_PCI_PCIISR_RE)
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{
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err("Retry error. Retry terminated or max retries reached. Cleared\r\n");
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MCF_PCI_PCIISR |= MCF_PCI_PCIISR_RE;
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}
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if (reason & MCF_PCI_PCIISR_IA)
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{
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err("Initiator abort. No target answered in time. Cleared.\r\n");
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MCF_PCI_PCIISR |= MCF_PCI_PCIISR_IA;
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}
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if (reason & MCF_PCI_PCIISR_TA)
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{
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err("Target abort. Cleared.\r\n");
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MCF_PCI_PCIISR |= MCF_PCI_PCIISR_TA;
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}
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return true;
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return true;
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}
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}
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