From bc1cd70d8edc213cd7b2e70dd5637a9a65c4a3ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 9 Nov 2013 18:09:01 +0000 Subject: [PATCH] hang on USB hc reset --- sources/ohci-hcd.c | 6 ++++-- sources/pci.c | 10 +++++----- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/sources/ohci-hcd.c b/sources/ohci-hcd.c index 0d63a5c..8619016 100644 --- a/sources/ohci-hcd.c +++ b/sources/ohci-hcd.c @@ -73,7 +73,7 @@ #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS #ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS #define readl(a) swpl(*((volatile uint32_t *)(a))) -#define writel(a, b) (*((volatile uint32_t *)(b)) = swpl((volatile uint32_t)a)) +#define writel(a, b) (*((volatile uint32_t *)(b)) = swpl((volatile uint32_t)(a))) #else #define readl(a) (*((volatile uint32_t *)(a))) #define writel(a, b) (*((volatile uint32_t *)(b)) = ((volatile uint32_t)a)) @@ -1643,7 +1643,6 @@ static int hc_reset(ohci_t *ohci) } xprintf("control: %x\r\n", readl(&ohci->regs->control)); - ohci_dump_status(ohci); if (readl(&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ @@ -1659,8 +1658,10 @@ static int hc_reset(ohci_t *ohci) } } } + /* Disable HC interrupts */ writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); + ohci_dump_status(ohci); dbg("USB OHCI HC reset_hc usb-%s-%c: ctrl = 0x%X", ohci->slot_name, (char)ohci->controller + '0', readl(&ohci->regs->control)); /* Reset USB (needed by some controllers) */ ohci->hc_control = 0; @@ -1673,6 +1674,7 @@ static int hc_reset(ohci_t *ohci) if (--timeout == 0) { err("USB HC reset timed out!"); + ohci_dump_status(ohci); return -1; } wait(10); diff --git a/sources/pci.c b/sources/pci.c index 99c067c..a60489a 100644 --- a/sources/pci.c +++ b/sources/pci.c @@ -362,10 +362,10 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function) /* fill resource descriptor */ rd->next = sizeof(struct pci_rd); - rd->flags = 0 | FLG_8BIT | FLG_16BIT | FLG_32BIT | ORD_MOTOROLA; + rd->flags = 0 | FLG_8BIT | FLG_16BIT | FLG_32BIT; rd->start = mem_address; rd->length = size; - rd->offset = PCI_MEMORY_OFFSET; + rd->offset = 0; /* PCI_MEMORY_OFFSET; */ rd->dmaoffset = 0; /* adjust memory adress for next turn */ @@ -389,9 +389,9 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function) rd->next = sizeof(struct pci_rd); rd->flags = FLG_IO | FLG_8BIT | FLG_16BIT | FLG_32BIT | 1; rd->start = io_address; - rd->offset = PCI_IO_OFFSET; + rd->offset = 0; /* PCI_IO_OFFSET; */ rd->length = size; - rd->dmaoffset = PCI_MEMORY_OFFSET; + rd->dmaoffset = 0; io_address += size; @@ -509,7 +509,7 @@ void init_pci(void) + MCF_PCIARB_PACR_EXTMINTEN(0x1F); /* Setup burst parameters */ - MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32); /* TODO: test increased latency timer */ + MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(16); /* TODO: test increased latency timer */ MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16); /* Turn on error signaling, 32 write retries on failure */