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repaired jtagwait magic type conflict

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added "native PCI" driver interface
This commit is contained in:
Markus Fröschle
2015-04-03 14:28:41 +00:00
parent b42a1aea32
commit b1d1dd5cdd
11 changed files with 102 additions and 106 deletions
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1
BaS_gcc/BaS_gcc.files
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@@ -216,3 +216,4 @@ video/offscreen.c
video/vdi_fill.c
video/videl.c
video/video.c
tos/jtagwait/Makefile

2
BaS_gcc/flash_scripts/flash_m548x_bas.bdm
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@@ -54,7 +54,7 @@ sleep 10
#flash-plugin 0x1000 0xf000 flash29.plugin
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
flash 0xE0000000
flash-plugin 0x1000 0xf000 flashintelc3.plugin
#flash-plugin 0x1000 0xf000 flashintelc3.plugin
# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for bas)
#

53
BaS_gcc/flash_scripts/flash_m548x_dbug.bdm
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@@ -10,20 +10,20 @@ wait
write-ctrl 0x0801 0x00000000
dump-register VBR
# Turn on MBAR at 0xFF00_0000
write-ctrl 0x0C0F 0xFF000000
# Turn on MBAR at 0x1000_0000
write-ctrl 0x0C0F 0x10000000
dump-register MBAR
# Turn on RAMBAR0 at address FF10_0000
write-ctrl 0x0C04 0xFF100007
# Turn on RAMBAR0 at address 2000_0000
write-ctrl 0x0C04 0x20000007
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
write-ctrl 0x0C05 0xFF101001
write-ctrl 0x0C05 0x20001001
#
# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 4Mbytes)
write 0xFF000500 0xE0000000 4
write 0xFF000508 0x00041180 4
# Init CS0 (BootFLASH @ FF80_0000 - FFBF_FFFF 4Mbytes)
write 0xFF000500 0xFF800000 4
write 0xFF000508 0x00100D80 4
write 0xFF000504 0x003F0001 4
# SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 Mbytes
@@ -52,27 +52,26 @@ sleep 10
# This seems to be related to large flash buffers and PC-relative adressing of the plugin
#flash-plugin 0x1000 0xf000 flash29.plugin
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
flash 0xE0000000
flash-plugin 0x1000 0xf000 flashintelc3.plugin
flash 0xFF800000
#flash-plugin 0x1000 0xf000 flashintelc3.plugin
# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for bas)
#
# Caution: sector offset numbers need to be the ones from the x16 address range
# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
# Erase flash from 0xFF800000 to 0xFFBFFFFF (reserved space for bas)
#
# contrary to documentation, it seems we need to erase-wait after each sector
#erase 0xE0000000 0x0
#erase 0xE0002000 0x0
#erase 0xE0000000 0x00004000
#erase 0xE0000000 0x00005000
#erase 0xE0000000 0x00006000
#erase 0xE0000000 0x00007000
#erase 0xE0000000 0x00008000
#erase 0xE0000000 0x00009000
#erase 0xE0000000 0x0000a000
#erase 0xE0000000 0x0000b000
#erase-wait 0xe0000000
#blank-chk 0xE0000000 0x0
load -v m5484lite_dbug_flash.elf
erase 0xFF800000 0
erase 0xFF800000 1
erase 0xFF800000 2
erase 0xFF800000 3
erase 0xFF800000 4
erase 0xFF800000 5
erase 0xFF800000 6
erase 0xFF800000 7
erase 0xFF800000 8
erase 0xFF800000 9
erase 0xFF800000 10
erase 0xFF800000 11
erase 0xFF800000 12
erase 0xFF800000 13
load -v m548xlite_dbug_flash.elf
wait

2
BaS_gcc/if/driver_vec.c
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@@ -127,7 +127,7 @@ static struct pci_bios_interface pci_interface =
static struct pci_native_driver_interface pci_native_interface =
{
.pci_read_config_longword = pci_read_config_longword,
.pci_read_config_word = pci_read_config_longword,
.pci_read_config_word = pci_read_config_word,
.pci_read_config_byte = pci_read_config_byte,
.pci_write_config_longword = pci_write_config_longword,
.pci_write_config_word = pci_write_config_word,

2
BaS_gcc/include/driver_vec.h
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@@ -283,7 +283,7 @@ struct pci_native_driver_interface
int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter);
int32_t (*pci_unhook_interrupt)(int32_t handle);
struct pci_rd (*pci_get_resource)(int32_t handle);
struct pci_rd * (*pci_get_resource)(int32_t handle);
};
union interface

10
BaS_gcc/include/pci.h
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@@ -24,10 +24,10 @@
#include <bas_types.h>
#include "util.h" /* for swpX() */
#define PCI_MEMORY_OFFSET (0x80000000)
#define PCI_MEMORY_SIZE (0x40000000) /* 1 GByte PCI memory window */
#define PCI_IO_OFFSET (0xD0000000)
#define PCI_IO_SIZE (0x10000000) /* 128 MByte PCI I/O window */
#define PCI_MEMORY_OFFSET 0x80000000
#define PCI_MEMORY_SIZE 0x40000000 /* 1 GByte PCI memory window */
#define PCI_IO_OFFSET 0xD0000000
#define PCI_IO_SIZE 0x10000000 /* 128 MByte PCI I/O window */
/*
* Note: the byte offsets are in little endian format, so you can't use them
@@ -134,7 +134,7 @@ struct pci_rd /* structure of resource descriptor */
unsigned long length; /* length of resource */
unsigned long offset; /* offset PCI to phys. CPU Address */
unsigned long dmaoffset; /* offset for DMA-transfers */
} __attribute__ ((packed));
};
typedef struct /* structure of address conversion */
{

2
BaS_gcc/pci/pci.c
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@@ -33,7 +33,7 @@
#include "interrupts.h"
#include "wait.h"
#define DEBUG_PCI
//#define DEBUG_PCI
#ifdef DEBUG_PCI
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else

10
BaS_gcc/sys/init_fpga.c
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@@ -50,8 +50,8 @@ extern uint8_t _FPGA_CONFIG_SIZE[];
* been loaded through the onboard JTAG interface.
* init_fpga() will honour this and not overwrite config.
*/
extern bool _FPGA_JTAG_LOADED;
extern int32_t _FPGA_JTAG_VALID;
extern uint32_t _FPGA_JTAG_LOADED;
extern uint32_t _FPGA_JTAG_VALID;
#define VALID_JTAG 0xaffeaffe
void config_gpio_for_fpga_config(void)
@@ -94,10 +94,10 @@ bool init_fpga(void)
volatile int32_t time, start, end;
int i;
dbg("FPGA load config\r\n(_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
if (_FPGA_JTAG_LOADED == true && _FPGA_JTAG_VALID == VALID_JTAG)
xprintf("FPGA load config...\r\n");
if (_FPGA_JTAG_LOADED == 1 && _FPGA_JTAG_VALID == VALID_JTAG)
{
dbg("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
xprintf("detected _FPGA_JTAG_LOADED flag. FPGA config skipped.\r\n");
/* reset the flag so that next boot will load config again from flash */
_FPGA_JTAG_LOADED = 0;

6
BaS_gcc/sys/sysinit.c
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@@ -939,8 +939,6 @@ void clear_bss_segment(void)
void initialize_hardware(void)
{
bool coldboot = true;
/* Test for FireTOS switch: DIP switch #5 up */
#ifdef MACHINE_FIREBEE
if (!(DIP_SWITCH & (1 << 6))) {
@@ -1056,7 +1054,7 @@ void initialize_hardware(void)
init_slt();
init_fbcs();
coldboot = init_ddram();
init_ddram();
#if defined(MACHINE_M5484LITE)
xprintf("Fire Engine Control register: %02x\r\n", * (uint8_t *) 0x61000000);
@@ -1117,8 +1115,6 @@ void initialize_hardware(void)
}
#if MACHINE_FIREBEE
if (coldboot) /* does not work with BDM */
;
fpga_configured = init_fpga();
init_pll();

8
BaS_gcc/tos/jtagwait/sources/jtagwait.c
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@@ -7,8 +7,8 @@
#include "MCF5475.h"
#include "driver_vec.h"
extern long _FPGA_JTAG_LOADED;
extern long _FPGA_JTAG_VALID;
extern uint32_t _FPGA_JTAG_LOADED;
extern uint32_t _FPGA_JTAG_VALID;
#define VALID_JTAG 0xaffeaffe
@@ -22,7 +22,6 @@ extern long _FPGA_JTAG_VALID;
#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
long bas_start = 0xe0000000;
volatile uint32_t *_VRAM = (uint32_t *) 0x60000000;
void wait_for_jtag(void)
@@ -75,6 +74,7 @@ void wait_for_jtag(void)
/* wait */
xprintf("wait a little to let things settle...\r\n");
for (i = 0; i < 100000; i++);
xprintf("reset and restart...");
__asm__ __volatile__(
" jmp (%[bas_start])\n\t"
@@ -87,7 +87,7 @@ void wait_for_jtag(void)
int main(int argc, char *argv[])
{
printf("\033E\r\nFPGA JTAG configuration support\r\n");
printf("<C> 2014 M. Froeschle\r\n");
printf("\a9 2014 M. Fr\f6schle\r\n");
printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
"and your Firebee will reboot once finished using that new configuration.\r\n");

2
BaS_gcc/video/video.c
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@@ -315,7 +315,7 @@ void video_init(void)
dbg("\r\n");
/* FIXME: we currently just return here because the PCI configuration of ATI cards does not (yet) work */
return;
//return;
do
{