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temporary disabled PCI interrupts

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This commit is contained in:
Markus Fröschle
2015-10-03 08:31:58 +00:00
parent dad6a94b5e
commit b13413e60e
13 changed files with 835 additions and 746 deletions
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1
BaS_gcc.config
View File

@@ -1 +1,2 @@
// ADD PREDEFINED MACROS HERE!
#define MACHINE_FIREBEE

19
Makefile
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@@ -37,25 +37,19 @@ endif
INCLUDE=-Iinclude
CFLAGS=-mcpu=5474 \
-g \
-Wall \
-fomit-frame-pointer \
-ffreestanding \
-fleading-underscore \
-mno-strict-align \
-Wa,--register-prefix-optional
CFLAGS_OPTIMIZED = -mcpu=5474 \
-Wall \
-O2 \
-ffixed-a3 \
-ffixed-a4 \
-ffixed-a5 \
-g \
-fomit-frame-pointer \
-ffreestanding \
-fleading-underscore \
-Wa,--register-prefix-optional
LDFLAGS=-g
LDFLAGS=
TRGTDIRS= ./firebee ./m5484lite ./m54455
OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
@@ -212,17 +206,6 @@ define CC_TEMPLATE
#MACHINE=MACHINE_M5484LITE
#endif
# always optimize x86 emulator objects
#$(1)/objs/x86decode.o: CFLAGS=$(CFLAGS_OPTIMIZED)
#$(1)/objs/x86sys.o: CFLAGS=$(CFLAGS_OPTIMIZED)
#$(1)/objs/x86debug.o: CFLAGS=$(CFLAGS_OPTIMIZED)
#$(1)/objs/x86prim_ops.o:CFLAGS=$(CFLAGS_OPTIMIZED)
#$(1)/objs/x86ops.o: CFLAGS=$(CFLAGS_OPTIMIZED)
#$(1)/objs/x86ops2.o: CFLAGS=$(CFLAGS_OPTIMIZED)
#$(1)/objs/x86fpu.o: CFLAGS=$(CFLAGS_OPTIMIZED)
$(1)/objs/x86biosemu.o: CFLAGS=$(CFLAGS_OPTIMIZED)
#$(1)/objs/x86pcibios.o: CFLAGS=$(CFLAGS_OPTIMIZED)
$(1)/objs/%.o:%.c
$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@

2
dma/dma.c
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@@ -646,8 +646,8 @@ void *dma_memcpy(void *dst, void *src, size_t n)
#ifdef DBG_DMA
end = MCF_SLT0_SCNT;
time = (start - end) / (SYSCLK / 1000) / 1000;
#endif /* DBG_DMA */
dbg("took %d ms (%f Mbytes/second)\r\n", time, n / (float) time / 1000.0);
#endif /* DBG_DMA */
return dst;
}

20
pci/pci.c
View File

@@ -132,7 +132,7 @@ static inline __attribute__((aligned(16))) void chip_errata_135(void)
" tpf.l #0x0 \n\t"
" tpf.l #0x0 \n\t"
" tpf.l #0x0 \n\t"
::: "memory");
::: "d0", "memory");
}
static inline void chip_errata_055(int32_t handle)
@@ -242,7 +242,7 @@ static char *device_class(int classcode)
return pci_classes[i].description;
}
}
return "not found";
return "unknown device class";
}
/*
@@ -298,11 +298,6 @@ static int pci_check_status(void)
ret = 1;
}
if (!ret)
{
dbg("no error\r\n");
}
return ret;
}
@@ -331,7 +326,7 @@ uint32_t pci_read_config_longword(int32_t handle, int offset)
/* finish PCI configuration access special cycle (allow regular PCI accesses) */
MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
//pci_check_status();
pci_check_status();
return value;
}
@@ -544,7 +539,7 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
if (value != 0xffffffff) /* device found */
{
if (vendor_id == 0xffff ||
(PCI_VENDOR_ID(value) == vendor_id && PCI_DEVICE_ID(value) == device_id))
((PCI_VENDOR_ID(value) == vendor_id) && (PCI_DEVICE_ID(value) == device_id)))
{
if (n == index)
{
@@ -648,7 +643,7 @@ int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter)
{
int i;
pci_interrupt_handler h = handler;
// pci_interrupt_handler h = handler;
/*
* find empty slot
@@ -1072,6 +1067,7 @@ void pci_scan(void)
uint32_t value;
value = pci_read_config_longword(handle, PCIIDR);
xprintf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x)\r\n",
PCI_BUS_FROM_HANDLE(handle),
PCI_DEVICE_FROM_HANDLE(handle),
@@ -1083,6 +1079,7 @@ void pci_scan(void)
/* save handle to index value so that we'll be able to later find our resources */
handles[index] = handle;
if (PCI_VENDOR_ID(value) != 0x1057 && PCI_DEVICE_ID(value) != 0x5806) /* do not configure bridge */
{
/* configure memory and I/O for card */
@@ -1116,6 +1113,7 @@ void init_eport(void)
MCF_EPORT_EPPAR_EPPA3(MCF_EPORT_EPPAR_FALLING) |
MCF_EPORT_EPPAR_EPPA2(MCF_EPORT_EPPAR_FALLING) |
MCF_EPORT_EPPAR_EPPA1(MCF_EPORT_EPPAR_FALLING);
MCF_EPORT_EPDDR = 0; /* clear data direction register. All pins as input */
MCF_EPORT_EPFR = -1; /* clear all EPORT interrupt flags */
MCF_EPORT_EPIER = 0xfe; /* enable all EPORT interrupts (for now) */
@@ -1172,7 +1170,7 @@ void init_pci(void)
init_eport();
init_xlbus_arbiter();
MCF_PCI_PCIGSCR = 1; /* reset PCI */
MCF_PCI_PCIGSCR = -1;
/*
* setup the PCI arbiter

13
sys/BaS.c
View File

@@ -242,11 +242,12 @@ void enable_coldfire_interrupts()
FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */
FBEE_INTR_INT_MFP_IRQ6 | /* enable MFP interrupts */
FBEE_INTR_INT_FPGA_IRQ5 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
FBEE_INTR_INT_VSYNC_IRQ4 | /* enable vsync interrupts */
FBEE_INTR_PCI_INTA | /* enable PCI interrupts */
FBEE_INTR_PCI_INTB |
FBEE_INTR_PCI_INTC |
FBEE_INTR_PCI_INTD;
FBEE_INTR_INT_VSYNC_IRQ4 //| /* enable vsync interrupts */
//FBEE_INTR_PCI_INTA | /* enable PCI interrupts */
//FBEE_INTR_PCI_INTB |
//FBEE_INTR_PCI_INTC |
//FBEE_INTR_PCI_INTD;
;
#endif
xprintf("finished\r\n");
@@ -345,7 +346,7 @@ void init_isr(void)
MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */
MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */
if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 7, 1, pciarb_interrupt_handler, NULL, NULL))
if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 5, 1, pciarb_interrupt_handler, NULL, NULL))
{
dbg("Error: unable to register isr for PCIARB interrupts\r\n");

2
sys/driver_mem.c
View File

@@ -27,7 +27,7 @@
#error "unknown machine!"
#endif
//#define DBG_DM
#define DBG_DM
#ifdef DBG_DM
#define dbg(fmt, args...) xprintf(fmt, ##args)
#else

6
sys/startcf.S
View File

@@ -6,8 +6,8 @@
.equ MCF_MMU_MMUCR, __MMUBAR + 0
.global _rom_header
.global _rom_entry
.globl _rom_header
.globl _rom_entry
.extern _initialize_hardware
.extern _rt_mbar
@@ -26,7 +26,7 @@ _rom_header:
/* ROM entry point */
_rom_entry:
/* disable interrupts */
move.w #0x2700,SR
move.w #0x2700,sr
/* Initialize MBAR */
move.l #__MBAR,d0

67
sys/sysinit.c
View File

@@ -46,8 +46,6 @@
#else
#error "unknown machine"
#endif /* MACHINE_M5484LITE */
#
#include "dma.h"
#include "mod_devicetable.h"
#include "pci_ids.h"
@@ -70,7 +68,7 @@ extern volatile long _VRAM; /* start address of video ram from linker script */
* BYT3 = 7.576ns/tick = 132.00MHz offset 3
* count down!!! 132MHz!!!
*/
void init_slt(void)
static void init_slt(void)
{
xprintf("slice timer initialization: ");
MCF_SLT0_STCNT = 0xffffffff;
@@ -81,7 +79,7 @@ void init_slt(void)
/*
* init GPIO general purpose I/O module
*/
void init_gpio(void)
static void init_gpio(void)
{
/*
* pad register P.S.:FBCTL and FBCS set correctly at reset
@@ -214,7 +212,7 @@ void init_gpio(void)
/*
* init serial
*/
void init_serial(void)
static void init_serial(void)
{
/* PSC0: SER1 */
MCF_PSC0_PSCSICR = 0; /* PSC control register: select UART mode */
@@ -276,7 +274,7 @@ void init_serial(void)
/********************************************************************/
/* Initialize DDR DIMMs on the EVB board */
/********************************************************************/
bool init_ddram(void)
static bool init_ddram(void)
{
xprintf("SDRAM controller initialization: ");
@@ -401,43 +399,46 @@ bool init_ddram(void)
/*
* initialize FlexBus chip select registers
*/
void init_fbcs()
static void init_fbcs()
{
xprintf("FlexBus chip select registers initialization: ");
/* Flash */
MCF_FBCS0_CSAR = MCF_FBCS_CSAR_BA(BOOTFLASH_BASE_ADDRESS); /* flash base address */
MCF_FBCS0_CSCR = MCF_FBCS_CSCR_PS_16 | /* 16 bit word access */
MCF_FBCS_CSCR_WS(6)| /* 6 Waitstates */
MCF_FBCS_CSCR_AA |
MCF_FBCS_CSCR_ASET(1) |
MCF_FBCS_CSCR_WS(8)| /* 6 wait states */
MCF_FBCS_CSCR_AA | /* auto /TA acknowledge */
MCF_FBCS_CSCR_ASET(1) | /* assert chip select on second rising edge after address assertion */
MCF_FBCS_CSCR_RDAH(1); /* chip errata SECF077 */
MCF_FBCS0_CSMR = BOOTFLASH_BAM |
MCF_FBCS_CSMR_V; /* enable */
#if defined(MACHINE_FIREBEE) /* FBC setup for FireBee */
MCF_FBCS1_CSAR = MCF_FBCS_CSAR_BA(0xFFF00000); /* ATARI I/O ADRESS */
MCF_FBCS1_CSAR = MCF_FBCS_CSAR_BA(0xFFF00000); /* ATARI I/O address range */
MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */
| MCF_FBCS_CSCR_WS(8) /* DEFAULT 8WS */
| MCF_FBCS_CSCR_AA; /* AA */
| MCF_FBCS_CSCR_WS(32) /* 8 wait states */
| MCF_FBCS_CSCR_AA; /* auto /TA acknowledge */
MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V;
MCF_FBCS2_CSAR = MCF_FBCS_CSAR_BA(0xF0000000); /* Firebee new I/O address range */
MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 /* 32BIT PORT */
| MCF_FBCS_CSCR_WS(4) /* DEFAULT 4WS */
| MCF_FBCS_CSCR_AA; /* AA */
| MCF_FBCS_CSCR_WS(32) /* 4 wait states */
| MCF_FBCS_CSCR_AA; /* auto /TA acknowledge */
MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M /* F000'0000-F7FF'FFFF */
| MCF_FBCS_CSMR_V);
MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xF8000000); /* Firebee new I/O address range */
MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 /* 16 bit port */
| MCF_FBCS_CSCR_WS(32) /* 0 wait states */
| MCF_FBCS_CSCR_AA; /* auto /TA acknowledge */
MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M /* F800'0000-FBFF'FFFF */
| MCF_FBCS_CSMR_V);
MCF_FBCS4_CSAR = MCF_FBCS_CSAR_BA(0x40000000); /* video ram area, FB_CS3 not used, decoded on FPGA */
MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 /* 32BIT PORT */
MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 /* 32 bit port */
| MCF_FBCS_CSCR_WS(32) /* 0 wait states */
| MCF_FBCS_CSCR_AA /* /TA auto acknowledge */
| MCF_FBCS_CSCR_BSTR /* burst read enable */
| MCF_FBCS_CSCR_BSTW; /* burst write enable */
MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G /* 4000'0000-7FFF'FFFF */
@@ -470,7 +471,8 @@ void init_fbcs()
xprintf("finished\r\n");
}
void wait_pll(void)
#ifdef MACHINE_FIREBEE
static void wait_pll(void)
{
int32_t trgt = MCF_SLT0_SCNT - 100000;
do
@@ -481,7 +483,7 @@ void wait_pll(void)
static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
void init_pll(void)
static void init_pll(void)
{
xprintf("FPGA PLL initialization: ");
@@ -528,13 +530,10 @@ void init_pll(void)
xprintf("finished\r\n");
}
/*
* INIT VIDEO DDR RAM
*/
void init_video_ddr(void) {
static void init_video_ddr(void) {
xprintf("init video RAM: ");
* (volatile uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */
@@ -563,10 +562,11 @@ void init_video_ddr(void) {
NOP();
* (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */
// * (uint32_t *) 0xf0000400 = 0x0107820b; /* fifo on, refresh on, ddrcs und cke on, video dac on */
xprintf("finished\r\n");
}
#endif /* MACHINE_FIREBEE */
/*
* probe for NEC compatible USB host controller and install if found
@@ -635,6 +635,8 @@ void init_usb(void)
xprintf("finished (found %d USB controller(s))\r\n", usb_found);
}
#ifdef MACHINE_FIREBEE
static bool i2c_transfer_finished(void)
{
if (MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)
@@ -657,7 +659,7 @@ static bool i2c_bus_free(void)
/*
* TFP410 (DVI) on
*/
void dvi_on(void)
static void dvi_on(void)
{
uint8_t receivedByte;
uint8_t dummyByte; /* only used for a dummy read */
@@ -806,7 +808,7 @@ try_again:
/*
* AC97
*/
void init_ac97(void)
static void init_ac97(void)
{
// PSC2: AC97 ----------
int i;
@@ -900,6 +902,7 @@ livo:
MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data
xprintf(" finished\r\n");
}
#endif /* MACHINE_FIREBEE */
/* Symbols from the linker script */
@@ -927,14 +930,14 @@ extern uint8_t _BAS_RESIDENT_TEXT[];
extern uint8_t _BAS_RESIDENT_TEXT_SIZE[];
#define BAS_RESIDENT_TEXT_SIZE ((uint32_t) _BAS_RESIDENT_TEXT_SIZE)
void clear_bss_segment(void)
static void clear_bss_segment(void)
{
extern uint8_t _BAS_BSS_START[];
uint8_t * BAS_BSS_START = &_BAS_BSS_START[0];
extern uint8_t _BAS_BSS_END[];
uint8_t *BAS_BSS_END = &_BAS_BSS_END[0];
bzero(BAS_BSS_START, BAS_BSS_END - BAS_BSS_START - 1);
bzero(BAS_BSS_START, BAS_BSS_END - BAS_BSS_START + 1);
}
void initialize_hardware(void)
@@ -1120,13 +1123,9 @@ void initialize_hardware(void)
init_pll();
init_video_ddr();
dvi_on();
#endif /* MACHINE_FIREBEE */
driver_mem_init();
#if MACHINE_FIREBEE
init_ac97();
#endif /* MACHINE_FIREBEE */
driver_mem_init();
/* jump into the BaS */
extern void BaS(void);

6
tos/jtagwait/sources/bas_printf.c
View File

@@ -104,7 +104,8 @@ static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap)
f++; /* skip the % */
if (*f == '-')
{ /* minus: flush left */
{
/* minus: flush left */
flush_left = 1;
f++;
}
@@ -118,6 +119,7 @@ static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap)
if (*f == '*')
{
/* field width */
f_width = va_arg(ap, int);
f++;
}
@@ -377,6 +379,7 @@ int sprintf(char *str, const char *format, ...)
void xsnprintf(char *str, size_t size, const char *fmt, ...)
{
va_list va;
va_start(va, fmt);
xstring = str;
@@ -389,6 +392,7 @@ void xsnprintf(char *str, size_t size, const char *fmt, ...)
void xprintf(const char *fmt, ...)
{
va_list va;
va_start(va, fmt);
doprnt(xputchar, fmt, va);
va_end(va);

8
tos/vmem_test/sources/printf_helper.S
View File

@@ -20,13 +20,15 @@
*
* Copyright 2010 - 2012 F. Aschwanden
* Copyright 2011 - 2012 V. Riviere
* Copyright 2012 M. Froeschle
* Copyright 2012 - 2025 M. Froeschle
*/
.global printf_helper
.globl printf_helper
printf_helper:
.extern __MBAR
.wait_txready:
move.w __MBAR+0x8604,d2 // PSCSCR0 status register
btst #10,d2 // space left in TX fifo?
@@ -34,5 +36,3 @@ printf_helper:
lea __MBAR+0x860C,a0 // PSCSTB0 transmitter buffer register
move.b d0,(a0) // send byte
rts
// vim: set syntax=asm68k :

101
tos/vmem_test/sources/vmem_test.c
View File

@@ -24,6 +24,100 @@ extern volatile uint32_t _VRAM[];
volatile int32_t time, start, end;
int i;
static void wait_pll(void)
{
int32_t trgt = MCF_SLT0_SCNT - 100000;
do
{
;
} while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt);
}
static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
static void init_pll(void)
{
xprintf("FPGA PLL initialization: ");
wait_pll();
* (volatile uint16_t *) (pll_base + 0x48) = 27; /* loopfilter r */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */
wait_pll();
* (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */
wait_pll();
* (volatile uint8_t *) 0xf0000800 = 0; /* set */
xprintf("finished\r\n");
}
/*
* INIT VIDEO DDR RAM
*/
static void init_video_ddr(void) {
xprintf("init video RAM: ");
* (volatile uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */
NOP();
_VRAM[0] = 0x00050400; /* IPALL */
NOP();
_VRAM[0] = 0x00072000; /* load EMR pll on */
NOP();
_VRAM[0] = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */
NOP();
_VRAM[0] = 0x00050400; /* IPALL */
NOP();
_VRAM[0] = 0x00060000; /* auto refresh */
NOP();
_VRAM[0] = 0x00060000; /* auto refresh */
NOP();
/* FIXME: what's this? */
_VRAM[0] = 0000070022; /* load MR dll on */
NOP();
* (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */
xprintf("finished\r\n");
}
void do_tests(void)
{
uint32_t version;
@@ -121,6 +215,13 @@ void wait_for_jtag(void)
: /* no output */
: /* no input */
: "d0", "memory");
xprintf("init FPGA PLLs\r\n");
init_pll();
xprintf("init video DDR RAM\r\n");
init_video_ddr();
/* begin of tests */
do_tests();

2
util/bas_string.c
View File

@@ -58,7 +58,7 @@ void *memset(void *s, int c, size_t n)
int memcmp(const void *s1, const void *s2, size_t max)
{
int i;
int cmp;
int cmp = 0;
for (i = 0; i < max; i++)
{

6
video/video.c
View File

@@ -243,13 +243,15 @@ void videl_screen_init(void)
/* first set the physbase to a safe memory */
setphys(0xd00000, 0);
if (!lookup_videl_mode(boot_resolution, monitor_type)) { /* mode isn't in table */
if (!lookup_videl_mode(boot_resolution, monitor_type)) /* mode isn't in table */
{
xprintf("Invalid video mode 0x%04x changed to 0x%04x\r\n",
boot_resolution, FALCON_DEFAULT_BOOT);
boot_resolution = FALCON_DEFAULT_BOOT; /* so pick one that is */
}
if (!VALID_VDI_BPP(boot_resolution)) { /* mustn't confuse VDI */
if (!VALID_VDI_BPP(boot_resolution)) /* mustn't confuse VDI */
{
xprintf("VDI doesn't support video mode 0x%04x, changed to 0x%04x\r\n",
boot_resolution, FALCON_DEFAULT_BOOT);
boot_resolution = FALCON_DEFAULT_BOOT; /* so use default */