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FPGA pins (clock, config) were the wrong way round for FPGA programming in init_fpga. Corrected.

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This commit is contained in:
Markus Fröschle
2012-10-16 05:53:53 +00:00
parent 1796318f0d
commit b06765d595
1 changed files with 5 additions and 5 deletions
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10
BaS_GNU/BaS_GNU/sources/sysinit.c
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@@ -216,8 +216,8 @@ void init_fpga(void)
uart_out_word('FPGA'); uart_out_word('FPGA');
MCF_GPIO_PODR_FEC1L |= (1 << 1); MCF_GPIO_PODR_FEC1L &= ~(1 << 1); /* FPGA clock => low */
MCF_GPIO_PODR_FEC1L |= (1 << 2); MCF_GPIO_PODR_FEC1L &= ~(1 << 2); /* FPGA config => low */
while ((! (MCF_GPIO_PPDSDR_FEC1L & (1 << 0))) && (! (MCF_GPIO_PPDSDR_FEC1L & (1 << 5)))); while ((! (MCF_GPIO_PPDSDR_FEC1L & (1 << 0))) && (! (MCF_GPIO_PPDSDR_FEC1L & (1 << 5))));
@@ -283,10 +283,10 @@ void init_fpga(void)
} }
else else
{ {
MCF_PSC0_PSCTB_8BIT = ' NOT'; uart_out_word(' NOT');
} }
MCF_PSC0_PSCTB_8BIT = 'OK! '; uart_out_word(' OK!');
MCF_PSC0_PSCTB_8BIT = 0x0d0a; uart_out_word(0x0d0a);
} }
void wait_pll(void) void wait_pll(void)