Reverse merge from trunk in pci_BaS_gcc branch
This commit is contained in:
124
sys/sysinit.c
124
sys/sysinit.c
@@ -2,7 +2,7 @@
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* File: sysinit.c
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* Purpose: Power-on Reset configuration of the Firebee board.
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*
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* Notes:
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* Notes:
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*
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* This file is part of BaS_gcc.
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*
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@@ -37,17 +37,14 @@
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#include "wait.h"
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#include "util.h"
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#include "version.h"
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#if defined(MACHINE_FIREBEE)
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#ifdef MACHINE_FIREBEE
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#include "firebee.h"
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#elif defined(MACHINE_M5484LITE)
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#endif /* MACHINE_FIREBEE */
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#ifdef MACHINE_M5484LITE
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#include "m5484l.h"
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#elif defined(MACHINE_M54455)
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#include "m54455.h"
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#else
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#error "unknown machine"
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#endif /* MACHINE_M5484LITE */
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#
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#include "dma.h"
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#include "mod_devicetable.h"
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#include "pci_ids.h"
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@@ -55,14 +52,12 @@
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#include "usb.h"
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#include "video.h"
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#define UNUSED(x) (void)(x) /* Unused variable */
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bool fpga_configured = false; /* for FPGA JTAG configuration */
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#define UNUSED(x) (void)(x) /* Unused variable */
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extern volatile long _VRAM; /* start address of video ram from linker script */
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/*
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* init SLICE TIMER 0
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* init SLICE TIMER 0
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* all = 32.538 sec = 30.736mHz
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* BYT0 = 127.1ms/tick = 7.876Hz offset 0
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* BYT1 = 496.5us/tick = 2.014kHz offset 1
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@@ -91,16 +86,16 @@ void init_gpio(void)
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* configure all four 547x GPIO module DMA pins:
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*
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* /DACK1 - DMA acknowledge 1
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* /DACK0 - DMA acknowledge 0
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* /DREQ1 - DMA request 1
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* /DREQ0 - DMA request 0
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*
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* /DACK0 - DMA acknowledge 0
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* /DREQ1 - DMA request 1
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* /DREQ0 - DMA request 0
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*
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* for DMA operation
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*/
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MCF_PAD_PAR_DMA = MCF_PAD_PAR_DMA_PAR_DACK0(0x3) |
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MCF_PAD_PAR_DMA_PAR_DACK1(0x3) |
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MCF_PAD_PAR_DMA_PAR_DREQ1(0x3) |
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MCF_PAD_PAR_DMA_PAR_DREQ0(0x3);
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MCF_PAD_PAR_DMA = MCF_PAD_PAR_DMA_PAR_DACK0(0b11) |
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MCF_PAD_PAR_DMA_PAR_DACK1(0b11) |
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MCF_PAD_PAR_DMA_PAR_DREQ1(0b11) |
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MCF_PAD_PAR_DMA_PAR_DREQ0(0b11);
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/*
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* configure FEC0 pin assignment on GPIO module as FEC0
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@@ -209,6 +204,20 @@ void init_gpio(void)
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MCF_PAD_PAR_TIMER_PAR_TOUT3 |
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MCF_PAD_PAR_TIMER_PAR_TIN2(MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2) |
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MCF_PAD_PAR_TIMER_PAR_TOUT2;
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#if defined(MACHINE_FIREBEE)
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/*
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* Configure GPIO FEC1L port directions (needed to load FPGA configuration)
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*/
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MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */
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0 | /* bit 6 = input */
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0 | /* bit 5 = input */
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MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */
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MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */
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MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 | /* bit 2 = FPGA_CONFIG => output */
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MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 | /* bit 1 = PRG_CLK (FPGA) => output */
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0; /* bit 0 => input */
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#endif /* MACHINE_FIREBEE */
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}
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/*
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@@ -418,27 +427,27 @@ void init_fbcs()
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#if MACHINE_FIREBEE /* FBC setup for FireBee */
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MCF_FBCS1_CSAR = 0xFFF00000; /* ATARI I/O ADRESS */
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MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */
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| MCF_FBCS_CSCR_WS(8) /* DEFAULT 8WS */
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| MCF_FBCS_CSCR_AA; /* AA */
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| MCF_FBCS_CSCR_WS(8) /* DEFAULT 8WS */
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| MCF_FBCS_CSCR_AA; /* AA */
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MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V;
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MCF_FBCS2_CSAR = 0xF0000000; // NEUER I/O ADRESS-BEREICH
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MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
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| MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS
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| MCF_FBCS_CSCR_AA; // AA
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| MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS
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| MCF_FBCS_CSCR_AA; // AA
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MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M // F000'0000-F7FF'FFFF
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| MCF_FBCS_CSMR_V);
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MCF_FBCS3_CSAR = 0xF8000000; // NEUER I/O ADRESS-BEREICH
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MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT
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| MCF_FBCS_CSCR_AA; // AA
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| MCF_FBCS_CSCR_AA; // AA
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MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M // F800'0000-FBFF'FFFF
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| MCF_FBCS_CSMR_V);
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MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BENÜTZT, DECODE DIREKT AUF DEM FPGA
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MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
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| MCF_FBCS_CSCR_BSTR // BURST READ ENABLE
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| MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE
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| MCF_FBCS_CSCR_BSTR // BURST READ ENABLE
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| MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE
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MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF
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| MCF_FBCS_CSMR_V;
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#elif MACHINE_M5484LITE
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@@ -453,7 +462,7 @@ void init_fbcs()
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| MCF_FBCS_CSCR_WS(32)
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| MCF_FBCS_CSCR_ASET(1)
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| MCF_FBCS_CSCR_AA;
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MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M
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MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M
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| MCF_FBCS_CSMR_V;
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#endif /* MACHINE_FIREBEE */
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@@ -571,7 +580,7 @@ void init_video_ddr(void) {
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/*
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* probe for NEC compatible USB host controller and install if found
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*/
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void init_usb(void)
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void init_usb(void)
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{
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extern struct pci_device_id ohci_usb_pci_table[];
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extern struct pci_device_id ehci_usb_pci_table[];
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@@ -657,20 +666,18 @@ static bool i2c_bus_free(void)
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/*
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* TFP410 (DVI) on
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*/
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void dvi_on(void)
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{
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void dvi_on(void) {
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uint8_t receivedByte;
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uint8_t dummyByte; /* only used for a dummy read */
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int num_tries = 0;
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xprintf("DVI digital video output initialization: ");
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MCF_I2C_I2FDR = 0x3c; /* divide system clock by 1280: 100kHz standard */
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do
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{
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do {
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/* disable all i2c interrupt routing targets */
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MCF_I2C_I2ICR = 0x0; // ~(MCF_I2C_I2ICR_IE | MCF_I2C_I2ICR_RE | MCF_I2C_I2ICR_TE | MCF_I2C_I2ICR_BNBE);
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MCF_I2C_I2ICR = 0x0; //~(MCF_I2C_I2ICR_IE | MCF_I2C_I2ICR_RE | MCF_I2C_I2ICR_TE | MCF_I2C_I2ICR_BNBE);
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/* disable i2c, disable i2c interrupts, slave, receive, i2c = acknowledge, no repeat start */
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MCF_I2C_I2CR = 0x0;
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@@ -807,16 +814,16 @@ void init_ac97(void) {
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int va;
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int vb;
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int vc;
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xprintf("AC97 sound chip initialization: ");
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MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS // PSC2=TX,RX BCLK,CTS->AC'97
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| MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK
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| MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK
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| MCF_PAD_PAR_PSC2_PAR_TXD2
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| MCF_PAD_PAR_PSC2_PAR_RXD2;
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MCF_PSC2_PSCMR1 = 0x0;
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MCF_PSC2_PSCMR2 = 0x0;
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MCF_PSC2_PSCIMR = 0x0300;
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MCF_PSC2_PSCSICR = 0x03; //AC97
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MCF_PSC2_PSCSICR = 0x03; //AC97
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MCF_PSC2_PSCRFCR = 0x0f000000;
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MCF_PSC2_PSCTFCR = 0x0f000000;
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MCF_PSC2_PSCRFAR = 0x00F0;
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@@ -837,7 +844,7 @@ void init_ac97(void) {
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{
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MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
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}
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// read register
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MCF_PSC2_PSCTB_AC97 = 0xc0000000; //START SLOT1 + SLOT2, FIRST FRAME
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MCF_PSC2_PSCTB_AC97 = 0x82000000; //SLOT1:master volume
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@@ -847,7 +854,7 @@ void init_ac97(void) {
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MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0
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}
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wait(50);
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va = MCF_PSC2_PSCTB_AC97;
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if ((va & 0x80000fff) == 0x80000800) {
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vb = MCF_PSC2_PSCTB_AC97;
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@@ -951,10 +958,10 @@ void initialize_hardware(void)
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* (volatile uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
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* (volatile uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
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/* TT-RAM */
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/* TT-RAM */
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* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
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* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
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* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
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* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
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/* Jump into FireTOS */
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typedef void void_func(void);
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@@ -967,7 +974,7 @@ void initialize_hardware(void)
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init_serial();
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xprintf("\n\n");
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xprintf("%s BASIS system (BaS) v %d.%d (%s, %s)\r\n\r\n",
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xprintf("%s BASIS system (BaS) v %d.%d (%s, %s)\r\n\r\n",
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#if MACHINE_FIREBEE
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"Firebee"
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#elif MACHINE_M5484LITE
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@@ -1045,7 +1052,7 @@ void initialize_hardware(void)
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/*
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* Determine the processor revision
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*/
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xprintf(" (revision %d)\r\n", ((MCF_SIU_JTAGID & MCF_SIU_JTAGID_REV) >> 28));
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xprintf(" (revision %d)\r\n",((MCF_SIU_JTAGID & MCF_SIU_JTAGID_REV) >> 28));
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init_slt();
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init_fbcs();
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@@ -1083,7 +1090,6 @@ void initialize_hardware(void)
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/* the following only makes sense _after_ DDRAM has been initialized */
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clear_bss_segment();
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xprintf(".bss segment cleared\r\n");
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if (BAS_LMA != BAS_IN_RAM)
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{
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@@ -1097,17 +1103,39 @@ void initialize_hardware(void)
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#if MACHINE_FIREBEE
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if (coldboot) /* does not work with BDM */
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;
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fpga_configured = init_fpga();
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init_fpga();
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init_pll();
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init_video_ddr();
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dvi_on();
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#ifdef _NOT_USED_
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/* experimental */
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{
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int i;
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uint32_t *scradr = (uint32_t *) 0xd00000;
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for (i = 0; i < 100; i++)
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{
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uint32_t *p = scradr;
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for (p = scradr; p < scradr + 1024 * 150L; p++)
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{
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*p = 0xffffffff;
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}
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for (p = scradr; p < scradr + 1024 * 150L; p++)
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{
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*p = 0x0;
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}
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}
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}
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#endif /* _NOT_USED_ */
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#endif /* MACHINE_FIREBEE */
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driver_mem_init();
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init_pci();
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video_init();
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/* do not try to init USB for now on the Firebee, it hangs the machine */
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#ifndef MACHINE_FIREBEE
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//init_usb();
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