Initial checkin of DSP 56k VHDL code.

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Matthias Alles
2010-11-02 07:29:43 +00:00
parent ebdb8e0d71
commit af014dc0d6
56 changed files with 7279 additions and 0 deletions

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------------------------------------------------------------------------------
--! @file
--! @author Matthias Alles
--! @date 01/2009
--! @brief Global parameters
--!
------------------------------------------------------------------------------
package parameter_pkg is
constant BW_ADDRESS : natural := 16;
-- number of pipeline register stages
constant PIPELINE_DEPTH : natural := 4;
constant NUM_ACT_SIGNALS : natural := 26;
end package;