Initial checkin of DSP 56k VHDL code.

This commit is contained in:
Matthias Alles
2010-11-02 07:29:43 +00:00
parent ebdb8e0d71
commit af014dc0d6
56 changed files with 7279 additions and 0 deletions

View File

@@ -0,0 +1,10 @@
move #20,r1
move #$ABCDEF,x0
move #$123456,b
andi #$00,ccr
tcs x0,a r1,r3
tcc x0,b r1,r2
; set Zero Flag
ori #$04,ccr
teq x0,a r1,r3
tne x0,b r1,r2