Initial checkin of DSP 56k VHDL code.
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10
vhdl/dsp56k/asm/test_alu/test_tcc.asm
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10
vhdl/dsp56k/asm/test_alu/test_tcc.asm
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move #20,r1
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move #$ABCDEF,x0
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move #$123456,b
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andi #$00,ccr
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tcs x0,a r1,r3
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tcc x0,b r1,r2
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; set Zero Flag
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ori #$04,ccr
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teq x0,a r1,r3
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tne x0,b r1,r2
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