Initial checkin of DSP 56k VHDL code.

2010-11-02 07:29:43 +00:00
parent ebdb8e0d71
commit af014dc0d6
56 changed files with 7279 additions and 0 deletions
--- a/vhdl/dsp56k/asm/test_alu/test_sub.asm
+++ b/vhdl/dsp56k/asm/test_alu/test_sub.asm
@@ -0,0 +1,15 @@
+	move	#>0,y0
+	move	#>1,y1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	sub		y,b
+	move	#>$800000,y1
+	move	#>$80,b2
+	sub		y,b
+	clr		b
+	move	#>$80,b2
+	move	#>$1,y1
+	sub		y1,b