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Initial checkin of DSP 56k VHDL code.

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Matthias Alles
2010-11-02 07:29:43 +00:00
parent ebdb8e0d71
commit af014dc0d6
56 changed files with 7279 additions and 0 deletions
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vhdl/dsp56k/asm/test_alu/test_ror.asm Normal file
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andi #$00,CCR
move #>$AAAAAA,a
move #>$BCDEFA,a0
rep #24
ror a