Initial checkin of DSP 56k VHDL code.
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17
vhdl/dsp56k/asm/test_alu/test_macr.asm
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17
vhdl/dsp56k/asm/test_alu/test_macr.asm
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andi #$00,CCR
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clr a
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move #$100000,a
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move #>$123456,x0
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move #>$123456,y0
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macr x0,y0,a
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move #$100001,a
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move #>$123456,x0
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move #>$123456,y0
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macr x0,y0,a
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move #$100000,a
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move #$800000,a0
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move #>$123456,x0
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move #>$123456,y0
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macr x0,y0,a
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