Initial checkin of DSP 56k VHDL code.
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17
vhdl/dsp56k/asm/test_alu/test_mac.asm
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17
vhdl/dsp56k/asm/test_alu/test_mac.asm
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andi #$00,CCR
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clr a
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move #$80,a2
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move #>0.25,x0
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move #>0.50,y0
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mac -x0,y0,a
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move #>-0.25,x0
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move #>-0.55,y0
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mac x0,y0,a
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move #>-0.20,x0
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move #>+0.55,y0
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mac x0,y0,a
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move #>-0.20,x0
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move #>+0.55,y0
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mac -x0,y0,a
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