Initial checkin of DSP 56k VHDL code.

This commit is contained in:
Matthias Alles
2010-11-02 07:29:43 +00:00
parent ebdb8e0d71
commit af014dc0d6
56 changed files with 7279 additions and 0 deletions

View File

@@ -0,0 +1,12 @@
; clear CCR
andi #$00,CCR
move #>0.25,a
abs a
move #>-0.25,a
abs a
move #>0,a
abs a
move #>$80,a2
abs a