Initial checkin of DSP 56k VHDL code.
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12
vhdl/dsp56k/asm/test_alu/test_abs.asm
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12
vhdl/dsp56k/asm/test_alu/test_abs.asm
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; clear CCR
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andi #$00,CCR
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move #>0.25,a
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abs a
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move #>-0.25,a
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abs a
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move #>0,a
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abs a
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move #>$80,a2
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abs a
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