Initial checkin of DSP 56k VHDL code.

vhdl/dsp56k/asm/test_alu/test_abs.asm

@@ -0,0 +1,12 @@
+
+; clear CCR
+	andi	#$00,CCR
+	move	#>0.25,a
+	abs		a
+	move	#>-0.25,a
+	abs		a
+	move	#>0,a
+	abs		a
+	move	#>$80,a2
+	abs		a
+

vhdl/dsp56k/asm/test_alu/test_adc.asm

@@ -0,0 +1,11 @@
+	move	#>0,y0
+	move	#>1,y1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	adc		y,b
+	move	#>$800000,y1
+	move	#>$80,b2
+	adc		y,b

vhdl/dsp56k/asm/test_alu/test_add.asm

@@ -0,0 +1,11 @@
+	move	#>0,y0
+	move	#>1,y1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	add		y,b
+	move	#>$800000,y1
+	move	#>$80,b2
+	add		y,b

vhdl/dsp56k/asm/test_alu/test_addl.asm

@@ -0,0 +1,9 @@
+	move	#>$55,a
+	clr		b
+	move	#>$55,b0
+	andi	#$00,ccr
+	addl	a,b
+	move	#>$AA,a
+	addl	a,b
+	move	#>$80,b2
+	addl	a,b

vhdl/dsp56k/asm/test_alu/test_addr.asm

@@ -0,0 +1,9 @@
+	move	#>$55,a
+	clr		b
+	move	#>$55,b0
+	andi	#$00,ccr
+	addr	a,b
+	move	#>$AA,a
+	addr	a,b
+	move	#>$80,b2
+	addr	a,b

vhdl/dsp56k/asm/test_alu/test_and.asm

@@ -0,0 +1,12 @@
+	move	#>$000FFF,y0
+	move	#>$FFFFFF,b
+	andi	#$00,ccr
+	and		y0,b
+	move	#>$FFF000,y0
+	move	#>$FFFFFF,b
+	andi	#$00,ccr
+	and		y0,b
+	move	#>$000000,y0
+	move	#>$FFFFFF,b
+	andi	#$00,ccr
+	and		y0,b

vhdl/dsp56k/asm/test_alu/test_asl.asm

@@ -0,0 +1,8 @@
+;	move	#>0,y0
+;	move	#>1,y1
+	clr		b
+	move	#>$A5,b0
+	move	#>$A5,b1
+	move	#>$A5,b2
+	andi	#$00,ccr
+	asl		b

vhdl/dsp56k/asm/test_alu/test_asr.asm

@@ -0,0 +1,8 @@
+;	move	#>0,y0
+;	move	#>1,y1
+	clr		b
+	move	#>$A5,b0
+	move	#>$A5,b1
+	move	#>$A5,b2
+	andi	#$00,ccr
+	asr		b

vhdl/dsp56k/asm/test_alu/test_carry.asm

@@ -0,0 +1,20 @@
+	clr		a
+	clr		b
+	andi	#$00,ccr
+	move 	#>$7F,a2
+	move 	#>$7F,b2
+	add		a,b
+
+	clr		a
+	clr		b
+	andi	#$00,ccr
+	move 	#>$80,a2
+	move 	#>$7F,b2
+	add		a,b
+
+	clr		a
+	clr		b
+	andi	#$00,ccr
+	move 	#>$80,a2
+	move 	#>$80,b2
+	add		a,b

vhdl/dsp56k/asm/test_alu/test_clr.asm

@@ -0,0 +1,9 @@
+
+; clear CCR
+	andi	#$00,CCR
+	move	#>0.25,a
+	clr		a
+	move	#>-0.25,a
+	andi	#$00,CCR
+	ori		#$01,CCR
+	clr		a

vhdl/dsp56k/asm/test_alu/test_cmp.asm

@@ -0,0 +1,20 @@
+	move	#$20,b
+	move	#$24,y0
+	andi	#$00,ccr
+	cmp		y0,b
+	move	#$20,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmp		y0,b
+	move	#$24,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmp		y0,b
+	move	#$800AAA,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmp		y0,b
+	move	#$800AAA,y0
+	move	#$20,b
+	andi	#$00,ccr
+	cmp		y0,b

vhdl/dsp56k/asm/test_alu/test_cmpm.asm

@@ -0,0 +1,20 @@
+	move	#$20,b
+	move	#$24,y0
+	andi	#$00,ccr
+	cmpm		y0,b
+	move	#$20,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmpm		y0,b
+	move	#$24,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmpm		y0,b
+	move	#$800AAA,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmpm		y0,b
+	move	#$800AAA,y0
+	move	#$20,b
+	andi	#$00,ccr
+	cmpm		y0,b

vhdl/dsp56k/asm/test_alu/test_eor.asm

@@ -0,0 +1,8 @@
+	move	#>$000FFF,y0
+	move	#>$FF00FF,b
+	andi	#$00,ccr
+	eor		y0,b
+	move	#>$FFFFFF,y0
+	move	#>$FFFFFF,b
+	andi	#$00,ccr
+	eor		y0,b

vhdl/dsp56k/asm/test_alu/test_lsl.asm

@@ -0,0 +1,7 @@
+
+	andi	#$00,CCR
+	move	#>0.25,a
+	move	#>$AAAAAA,a
+	move	#>$BCDEFA,a0
+	rep		#24
+	lsl		a

vhdl/dsp56k/asm/test_alu/test_lsr.asm

@@ -0,0 +1,7 @@
+
+	andi	#$00,CCR
+	move	#>0.25,a
+	move	#>$AAAAAA,a
+	move	#>$BCDEFA,a0
+	rep		#24
+	lsr		a

vhdl/dsp56k/asm/test_alu/test_mac.asm

@@ -0,0 +1,17 @@
+
+	andi	#$00,CCR
+	clr		a
+	move	#$80,a2
+	move	#>0.25,x0
+	move	#>0.50,y0
+	mac		-x0,y0,a
+	move	#>-0.25,x0
+	move	#>-0.55,y0
+	mac		x0,y0,a
+	move	#>-0.20,x0
+	move	#>+0.55,y0
+	mac		x0,y0,a
+	move	#>-0.20,x0
+	move	#>+0.55,y0
+	mac		-x0,y0,a
+

vhdl/dsp56k/asm/test_alu/test_macr.asm

@@ -0,0 +1,17 @@
+
+	andi	#$00,CCR
+	clr		a
+	move	#$100000,a
+	move	#>$123456,x0
+	move	#>$123456,y0
+	macr	x0,y0,a
+	move	#$100001,a
+	move	#>$123456,x0
+	move	#>$123456,y0
+	macr	x0,y0,a
+	move	#$100000,a
+	move	#$800000,a0
+	move	#>$123456,x0
+	move	#>$123456,y0
+	macr	x0,y0,a
+

vhdl/dsp56k/asm/test_alu/test_mpy.asm

@@ -0,0 +1,15 @@
+
+	andi	#$00,CCR
+	move	#>0.25,x0
+	move	#>0.50,y0
+	mpy		x0,y0,a
+	move	#>-0.25,x0
+	move	#>-0.55,y0
+	mpy		x0,y0,a
+	move	#>-0.20,x0
+	move	#>+0.55,y0
+	mpy		x0,y0,a
+	move	#>-0.20,x0
+	move	#>+0.55,y0
+	mpy		-x0,y0,a
+

vhdl/dsp56k/asm/test_alu/test_mpyr.asm

@@ -0,0 +1,5 @@
+
+	andi	#$00,CCR
+	move	#>$654321,y0
+	mpyr	-y0,y0,a
+

vhdl/dsp56k/asm/test_alu/test_neg.asm

@@ -0,0 +1,10 @@
+
+	andi	#$00,CCR
+	move	#>$654321,a
+	neg		a
+	clr		a
+	move 	#>$80,a2
+	neg		a
+	move	#>$800000,a
+	neg		a
+

vhdl/dsp56k/asm/test_alu/test_norm.asm

@@ -0,0 +1,14 @@
+	clr		a
+	move 	#$000001,a1
+	tst		a
+	rep		#$2F
+	norm	R3,a
+	clr		a
+	move 	#$FF0000,a
+	move	#$84,a2
+	tst		a
+	rep		#$2F
+	norm	R1,a
+	clr		a
+	rep		#$2F
+	norm	R2,a

vhdl/dsp56k/asm/test_alu/test_not.asm

@@ -0,0 +1,8 @@
+	move	#>$000FFF,y0
+	move	#>$7F00FF,b
+	andi	#$00,ccr
+	not 	b
+	move	#>$000000,y0
+	move	#>$FFFFFF,b
+	andi	#$00,ccr
+	not		b

vhdl/dsp56k/asm/test_alu/test_or.asm

@@ -0,0 +1,8 @@
+	move	#>$000FFF,y0
+	move	#>$FF00FF,b
+	andi	#$00,ccr
+	or		y0,b
+	move	#>$000000,y0
+	move	#>$000000,b
+	andi	#$00,ccr
+	or		y0,b

vhdl/dsp56k/asm/test_alu/test_rnd.asm

@@ -0,0 +1,11 @@
+
+	andi	#$00,CCR
+	move	#>$123456,a1
+	move	#>$789ABC,a0
+	rnd		a
+	move	#>$123456,a1
+	move	#>$800000,a0
+	rnd		a
+	move	#>$123455,a1
+	move	#>$800000,a0
+	rnd		a

vhdl/dsp56k/asm/test_alu/test_rol.asm

@@ -0,0 +1,6 @@
+
+	andi	#$00,CCR
+	move	#>$AAAAAA,a
+	move	#>$BCDEFA,a0
+	rep		#24
+	rol		a

vhdl/dsp56k/asm/test_alu/test_ror.asm

@@ -0,0 +1,6 @@
+
+	andi	#$00,CCR
+	move	#>$AAAAAA,a
+	move	#>$BCDEFA,a0
+	rep		#24
+	ror		a

vhdl/dsp56k/asm/test_alu/test_sbc.asm

@@ -0,0 +1,15 @@
+	move	#>0,y0
+	move	#>1,y1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	sbc		y,b
+	move	#>$800000,y1
+	move	#>$80,b2
+	sbc		y,b
+	clr		b
+	move	#>$80,b2
+	move	#>$1,y1
+	sbc		y,b

vhdl/dsp56k/asm/test_alu/test_sub.asm

@@ -0,0 +1,15 @@
+	move	#>0,y0
+	move	#>1,y1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	sub		y,b
+	move	#>$800000,y1
+	move	#>$80,b2
+	sub		y,b
+	clr		b
+	move	#>$80,b2
+	move	#>$1,y1
+	sub		y1,b

vhdl/dsp56k/asm/test_alu/test_subl.asm

@@ -0,0 +1,15 @@
+	move	#>0,a0
+	move	#>1,a1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	subl	a,b
+	move	#>$800000,a1
+	move	#>$80,b2
+	subl	a,b
+	clr		b
+	move	#>$80,b2
+	move	#>$1,a1
+	subl	a,b

vhdl/dsp56k/asm/test_alu/test_subr.asm

@@ -0,0 +1,15 @@
+	move	#>0,a0
+	move	#>1,a1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	subr	a,b
+	move	#>$800000,a1
+	move	#>$80,b2
+	subr	a,b
+	clr		b
+	move	#>$80,b2
+	move	#>$1,a1
+	subr	a,b

vhdl/dsp56k/asm/test_alu/test_tcc.asm

@@ -0,0 +1,10 @@
+	move	#20,r1
+	move	#$ABCDEF,x0
+	move	#$123456,b
+	andi	#$00,ccr
+	tcs		x0,a	r1,r3
+	tcc		x0,b	r1,r2	
+	; set Zero Flag
+	ori		#$04,ccr
+	teq		x0,a	r1,r3
+	tne		x0,b	r1,r2	

vhdl/dsp56k/asm/test_alu/test_tfr.asm

@@ -0,0 +1,7 @@
+	move	#$ABCDEF,a
+	move	#$123456,b
+	tfr		a,b	b,a
+	move	#$555555,x0
+	move	#$AAAAAA,y1
+	tfr		x0,a	a,x0
+	tfr		y1,b	b,y0

vhdl/dsp56k/asm/test_alu/test_tst.asm

@@ -0,0 +1,9 @@
+	clr		b
+	tst		b
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	move	#>$80,b2
+	tst	b
+	move	#>$7F,b2
+	tst	b