more consistant file name

BaS_gcc/bas_firebee.bdm

@@ -0,0 +1,71 @@
+#!/usr/local/bin/bdmctrl -D2 -v9 -d9
+#
+# firebee board initialization for bdmctrl 
+#
+open $1
+reset
+sleep 10
+
+# Turn on MBAR at 0xFF00_0000
+write-ctrl 0x0C0F 0xFF000000
+
+# set VBR
+write-ctrl 0x0801 0x00000000
+
+# Turn on RAMBAR0 at address FF10_0000 
+write-ctrl 0x0C04 0xFF100007
+
+# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
+write-ctrl 0x0C05 0xFF101001
+
+# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+write 0xFF000500 0xE0000000 4
+write 0xFF000508 0x00041180 4
+write 0xFF000504 0x007F0001 4
+wait
+
+# Init CS1 (Atari I/O address range)
+write 0xFF00050C 0xFFF00000 4
+write 0xFF000514 0x00002180 4
+write 0xFF000510 0x000F0001 4
+# Init CS2 (FireBee 32 bit I/O address range)
+write 0xFF000518 0xF0000000 4
+write 0xFF000520 0x00002100 4
+write 0xFF00051C 0x07FF0001 4
+# Init CS3 (FireBee 16 bit I/O address range)
+write 0xFF000524 0xF8000000 4
+write 0xFF00052C 0x00000180 4
+write 0xFF000528 0x03FF0001 4
+# Init CS4 (FireBee video address range)
+write 0xFF000530 0x40000000 4
+write 0xFF000538 0x00000018 4
+write 0xFF000534 0x003F0001 4
+
+
+# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
+write 0xFF000004 0x000002AA 4	# SDRAMDS configuration
+write 0xFF000020 0x0000001A 4	# SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+write 0xFF000024 0x0800001A 4	# SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+write 0xFF000028 0x1000001A 4	# SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
+write 0xFF00002C 0x1800001A 4	# SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+write 0xFF000108 0x73622830 4	# SDCFG1
+write 0xFF00010C 0x46770000 4	# SDCFG2
+
+write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
+write 0xFF000100 0x40010000 4	# SDMR (write to LEMR)
+write 0xFF000100 0x048D0000 4	# SDMR (write to LMR)
+sleep 100
+write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
+write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
+write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
+write 0xFF000100 0x008D0000 4	# SDMR (write to LMR)
+write 0xFF000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
+sleep 100
+
+load -v firebee/ram.elf
+write-ctrl 0x80e	0x2700
+write-ctrl 0x2	0xa50c8120
+dump-register SR
+dump-register CACR
+dump-register MBAR
+execute

BaS_gcc/sources/pci.c

@@ -300,8 +300,8 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 	int16_t index = - 1;
 	struct pci_rd *descriptors;
 	int i;
-	uint32_t mem_address = PCI_MEMORY_OFFSET;
+	static uint32_t mem_address = PCI_MEMORY_OFFSET;
-	uint32_t io_address = PCI_IO_OFFSET;
+	static uint32_t io_address = PCI_IO_OFFSET;
 
 	/* determine pci handle from bus, device + function number */
 	handle = PCI_HANDLE(bus, device, function);
@@ -498,7 +498,7 @@ void init_pci(void)
        + MCF_PCIARB_PACR_EXTMINTEN(0x1F);
 
 	/* Setup burst parameters */
-	MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(64); /* TODO: test increased latency timer */
+	MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32); /* TODO: test increased latency timer */
 	MCF_PCI_PCICR2 = MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16);
 
 	/* Turn on error signaling, 32 write retries on failure */
@@ -508,11 +508,11 @@ void init_pci(void)
 	/* Configure Initiator Windows */
 
 	/*
-	 * initiator window 0 base / translation adress register
-	 *
 	 * Window starts at PCI_MEMORY_OFFSET, ends at PCI_MEMORY_OFFSET + PCI_MEMORY_SIZE - 1 (2 GB)
-	 * There is no translation from M54xx address space to PCI address space
+	 * There is no translation from M54xx address space to PCI address space (same addresses)
 	 */
+
+	/* initiator window 0 base / translation adress register */
 	MCF_PCI_PCIIW0BTAR = PCI_MEMORY_OFFSET | (((PCI_MEMORY_SIZE - 1) >> 8) & 0xffff0000) |
 							PCI_MEMORY_OFFSET >> 16;
 
@@ -550,40 +550,7 @@ void init_pci(void)
 	/* initialize resource descriptor table */
 	memset(&resource_descriptors, 0, NUM_CARDS * NUM_RESOURCES * sizeof(struct pci_rd));
 	/* initialize handles array */
-	memset(handles, 0, NUM_CARDS * sizeof(uint16_t));
+	memset(handles, 0, NUM_CARDS * sizeof(int32_t));
-
-#if _NOT_USED_
-	/*
-	 * experimental: leave "old" USB initialization in place for the FireBee USB controller
-	 * which seems to be found on second access only with the new PCI scan routines
-	 */
-
-	/* PCI config space access for UPD720101 on AD17 */
-	MCF_PCI_PCICAR = MCF_PCI_PCICAR_E +
-		MCF_PCI_PCICAR_DEVNUM(17) +
-		MCF_PCI_PCICAR_FUNCNUM(0) +
-		MCF_PCI_PCICAR_DWORD(0);
-
-	if (* (uint32_t *) PCI_IO_OFFSET == 0x33103500)
-	{
-		/* device found */
-
-		MCF_PCI_PCICAR = MCF_PCI_PCICAR_E + 
-			MCF_PCI_PCICAR_DEVNUM(17) +
-			MCF_PCI_PCICAR_FUNCNUM(0) +
-			MCF_PCI_PCICAR_DWORD(57);	/* FIXME: PCI configuration access to reserved register? */
-
-		* (uint8_t *) PCI_IO_OFFSET = 0x20;	// commented out (hangs currently)
-	}
-	else
-	{
-		xprintf("FireBee USB controller not found - disable");
-
-		MCF_PCI_PCICAR = MCF_PCI_PCICAR_DEVNUM(17) +
-			MCF_PCI_PCICAR_FUNCNUM(0) +
-			MCF_PCI_PCICAR_DWORD(57);
-	}
-#endif /* _NOT_USED_ */
 
 	/*
 	 * do normal initialization