This commit is contained in:
Markus Fröschle
@@ -1,36 +1,37 @@
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/*
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* File: sysinit.h
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* Purpose: Firebee Power-on Reset configuration
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*
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* Notes:
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2011 - 2012 V. Riviere
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* Copyright 2012 M. Froeschle
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*
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*/
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#ifndef __SYSINIT_H__
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#define __SYSINIT_H__
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/* function(s) from init_fpga.c */
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extern void init_fpga(void);
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#endif /* __SYSINIT_H__ */
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/*
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* File: sysinit.h
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* Purpose: Firebee Power-on Reset configuration
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*
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* Notes:
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*
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* This file is part of BaS_gcc.
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*
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* BaS_gcc is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* BaS_gcc is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright 2010 - 2012 F. Aschwanden
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* Copyright 2011 - 2012 V. Riviere
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* Copyright 2012 M. Froeschle
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*
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*/
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#ifndef __SYSINIT_H__
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#define __SYSINIT_H__
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/* function(s) from init_fpga.c */
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extern void init_fpga(void);
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extern void init_usb(void);
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#endif /* __SYSINIT_H__ */
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@@ -27,6 +27,7 @@
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#include "MCF5475.h"
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#include "MCF5475_SLT.h"
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#include "startcf.h"
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#include "sysinit.h"
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#include "cache.h"
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#include "bas_printf.h"
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#include "bas_string.h"
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@@ -254,6 +255,8 @@ void BaS(void)
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NOP(); /* force pipeline sync */
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xprintf("finished\r\n");
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init_usb();
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#ifdef MACHINE_FIREBEE
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xprintf("IDE reset: ");
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/* IDE reset */
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@@ -86,10 +86,32 @@
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//
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// to avoid chicken and egg situations, we need to make sure that MMU TLB miss exceptions do not end up in a memory
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// area that in turn cause a TLB miss exception themself after the MMU is enabled. At least the exception handler must live
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// in an area that's either covered by one of the ACR's or a locked MMU TLB entry. This is especially important when we link
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// BaS for RAM.
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// area that in turn cause a TLB miss exception themself after the MMU is enabled. At least the exception handler
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// must live in an area that's either covered by one of the ACR's or a locked MMU TLB entry. This is especially
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// important when we link BaS for RAM.
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//
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// some ACR bit defines upfront
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#define ACR_BA(x) ((x) & 0xffff0000)
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#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
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#define ACR_E(x) (((x) & 1) << 15)
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#define ACR_S(x) (((x) & 3) << 13)
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#define ACR_S_USERMODE 0
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#define ACR_S_SUPERVISOR_MODE 1
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#define ACR_S_ALL 2
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#define ACR_AMM(x) (((x) & 1) << 10)
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#define ACR_CM(x) (((x) & 3) << 5)
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#define ACR_CM_CACHEABLE_WT 0x0
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#define ACR_CM_CACHEABLE_CB 0x1
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#define ACR_CM_CACHE_INH_PRECISE 0x2
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#define ACR_CM_CACHE_INH_IMPRECISE 0x3
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#define ACR_SP(x) (((x) & 1) << 3)
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#define ACR_W(x) (((x) & 1) << 2)
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.text
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_mmu_init:
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move.l d3,-(sp) // Backup registers
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@@ -98,9 +120,17 @@ _mmu_init:
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clr.l d0
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movec d0,ASID // ASID always 0
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move.l d0,_rt_asid // save shadow register
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move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff
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movec d0,ACR0
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move.l #0 |\
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ACR_W(0) | /* read and write accesses permitted */ \
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ACR_SP(0) | /* supervisor AND user mode access permitted */ \
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ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */ \
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ACR_AMM(0) | /* control region > 16M */ \
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ACR_S(ACR_S_ALL) | /* match addresses in user AND supervisor mode */ \
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ACR_E(1) | /* enable ACR */ \
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ACR_ADMSK(0x3f) | /* cover 1 GB area from 0xC0000000 to 0xFFFFFFFF */ \
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ACR_BA(0xC0000000),d0 /* (equals area from 3 to 4 GB) */
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movec d0,ACR0 // ACR0 covers data
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move.l d0,_rt_acr0 // save shadow register
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move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff
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@@ -175,12 +205,9 @@ _mmu_init:
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move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
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#endif /* MACHINE_FIREBEE */
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// 1ff0'0000 locked
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// maps virtual 0x1FF0'0000 - 0x1FFF'FFFF to the same physical address
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move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | std_mmutr, d0 // last MB of physical RAM reserved for BaS
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// move.l #0x1FF00000|std_mmutr,d0 // last megabyte of physical RAM. Reserved for BaS
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// maps (locked) the last MB (this is where BaS .data and .bss resides) of physical SDRAM to the same physical address
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move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | std_mmutr, d0
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move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | copyback_mmudr | MCF_MMU_MMUDR_LK,d1
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// move.l #0x1FF00000|copyback_mmudr|MCF_MMU_MMUDR_LK,d1
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move.l d0,MCF_MMU_MMUTR
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move.l d1,MCF_MMU_MMUDR
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move.l d2,MCF_MMU_MMUOR // setzen data
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@@ -191,7 +218,7 @@ _mmu_init:
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rts
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/*
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* Everything else gets 1:1 mapped on miss
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* Everything else (that is not filtered out in the access error handler) gets a 1:1 mapping on miss
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*/
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_mmutr_miss:
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lea -4 * 4(sp),sp
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@@ -1010,8 +1010,8 @@ void initialize_hardware(void)
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init_video_ddr();
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dvi_on();
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#endif /* MACHINE_FIREBEE */
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init_usb();
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//video_1280_1024();
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/* moved the following line (temporarily) to BaS (after MMU init) to be able to catch adressing errors on USB init */
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//init_usb();
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#ifdef MACHINE_FIREBEE
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init_ac97();
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#endif /* MACHINE_FIREBEE */
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