This commit is contained in:
Markus Fröschle
2013-11-04 11:25:33 +00:00
parent 89a2028a83
commit accd53507b
4 changed files with 81 additions and 50 deletions

View File

@@ -1,36 +1,37 @@
/* /*
* File: sysinit.h * File: sysinit.h
* Purpose: Firebee Power-on Reset configuration * Purpose: Firebee Power-on Reset configuration
* *
* Notes: * Notes:
* *
* This file is part of BaS_gcc. * This file is part of BaS_gcc.
* *
* BaS_gcc is free software: you can redistribute it and/or modify * BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or * the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version. * (at your option) any later version.
* *
* BaS_gcc is distributed in the hope that it will be useful, * BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>. * along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
* *
* Copyright 2010 - 2012 F. Aschwanden * Copyright 2010 - 2012 F. Aschwanden
* Copyright 2011 - 2012 V. Riviere * Copyright 2011 - 2012 V. Riviere
* Copyright 2012 M. Froeschle * Copyright 2012 M. Froeschle
* *
*/ */
#ifndef __SYSINIT_H__ #ifndef __SYSINIT_H__
#define __SYSINIT_H__ #define __SYSINIT_H__
/* function(s) from init_fpga.c */ /* function(s) from init_fpga.c */
extern void init_fpga(void); extern void init_fpga(void);
extern void init_usb(void);
#endif /* __SYSINIT_H__ */
#endif /* __SYSINIT_H__ */

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@@ -27,6 +27,7 @@
#include "MCF5475.h" #include "MCF5475.h"
#include "MCF5475_SLT.h" #include "MCF5475_SLT.h"
#include "startcf.h" #include "startcf.h"
#include "sysinit.h"
#include "cache.h" #include "cache.h"
#include "bas_printf.h" #include "bas_printf.h"
#include "bas_string.h" #include "bas_string.h"
@@ -254,6 +255,8 @@ void BaS(void)
NOP(); /* force pipeline sync */ NOP(); /* force pipeline sync */
xprintf("finished\r\n"); xprintf("finished\r\n");
init_usb();
#ifdef MACHINE_FIREBEE #ifdef MACHINE_FIREBEE
xprintf("IDE reset: "); xprintf("IDE reset: ");
/* IDE reset */ /* IDE reset */

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@@ -86,10 +86,32 @@
// //
// to avoid chicken and egg situations, we need to make sure that MMU TLB miss exceptions do not end up in a memory // to avoid chicken and egg situations, we need to make sure that MMU TLB miss exceptions do not end up in a memory
// area that in turn cause a TLB miss exception themself after the MMU is enabled. At least the exception handler must live // area that in turn cause a TLB miss exception themself after the MMU is enabled. At least the exception handler
// in an area that's either covered by one of the ACR's or a locked MMU TLB entry. This is especially important when we link // must live in an area that's either covered by one of the ACR's or a locked MMU TLB entry. This is especially
// BaS for RAM. // important when we link BaS for RAM.
// //
// some ACR bit defines upfront
#define ACR_BA(x) ((x) & 0xffff0000)
#define ACR_ADMSK(x) (((x) & 0xffff) << 16)
#define ACR_E(x) (((x) & 1) << 15)
#define ACR_S(x) (((x) & 3) << 13)
#define ACR_S_USERMODE 0
#define ACR_S_SUPERVISOR_MODE 1
#define ACR_S_ALL 2
#define ACR_AMM(x) (((x) & 1) << 10)
#define ACR_CM(x) (((x) & 3) << 5)
#define ACR_CM_CACHEABLE_WT 0x0
#define ACR_CM_CACHEABLE_CB 0x1
#define ACR_CM_CACHE_INH_PRECISE 0x2
#define ACR_CM_CACHE_INH_IMPRECISE 0x3
#define ACR_SP(x) (((x) & 1) << 3)
#define ACR_W(x) (((x) & 1) << 2)
.text .text
_mmu_init: _mmu_init:
move.l d3,-(sp) // Backup registers move.l d3,-(sp) // Backup registers
@@ -98,9 +120,17 @@ _mmu_init:
clr.l d0 clr.l d0
movec d0,ASID // ASID always 0 movec d0,ASID // ASID always 0
move.l d0,_rt_asid // save shadow register move.l d0,_rt_asid // save shadow register
move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff move.l #0 |\
movec d0,ACR0 ACR_W(0) | /* read and write accesses permitted */ \
ACR_SP(0) | /* supervisor AND user mode access permitted */ \
ACR_CM(ACR_CM_CACHE_INH_PRECISE) | /* cache inhibit, precise */ \
ACR_AMM(0) | /* control region > 16M */ \
ACR_S(ACR_S_ALL) | /* match addresses in user AND supervisor mode */ \
ACR_E(1) | /* enable ACR */ \
ACR_ADMSK(0x3f) | /* cover 1 GB area from 0xC0000000 to 0xFFFFFFFF */ \
ACR_BA(0xC0000000),d0 /* (equals area from 3 to 4 GB) */
movec d0,ACR0 // ACR0 covers data
move.l d0,_rt_acr0 // save shadow register move.l d0,_rt_acr0 // save shadow register
move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff
@@ -175,12 +205,9 @@ _mmu_init:
move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise, move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
#endif /* MACHINE_FIREBEE */ #endif /* MACHINE_FIREBEE */
// 1ff0'0000 locked // maps (locked) the last MB (this is where BaS .data and .bss resides) of physical SDRAM to the same physical address
// maps virtual 0x1FF0'0000 - 0x1FFF'FFFF to the same physical address move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | std_mmutr, d0
move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | std_mmutr, d0 // last MB of physical RAM reserved for BaS
// move.l #0x1FF00000|std_mmutr,d0 // last megabyte of physical RAM. Reserved for BaS
move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | copyback_mmudr | MCF_MMU_MMUDR_LK,d1 move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | copyback_mmudr | MCF_MMU_MMUDR_LK,d1
// move.l #0x1FF00000|copyback_mmudr|MCF_MMU_MMUDR_LK,d1
move.l d0,MCF_MMU_MMUTR move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // setzen data move.l d2,MCF_MMU_MMUOR // setzen data
@@ -191,7 +218,7 @@ _mmu_init:
rts rts
/* /*
* Everything else gets 1:1 mapped on miss * Everything else (that is not filtered out in the access error handler) gets a 1:1 mapping on miss
*/ */
_mmutr_miss: _mmutr_miss:
lea -4 * 4(sp),sp lea -4 * 4(sp),sp

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@@ -1010,8 +1010,8 @@ void initialize_hardware(void)
init_video_ddr(); init_video_ddr();
dvi_on(); dvi_on();
#endif /* MACHINE_FIREBEE */ #endif /* MACHINE_FIREBEE */
init_usb(); /* moved the following line (temporarily) to BaS (after MMU init) to be able to catch adressing errors on USB init */
//video_1280_1024(); //init_usb();
#ifdef MACHINE_FIREBEE #ifdef MACHINE_FIREBEE
init_ac97(); init_ac97();
#endif /* MACHINE_FIREBEE */ #endif /* MACHINE_FIREBEE */