From ab59c420468ee011d1eabe2bd2f5c5dd85a88837 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 13 Nov 2013 21:08:52 +0000 Subject: [PATCH] fixex wrong parentheses in pci_write_config_longword() --- BaS_gcc/.gdbinit | 5 ++--- BaS_gcc/mcf5474.gdb | 2 +- BaS_gcc/sources/pci.c | 10 ++++++---- BaS_gcc/sources/sysinit.c | 16 ++++++++++++++++ 4 files changed, 25 insertions(+), 8 deletions(-) diff --git a/BaS_gcc/.gdbinit b/BaS_gcc/.gdbinit index bebe01d..598dbde 100644 --- a/BaS_gcc/.gdbinit +++ b/BaS_gcc/.gdbinit @@ -1,13 +1,12 @@ #set disassemble-next-line on define tr - #target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3 - target remote | m68k-bdm-gdbserver pipe /dev/tblcf3 + target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3 + #target remote | m68k-bdm-gdbserver pipe /dev/tblcf3 #target dbug /dev/ttyS0 #monitor bdm-reset end define tbtr target remote | m68k-bdm-gdbserver pipe /dev/tblcf3 - monitor bdm-reset end source mcf5474.gdb set breakpoint auto-hw diff --git a/BaS_gcc/mcf5474.gdb b/BaS_gcc/mcf5474.gdb index 42cfa3f..c4559eb 100644 --- a/BaS_gcc/mcf5474.gdb +++ b/BaS_gcc/mcf5474.gdb @@ -61,6 +61,6 @@ define ib setup-dram end -ib tr +ib load diff --git a/BaS_gcc/sources/pci.c b/BaS_gcc/sources/pci.c index 63d1044..ee51006 100644 --- a/BaS_gcc/sources/pci.c +++ b/BaS_gcc/sources/pci.c @@ -98,7 +98,9 @@ void chip_errata_135(void) __asm__ __volatile( " .extern __MBAR\n\t" + " bra .errata\n\t" " .align 16\n\t" /* force function start to 16-byte boundary */ + ".errata:\n\t" " clr.l d0\n\t" " move.l d0,__MBAR+0xF0C\n\t" /* Must use direct addressing. write to EPORT module */ /* xlbus -> slavebus -> eport, writing '0' to register */ @@ -212,11 +214,11 @@ uint8_t pci_read_config_byte(int32_t handle, int offset) MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ MCF_PCI_PCICAR_DWORD(offset / 4); - __asm__ __volatile__("nop"); + __asm__ __volatile__("nop" ::: "memory"); - value = * (volatile uint8_t *) PCI_IO_OFFSET + (offset & 3); + value = * (volatile uint8_t *) (PCI_IO_OFFSET + (offset & 3)); - __asm__ __volatile__("tpf"); + __asm__ __volatile__("tpf" ::: "memory"); MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E; @@ -237,7 +239,7 @@ int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value) MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) | /* function number */ MCF_PCI_PCICAR_DWORD(offset / 4); - __asm__ __volatile__("tpf"); + __asm__ __volatile__("nop"); * (volatile uint32_t *) PCI_IO_OFFSET = value; /* access device */ diff --git a/BaS_gcc/sources/sysinit.c b/BaS_gcc/sources/sysinit.c index b5ca71b..d94020f 100644 --- a/BaS_gcc/sources/sysinit.c +++ b/BaS_gcc/sources/sysinit.c @@ -120,11 +120,19 @@ void init_gpio(void) * /PCIBG1 used as /PCIBG1 * /PCIBG0 used as /PCIBG0 */ +#if MACHINE_FIREBEE MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST | MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO | MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 | MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 | MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0; +#elif MACHINE_M5484LITE + MCF_PAD_PAR_PCIBG = MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 | + MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0; +#endif /* MACHINE_FIREBEE */ /* * configure PCI request pin assignment on GPIO module: @@ -134,11 +142,19 @@ void init_gpio(void) * /PCIBR1 as /PCIBR1 * /PCIBR0 as /PCIBR0 */ +#if MACHINE_FIREBEE MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 | MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO | MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 | MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 | MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0; +#elif MACHINE_M5484LITE + MCF_PAD_PAR_PCIBR = MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 | + MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0; +#endif /* MACHINE_FIREBEE */ /* * configure PSC3 pin assignment on GPIO module: