Firebee/FireBee_SVN
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This commit is contained in:
Markus Fröschle
2013-07-23 19:39:48 +00:00
parent f23087ee19
commit a981488045
3 changed files with 32 additions and 40 deletions
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44
BaS_gcc/run_bas.bdm
View File

@@ -1,4 +1,4 @@
#!/usr/local/bin/bdmctrl -D2 #!/usr/local/bin/bdmctrl -D2 -v9 -d9
# #
# firebee board initialization for bdmctrl # firebee board initialization for bdmctrl
# #
@@ -6,44 +6,36 @@ open $1
reset reset
sleep 10 sleep 10
wait
# set VBR # set VBR
#write-ctrl 0x0801 0x00000000 write-ctrl 0x0801 0x00000000
sleep 10
# Turn on MBAR at 0xFF00_0000 # Turn on MBAR at 0xFF00_0000
write-ctrl 0x0C0F 0xFF000000 write-ctrl 0x0C0F 0xFF000000
# Turn on MMUBAR at 0xFF04_0000
write-ctrl 0x0008 0xFF040001
# Turn on RAMBAR0 at address FF10_0000 # Turn on RAMBAR0 at address FF10_0000
write-ctrl 0x0C04 0xFF100007 write-ctrl 0x0C04 0xFF100007
sleep 10
# Turn on RAMBAR1 at address FF10_1000 # Turn on RAMBAR1 at address FF10_1000
write-ctrl 0x0C05 0xFF101001 write-ctrl 0x0C05 0xFF101001
sleep 10
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) # Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
write 0xFF000500 0xE0000000 4 write 0xFF000500 0xE0000000 4
write 0xFF000508 0x00001180 4 write 0xFF000508 0x00041180 4
write 0xFF000504 0x007F0001 4 write 0xFF000504 0x007F0001 4
# Init CS1 (Atari I/O address range) # Init CS1 (Atari I/O address range)
write 0xFF00050C 0xFFF00000 4 #write 0xFF00050C 0xFFF00000 4
write 0xFF000514 0x00002180 4 #write 0xFF000514 0x00002180 4
write 0xFF000510 0x000F0001 4 #write 0xFF000510 0x000F0001 4
# Init CS2 (FireBee 32 bit I/O address range) # Init CS2 (FireBee 32 bit I/O address range)
write 0xFF000518 0xF0000000 4 #write 0xFF000518 0xF0000000 4
write 0xFF000520 0x00002100 4 #write 0xFF000520 0x00002100 4
write 0xFF00051C 0x07FF0001 4 #write 0xFF00051C 0x07FF0001 4
# Init CS3 (FireBee 16 bit I/O address range) # Init CS3 (FireBee 16 bit I/O address range)
write 0xFF000524 0xF8000000 4 #write 0xFF000524 0xF8000000 4
write 0xFF00052C 0x00000180 4 #write 0xFF00052C 0x00000180 4
write 0xFF000528 0x03FF0001 4 #write 0xFF000528 0x03FF0001 4
# Init CS4 (FireBee video address range) # Init CS4 (FireBee video address range)
write 0xFF000530 0x40000000 4 #write 0xFF000530 0x40000000 4
write 0xFF000538 0x00000018 4 #write 0xFF000538 0x00000018 4
write 0xFF000534 0x003F0001 4 #write 0xFF000534 0x003F0001 4
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes # SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
@@ -64,9 +56,7 @@ write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR) write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh) write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
write 0xFF000240 0x80000000 4 # disable watchdog arbiter
load -v ram.elf load -v ram.elf
wait wait
sleep 100 sleep 10
execute execute

6
BaS_gcc/sources/init_fpga.c
View File

@@ -38,8 +38,8 @@
*/ */
void init_fpga(void) void init_fpga(void)
{ {
register uint8_t *fpga_data; uint8_t *fpga_data;
register int i; int i;
xprintf("FPGA load config... "); xprintf("FPGA load config... ");
@@ -93,6 +93,7 @@ void init_fpga(void)
} }
} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END)); } while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END));
#ifdef _NOT_USED_ /* doesn't seem to be needed */
if (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END) if (fpga_data < (uint8_t *) FPGA_FLASH_DATA_END)
{ {
while (fpga_data++ < (uint8_t *) FPGA_FLASH_DATA_END) while (fpga_data++ < (uint8_t *) FPGA_FLASH_DATA_END)
@@ -108,4 +109,5 @@ void init_fpga(void)
{ {
xprintf("FAILED!\r\n"); xprintf("FAILED!\r\n");
} }
#endif /* _NOT_USED_ */
} }

22
BaS_gcc/sources/mmu.S
View File

@@ -84,28 +84,28 @@ _mmu_init:
move.l d2,-(sp) move.l d2,-(sp)
clr.l d0 clr.l d0
movec d0,ASID // ASID allways 0 movec d0,ASID // ASID always 0
move.l d0,_rt_asid // sichern move.l d0,_rt_asid // save
move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff
movec d0,ACR0 movec d0,ACR0
move.l d0,_rt_acr0 // sichern move.l d0,_rt_acr0 // save
move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff move.l #0x601FC000,d0 // data r/w wt 6000'0000-7fff'ffff
movec d0,ACR1 movec d0,ACR1
move.l d0,_rt_acr1 // sichern move.l d0,_rt_acr1 // save
move.l #0xe007C400,d0 // instruction r wt e000'0000-e07f'ffff move.l #0xe007C400,d0 // instruction r wt e000'0000-e07f'ffff
movec d0,ACR2 movec d0,ACR2
move.l d0,_rt_acr2 // sichern move.l d0,_rt_acr2 // save
clr.l d0 // acr3 aus clr.l d0 // acr3 off
movec d0,ACR3 movec d0,ACR3
move.l d0,_rt_acr3 // sichern move.l d0,_rt_acr3 // save
move.l #__MMUBAR+1,d0 move.l #__MMUBAR+1,d0
movec d0,MMUBAR //mmubar setzen movec d0,MMUBAR // set MMUBAR
move.l d0,_rt_mmubar // sichern move.l d0,_rt_mmubar // save
nop nop
@@ -188,8 +188,8 @@ _mmutr_miss:
or.l #cb_mmudr,d0 or.l #cb_mmudr,d0
move.l d0,MCF_MMU_MMUDR move.l d0,MCF_MMU_MMUDR
moveq.l #mmuord_d,d0 // MMU update data moveq.l #mmuord_d,d0 // MMU update data
move.l d0,MCF_MMU_MMUOR // setzen move.l d0,MCF_MMU_MMUOR // set
moveq.l #mmuord_i,d0 // MMU update instruction moveq.l #mmuord_i,d0 // MMU update instruction
move.l d0,MCF_MMU_MMUOR // setzen move.l d0,MCF_MMU_MMUOR // set
move.l (sp)+,d0 move.l (sp)+,d0
rte rte