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stack was misaligned

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Markus Fröschle
2013-11-19 14:59:20 +00:00
parent 1c1362f33a
commit a97d38e9f9
2 changed files with 5 additions and 2 deletions
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4
sources/exceptions.S
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@@ -554,7 +554,9 @@ access_mmu:
move.l MCF_MMU_MMUAR,d0
cmp.l #__FASTRAM_END,d0 // above max User RAM area?
bge bus_error // -> bus error
bra _mmutr_miss // else we have an MMU TLB miss
bsr _mmutr_miss // else we have an MMU TLB miss
move.l (sp)+,d0 // restore register
rte
bus_error:
move.l (sp)+,d0 // restore register