From a7eb46e1587069f76beac16aae8dfc8b06fe1256 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 25 Dec 2014 10:08:53 +0000 Subject: [PATCH] used design assistant to force the fitter to put more effort into getting the timing right which removed negative slack --- vhdl/backend/Altera/Firebee/firebee.qsf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vhdl/backend/Altera/Firebee/firebee.qsf b/vhdl/backend/Altera/Firebee/firebee.qsf index 1771384..13a6b38 100755 --- a/vhdl/backend/Altera/Firebee/firebee.qsf +++ b/vhdl/backend/Altera/Firebee/firebee.qsf @@ -374,9 +374,9 @@ set_location_assignment PIN_U1 -to SCSI_DRQn set_location_assignment PIN_H1 -to SCSI_CDn set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL NORMAL -set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL set_global_assignment -name EDA_TEST_BENCH_NAME ddr_ctlr_tb -section_id eda_simulation set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ddr_ctlr_tb