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get rid of CLK33M

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This commit is contained in:
Markus Fröschle
2015-09-20 12:32:02 +00:00
parent 2addea7cf3
commit a7bf118e2d
5 changed files with 57 additions and 470 deletions
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23
Video/DDR_CTR.tdf
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@@ -225,15 +225,16 @@ BEGIN
DDR_CS.CLK = MAIN_CLK;
DDR_CS.ENA = FB_ALE;
DDR_CS = DDR_SEL;
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
CPU_REQ.CLK = DDR_SYNC_66M;
CPU_REQ = CPU_SIG
# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
BUS_CYC.CLK = DDRCLK0;
BUS_CYC = BUS_CYC & !BUS_CYC_END;
-- STATE MACHINE SYNCHRONISIEREN -----------------
MCS[].CLK = DDRCLK0;
MCS0 = MAIN_CLK;
@@ -341,7 +342,7 @@ BEGIN
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN
DDR_SM = DS_T5R;
@@ -383,7 +384,7 @@ BEGIN
VCAS = VCC;
VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W;
@@ -391,7 +392,7 @@ BEGIN
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
DDR_SM = DS_T8W;
WHEN DS_T8W =>
@@ -523,12 +524,12 @@ BEGIN
-- CLOSE FIFO BANK
WHEN DS_CB6 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_N7;
WHEN DS_CB8 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_T1;
-- REFRESH 70NS = 10 ZYCLEN
@@ -584,14 +585,14 @@ BEGIN
FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
FIFO_BANK_OK.CLK = DDRCLK0;
FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
CLR_FIFO_SYNC.CLK =DDRCLK0;
CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN
CLEAR_FIFO_CNT.CLK = DDRCLK0;
CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
STOP.CLK = DDRCLK0;
STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-- Z<>HLEN -----------------------------------------------
-- Z<>HLEN -----------------------------------------------
VIDEO_ADR_CNT[].CLK = DDRCLK0;
VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
@@ -608,12 +609,12 @@ BEGIN
-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
-----------------------------------------------------------------------------------------
DDR_REFRESH_CNT[].CLK = CLK33M;
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
REFRESH_TIME.CLK = DDRCLK0;
REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC
DDR_REFRESH_SIG[].CLK = DDRCLK0;
DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
# !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT
DDR_REFRESH_REQ.CLK = DDRCLK0;
DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;