make ModelSim compile work

This commit is contained in:
Markus Fröschle
2015-09-08 16:30:44 +00:00
parent ce916f80df
commit a60aa7fcc0
3 changed files with 1000 additions and 1946 deletions

View File

@@ -72,8 +72,8 @@
-- Revision 2K6B 2006/11/07 WF
-- Modified Source to compile with the Xilinx ISE.
-- Top level file provided for SOC (systems on programmable chips).
-- Revision 2K8A 2008/07/14 WF
-- Minor changes.
-- Revision 2K8A 2008/07/14 WF
-- Minor changes.
--
library ieee;
@@ -119,6 +119,7 @@ signal ADR_I : bit_vector(3 downto 0);
signal CTRL_REG : bit_vector(7 downto 0);
signal PORT_A : bit_vector(7 downto 0);
signal PORT_B : bit_vector(7 downto 0);
SIGNAL bsel : bit_vector(2 DOWNTO 0);
begin
P_WAVSTRB: process(RESETn, SYS_CLK)
variable LOCK : boolean;
@@ -143,8 +144,8 @@ begin
end if;
end if;
end process P_WAVSTRB;
with BDIR & BC2 & BC1 select
bsel <= bdir & bc2 & bc1;
with bsel select
BUSCYCLE <= INACTIVE when "000" | "010" | "101",
ADDRESS when "001" | "100" | "111",
R_READ when "011",