make ModelSim compile work
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@@ -72,8 +72,8 @@
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-- Revision 2K6B 2006/11/07 WF
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-- Modified Source to compile with the Xilinx ISE.
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-- Top level file provided for SOC (systems on programmable chips).
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-- Revision 2K8A 2008/07/14 WF
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-- Minor changes.
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-- Revision 2K8A 2008/07/14 WF
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-- Minor changes.
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--
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library ieee;
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@@ -119,6 +119,7 @@ signal ADR_I : bit_vector(3 downto 0);
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signal CTRL_REG : bit_vector(7 downto 0);
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signal PORT_A : bit_vector(7 downto 0);
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signal PORT_B : bit_vector(7 downto 0);
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SIGNAL bsel : bit_vector(2 DOWNTO 0);
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begin
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P_WAVSTRB: process(RESETn, SYS_CLK)
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variable LOCK : boolean;
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@@ -143,8 +144,8 @@ begin
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end if;
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end if;
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end process P_WAVSTRB;
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with BDIR & BC2 & BC1 select
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bsel <= bdir & bc2 & bc1;
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with bsel select
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BUSCYCLE <= INACTIVE when "000" | "010" | "101",
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ADDRESS when "001" | "100" | "111",
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R_READ when "011",
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