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card and ROM now properly detected, but bios emulator hangs in endless loop

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This commit is contained in:
Markus Fröschle
2013-12-31 15:24:10 +00:00
parent 17d11c23f0
commit a48aa15fe6
2 changed files with 48 additions and 38 deletions
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41
BaS_gcc/radeon/radeon_base.c
View File

@@ -1939,31 +1939,32 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
else else
rinfo->vram_width = 64; rinfo->vram_width = 64;
} }
/* This may not be correct, as some cards can have half of channel disabled
/*
* This may not be correct, as some cards can have half of channel disabled
* ToDo: identify these cases * ToDo: identify these cases
*/ */
dbg("radeonfb:");
switch(rinfo->family) switch(rinfo->family)
{ {
case CHIP_FAMILY_LEGACY: dbg("LEGACY"); break; case CHIP_FAMILY_LEGACY: dbg("%s chip type: %s\r\n", __FUNCTION__, "LEGACY"); break;
case CHIP_FAMILY_RADEON: dbg("RADEON"); break; case CHIP_FAMILY_RADEON: dbg("%s chip type: %s\r\n", __FUNCTION__, "RADEON"); break;
case CHIP_FAMILY_RV100: dbg("RV100"); break; case CHIP_FAMILY_RV100: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV100"); break;
case CHIP_FAMILY_RS100: dbg("RS100"); break; case CHIP_FAMILY_RS100: dbg("%s chip type: %s\r\n", __FUNCTION__, "RS100"); break;
case CHIP_FAMILY_RV200: dbg("RV200"); break; case CHIP_FAMILY_RV200: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV200"); break;
case CHIP_FAMILY_RS200: dbg("RS200"); break; case CHIP_FAMILY_RS200: dbg("%s chip type: %s\r\n", __FUNCTION__, "RS200"); break;
case CHIP_FAMILY_R200: dbg("R200"); break; case CHIP_FAMILY_R200: dbg("%s chip type: %s\r\n", __FUNCTION__, "R200"); break;
case CHIP_FAMILY_RV250: dbg("RV250"); break; case CHIP_FAMILY_RV250: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV250"); break;
case CHIP_FAMILY_RS300: dbg("RS300"); break; case CHIP_FAMILY_RS300: dbg("%s chip type: %s\r\n", __FUNCTION__, "RS300"); break;
case CHIP_FAMILY_RV280: dbg("RV280"); break; case CHIP_FAMILY_RV280: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV280"); break;
case CHIP_FAMILY_R300: dbg("R300"); break; case CHIP_FAMILY_R300: dbg("%s chip type: %s\r\n", __FUNCTION__, "R300"); break;
case CHIP_FAMILY_R350: dbg("R350"); break; case CHIP_FAMILY_R350: dbg("%s chip type: %s\r\n", __FUNCTION__, "R350"); break;
case CHIP_FAMILY_RV350: dbg("RV350"); break; case CHIP_FAMILY_RV350: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV350"); break;
case CHIP_FAMILY_RV380: dbg("RV380"); break; case CHIP_FAMILY_RV380: dbg("%s chip type: %s\r\n", __FUNCTION__, "RV380"); break;
case CHIP_FAMILY_R420: dbg("R420"); break; case CHIP_FAMILY_R420: dbg("%s chip type: %s\r\n", __FUNCTION__, "R420"); break;
default: dbg("UNKNOW"); break; default: dbg("%s chip type: %s\r\n", "UNKNOW"); break;
} }
dbg("%s: found %d KB of %s %d bits wide video RAM\r\n", __FUNCTION__, rinfo->video_ram / 1024, dbg("%s: found %d KB of %d bits wide %s video RAM\r\n", __FUNCTION__, rinfo->video_ram / 1024,
rinfo->vram_ddr ? "DDR " : "SDRAM ", rinfo->vram_width); rinfo->vram_width, rinfo->vram_ddr ? "DDR " : "SDRAM ");
} }
int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent) int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)

43
BaS_gcc/x86emu/x86biosemu.c
View File

@@ -105,10 +105,10 @@ uint8_t inb(uint16_t port)
if ((port >= offset_port) && (port <= offset_port + 0xFF)) if ((port >= offset_port) && (port <= offset_port + 0xFF))
{ {
dbg("%s:\r\n", __FUNCTION__); //dbg("%s:\r\n", __FUNCTION__);
val = *(uint8_t *)(offset_io+(uint32_t)port); val = *(uint8_t *)(offset_io+(uint32_t)port);
dbg("%s: inb(0x%x) = 0x%x\r\n", __FUNCTION__, port, val); //dbg("%s: inb(0x%x) = 0x%x\r\n", __FUNCTION__, port, val);
} }
return val; return val;
} }
@@ -119,9 +119,9 @@ uint16_t inw(uint16_t port)
if ((port >= offset_port) && (port <= offset_port+0xFF)) if ((port >= offset_port) && (port <= offset_port+0xFF))
{ {
dbg("inw("); //dbg("inw(");
val = swpw(*(uint16_t *)(offset_io+(uint32_t)port)); val = swpw(*(uint16_t *)(offset_io+(uint32_t)port));
dbg("0x%x) = 0x%x\r\n", port, val); //dbg("0x%x) = 0x%x\r\n", port, val);
} }
return val; return val;
} }
@@ -131,15 +131,15 @@ uint32_t inl(uint16_t port)
uint32_t val = 0; uint32_t val = 0;
if ((port >= offset_port) && (port <= offset_port+0xFF)) if ((port >= offset_port) && (port <= offset_port+0xFF))
{ {
dbg("inl("); //dbg("inl(");
val = swpl(*(uint32_t *)(offset_io+(uint32_t)port)); val = swpl(*(uint32_t *)(offset_io+(uint32_t)port));
dbg("0x%x) = 0x%x\r\n", port, val); //dbg("0x%x) = 0x%x\r\n", port, val);
} }
else if (port == 0xCF8) else if (port == 0xCF8)
{ {
dbg("inl("); //dbg("inl(");
val = config_address_reg; val = config_address_reg;
dbg("0x%x) = 0x%x\r\n", port, val); //dbg("0x%x) = 0x%x\r\n", port, val);
} }
else if ((port == 0xCFC) && ((config_address_reg & 0x80000000) != 0)) else if ((port == 0xCFC) && ((config_address_reg & 0x80000000) != 0))
{ {
@@ -155,16 +155,21 @@ uint32_t inl(uint16_t port)
val = pci_read_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC); val = pci_read_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC);
break; break;
} }
dbg("inl(0x%x) = 0x%x\r\n", port, val); //dbg("inl(0x%x) = 0x%x\r\n", port, val);
} }
return val; return val;
} }
#ifdef DBG_X86EMU
#undef DBG_X86EMU
#define DBG_
#endif
void outb(uint8_t val, uint16_t port) void outb(uint8_t val, uint16_t port)
{ {
if ((port >= offset_port) && (port <= offset_port + 0xFF)) if ((port >= offset_port) && (port <= offset_port + 0xFF))
{ {
dbg("outb(0x%x, 0x%x)\r\n", port, val); //dbg("outb(0x%x, 0x%x)\r\n", port, val);
*(uint8_t *)(offset_io + (uint32_t) port) = val; *(uint8_t *)(offset_io + (uint32_t) port) = val;
} }
} }
@@ -173,7 +178,7 @@ void outw(uint16_t val, uint16_t port)
{ {
if ((port >= offset_port) && (port <= offset_port + 0xFF)) if ((port >= offset_port) && (port <= offset_port + 0xFF))
{ {
dbg("outw(0x%x, 0x%x)\r\n", port, val); //dbg("outw(0x%x, 0x%x)\r\n", port, val);
*(uint16_t *)(offset_io + (uint32_t) port) = swpw(val); *(uint16_t *)(offset_io + (uint32_t) port) = swpw(val);
} }
} }
@@ -182,12 +187,12 @@ void outl(uint32_t val, uint16_t port)
{ {
if ((port >= offset_port) && (port <= offset_port + 0xFF)) if ((port >= offset_port) && (port <= offset_port + 0xFF))
{ {
dbg("outl(0x%x, 0x%x)\r\n", port, val); //dbg("outl(0x%x, 0x%x)\r\n", port, val);
*(uint32_t *)(offset_io + (uint32_t) port) = swpl(val); *(uint32_t *)(offset_io + (uint32_t) port) = swpl(val);
} }
else if (port == 0xCF8) else if (port == 0xCF8)
{ {
dbg("outl(0x%x, 0x%x)\r\n", port, val); //dbg("outl(0x%x, 0x%x)\r\n", port, val);
config_address_reg = val; config_address_reg = val;
} }
else if ((port == 0xCFC) && ((config_address_reg & 0x80000000) !=0)) else if ((port == 0xCFC) && ((config_address_reg & 0x80000000) !=0))
@@ -196,12 +201,16 @@ void outl(uint32_t val, uint16_t port)
offset_port = (uint16_t)val & 0xFFFC; offset_port = (uint16_t)val & 0xFFFC;
else else
{ {
dbg("outl(0x%x, 0x%x)\r\n", port, val); //dbg("outl(0x%x, 0x%x)\r\n", port, val);
pci_write_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC, val); pci_write_config_longword(rinfo_biosemu->handle, config_address_reg & 0xFC, val);
} }
} }
} }
#ifdef DBG_
#define DBG_X86EMU
#endif
/* Interrupt multiplexer */ /* Interrupt multiplexer */
void do_int(int num) void do_int(int num)
@@ -387,8 +396,7 @@ static uint8_t find_vga_entry(uint8_t mode)
line=i; line=i;
break; break;
} }
} } return(line);
return(line);
} }
void biosfn_set_video_mode(uint8_t mode) void biosfn_set_video_mode(uint8_t mode)
@@ -565,7 +573,8 @@ void run_bios(struct radeonfb_info *rinfo)
rom_size = (unsigned long) BIOS_IN8((long) &rom_header->size) * 512; rom_size = (unsigned long) BIOS_IN8((long) &rom_header->size) * 512;
if (PCI_CLASS_DISPLAY_VGA == BIOS_IN16((long) &rom_data->class_hi)) if (PCI_CLASS_DISPLAY_VGA == BIOS_IN16((long) &rom_data->class_hi))
{ {
biosmem = driver_mem_alloc(SIZE_EMU); //biosmem = driver_mem_alloc(SIZE_EMU);
biosmem = (char *) 0x100000;
if (biosmem == 0) if (biosmem == 0)
{ {
dbg("%s: could not allocate X86 BIOS memory\r\n", __FUNCTION__); dbg("%s: could not allocate X86 BIOS memory\r\n", __FUNCTION__);