patch with Fredi's lp fix (and others)
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@@ -64,7 +64,7 @@ type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS);
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component WF2149IP_WAVE
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port(
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RESETn : in bit;
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SYS_CLK : in std_logic;
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SYS_CLK : in bit;
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WAV_STRB : in bit;
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@@ -83,7 +83,7 @@ LIBRARY ieee;
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ENTITY WF2149IP_TOP_SOC IS
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PORT(
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SYS_CLK : IN std_logic; -- Read the inforation in the header!
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SYS_CLK : in bit; -- Read the inforation in the header!
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RESETn : IN bit;
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WAV_CLK : IN bit; -- Read the inforation in the header!
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@@ -110,7 +110,7 @@ ENTITY WF2149IP_TOP_SOC IS
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);
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END WF2149IP_TOP_SOC;
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ARCHITECTURE rtl OF WF2149IP_TOP_SOC IS
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architecture STRUCTURE of WF2149IP_TOP_SOC is
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SIGNAL BUSCYCLE : BUSCYCLES;
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SIGNAL DATA_OUT_I : std_logic_vector(7 DOWNTO 0);
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SIGNAL DATA_EN_I : bit;
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@@ -127,11 +127,10 @@ BEGIN
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IF RESETn = '0' THEN
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LOCK := false;
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TMP := '0';
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ELSIF rising_edge(SYS_CLK) THEN
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elsif SYS_CLK = '1' and SYS_CLK' event then
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IF WAV_CLK = '1' and LOCK = false THEN
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LOCK := true;
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TMP := not TMP; -- Divider by 2.
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CASE SELn IS
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WHEN '1' => WAV_STRB <= '1';
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WHEN OTHERS => WAV_STRB <= TMP;
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@@ -158,7 +157,7 @@ BEGIN
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BEGIN
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IF RESETn = '0' THEN
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ADR_I <= (OTHERS => '0');
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ELSIF rising_edge(SYS_CLK) THEN
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elsif SYS_CLK = '1' and SYS_CLK' event then
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IF BUSCYCLE = ADDRESS AND A9n = '0' AND A8 = '1' AND DA_IN(7 DOWNTO 4) = x"0" THEN
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ADR_I <= To_BitVector(DA_IN(3 DOWNTO 0));
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END IF;
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@@ -170,7 +169,7 @@ BEGIN
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BEGIN
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IF RESETn = '0' THEN
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CTRL_REG <= x"00";
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ELSIF rising_edge(SYS_CLK) THEN
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elsif SYS_CLK = '1' and SYS_CLK' event then
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IF BUSCYCLE = R_WRITE AND ADR_I = x"7" THEN
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CTRL_REG <= To_BitVector(DA_IN);
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END IF;
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@@ -182,7 +181,7 @@ BEGIN
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IF RESETn = '0' THEN
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PORT_A <= x"00";
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PORT_B <= x"00";
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ELSIF rising_edge(SYS_CLK) THEN
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elsif SYS_CLK = '1' and SYS_CLK' event then
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IF BUSCYCLE = R_WRITE AND ADR_I = x"E" THEN
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PORT_A <= To_BitVector(DA_IN);
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ELSIF BUSCYCLE = R_WRITE and ADR_I = x"F" THEN
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@@ -227,4 +226,4 @@ BEGIN
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To_StdLogicVector(IO_B_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE
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To_StdLogicVector(CTRL_REG) WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE (OTHERS => '0');
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END rtl;
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end STRUCTURE;
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@@ -65,7 +65,7 @@ use work.wf2149ip_pkg.all;
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entity WF2149IP_WAVE is
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port(
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RESETn : in bit;
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SYS_CLK : in std_logic;
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SYS_CLK : in bit;
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WAV_STRB : in bit;
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