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fixed missing data_in

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This commit is contained in:
Markus Fröschle
2014-12-21 11:13:58 +00:00
parent ff7faf4395
commit 9d7858a144
1 changed files with 66 additions and 66 deletions
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132
vhdl/testbenches/ddr_ctlr_tb.vhd
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@@ -17,42 +17,42 @@ ARCHITECTURE beh OF ddr_ctlr_tb IS
SIGNAL clock : STD_LOGIC := '0'; -- main clock
SIGNAL ddr_clk : STD_LOGIC := '0'; -- ddr clock
SIGNAL FB_ADR : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL DDR_SYNC_66M : STD_LOGIC := '0';
SIGNAL FB_CS1_n : STD_LOGIC;
SIGNAL FB_OE_n : STD_LOGIC := '1'; -- only write cycles for now
SIGNAL FB_SIZE0 : STD_LOGIC := '1';
SIGNAL FB_SIZE1 : STD_LOGIC := '1'; -- long word access
SIGNAL FB_ALE : STD_LOGIC := 'Z'; -- defined reset state
SIGNAL FB_WRn : STD_LOGIC;
SIGNAL FIFO_CLR : STD_LOGIC;
SIGNAL VIDEO_RAM_CTR : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL BLITTER_ADR : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL BLITTER_SIG : STD_LOGIC;
SIGNAL BLITTER_WR : STD_LOGIC;
SIGNAL fb_adr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ddr_sync_66m : STD_LOGIC := '0';
SIGNAL fb_cs1_n : STD_LOGIC;
SIGNAL fb_oe_n : STD_LOGIC := '1'; -- only write cycles for now
SIGNAL fb_size0 : STD_LOGIC := '1';
SIGNAL fb_size1 : STD_LOGIC := '1'; -- long word access
SIGNAL fb_ale : STD_LOGIC := 'Z'; -- defined reset state
SIGNAL fb_wr_n : STD_LOGIC;
SIGNAL fifo_clr : STD_LOGIC;
SIGNAL video_ram_ctr : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL blitter_adr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL blitter_sig : STD_LOGIC;
SIGNAL blitter_wr : STD_LOGIC;
SIGNAL ddrclk0 : STD_LOGIC;
SIGNAL CLK_33M : STD_LOGIC := '0';
SIGNAL FIFO_MW : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL clk_33m : STD_LOGIC := '0';
SIGNAL fifo_mw : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL va : STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL vwe_n : STD_LOGIC;
SIGNAL vras_n : STD_LOGIC;
SIGNAL vcs_n : STD_LOGIC;
SIGNAL vcke : STD_LOGIC;
SIGNAL vcas_n : STD_LOGIC;
SIGNAL FB_LE : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL FB_VDOE : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SR_FIFO_WRE : STD_LOGIC;
SIGNAL SR_DDR_FB : STD_LOGIC;
SIGNAL SR_DDR_WR : STD_LOGIC;
SIGNAL SR_DDRWR_D_SEL : STD_LOGIC;
SIGNAL fb_le : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL fb_vdoe : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sr_fifo_wre : STD_LOGIC;
SIGNAL sr_ddr_fb : STD_LOGIC;
SIGNAL sr_ddr_wr : STD_LOGIC;
SIGNAL sr_ddrwr_d_sel : STD_LOGIC;
SIGNAL sr_vdmp : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL VIDEO_DDR_TA : STD_LOGIC;
SIGNAL SR_BLITTER_DACK : STD_LOGIC;
SIGNAL video_ddr_ta : STD_LOGIC;
SIGNAL sr_blitter_dack : STD_LOGIC;
SIGNAL ba : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL DDRWR_D_SEL1 : STD_LOGIC;
SIGNAL VDM_SEL : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DATA_IN : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL DATA_OUT : STD_LOGIC_VECTOR(31 DOWNTO 16);
SIGNAL ddrwr_d_sel1 : STD_LOGIC;
SIGNAL vdm_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_in : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 16);
SIGNAL data_en_h : STD_LOGIC;
SIGNAL data_en_l : STD_LOGIC;
@@ -63,43 +63,43 @@ BEGIN
t : DDR_CTRL
PORT map
(
CLK_MAIN => clock,
DDR_SYNC_66M => DDR_SYNC_66M,
FB_ADR => FB_ADR,
FB_CS1_n => fb_cs1_n,
FB_OE_n => FB_OE_n,
FB_SIZE0 => FB_SIZE0,
FB_SIZE1 => FB_SIZE1,
FB_ALE => FB_ALE,
FB_WR_n => FB_WRn,
FIFO_CLR => FIFO_CLR,
video_control_register => VIDEO_RAM_CTR,
BLITTER_ADR => BLITTER_ADR,
BLITTER_SIG => BLITTER_SIG,
BLITTER_WR => BLITTER_WR,
clk_main => clock,
ddr_sync_66m => ddr_sync_66m,
fb_adr => fb_adr,
fb_cs1_n => fb_cs1_n,
fb_oe_n => fb_oe_n,
fb_size0 => fb_size0,
fb_size1 => fb_size1,
fb_ale => fb_ale,
FB_WR_n => fb_wr_n,
fifo_clr => fifo_clr,
video_control_register => video_ram_ctr,
blitter_adr => blitter_adr,
blitter_sig => blitter_sig,
blitter_wr => blitter_wr,
ddrclk0 => ddrclk0,
CLK_33M => CLK_33M,
FIFO_MW => FIFO_MW,
clk_33m => clk_33m,
fifo_mw => fifo_mw,
va => va,
vwe_n => vwe_n,
vras_n => vras_n,
vcs_n => vcs_n,
vcke => vcke,
vcas_n => vcas_n,
FB_LE => FB_LE,
FB_VDOE => FB_VDOE,
SR_FIFO_WRE => SR_FIFO_WRE,
SR_DDR_FB => SR_DDR_FB,
SR_DDR_WR => SR_DDR_WR,
SR_DDRWR_D_SEL => SR_DDRWR_D_SEL,
fb_le => fb_le,
fb_vdoe => fb_vdoe,
sr_fifo_wre => sr_fifo_wre,
sr_ddr_fb => sr_ddr_fb,
sr_ddr_wr => sr_ddr_wr,
sr_ddrwr_d_sel => sr_ddrwr_d_sel,
sr_vdmp => sr_vdmp,
VIDEO_DDR_TA => VIDEO_DDR_TA,
SR_BLITTER_DACK => SR_BLITTER_DACK,
video_ddr_ta => video_ddr_ta,
sr_blitter_dack => sr_blitter_dack,
ba => ba,
DDRWR_D_SEL1 => DDRWR_D_SEL1,
VDM_SEL => VDM_SEL,
DATA_IN => DATA_IN,
DATA_OUT => DATA_OUT,
ddrwr_d_sel1 => ddrwr_d_sel1,
vdm_sel => vdm_sel,
data_in => data_in,
data_out => data_out,
data_en_h => data_en_h,
data_en_l => data_en_l
);
@@ -133,14 +133,14 @@ BEGIN
stimulate_33mHz_clock : process
BEGIN
WAIT FOR 30.3 ns;
CLK_33M <= NOT CLK_33M;
clk_33m <= NOT clk_33m;
END process;
stimulate_66MHz_clock : process
BEGIN
WAIT FOR 66.6 ns;
DDR_SYNC_66M <= NOT DDR_SYNC_66M;
ddrclk0 <= DDR_SYNC_66M;
ddr_sync_66m <= NOT ddr_sync_66m;
ddrclk0 <= ddr_sync_66m;
END process;
stimulate : process
@@ -150,25 +150,25 @@ BEGIN
CASE bus_state IS
WHEN S0 =>
-- address phase
FB_ADR <= adr;
FB_ALE <= '1';
FB_WRn <= '0';
fb_adr <= adr;
fb_ale <= '1';
fb_wr_n <= '0';
bus_state <= S1;
WHEN S1 =>
-- data phase
FB_ALE <= '0';
fb_ale <= '0';
fb_cs1_n <= '0';
FB_ADR <= x"47114711";
if (VIDEO_DDR_TA = '1') then
fb_adr <= x"47114711";
if (video_ddr_ta = '1') then
bus_state <= S2;
END if;
WHEN S2 =>
fb_cs1_n <= '0';
bus_state <= S3;
WHEN S3 =>
FB_ADR <= STD_LOGIC_VECTOR(UNSIGNED(FB_ADR) + 4);
fb_adr <= STD_LOGIC_VECTOR(UNSIGNED(fb_adr) + 4);
bus_state <= S0;
FB_WRn <= 'Z';
fb_wr_n <= 'Z';
WHEN others =>
REPORT("bus_state: ");
END CASE;