refactored assembler routines from exceptions.S into mmu.c (access exception handler). Seems to be better, but still hang.
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@@ -60,12 +60,12 @@
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#error "unknown machine!"
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#endif /* MACHINE_FIREBEE */
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//#define DEBUG_MMU
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#ifdef DEBUG_MMU
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#define DBG_MMU
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#ifdef DBG_MMU
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#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg);} while(0)
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#else
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#define dbg(format, arg...) do {;} while (0)
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#endif /* DEBUG_MMU */
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#endif /* DBG_MMU */
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/*
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* set ASID register
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@@ -404,12 +404,14 @@ bool access_exception(uint32_t pc, uint32_t format_status)
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int fault_status;
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uint32_t fault_address;
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bool is_tlb_miss = false; /* assume access error is not a TLB miss */
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extern uint8_t __FASTRAM_END[];
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uint32_t FASTRAM_END = (uint32_t) &__FASTRAM_END[0];
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extern uint8_t _FASTRAM_END[];
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uint32_t FASTRAM_END = (uint32_t) &_FASTRAM_END[0];
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fault_status = (((format_status & 0xc000000) >> 26) |
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fault_status = (((format_status & 0xc000000) >> 24) |
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((format_status & 0x30000) >> 16));
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dbg("%s: pc=%p, format_status = %p, fault_status = 0x%x\r\n", __FUNCTION__, pc, format_status, fault_status);
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/*
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* determine if access fault was caused by a TLB miss
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*/
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@@ -419,6 +421,7 @@ bool access_exception(uint32_t pc, uint32_t format_status)
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case 0x6: /* TLB miss on extension word of instruction fetch */
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case 0xa: /* TLB miss on data write */
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case 0xe: /* TLB miss on data read or read-modify-write */
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dbg("%s: access fault because of TLB miss at %p\r\n", __FUNCTION__, pc);
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is_tlb_miss = true;
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break;
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@@ -449,13 +452,13 @@ bool access_exception(uint32_t pc, uint32_t format_status)
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}
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}
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}
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return is_tlb_miss;
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return false;
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}
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void mmutr_miss(uint32_t address)
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{
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dbg("MMU TLB MISS at 0x%08x\r\n", address);
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dbg("MMU TLB MISS accessing 0x%08x\r\n", address);
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flush_and_invalidate_caches();
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/* add missed page to TLB */
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