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modified _VRAM storage class to volatile

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This commit is contained in:
Markus Fröschle
2012-10-17 20:31:30 +00:00
parent 12a26ab3cc
commit 9be86515a0
1 changed files with 13 additions and 13 deletions
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26
BaS_GNU/BaS_GNU/sources/sysinit.c
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@@ -12,7 +12,7 @@
#include "cache.h" #include "cache.h"
#include "sysinit.h" #include "sysinit.h"
extern unsigned long _VRAM; extern volatile long _VRAM;
extern unsigned long BaS; extern unsigned long BaS;
extern int copy_end(); extern int copy_end();
@@ -218,29 +218,29 @@ void init_pll(void)
* (volatile uint16_t *) (pll_base + 0x48) = 0x27; /* loopfilter r */ * (volatile uint16_t *) (pll_base + 0x48) = 0x27; /* loopfilter r */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */ * (volatile uint16_t *) (pll_base + 0x08) = 1; /* charge pump 1 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */ * (volatile uint16_t *) (pll_base + 0x00) = 12; /* N counter high = 12 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */ * (volatile uint16_t *) (pll_base + 0x40) = 12; /* N counter low = 12 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */ * (volatile uint16_t *) (pll_base + 0x114) = 1; /* ck1 bypass */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */ * (volatile uint16_t *) (pll_base + 0x118) = 1; /* ck2 bypass */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */ * (volatile uint16_t *) (pll_base + 0x11c) = 1; /* ck3 bypass */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */ * (volatile uint16_t *) (pll_base + 0x10) = 1; /* ck0 high = 1 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */ * (volatile uint16_t *) (pll_base + 0x50) = 1; /* ck0 low = 1 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */ * (volatile uint16_t *) (pll_base + 0x144) = 1; /* M odd division */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */ * (volatile uint16_t *) (pll_base + 0x44) = 1; /* M low = 1 */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */ * (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */
wait_pll(); wait_pll();
* (volatile uint8_t *) 0xf0000800 = 0; /* set */ * (volatile uint8_t *) 0xf0000800 = 0; /* set */
uart_out_word('SET!'); uart_out_word('SET!');
uart_out_word(0x0a0d); uart_out_word(0x0a0d);
@@ -255,7 +255,7 @@ void init_pll(void)
#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory") #define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
void init_video_ddr(void) { void init_video_ddr(void) {
* (uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */ * (volatile uint16_t *) 0xf0000400 = 0xb; /* set cke = 1, cs=1, config = 1 */
NOP(); NOP();
_VRAM = 0x00050400; /* IPALL */ _VRAM = 0x00050400; /* IPALL */