Firebee/FireBee_SVN
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fixed missing (not "translated" from the original .tdf) statements

Browse Source
This commit is contained in:
Markus Fröschle
2014-08-14 05:33:56 +00:00
parent 3691c94c5c
commit 9b1cb2255b
1 changed files with 136 additions and 130 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
View File

@@ -232,7 +232,7 @@ begin
end if; end if;
when FR_S2 => when FR_S2 =>
if DDR_CS = '1' and BUS_CYC = '0' and ACCESS_WIDTH = LONG and FB_WRn = '0' then -- Eventually wait during long word access. if DDR_CS = '1' and BUS_CYC = '0' and ACCESS_WIDTH = LONG and FB_WRn = '0' then -- wait during long word access if needed
FB_REGDDR_NEXT <= FR_S2; FB_REGDDR_NEXT <= FR_S2;
elsif DDR_CS = '1' then elsif DDR_CS = '1' then
FB_REGDDR_NEXT <= FR_S3; FB_REGDDR_NEXT <= FR_S3;
@@ -279,7 +279,7 @@ begin
end process DDR_STATE_REG; end process DDR_STATE_REG;
DDR_STATE_DEC: process(DDR_STATE, DDR_REFRESH_REQ, CPU_DDR_SYNC, DDR_CONFIG, FB_WRn, DDR_ACCESS, BLITTER_WR, FIFO_REQ, FIFO_BANK_OK, DDR_STATE_DEC: process(DDR_STATE, DDR_REFRESH_REQ, CPU_DDR_SYNC, DDR_CONFIG, FB_WRn, DDR_ACCESS, BLITTER_WR, FIFO_REQ, FIFO_BANK_OK,
FIFO_MW, CPU_REQ, VIDEO_ADR_CNT, DDR_SEL, FB_SIZE1, FB_SIZE0, DATA_IN, FIFO_BA, DDR_REFRESH_SIG) FIFO_MW, CPU_REQ, VIDEO_ADR_CNT, DDR_SEL, TSIZ, DATA_IN, FIFO_BA, DDR_REFRESH_SIG)
begin begin
case DDR_STATE is case DDR_STATE is
when DS_T1 => when DS_T1 =>
@@ -392,7 +392,7 @@ begin
end if; end if;
when DS_T10F => when DS_T10F =>
if DDR_SEL = '1' and (FB_WRn = '1' or (FB_SIZE0 and FB_SIZE1) = '0') and DATA_IN(13 downto 12) /= FIFO_BA then if DDR_SEL = '1' and (FB_WRn = '1' or TSIZ /= "11") and DATA_IN(13 downto 12) /= FIFO_BA then
DDR_NEXT_STATE <= DS_T3; DDR_NEXT_STATE <= DS_T3;
else else
DDR_NEXT_STATE <= DS_T7F; DDR_NEXT_STATE <= DS_T7F;
@@ -529,13 +529,13 @@ begin
BUS_CYC <= '1'; BUS_CYC <= '1';
elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' then elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' then
BUS_CYC <= '1'; BUS_CYC <= '1';
elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and (FB_SIZE0 = '0' or FB_SIZE1= '0') then elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and ACCESS_WIDTH /= LONG then
BUS_CYC <= '1'; BUS_CYC <= '1';
elsif DDR_STATE = DS_T2B then elsif DDR_STATE = DS_T2B then
BUS_CYC <= '1'; BUS_CYC <= '1';
elsif DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA then elsif DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA then
BUS_CYC <= '1'; BUS_CYC <= '1';
elsif DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA then elsif DDR_STATE = DS_T10F and ACCESS_WIDTH /= LONG and DATA_IN(13 downto 12) = FIFO_BA then
BUS_CYC <= '1'; BUS_CYC <= '1';
elsif DDR_STATE = DS_C3 then elsif DDR_STATE = DS_C3 then
BUS_CYC <= CPU_REQ; BUS_CYC <= CPU_REQ;
@@ -556,7 +556,7 @@ begin
elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' then elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' then
VA_S(10) <= '1'; VA_S(10) <= '1';
DDR_ACCESS <= CPU; DDR_ACCESS <= CPU;
elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and (FB_SIZE0 = '0' or FB_SIZE1= '0') then elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and ACCESS_WIDTH /= LONG then
VA_S(10) <= '1'; VA_S(10) <= '1';
DDR_ACCESS <= CPU; DDR_ACCESS <= CPU;
elsif DDR_STATE = DS_T2A then elsif DDR_STATE = DS_T2A then
@@ -564,6 +564,9 @@ begin
VA_S(10) <= not (FIFO_ACTIVE and FIFO_REQ); VA_S(10) <= not (FIFO_ACTIVE and FIFO_REQ);
DDR_ACCESS <= FIFO; DDR_ACCESS <= FIFO;
FIFO_BANK_OK <= FIFO_ACTIVE and FIFO_REQ; FIFO_BANK_OK <= FIFO_ACTIVE and FIFO_REQ;
if DDR_ACCESS = BLITTER and BLITTER_REQ = '1' then
DDR_ACCESS <= BLITTER;
end if;
-- ?? mfro BLITTER_AC <= BLITTER_ACTIVE and BLITTER_REQ; -- ?? mfro BLITTER_AC <= BLITTER_ACTIVE and BLITTER_REQ;
elsif DDR_STATE = DS_T2B then elsif DDR_STATE = DS_T2B then
FIFO_BANK_OK <= '0'; FIFO_BANK_OK <= '0';
@@ -580,8 +583,12 @@ begin
BA_S <= BLITTER_BA; BA_S <= BLITTER_BA;
end if; end if;
elsif DDR_STATE = DS_T4R then elsif DDR_STATE = DS_T4R then
-- mfro SR_DDR_FB <= CPU_AC; -- mfro change next two statements
-- mfro SR_BLITTER_DACK <= BLITTER_AC; if DDR_ACCESS = CPU then
SR_DDR_FB <= '1';
elsif DDR_ACCESS = BLITTER then
SR_BLITTER_DACK <= '1';
end if;
elsif DDR_STATE = DS_T5R and FIFO_REQ = '1' and FIFO_BANK_OK = '1' then elsif DDR_STATE = DS_T5R and FIFO_REQ = '1' and FIFO_BANK_OK = '1' then
VA_S(10) <= '0'; VA_S(10) <= '0';
VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR); VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR);
@@ -590,7 +597,10 @@ begin
VA_S(10) <= '1'; VA_S(10) <= '1';
elsif DDR_STATE = DS_T4W then elsif DDR_STATE = DS_T4W then
VA_S(10) <= VA_S(10); VA_S(10) <= VA_S(10);
-- mfro ??? SR_BLITTER_DACK <= BLITTER_AC; -- mfro changed next if
if DDR_ACCESS = BLITTER then
SR_BLITTER_DACK <= '1';
end if;
elsif DDR_STATE = DS_T5W then elsif DDR_STATE = DS_T5W then
VA_S(10) <= VA_S(10); VA_S(10) <= VA_S(10);
if DDR_ACCESS = CPU then if DDR_ACCESS = CPU then
@@ -600,7 +610,7 @@ begin
VA_S(9 downto 0) <= BLITTER_COL_ADR; VA_S(9 downto 0) <= BLITTER_COL_ADR;
BA_S <= BLITTER_BA; BA_S <= BLITTER_BA;
end if; end if;
if DDR_ACCESS = BLITTER and FB_SIZE1 = '1' and FB_SIZE0 = '1' then if DDR_ACCESS = BLITTER and ACCESS_WIDTH = LONG then
SR_VDMP <= BYTE_SEL & x"F"; SR_VDMP <= BYTE_SEL & x"F";
elsif DDR_ACCESS = BLITTER then elsif DDR_ACCESS = BLITTER then
SR_VDMP <= BYTE_SEL & x"0"; SR_VDMP <= BYTE_SEL & x"0";
@@ -610,7 +620,7 @@ begin
elsif DDR_STATE = DS_T6W then elsif DDR_STATE = DS_T6W then
SR_DDR_WR <= '1'; SR_DDR_WR <= '1';
SR_DDRWR_D_SEL <= '1'; SR_DDRWR_D_SEL <= '1';
if DDR_ACCESS = BLITTER or (FB_SIZE1 = '1' and FB_SIZE0 = '1') then if DDR_ACCESS = BLITTER or ACCESS_WIDTH = LONG then
SR_VDMP <= x"FF"; SR_VDMP <= x"FF";
else else
SR_VDMP <= x"00"; SR_VDMP <= x"00";
@@ -657,7 +667,7 @@ begin
elsif DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA then elsif DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA then
VA_S(10) <= '1'; VA_S(10) <= '1';
DDR_ACCESS <= CPU; DDR_ACCESS <= CPU;
elsif DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA then elsif DDR_STATE = DS_T10F and ACCESS_WIDTH /= LONG and DATA_IN(13 downto 12) = FIFO_BA then
VA_S(10) <= '1'; VA_S(10) <= '1';
DDR_ACCESS <= CPU; DDR_ACCESS <= CPU;
elsif DDR_STATE = DS_T10F then elsif DDR_STATE = DS_T10F then
@@ -691,11 +701,7 @@ begin
if DDR_SEL = '1' and FB_WRn = '1' and DDR_CONFIG = '0' then if DDR_SEL = '1' and FB_WRn = '1' and DDR_CONFIG = '0' then
CPU_REQ <= '1'; CPU_REQ <= '1';
elsif DDR_SEL = '1' and FB_SIZE1 = '0' and FB_SIZE1 = '0' and DDR_CONFIG = '0' then -- Start when not config and not long word access. elsif DDR_SEL = '1' and ACCESS_WIDTH /= LONG and DDR_CONFIG = '0' then -- Start when not config and not long word access.
CPU_REQ <= '1';
elsif DDR_SEL = '1' and FB_SIZE1 = '0' and FB_SIZE1 = '1' and DDR_CONFIG = '0' then -- Start when not config and not long word access.
CPU_REQ <= '1';
elsif DDR_SEL = '1' and FB_SIZE1 = '1' and FB_SIZE1 = '0' and DDR_CONFIG = '0' then -- Start when not config and not long word access.
CPU_REQ <= '1'; CPU_REQ <= '1';
elsif DDR_SEL = '1' and DDR_CONFIG = '1' then -- Config, start immediately. elsif DDR_SEL = '1' and DDR_CONFIG = '1' then -- Config, start immediately.
CPU_REQ <= '1'; CPU_REQ <= '1';
@@ -738,7 +744,7 @@ begin
'1' when DDR_STATE = DS_T2B else '1' when DDR_STATE = DS_T2B else
'1' when DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA else '1' when DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA else
'1' when DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA else '1' when DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA else
DATA_IN(18) and not FB_WRn and not FB_SIZE0 and not FB_SIZE1 when DDR_STATE = DS_C7 else DATA_IN(18) and not FB_WRn and not FB_SIZE0 and not FB_SIZE1 when DDR_STATE = DS_C7 else
'1' when DDR_STATE = DS_CB6 else '1' when DDR_STATE = DS_CB6 else
'1' when DDR_STATE = DS_CB8 else '1' when DDR_STATE = DS_CB8 else
'1' when DDR_STATE = DS_R2 else '0'; '1' when DDR_STATE = DS_R2 else '0';
@@ -802,7 +808,7 @@ DATA_IN(18) and not FB_WRn and not FB_SIZE0 and not FB_SIZE1 when DDR_STATE = DS
P_VIDEO_REGS: process P_VIDEO_REGS: process
-- Video registers. -- Video registers.
begin begin
wait until CLK_MAIN = '1' and CLK_MAIN' event; wait until rising_edge(CLK_MAIN);
if VIDEO_BASE_L = '1' and FB_WRn = '0' and BYTE_SEL(1) = '1' then if VIDEO_BASE_L = '1' and FB_WRn = '0' and BYTE_SEL(1) = '1' then
VIDEO_BASE_L_D <= DATA_IN(23 downto 16); -- 16 byte boarders. VIDEO_BASE_L_D <= DATA_IN(23 downto 16); -- 16 byte boarders.
end if; end if;
@@ -844,11 +850,11 @@ DATA_IN(18) and not FB_WRn and not FB_SIZE0 and not FB_SIZE1 when DDR_STATE = DS
DATA_EN_L <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L or VIDEO_CNT_M or VIDEO_CNT_H) and not FB_OEn; DATA_EN_L <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L or VIDEO_CNT_M or VIDEO_CNT_H) and not FB_OEn;
end architecture BEHAVIOUR; end architecture BEHAVIOUR;
-- VA : Video DDR address multiplexed. -- VA : Video DDR address multiplexed
-- VA_P : latched VA, wenn FIFO_AC, BLITTER_AC. -- VA_P : latched VA, wenn FIFO_AC, BLITTER_AC
-- VA_S : latch for default VA. -- VA_S : latch for default VA
-- BA : Video DDR bank address multiplexed. -- BA : Video DDR bank address multiplexed
-- BA_P : latched BA, wenn FIFO_AC, BLITTER_AC. -- BA_P : latched BA, wenn FIFO_AC, BLITTER_AC
-- BA_S : latch for default BA. -- BA_S : latch for default BA
-- --
--FB_SIZE ersetzen. --FB_SIZE ersetzen.