From 981192e99b01ee63cb1ad72a124a8359714e8f6a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 26 Dec 2013 21:20:47 +0000 Subject: [PATCH] added Firetos' radeon PCI driver --- BaS_gcc/Makefile | 4 +- BaS_gcc/dma/MCD_dmaApi.c | 60 +- BaS_gcc/dma/MCD_tasksInit.c | 8 +- BaS_gcc/include/MCD_tasksInit.h | 8 +- BaS_gcc/include/ati_ids.h | 211 ++ BaS_gcc/include/edid.h | 138 + BaS_gcc/include/fb.h | 600 ++++ BaS_gcc/include/i2c-algo-bit.h | 54 + BaS_gcc/include/i2c.h | 82 + BaS_gcc/include/radeon_reg.h | 5646 +++++++++++++++++++++++++++++++ BaS_gcc/include/radeonfb.h | 690 ++++ BaS_gcc/include/videl.h | 26 +- BaS_gcc/net/arp.c | 2 +- BaS_gcc/net/bootp.c | 2 +- BaS_gcc/net/nbuf.c | 4 +- BaS_gcc/net/nif.c | 7 +- BaS_gcc/net/tftp.c | 2 +- BaS_gcc/net/udp.c | 6 +- BaS_gcc/radeon/radeon_base.c | 2260 +++++++++++++ BaS_gcc/sys/BaS.c | 58 +- BaS_gcc/sys/exceptions.S | 20 +- BaS_gcc/sys/interrupts.c | 19 +- BaS_gcc/video/video.c | 8 +- 23 files changed, 9822 insertions(+), 93 deletions(-) create mode 100644 BaS_gcc/include/ati_ids.h create mode 100644 BaS_gcc/include/edid.h create mode 100644 BaS_gcc/include/fb.h create mode 100644 BaS_gcc/include/i2c-algo-bit.h create mode 100644 BaS_gcc/include/i2c.h create mode 100644 BaS_gcc/include/radeon_reg.h create mode 100644 BaS_gcc/include/radeonfb.h create mode 100644 BaS_gcc/radeon/radeon_base.c diff --git a/BaS_gcc/Makefile b/BaS_gcc/Makefile index 64394ff..3f88602 100644 --- a/BaS_gcc/Makefile +++ b/BaS_gcc/Makefile @@ -43,7 +43,7 @@ TRGTDIRS= ./firebee ./m5484lite OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS)) TOOLDIR=util -VPATH=dma exe flash fs if kbd pci spi sys usb net util video xhdi +VPATH=dma exe flash fs if kbd pci spi sys usb net util video radeon xhdi # Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC) LDCFILE=bas.lk @@ -106,6 +106,8 @@ CSRCS= \ videl.c \ video.c \ \ + radeon_base.c \ + \ basflash.c \ basflash_start.c diff --git a/BaS_gcc/dma/MCD_dmaApi.c b/BaS_gcc/dma/MCD_dmaApi.c index d57a15d..8b887d6 100755 --- a/BaS_gcc/dma/MCD_dmaApi.c +++ b/BaS_gcc/dma/MCD_dmaApi.c @@ -36,9 +36,12 @@ TaskTableEntry *MCD_modelTaskTable; * status, etc. */ static int MCD_chStatus[NCHANNELS] = -{ MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA }; +{ + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, + MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA +}; /* * Prototypes for local functions @@ -349,17 +352,17 @@ int MCD_dmaStatus(int channel) * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK */ -int MCD_startDma(int channel, /* the channel on which to run the DMA */ -int8_t *srcAddr, /* the address to move data from, or physical buffer-descriptor address */ -int16_t srcIncr, /* the amount to increment the source address per transfer */ -int8_t *destAddr, /* the address to move data to */ -int16_t destIncr, /* the amount to increment the destination address per transfer */ -uint32_t dmaSize, /* the number of bytes to transfer independent of the transfer size */ -uint32_t xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ -uint32_t initiator, /* what device initiates the DMA */ -int priority, /* priority of the DMA */ -uint32_t flags, /* flags describing the DMA */ -uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ +int __attribute__((flatten)) MCD_startDma(int channel, /* the channel on which to run the DMA */ + int8_t *srcAddr, /* the address to move data from, or physical buffer-descriptor address */ + int16_t srcIncr, /* the amount to increment the source address per transfer */ + int8_t *destAddr, /* the address to move data to */ + int16_t destIncr, /* the amount to increment the destination address per transfer */ + uint32_t dmaSize, /* the number of bytes to transfer independent of the transfer size */ + uint32_t xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ + uint32_t initiator, /* what device initiates the DMA */ + int priority, /* priority of the DMA */ + uint32_t flags, /* flags describing the DMA */ + uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ #ifdef MCD_NEED_ADDR_TRANS int8_t *srcAddrVirt /* virtual buffer descriptor address TBD*/ #endif @@ -412,15 +415,15 @@ uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actio #ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */ realFuncArray = (uint32_t *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00); /* Modify the LURC's normal and byte-residue-loop functions according to parameter. */ - realFuncArray[(LURC*16)] = xferSize == 4 ? - funcDesc : xferSize == 2 ? - funcDesc & 0xfffff00f : funcDesc & 0xffff000f; + realFuncArray[(LURC*16)] = xferSize == 4 ? funcDesc : xferSize == 2 ? funcDesc & 0xfffff00f : funcDesc & 0xffff000f; realFuncArray[(LURC*16+1)] = (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL; #endif - /* Write the initiator field in the TCR, and also set the initiator-hold - bit. Note that,due to a hardware quirk, this could collide with an - MDE access to the initiator-register file, so we have to verify that the write - reads back correctly. */ + /* + * Write the initiator field in the TCR, and also set the initiator-hold + * bit. Note that,due to a hardware quirk, this could collide with an + * MDE access to the initiator-register file, so we have to verify that the write + * reads back correctly. + */ MCD_dmaBar->taskControl[channel] = (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM; @@ -436,6 +439,7 @@ uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actio } MCD_dmaBar->priority[channel] = (uint8_t) priority & PRIORITY_PRI_MASK; + /* should be albe to handle this stuff with only one write to ts reg - tbd */ if (channel < 8 && channel >= 0) { @@ -460,8 +464,7 @@ uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actio MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECTX].TDTstart; MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend; - MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, - channel); + MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel); } else if (flags & MCD_FECRX_DMA) { @@ -473,10 +476,12 @@ uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actio } else if (flags & MCD_SINGLE_DMA) { - /* this buffer descriptor is used for storing off initial parameters for later - progress query calculation and for the DMA to write the resulting checksum - The DMA does not use this to determine how to operate, that info is passed - with the init routine*/ + /* + * this buffer descriptor is used for storing off initial parameters for later + * progress query calculation and for the DMA to write the resulting checksum + * The DMA does not use this to determine how to operate, that info is passed + * with the init routine + */ MCD_relocBuffDesc[channel].srcAddr = srcAddr; MCD_relocBuffDesc[channel].destAddr = destAddr; MCD_relocBuffDesc[channel].lastDestAddr = destAddr; /* definitely not its final value */ @@ -529,6 +534,7 @@ uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actio ((volatile int *) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int) ((MCD_bufDesc*) srcAddr)->destAddr; #else /* if using address translation, need the virtual addr of the first buffdesc */ + ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr; ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] diff --git a/BaS_gcc/dma/MCD_tasksInit.c b/BaS_gcc/dma/MCD_tasksInit.c index fd4ec2a..291fba9 100755 --- a/BaS_gcc/dma/MCD_tasksInit.c +++ b/BaS_gcc/dma/MCD_tasksInit.c @@ -57,7 +57,7 @@ void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xfer * Task 1 */ -void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) +void MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) { MCD_SET_VAR(taskTable+channel, 7, (uint32_t)srcAddr); /* var[7] */ @@ -127,7 +127,7 @@ void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSi * Task 3 */ -void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) +void MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) { MCD_SET_VAR(taskTable+channel, 8, (uint32_t)srcAddr); /* var[8] */ @@ -161,7 +161,7 @@ void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short d * Task 4 */ -void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel) +void MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel) { MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */ @@ -191,7 +191,7 @@ void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile * Task 5 */ -void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel) +void MCD_startDmaENetXmit(int8_t *bDBase, int8_t *currBD, int8_t *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel) { MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */ diff --git a/BaS_gcc/include/MCD_tasksInit.h b/BaS_gcc/include/MCD_tasksInit.h index daf871c..4b2807e 100755 --- a/BaS_gcc/include/MCD_tasksInit.h +++ b/BaS_gcc/include/MCD_tasksInit.h @@ -15,7 +15,7 @@ void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xfer /* * Task 1 */ -void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); +void MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); /* @@ -27,18 +27,18 @@ void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSi /* * Task 3 */ -void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); +void MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); /* * Task 4 */ -void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel); +void MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel); /* * Task 5 */ -void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel); +void MCD_startDmaENetXmit(int8_t *bDBase, int8_t *currBD, int8_t *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel); #endif /* MCD_TSK_INIT_H */ diff --git a/BaS_gcc/include/ati_ids.h b/BaS_gcc/include/ati_ids.h new file mode 100644 index 0000000..13321c6 --- /dev/null +++ b/BaS_gcc/include/ati_ids.h @@ -0,0 +1,211 @@ +/* + * ATI PCI IDs from XFree86, kept here to make sync'ing with + * XFree much simpler. Currently, this list is only used by + * radeonfb + */ + +#define PCI_CHIP_RV380_3150 0x3150 +#define PCI_CHIP_RV380_3151 0x3151 +#define PCI_CHIP_RV380_3152 0x3152 +#define PCI_CHIP_RV380_3153 0x3153 +#define PCI_CHIP_RV380_3154 0x3154 +#define PCI_CHIP_RV380_3156 0x3156 +#define PCI_CHIP_RV380_3E50 0x3E50 +#define PCI_CHIP_RV380_3E51 0x3E51 +#define PCI_CHIP_RV380_3E52 0x3E52 +#define PCI_CHIP_RV380_3E53 0x3E53 +#define PCI_CHIP_RV380_3E54 0x3E54 +#define PCI_CHIP_RV380_3E56 0x3E56 +#define PCI_CHIP_RS100_4136 0x4136 +#define PCI_CHIP_RS200_4137 0x4137 +#define PCI_CHIP_R300_AD 0x4144 +#define PCI_CHIP_R300_AE 0x4145 +#define PCI_CHIP_R300_AF 0x4146 +#define PCI_CHIP_R300_AG 0x4147 +#define PCI_CHIP_R350_AH 0x4148 +#define PCI_CHIP_R350_AI 0x4149 +#define PCI_CHIP_R350_AJ 0x414A +#define PCI_CHIP_R350_AK 0x414B +#define PCI_CHIP_RV350_AP 0x4150 +#define PCI_CHIP_RV350_AQ 0x4151 +#define PCI_CHIP_RV360_AR 0x4152 +#define PCI_CHIP_RV350_AS 0x4153 +#define PCI_CHIP_RV350_AT 0x4154 +#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_MACH32 0x4158 +#define PCI_CHIP_RS250_4237 0x4237 +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_R200_BC 0x4243 +#define PCI_CHIP_RS100_4336 0x4336 +#define PCI_CHIP_RS200_4337 0x4337 +#define PCI_CHIP_MACH64CT 0x4354 +#define PCI_CHIP_MACH64CX 0x4358 +#define PCI_CHIP_RS250_4437 0x4437 +#define PCI_CHIP_MACH64ET 0x4554 +#define PCI_CHIP_MACH64GB 0x4742 +#define PCI_CHIP_MACH64GD 0x4744 +#define PCI_CHIP_MACH64GI 0x4749 +#define PCI_CHIP_MACH64GL 0x474C +#define PCI_CHIP_MACH64GM 0x474D +#define PCI_CHIP_MACH64GN 0x474E +#define PCI_CHIP_MACH64GO 0x474F +#define PCI_CHIP_MACH64GP 0x4750 +#define PCI_CHIP_MACH64GQ 0x4751 +#define PCI_CHIP_MACH64GR 0x4752 +#define PCI_CHIP_MACH64GS 0x4753 +#define PCI_CHIP_MACH64GT 0x4754 +#define PCI_CHIP_MACH64GU 0x4755 +#define PCI_CHIP_MACH64GV 0x4756 +#define PCI_CHIP_MACH64GW 0x4757 +#define PCI_CHIP_MACH64GX 0x4758 +#define PCI_CHIP_MACH64GY 0x4759 +#define PCI_CHIP_MACH64GZ 0x475A +#define PCI_CHIP_RV250_Id 0x4964 +#define PCI_CHIP_RV250_Ie 0x4965 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_R420_JH 0x4A48 +#define PCI_CHIP_R420_JI 0x4A49 +#define PCI_CHIP_R420_JJ 0x4A4A +#define PCI_CHIP_R420_JK 0x4A4B +#define PCI_CHIP_R420_JL 0x4A4C +#define PCI_CHIP_R420_JM 0x4A4D +#define PCI_CHIP_R420_JN 0x4A4E +#define PCI_CHIP_R420_JP 0x4A50 +#define PCI_CHIP_MACH64LB 0x4C42 +#define PCI_CHIP_MACH64LD 0x4C44 +#define PCI_CHIP_RAGE128LE 0x4C45 +#define PCI_CHIP_RAGE128LF 0x4C46 +#define PCI_CHIP_MACH64LG 0x4C47 +#define PCI_CHIP_MACH64LI 0x4C49 +#define PCI_CHIP_MACH64LM 0x4C4D +#define PCI_CHIP_MACH64LN 0x4C4E +#define PCI_CHIP_MACH64LP 0x4C50 +#define PCI_CHIP_MACH64LQ 0x4C51 +#define PCI_CHIP_MACH64LR 0x4C52 +#define PCI_CHIP_MACH64LS 0x4C53 +#define PCI_CHIP_MACH64LT 0x4C54 +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Le 0x4C65 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_RV250_Ln 0x4C6E +#define PCI_CHIP_RAGE128MF 0x4D46 +#define PCI_CHIP_RAGE128ML 0x4D4C +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_R350_NH 0x4E48 +#define PCI_CHIP_R350_NI 0x4E49 +#define PCI_CHIP_R360_NJ 0x4E4A +#define PCI_CHIP_R350_NK 0x4E4B +#define PCI_CHIP_RV350_NP 0x4E50 +#define PCI_CHIP_RV350_NQ 0x4E51 +#define PCI_CHIP_RV350_NR 0x4E52 +#define PCI_CHIP_RV350_NS 0x4E53 +#define PCI_CHIP_RV350_NT 0x4E54 +#define PCI_CHIP_RV350_NV 0x4E56 +#define PCI_CHIP_RAGE128PA 0x5041 +#define PCI_CHIP_RAGE128PB 0x5042 +#define PCI_CHIP_RAGE128PC 0x5043 +#define PCI_CHIP_RAGE128PD 0x5044 +#define PCI_CHIP_RAGE128PE 0x5045 +#define PCI_CHIP_RAGE128PF 0x5046 +#define PCI_CHIP_RAGE128PG 0x5047 +#define PCI_CHIP_RAGE128PH 0x5048 +#define PCI_CHIP_RAGE128PI 0x5049 +#define PCI_CHIP_RAGE128PJ 0x504A +#define PCI_CHIP_RAGE128PK 0x504B +#define PCI_CHIP_RAGE128PL 0x504C +#define PCI_CHIP_RAGE128PM 0x504D +#define PCI_CHIP_RAGE128PN 0x504E +#define PCI_CHIP_RAGE128PO 0x504F +#define PCI_CHIP_RAGE128PP 0x5050 +#define PCI_CHIP_RAGE128PQ 0x5051 +#define PCI_CHIP_RAGE128PR 0x5052 +#define PCI_CHIP_RAGE128PS 0x5053 +#define PCI_CHIP_RAGE128PT 0x5054 +#define PCI_CHIP_RAGE128PU 0x5055 +#define PCI_CHIP_RAGE128PV 0x5056 +#define PCI_CHIP_RAGE128PW 0x5057 +#define PCI_CHIP_RAGE128PX 0x5058 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_R200_QH 0x5148 +#define PCI_CHIP_R200_QI 0x5149 +#define PCI_CHIP_R200_QJ 0x514A +#define PCI_CHIP_R200_QK 0x514B +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QM 0x514D +#define PCI_CHIP_R200_QN 0x514E +#define PCI_CHIP_R200_QO 0x514F +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RV100_QY 0x5159 +#define PCI_CHIP_RV100_QZ 0x515A +#define PCI_CHIP_RAGE128RE 0x5245 +#define PCI_CHIP_RAGE128RF 0x5246 +#define PCI_CHIP_RAGE128RG 0x5247 +#define PCI_CHIP_RAGE128RK 0x524B +#define PCI_CHIP_RAGE128RL 0x524C +#define PCI_CHIP_RAGE128SE 0x5345 +#define PCI_CHIP_RAGE128SF 0x5346 +#define PCI_CHIP_RAGE128SG 0x5347 +#define PCI_CHIP_RAGE128SH 0x5348 +#define PCI_CHIP_RAGE128SK 0x534B +#define PCI_CHIP_RAGE128SL 0x534C +#define PCI_CHIP_RAGE128SM 0x534D +#define PCI_CHIP_RAGE128SN 0x534E +#define PCI_CHIP_RAGE128TF 0x5446 +#define PCI_CHIP_RAGE128TL 0x544C +#define PCI_CHIP_RAGE128TR 0x5452 +#define PCI_CHIP_RAGE128TS 0x5453 +#define PCI_CHIP_RAGE128TT 0x5454 +#define PCI_CHIP_RAGE128TU 0x5455 +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV370_5461 0x5461 +#define PCI_CHIP_RV370_5462 0x5462 +#define PCI_CHIP_RV370_5463 0x5463 +#define PCI_CHIP_RV370_5464 0x5464 +#define PCI_CHIP_RV370_5465 0x5465 +#define PCI_CHIP_RV370_5466 0x5466 +#define PCI_CHIP_RV370_5467 0x5467 +#define PCI_CHIP_R423_UH 0x5548 +#define PCI_CHIP_R423_UI 0x5549 +#define PCI_CHIP_R423_UJ 0x554A +#define PCI_CHIP_R423_UK 0x554B +#define PCI_CHIP_R423_UQ 0x5551 +#define PCI_CHIP_R423_UR 0x5552 +#define PCI_CHIP_R423_UT 0x5554 +#define PCI_CHIP_MACH64VT 0x5654 +#define PCI_CHIP_MACH64VU 0x5655 +#define PCI_CHIP_MACH64VV 0x5656 +#define PCI_CHIP_RS300_5834 0x5834 +#define PCI_CHIP_RS300_5835 0x5835 +#define PCI_CHIP_RS300_5836 0x5836 +#define PCI_CHIP_RS300_5837 0x5837 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV370_5B61 0x5B61 +#define PCI_CHIP_RV370_5B62 0x5B62 +#define PCI_CHIP_RV370_5B63 0x5B63 +#define PCI_CHIP_RV370_5B64 0x5B64 +#define PCI_CHIP_RV370_5B65 0x5B65 +#define PCI_CHIP_RV370_5B66 0x5B66 +#define PCI_CHIP_RV370_5B67 0x5B67 +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5C61 0x5C61 +#define PCI_CHIP_RV280_5C63 0x5C63 +#define PCI_CHIP_R423_5D57 0x5D57 +#define PCI_CHIP_RS350_7834 0x7834 +#define PCI_CHIP_RS350_7835 0x7835 + diff --git a/BaS_gcc/include/edid.h b/BaS_gcc/include/edid.h new file mode 100644 index 0000000..432b919 --- /dev/null +++ b/BaS_gcc/include/edid.h @@ -0,0 +1,138 @@ +/* + * edid.h - EDID/DDC Header + * + * Based on: + * 1. XFree86 4.3.0, edid.h + * Copyright 1998 by Egbert Eich + * + * 2. John Fremlin and + * Ani Joshi + * + * DDC is a Trademark of VESA (Video Electronics Standard Association). + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. +*/ + +#ifndef __EDID_H__ +#define __EDID_H__ + +#define EDID_LENGTH 0x80 +#define EDID_HEADER 0x00 +#define EDID_HEADER_END 0x07 + +#define ID_MANUFACTURER_NAME 0x08 +#define ID_MANUFACTURER_NAME_END 0x09 +#define ID_MODEL 0x0a + +#define ID_SERIAL_NUMBER 0x0c + +#define MANUFACTURE_WEEK 0x10 +#define MANUFACTURE_YEAR 0x11 + +#define EDID_STRUCT_VERSION 0x12 +#define EDID_STRUCT_REVISION 0x13 + +#define EDID_STRUCT_DISPLAY 0x14 + +#define DPMS_FLAGS 0x18 +#define ESTABLISHED_TIMING_1 0x23 +#define ESTABLISHED_TIMING_2 0x24 +#define MANUFACTURERS_TIMINGS 0x25 + +/* standard timings supported */ +#define STD_TIMING 8 +#define STD_TIMING_DESCRIPTION_SIZE 2 +#define STD_TIMING_DESCRIPTIONS_START 0x26 + +#define DETAILED_TIMING_DESCRIPTIONS_START 0x36 +#define DETAILED_TIMING_DESCRIPTION_SIZE 18 +#define NO_DETAILED_TIMING_DESCRIPTIONS 4 + +#define DETAILED_TIMING_DESCRIPTION_1 0x36 +#define DETAILED_TIMING_DESCRIPTION_2 0x48 +#define DETAILED_TIMING_DESCRIPTION_3 0x5a +#define DETAILED_TIMING_DESCRIPTION_4 0x6c + +#define DESCRIPTOR_DATA 5 + +#define UPPER_NIBBLE( x ) \ + (((128|64|32|16) & (x)) >> 4) + +#define LOWER_NIBBLE( x ) \ + ((1|2|4|8) & (x)) + +#define COMBINE_HI_8LO( hi, lo ) \ + ( (((unsigned)hi) << 8) | (unsigned)lo ) + +#define COMBINE_HI_4LO( hi, lo ) \ + ( (((unsigned)hi) << 4) | (unsigned)lo ) + +#define PIXEL_CLOCK_LO (unsigned)block[ 0 ] +#define PIXEL_CLOCK_HI (unsigned)block[ 1 ] +#define PIXEL_CLOCK (COMBINE_HI_8LO( PIXEL_CLOCK_HI,PIXEL_CLOCK_LO )*10000) +#define H_ACTIVE_LO (unsigned)block[ 2 ] +#define H_BLANKING_LO (unsigned)block[ 3 ] +#define H_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 4 ] ) +#define H_ACTIVE COMBINE_HI_8LO( H_ACTIVE_HI, H_ACTIVE_LO ) +#define H_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 4 ] ) +#define H_BLANKING COMBINE_HI_8LO( H_BLANKING_HI, H_BLANKING_LO ) + +#define V_ACTIVE_LO (unsigned)block[ 5 ] +#define V_BLANKING_LO (unsigned)block[ 6 ] +#define V_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 7 ] ) +#define V_ACTIVE COMBINE_HI_8LO( V_ACTIVE_HI, V_ACTIVE_LO ) +#define V_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 7 ] ) +#define V_BLANKING COMBINE_HI_8LO( V_BLANKING_HI, V_BLANKING_LO ) + +#define H_SYNC_OFFSET_LO (unsigned)block[ 8 ] +#define H_SYNC_WIDTH_LO (unsigned)block[ 9 ] + +#define V_SYNC_OFFSET_LO UPPER_NIBBLE( (unsigned)block[ 10 ] ) +#define V_SYNC_WIDTH_LO LOWER_NIBBLE( (unsigned)block[ 10 ] ) + +#define V_SYNC_WIDTH_HI ((unsigned)block[ 11 ] & (1|2)) +#define V_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (4|8)) >> 2) + +#define H_SYNC_WIDTH_HI (((unsigned)block[ 11 ] & (16|32)) >> 4) +#define H_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (64|128)) >> 6) + +#define V_SYNC_WIDTH COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO ) +#define V_SYNC_OFFSET COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO ) + +#define H_SYNC_WIDTH COMBINE_HI_4LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO ) +#define H_SYNC_OFFSET COMBINE_HI_4LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO ) + +#define H_SIZE_LO (unsigned)block[ 12 ] +#define V_SIZE_LO (unsigned)block[ 13 ] + +#define H_SIZE_HI UPPER_NIBBLE( (unsigned)block[ 14 ] ) +#define V_SIZE_HI LOWER_NIBBLE( (unsigned)block[ 14 ] ) + +#define H_SIZE COMBINE_HI_8LO( H_SIZE_HI, H_SIZE_LO ) +#define V_SIZE COMBINE_HI_8LO( V_SIZE_HI, V_SIZE_LO ) + +#define H_BORDER (unsigned)block[ 15 ] +#define V_BORDER (unsigned)block[ 16 ] + +#define FLAGS (unsigned)block[ 17 ] + +#define INTERLACED (FLAGS&128) +#define SYNC_TYPE (FLAGS&3<<3) /* bits 4,3 */ +#define SYNC_SEPARATE (3<<3) +#define HSYNC_POSITIVE (FLAGS & 4) +#define VSYNC_POSITIVE (FLAGS & 2) + +#define V_MIN_RATE block[ 5 ] +#define V_MAX_RATE block[ 6 ] +#define H_MIN_RATE block[ 7 ] +#define H_MAX_RATE block[ 8 ] +#define MAX_PIXEL_CLOCK (((int)block[ 9 ]) * 10) +#define GTF_SUPPORT block[10] + +#define DPMS_ACTIVE_OFF (1 << 5) +#define DPMS_SUSPEND (1 << 6) +#define DPMS_STANDBY (1 << 7) + +#endif /* __EDID_H__ */ diff --git a/BaS_gcc/include/fb.h b/BaS_gcc/include/fb.h new file mode 100644 index 0000000..7728186 --- /dev/null +++ b/BaS_gcc/include/fb.h @@ -0,0 +1,600 @@ +#ifndef _FB_H +#define _FB_H + +/* Definitions of frame buffers */ + +#define FB_MAJOR 29 +#define FB_MAX 32 /* sufficient for now */ + +/* ioctls + 0x46 is 'F' */ +#define FBIOGET_VSCREENINFO 0x4600 +#define FBIOPUT_VSCREENINFO 0x4601 +#define FBIOGET_FSCREENINFO 0x4602 +#define FBIOPAN_DISPLAY 0x4606 +#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ +#define FBIO_ALLOC 0x4613 +#define FBIO_FREE 0x4614 + +/* picture format */ +#define PICT_FORMAT(bpp,type,a,r,g,b) (((bpp) << 24) | ((type) << 16) | ((a) << 12) | ((r) << 8) | ((g) << 4) | ((b))) +/* gray/color formats use a visual index instead of argb */ +#define PICT_VISFORMAT(bpp,type,vi) (((bpp) << 24) | ((type) << 16) | ((vi))) +#define PICT_FORMAT_BPP(f) (((f) >> 24) ) +#define PICT_FORMAT_TYPE(f) (((f) >> 16) & 0xff) +#define PICT_FORMAT_A(f) (((f) >> 12) & 0x0f) +#define PICT_FORMAT_R(f) (((f) >> 8) & 0x0f) +#define PICT_FORMAT_G(f) (((f) >> 4) & 0x0f) +#define PICT_FORMAT_B(f) (((f) ) & 0x0f) +#define PICT_FORMAT_RGB(f) (((f) ) & 0xfff) +#define PICT_FORMAT_VIS(f) (((f) ) & 0xffff) +#define PICT_TYPE_OTHER 0 +#define PICT_TYPE_A 1 +#define PICT_TYPE_ARGB 2 +#define PICT_TYPE_ABGR 3 +#define PICT_TYPE_COLOR 4 +#define PICT_TYPE_GRAY 5 +#define PICT_FORMAT_COLOR(f) (PICT_FORMAT_TYPE(f) & 2) +/* 32bpp formats */ +#define PICT_a8r8g8b8 PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8) +#define PICT_x8r8g8b8 PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8) +#define PICT_a8b8g8r8 PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8) +#define PICT_x8b8g8r8 PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8) +/* 24bpp formats */ +#define PICT_r8g8b8 PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8) +#define PICT_b8g8r8 PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8) +/* 16bpp formats */ +#define PICT_r5g6b5 PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5) +#define PICT_b5g6r5 PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5) +#define PICT_a1r5g5b5 PICT_FORMAT(16,PICT_TYPE_ARGB,1,5,5,5) +#define PICT_x1r5g5b5 PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5) +#define PICT_a1b5g5r5 PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5) +#define PICT_x1b5g5r5 PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5) +#define PICT_a4r4g4b4 PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4) +#define PICT_x4r4g4b4 PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4) +#define PICT_a4b4g4r4 PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4) +#define PICT_x4b4g4r4 PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4) +/* 8bpp formats */ +#define PICT_a8 PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0) +#define PICT_r3g3b2 PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2) +#define PICT_b2g3r3 PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2) +#define PICT_a2r2g2b2 PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2) +#define PICT_a2b2g2r2 PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2) +#define PICT_c8 PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0) +#define PICT_g8 PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0) + +/* fVDI */ +#define MODE_EMUL_MONO_FLAG 1 +#define MODE_VESA_FLAG 2 /* for modedb.c */ +struct mode_option { + short used; /* Whether the mode option was used or not. */ + short width; + short height; + short bpp; + short freq; + short flags; +}; + +extern struct mode_option resolution; /* fVDI */ + +#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ +#define FB_TYPE_PLANES 1 /* Non interleaved planes */ +#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */ +#define FB_TYPE_TEXT 3 /* Text/attributes */ +#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */ + +#define FB_AUX_TEXT_MDA 0 /* Monochrome text */ +#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */ +#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */ +#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */ +#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */ + +#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */ +#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */ +#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */ + +#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */ +#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */ +#define FB_VISUAL_TRUECOLOR 2 /* True color */ +#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */ +#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */ +#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */ + +#define FB_ACCEL_NONE 0 /* no hardware accelerator */ +#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */ +#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */ +#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */ +#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */ +#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */ +#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */ +#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */ +#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */ +#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */ +#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */ +#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */ +#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */ +#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */ +#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */ +#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */ +#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */ +#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */ +#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */ +#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */ +#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */ +#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */ +#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */ +#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */ +#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */ +#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */ +#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */ +#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */ +#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */ +#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */ +#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */ +#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */ +#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */ +#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */ +#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */ +#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */ +#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */ +#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */ +#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */ +#define FB_ACCEL_I810 39 /* Intel 810/815 */ +#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */ +#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */ +#define FB_ACCEL_I830 42 /* Intel 830M/845G/85x/865G */ +#define FB_ACCEL_NV_10 43 /* nVidia Arch 10 */ +#define FB_ACCEL_NV_20 44 /* nVidia Arch 20 */ +#define FB_ACCEL_NV_30 45 /* nVidia Arch 30 */ +#define FB_ACCEL_NV_40 46 /* nVidia Arch 40 */ +#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */ +#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */ +#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */ +#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */ +#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */ +#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */ +#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */ +#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */ +#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */ + +#define FB_ACCEL_SAVAGE4 0x80 /* S3 Savage4 */ +#define FB_ACCEL_SAVAGE3D 0x81 /* S3 Savage3D */ +#define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */ +#define FB_ACCEL_SAVAGE2000 0x83 /* S3 Savage2000 */ +#define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */ +#define FB_ACCEL_SAVAGE_MX 0x85 /* S3 Savage/MX */ +#define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */ +#define FB_ACCEL_SAVAGE_IX 0x87 /* S3 Savage/IX */ +#define FB_ACCEL_PROSAVAGE_PM 0x88 /* S3 ProSavage PM133 */ +#define FB_ACCEL_PROSAVAGE_KM 0x89 /* S3 ProSavage KM133 */ +#define FB_ACCEL_S3TWISTER_P 0x8a /* S3 Twister */ +#define FB_ACCEL_S3TWISTER_K 0x8b /* S3 TwisterK */ +#define FB_ACCEL_SUPERSAVAGE 0x8c /* S3 Supersavage */ +#define FB_ACCEL_PROSAVAGE_DDR 0x8d /* S3 ProSavage DDR */ +#define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */ + +struct fb_fix_screeninfo { + char id[16]; /* identification string eg "TT Builtin" */ + unsigned long smem_start; /* Start of frame buffer mem */ + /* (physical address) */ + unsigned long smem_len; /* Length of frame buffer mem */ + unsigned long type; /* see FB_TYPE_* */ + unsigned long type_aux; /* Interleave for interleaved Planes */ + unsigned long visual; /* see FB_VISUAL_* */ + unsigned short xpanstep; /* zero if no hardware panning */ + unsigned short ypanstep; /* zero if no hardware panning */ + unsigned short ywrapstep; /* zero if no hardware ywrap */ + unsigned long line_length; /* length of a line in bytes */ + unsigned long mmio_start; /* Start of Memory Mapped I/O */ + /* (physical address) */ + unsigned long mmio_len; /* Length of Memory Mapped I/O */ + unsigned long accel; /* Indicate to driver which */ + /* specific chip/card we have */ + unsigned short reserved[3]; /* Reserved for future compatibility */ +}; + +/* Interpretation of offset for color fields: All offsets are from the right, + * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you + * can use the offset as right argument to <<). A pixel afterwards is a bit + * stream and is written to video memory as that unmodified. This implies + * big-endian byte order if bits_per_pixel is greater than 8. + */ +struct fb_bitfield { + unsigned long offset; /* beginning of bitfield */ + unsigned long length; /* length of bitfield */ + unsigned long msb_right; /* != 0 : Most significant bit is */ + /* right */ +}; + +#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ + +#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/ +#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */ +#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */ +#define FB_ACTIVATE_MASK 15 + /* values */ +#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */ +#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */ +#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */ +#define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/ +#define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */ + +#define FB_ACCELF_TEXT 1 /* (OBSOLETE) see fb_info.flags and vc_mode */ + +#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_EXT 4 /* external sync */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ + /* vtotal = 144d/288n/576i => PAL */ + /* vtotal = 121d/242n/484i => NTSC */ +#define FB_SYNC_ON_GREEN 32 /* sync on green */ + +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +#define FB_VMODE_INTERLACED 1 /* interlaced */ +#define FB_VMODE_DOUBLE 2 /* double scan */ +#define FB_VMODE_MASK 255 + +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ +#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ + +#define PICOS2KHZ(a) (1000000000UL/(a)) +#define KHZ2PICOS(a) (1000000000UL/(a)) + +struct fb_var_screeninfo { + unsigned long xres; /* visible resolution */ + unsigned long yres; + unsigned long xres_virtual; /* virtual resolution */ + unsigned long yres_virtual; + unsigned long xoffset; /* offset from virtual to visible */ + unsigned long yoffset; /* resolution */ + + unsigned long bits_per_pixel; /* guess what */ + unsigned long grayscale; /* != 0 Graylevels instead of colors */ + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ + struct fb_bitfield blue; + struct fb_bitfield transp; /* transparency */ + + unsigned long nonstd; /* != 0 Non standard pixel format */ + + unsigned long activate; /* see FB_ACTIVATE_* */ + + unsigned long height; /* height of picture in mm */ + unsigned long width; /* width of picture in mm */ + + unsigned long accel_flags; /* (OBSOLETE) see fb_info.flags */ + + /* Timing: All values in pixclocks, except pixclock (of course) */ + unsigned long pixclock; /* pixel clock in ps (pico seconds) */ + unsigned long left_margin; /* time from sync to picture */ + unsigned long right_margin; /* time from picture to sync */ + unsigned long upper_margin; /* time from sync to picture */ + unsigned long lower_margin; + unsigned long hsync_len; /* length of horizontal sync */ + unsigned long vsync_len; /* length of vertical sync */ + unsigned long sync; /* see FB_SYNC_* */ + unsigned long vmode; /* see FB_VMODE_* */ + unsigned long rotate; /* angle we rotate counter clockwise */ + unsigned long refresh; + unsigned long reserved[4]; /* Reserved for future compatibility */ +}; + +/* VESA Blanking Levels */ +#define VESA_NO_BLANKING 0 +#define VESA_VSYNC_SUSPEND 1 +#define VESA_HSYNC_SUSPEND 2 +#define VESA_POWERDOWN 3 + +enum { + /* screen: unblanked, hsync: on, vsync: on */ + FB_BLANK_UNBLANK = VESA_NO_BLANKING, + /* screen: blanked, hsync: on, vsync: on */ + FB_BLANK_NORMAL = VESA_NO_BLANKING + 1, + /* screen: blanked, hsync: on, vsync: off */ + FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1, + /* screen: blanked, hsync: off, vsync: on */ + FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1, + /* screen: blanked, hsync: off, vsync: off */ + FB_BLANK_POWERDOWN = VESA_POWERDOWN + 1 +}; + +#define FB_VBLANK_VBLANKING 0x001 /* currently in a vertical blank */ +#define FB_VBLANK_HBLANKING 0x002 /* currently in a horizontal blank */ +#define FB_VBLANK_HAVE_VBLANK 0x004 /* vertical blanks can be detected */ +#define FB_VBLANK_HAVE_HBLANK 0x008 /* horizontal blanks can be detected */ +#define FB_VBLANK_HAVE_COUNT 0x010 /* global retrace counter is available */ +#define FB_VBLANK_HAVE_VCOUNT 0x020 /* the vcount field is valid */ +#define FB_VBLANK_HAVE_HCOUNT 0x040 /* the hcount field is valid */ +#define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */ +#define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */ + +struct fb_vblank { + unsigned long flags; /* FB_VBLANK flags */ + unsigned long count; /* counter of retraces since boot */ + unsigned long vcount; /* current scanline position */ + unsigned long hcount; /* current scandot position */ + unsigned long reserved[4]; /* reserved for future compatibility */ +}; + +struct vm_area_struct; +struct fb_info; +struct device; +struct file; + +/* Definitions below are used in the parsed monitor specs */ +#define FB_DPMS_ACTIVE_OFF 1 +#define FB_DPMS_SUSPEND 2 +#define FB_DPMS_STANDBY 4 + +#define FB_DISP_DDI 1 +#define FB_DISP_ANA_700_300 2 +#define FB_DISP_ANA_714_286 4 +#define FB_DISP_ANA_1000_400 8 +#define FB_DISP_ANA_700_000 16 + +#define FB_DISP_MONO 32 +#define FB_DISP_RGB 64 +#define FB_DISP_MULTI 128 +#define FB_DISP_UNKNOWN 256 + +#define FB_SIGNAL_NONE 0 +#define FB_SIGNAL_BLANK_BLANK 1 +#define FB_SIGNAL_SEPARATE 2 +#define FB_SIGNAL_COMPOSITE 4 +#define FB_SIGNAL_SYNC_ON_GREEN 8 +#define FB_SIGNAL_SERRATION_ON 16 + +#define FB_MISC_PRIM_COLOR 1 +#define FB_MISC_1ST_DETAIL 2 /* First Detailed Timing is preferred */ +struct fb_chroma { + unsigned long redx; /* in fraction of 1024 */ + unsigned long greenx; + unsigned long bluex; + unsigned long whitex; + unsigned long redy; + unsigned long greeny; + unsigned long bluey; + unsigned long whitey; +}; + +struct fb_monspecs { + struct fb_chroma chroma; + struct fb_videomode *modedb; /* mode database */ + unsigned char manufacturer[4]; /* Manufacturer */ + unsigned char monitor[14]; /* Monitor String */ + unsigned char serial_no[14]; /* Serial Number */ + unsigned char ascii[14]; /* ? */ + unsigned long modedb_len; /* mode database length */ + unsigned long model; /* Monitor Model */ + unsigned long serial; /* Serial Number - Integer */ + unsigned long year; /* Year manufactured */ + unsigned long week; /* Week Manufactured */ + unsigned long hfmin; /* hfreq lower limit (Hz) */ + unsigned long hfmax; /* hfreq upper limit (Hz) */ + unsigned long dclkmin; /* pixelclock lower limit (Hz) */ + unsigned long dclkmax; /* pixelclock upper limit (Hz) */ + unsigned short input; /* display type - see FB_DISP_* */ + unsigned short dpms; /* DPMS support - see FB_DPMS_ */ + unsigned short signal; /* Signal Type - see FB_SIGNAL_* */ + unsigned short vfmin; /* vfreq lower limit (Hz) */ + unsigned short vfmax; /* vfreq upper limit (Hz) */ + unsigned short gamma; /* Gamma - in fractions of 100 */ + unsigned short gtf : 1; /* supports GTF */ + unsigned short misc; /* Misc flags - see FB_MISC_* */ + unsigned char version; /* EDID version... */ + unsigned char revision; /* ...and revision */ + unsigned char max_x; /* Maximum horizontal size (cm) */ + unsigned char max_y; /* Maximum vertical size (cm) */ +}; + +struct fb_ops { + /* checks var and eventually tweaks if to soomething supported, + * DO NOT MODIFY PAR */ + int (*fb_check_var)(struct fb_var_screeninfo *var, struct fb_info *info); + /* set the video mode according to info->var */ + int (*fb_set_par)(struct fb_info *info); + /* set color register */ + int (*fb_setcolreg)(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, struct fb_info *info); + /* pan display */ + int (*fb_pan_display)(struct fb_var_screeninfo *var, struct fb_info *info); + /* blank display */ + int (*fb_blank)(int blank, struct fb_info *info); + /* wait for blit idle */ + int (*fb_sync)(struct fb_info *info); + /* perform fb specific ioctl */ + int (*fb_ioctl)(unsigned int cmd, unsigned long arg, struct fb_info *info); + /* Buildthe modedb for head 1 (head 2 will come later), check panel infos + * from either BIOS or EDID, and pick up the default mode */ + void (*fb_check_modes)(struct fb_info *info, struct mode_option *resolution); + /* Accel functions */ +#define DEGREES_0 0 +#define DEGREES_90 1 +#define DEGREES_180 2 +#define DEGREES_270 3 +#define OMIT_LAST 1 + void (*SetupForSolidFill)(struct fb_info *info, int color, int rop, unsigned int planemask); + void (*SubsequentSolidFillRect)(struct fb_info *info, int x, int y, int w, int h); + void (*SetupForSolidLine)(struct fb_info *info, int color, int rop, unsigned int planemask); + void (*SubsequentSolidHorVertLine)(struct fb_info *info, int x, int y, int len, int dir); + void (*SubsequentSolidTwoPointLine)(struct fb_info *info, int xa, int ya, int xb, int yb, int flags); + void (*SetupForDashedLine)(struct fb_info *info, int fg, int bg, int rop, unsigned int planemask, int length, unsigned char *pattern); + void (*SubsequentDashedTwoPointLine)(struct fb_info *info, int xa, int ya, int xb, int yb, int flags, int phase); + void (*SetupForScreenToScreenCopy)(struct fb_info *info, int xdir, int ydir, int rop, unsigned int planemask, int trans_color); + void (*SubsequentScreenToScreenCopy)(struct fb_info *info, int xa, int ya, int xb, int yb, int w, int h); + void (*ScreenToScreenCopy)(struct fb_info *info, int xa, int ya, int xb, int yb, int w, int h, int rop); + void (*SetupForMono8x8PatternFill)(struct fb_info *info, int patternx, int patterny, int fg, int bg, int rop, unsigned int planemask); + void (*SubsequentMono8x8PatternFillRect)(struct fb_info *info, int patternx, int patterny, int x, int y, int w, int h); + void (*SetupForScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int fg, int bg, int rop, unsigned int planemask); + void (*SubsequentScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int x, int y, int w, int h, int skipleft); + void (*SubsequentScanline)(struct fb_info *info, unsigned long *buf); + void (*SetupForScanlineImageWrite)(struct fb_info *info, int rop, unsigned int planemask, int trans_color, int bpp); + void (*SubsequentScanlineImageWriteRect)(struct fb_info *info, int x, int y, int w, int h, int skipleft); + void (*SetClippingRectangle)(struct fb_info *info, int xa, int ya, int xb, int yb); + void (*DisableClipping)(struct fb_info *info); + int (*SetupForCPUToScreenAlphaTexture)(struct fb_info *info, + int op, unsigned short red, unsigned short green, unsigned short blue, unsigned short alpha, unsigned long maskFormat, unsigned long dstFormat, unsigned char *alphaPtr, int alphaPitch, int width, int height, int flags); + int (*SetupForCPUToScreenTexture)(struct fb_info *info, int op, unsigned long srcFormat, unsigned long dstFormat, unsigned char *texPtr, int texPitch, int width, int height, int flags); + void (*SubsequentCPUToScreenTexture)(struct fb_info *info, int dstx, int dsty, int srcx, int srcy, int width, int height); + /* Cursor functions */ + void (*SetCursorColors)(struct fb_info *info, int bg, int fg); + void (*SetCursorPosition)(struct fb_info *info, int x, int y); + void (*LoadCursorImage)(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom); + void (*HideCursor)(struct fb_info *info); + void (*ShowCursor)(struct fb_info *info); + long (*CursorInit)(struct fb_info *info); + void (*WaitVbl)(struct fb_info *info); +}; + +struct fb_info { + struct fb_var_screeninfo var; /* Current var */ + struct fb_fix_screeninfo fix; /* Current fix */ + struct fb_monspecs monspecs; /* Current Monitor specs */ + struct fb_videomode *mode; /* current mode */ + char *screen_base; /* Virtual address */ + unsigned long screen_size; + char *ram_base; /* base vram */ + unsigned long ram_size; /* vram size */ + char *screen_mono; + long update_mono; + struct fb_ops *fbops; + void *par; /* device dependent */ +}; + +/* fbmem.c */ +extern int fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var); +extern int fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var); +extern int fb_blank(struct fb_info *info, int blank); +extern int fb_ioctl(unsigned int cmd, unsigned long arg); +extern struct fb_info *framebuffer_alloc(unsigned long size); +extern void framebuffer_release(struct fb_info *info); + +/* offscreen.c */ +extern long offscreen_free(struct fb_info *info, long addr); +extern long offscreen_alloc(struct fb_info *info, long amount); +extern long offscren_reserved(void); +extern void offscreen_init(struct fb_info *info); + +/* fbmon.c */ +#define FB_MAXTIMINGS 0 +#define FB_VSYNCTIMINGS 1 +#define FB_HSYNCTIMINGS 2 +#define FB_DCLKTIMINGS 3 +#define FB_IGNOREMON 0x100 + +#define FB_MODE_IS_UNKNOWN 0 +#define FB_MODE_IS_DETAILED 1 +#define FB_MODE_IS_STANDARD 2 +#define FB_MODE_IS_VESA 4 +#define FB_MODE_IS_CALCULATED 8 +#define FB_MODE_IS_FIRST 16 +#define FB_MODE_IS_FROM_VAR 32 + +extern void fb_destroy_modedb(struct fb_videomode *modedb); +extern int fb_parse_edid(unsigned char *edid, struct fb_var_screeninfo *var); +extern void fb_edid_to_monspecs(unsigned char *edid, struct fb_monspecs *specs); +extern int fb_get_mode(int flags, unsigned long val, struct fb_var_screeninfo *var, struct fb_info *info); +extern int fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info); + +/* modedb.c */ +#define VESA_MODEDB_SIZE 34 +extern int fb_find_mode(struct fb_var_screeninfo *var, + struct fb_info *info, struct mode_option *resolution , + const struct fb_videomode *db, unsigned int dbsize, + const struct fb_videomode *default_mode, unsigned int default_bpp); +extern void fb_var_to_videomode(struct fb_videomode *mode, struct fb_var_screeninfo *var); +extern void fb_videomode_to_var(struct fb_var_screeninfo *var, struct fb_videomode *mode); +extern int fb_mode_is_equal(struct fb_videomode *mode1, struct fb_videomode *mode2); + +struct fb_videomode { + unsigned short refresh; /* optional */ + unsigned short xres; + unsigned short yres; + unsigned long pixclock; + unsigned short left_margin; + unsigned short right_margin; + unsigned short upper_margin; + unsigned short lower_margin; + unsigned short hsync_len; + unsigned short vsync_len; + unsigned short sync; + unsigned short vmode; + unsigned short flag; +}; + +extern const struct fb_videomode vesa_modes[]; + +/* timer */ +extern void udelay(long usec); +#ifdef COLDFIRE +#ifdef MCF5445X +#define US_TO_TIMER(a) (a) +#define TIMER_TO_US(a) (a) +#else /* MCF548X */ +#define US_TO_TIMER(a) ((a)*100) +#define TIMER_TO_US(a) ((a)/100) +#endif +#else +#define US_TO_TIMER(a) (((a)*256)/5000) +#define TIMER_TO_US(a) (((a)*5000)/256) +#endif +extern long get_timer(void); +extern void start_timeout(void); +extern int end_timeout(long msec); +extern void mdelay(long msec); +extern void install_vbl_timer(void *func, int remove); +extern void uninstall_vbl_timer(void *func); + +/* + * fVDI access + */ +extern void Funcs_copymem(const void *s, void *d, long n); +extern const char *Funcs_next_line(const char *ptr); +extern const char *Funcs_skip_space(const char *ptr); +extern const char *Funcs_get_token(const char *ptr, char *buf, long n); +extern long Funcs_equal(const char *str1, const char *str2); +extern long Funcs_length(const char *text); +extern void Funcs_copy(const char *src, char *dest); +extern void Funcs_cat(const char *src, char *dest); +extern long Funcs_numeric(long ch); +extern long Funcs_atol(const char *text); +extern void Funcs_error(const char *text1, const char *text2); +extern void *Funcs_malloc(long size, long type); +extern long Funcs_free(void *addr); +extern int Funcs_puts(const char *text); +extern void Funcs_ltoa(char *buf, long n, unsigned long base); +extern long Funcs_get_cookie(const unsigned char *cname, long super); +extern long Funcs_set_cookie(const unsigned char *cname, long value); +//extern long Funcs_fixup_font(Fontheader *font, char *buffer, long flip); +//extern long Funcs_unpack_font(Fontheader *header, long format); +//extern long Funcs_insert_font(Fontheader **first_font, Fontheader *new_font); +extern long Funcs_get_size(const char *name); +extern char *Funcs_allocate_block(long size); +extern void Funcs_free_block(void *address); +extern void Funcs_cache_flush(void); +extern long Funcs_misc(long func, long par, const char *token); +extern long Funcs_event(long id_type, long data); + +extern struct fb_info *info_fvdi; + +/* + * Debugging stuffs + */ +extern short debug; +extern void debug_print(const char *string); +extern void debug_print_value(const char *string, long val); +extern void debug_print_value_hex(const char *string, long val); +extern void debug_print_value_hex_byte(const char *string, unsigned char val); +extern void debug_print_value_hex_word(const char *string, unsigned short val); +extern void debug_print_value_hex_long(const char *string, unsigned long val); +#define DPRINT debug_print +#define DPRINTVAL debug_print_value +#define DPRINTVALHEX debug_print_value_hex +#define DPRINTVALHEXBYTE debug_print_value_hex_byte +#define DPRINTVALHEXWORD debug_print_value_hex_word +#define DPRINTVALHEXLONG debug_print_value_hex_long + +#endif /* _FB_H */ diff --git a/BaS_gcc/include/i2c-algo-bit.h b/BaS_gcc/include/i2c-algo-bit.h new file mode 100644 index 0000000..9570b82 --- /dev/null +++ b/BaS_gcc/include/i2c-algo-bit.h @@ -0,0 +1,54 @@ +/* ------------------------------------------------------------------------- */ +/* i2c-algo-bit.h i2c driver algorithms for bit-shift adapters */ +/* ------------------------------------------------------------------------- */ +/* Copyright (C) 1995-99 Simon G. Vogl + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ +/* ------------------------------------------------------------------------- */ + +/* With some changes from Kyösti Mälkki and even + Frodo Looijaard */ + +/* $Id: i2c-algo-bit.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */ + +#ifndef I2C_ALGO_BIT_H +#define I2C_ALGO_BIT_H + +/* --- Defines for bit-adapters --------------------------------------- */ +/* + * This struct contains the hw-dependent functions of bit-style adapters to + * manipulate the line states, and to init any hw-specific features. This is + * only used if you have more than one hw-type of adapter running. + */ +struct i2c_algo_bit_data { + void *data; /* private data for lowlevel routines */ + void (*setsda) (void *data, int state); + void (*setscl) (void *data, int state); + int (*getsda) (void *data); + int (*getscl) (void *data); + + /* local settings */ + int udelay; /* half-clock-cycle time in microsecs */ + /* i.e. clock is (500 / udelay) KHz */ + int mdelay; /* in millisecs, unused */ + int timeout; /* in jiffies */ +}; + +#define I2C_BIT_ADAP_MAX 16 + +int i2c_bit_add_bus(struct i2c_adapter *); +int i2c_bit_del_bus(struct i2c_adapter *); + +#endif /* I2C_ALGO_BIT_H */ diff --git a/BaS_gcc/include/i2c.h b/BaS_gcc/include/i2c.h new file mode 100644 index 0000000..81f9ec6 --- /dev/null +++ b/BaS_gcc/include/i2c.h @@ -0,0 +1,82 @@ +/* ------------------------------------------------------------------------- */ +/* */ +/* i2c.h - definitions for the i2c-bus interface */ +/* */ +/* ------------------------------------------------------------------------- */ +/* Copyright (C) 1995-2000 Simon G. Vogl + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ +/* ------------------------------------------------------------------------- */ + +/* With some changes from Kyösti Mälkki and + Frodo Looijaard */ + +/* $Id: i2c.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */ + +#ifndef _I2C_H +#define _I2C_H + +/* --- General options ------------------------------------------------ */ + +struct i2c_msg; +struct i2c_algorithm; +struct i2c_adapter; + +/* Transfer num messages. + */ +extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); + +/* + * The following structs are for those who like to implement new bus drivers: + * i2c_algorithm is the interface to a class of hardware solutions which can + * be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584 + * to name two of the most common. + */ +struct i2c_algorithm { + unsigned int id; + int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs, int num); + /* --- ioctl like call to set div. parameters. */ + int (*algo_control)(struct i2c_adapter *, unsigned int, unsigned long); +}; + +/* + * i2c_adapter is the structure used to identify a physical i2c bus along + * with the access algorithms necessary to access it. + */ +struct i2c_adapter { + struct i2c_algorithm *algo;/* the algorithm to access the bus */ + void *algo_data; + int timeout; + int retries; + int nr; +}; + +/* + * I2C Message - used for pure i2c transaction, also from /dev interface + */ +struct i2c_msg { + unsigned short addr; /* slave address */ + unsigned short flags; +#define I2C_M_TEN 0x10 /* we have a ten bit chip address */ +#define I2C_M_RD 0x01 +#define I2C_M_NOSTART 0x4000 +#define I2C_M_REV_DIR_ADDR 0x2000 +#define I2C_M_IGNORE_NAK 0x1000 +#define I2C_M_NO_RD_ACK 0x0800 + unsigned short len; /* msg length */ + unsigned char *buf; /* pointer to msg data */ +}; + +#endif /* _I2C_H */ diff --git a/BaS_gcc/include/radeon_reg.h b/BaS_gcc/include/radeon_reg.h new file mode 100644 index 0000000..aebaa31 --- /dev/null +++ b/BaS_gcc/include/radeon_reg.h @@ -0,0 +1,5646 @@ +#ifndef _RADEON_H +#define _RADEON_H + +/* to fix: multiple definition from Linux defines and Xfree defines added for VIDX and RENDER */ + +#define RADEON_REGSIZE 0x4000 + +#define MM_INDEX 0x0000 +#define MM_DATA 0x0004 +#define BUS_CNTL 0x0030 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +#define I2C_CNTL_1 0x0094 +#define CONFIG_CNTL 0x00E0 +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define PAD_CTLR_MISC 0x0aa0 +#define AGP_CNTL 0x0174 +#define BM_STATUS 0x0160 +#define CAP0_TRIG_CNTL 0x0950 +#define CAP1_TRIG_CNTL 0x09c0 +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define BASE_CODE 0x0F0B +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +#define AGP_COMMAND 0x0F60 +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +#define DAC_CNTL2 0x007c +#define CRTC_GEN_CNTL 0x0050 +#define MEM_CNTL 0x0140 +#define MC_CNTL 0x0140 +#define EXT_MEM_CNTL 0x0144 +#define MC_TIMING_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_REFRESH_CNTL 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MC_INIT_GFX_LAT_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#define MEM_IO_CNTL_A1 0x017C +#define MC_READ_CNTL_AB 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MC_INIT_MISC_LAT_TIMER 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_IOPAD_CNTL 0x0184 +#define MC_DEBUG 0x0188 +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_CHIP_IO_OE_CNTL_AB 0x018C +#define MC_FB_LOCATION 0x0148 +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define TEST_DEBUG_CNTL 0x0120 +#define TEST_DEBUG_MUX 0x0124 +#define TEST_DEBUG_OUT 0x012c +#define CRTC2_GEN_CNTL 0x03f8 +#define CRTC2_DISPLAY_BASE_ADDR 0x033c +#define SURFACE_CNTL 0x0B00 +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define BRUSH_DATA0 0x1480 +#define BRUSH_DATA1 0x1484 +#define BRUSH_DATA2 0x1488 +#define BRUSH_DATA3 0x148c +#define BRUSH_DATA4 0x1490 +#define BRUSH_DATA5 0x1494 +#define BRUSH_DATA7 0x149c +#define BRUSH_DATA8 0x14a0 +#define BRUSH_DATA9 0x14a4 +#define BRUSH_DATA10 0x14a8 +#define BRUSH_DATA11 0x14ac +#define BRUSH_DATA12 0x14b0 +#define BRUSH_DATA13 0x14b4 +#define BRUSH_DATA14 0x14b8 +#define BRUSH_DATA15 0x14bc +#define BRUSH_DATA16 0x14c0 +#define BRUSH_DATA17 0x14c4 +#define BRUSH_DATA18 0x14c8 +#define BRUSH_DATA19 0x14cc +#define BRUSH_DATA20 0x14d0 +#define BRUSH_DATA21 0x14d4 +#define BRUSH_DATA22 0x14d8 +#define BRUSH_DATA23 0x14dc +#define BRUSH_DATA24 0x14e0 +#define BRUSH_DATA25 0x14e4 +#define BRUSH_DATA26 0x14e8 +#define BRUSH_DATA27 0x14ec +#define BRUSH_DATA28 0x14f0 +#define BRUSH_DATA29 0x14f4 +#define BRUSH_DATA30 0x14f8 +#define BRUSH_DATA31 0x14fc +#define BRUSH_DATA32 0x1500 +#define BRUSH_DATA33 0x1504 +#define BRUSH_DATA34 0x1508 +#define BRUSH_DATA35 0x150c +#define BRUSH_DATA36 0x1510 +#define BRUSH_DATA37 0x1514 +#define BRUSH_DATA38 0x1518 +#define BRUSH_DATA39 0x151c +#define BRUSH_DATA40 0x1520 +#define BRUSH_DATA41 0x1524 +#define BRUSH_DATA42 0x1528 +#define BRUSH_DATA43 0x152c +#define BRUSH_DATA44 0x1530 +#define BRUSH_DATA45 0x1534 +#define BRUSH_DATA46 0x1538 +#define BRUSH_DATA47 0x153c +#define BRUSH_DATA48 0x1540 +#define BRUSH_DATA49 0x1544 +#define BRUSH_DATA50 0x1548 +#define BRUSH_DATA51 0x154c +#define BRUSH_DATA52 0x1550 +#define BRUSH_DATA53 0x1554 +#define BRUSH_DATA54 0x1558 +#define BRUSH_DATA55 0x155c +#define BRUSH_DATA56 0x1560 +#define BRUSH_DATA57 0x1564 +#define BRUSH_DATA58 0x1568 +#define BRUSH_DATA59 0x156c +#define BRUSH_DATA6 0x1498 +#define BRUSH_DATA60 0x1570 +#define BRUSH_DATA61 0x1574 +#define BRUSH_DATA62 0x1578 +#define BRUSH_DATA63 0x157c +#define BRUSH_SCALE 0x1470 +#define BRUSH_Y_X 0x1474 +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +#define CRTC_EXT_CNTL 0x0054 +#define RB3D_CNTL 0x1C3C +#define WAIT_UNTIL 0x1720 +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define GPIO_CRT2_DDC 0x006c +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +#define CRTC_H_SYNC_STRT_WID 0x0204 +#define CRTC_V_TOTAL_DISP 0x0208 +#define CRTC_V_SYNC_STRT_WID 0x020C +#define CRTC_VLINE_CRNT_VLINE 0x0210 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC_DEBUG 0x021C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC_OFFSET_CNTL 0x0228 +#define CRTC_PITCH 0x022C +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +#define FP_HORZ_STRETCH 0x028C +#define FP_VERT_STRETCH 0x0290 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +//#define DDA_CONFIG 0x02e0 +//#define DDA_ON_OFF 0x02e4 +#define DVI_I2C_CNTL_1 0x02e4 +#define GRPH_BUFFER_CNTL 0x02F0 +#define GRPH2_BUFFER_CNTL 0x03F0 +#define VGA_BUFFER_CNTL 0x02F4 +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_REG_LOAD_CNTL 0x0410 +#define OV0_SCALE_CNTL 0x0420 +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +#define OV0_P23_V_ACCUM_INIT 0x042C +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +#define OV0_BASE_ADDR 0x043C +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +#define OV0_VID_BUF3_BASE_ADRS 0x044C +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTRL 0x0470 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +#define OV0_FOUR_TAP_COEF_0 0x04B0 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +#define OV0_FOUR_TAP_COEF_3 0x04BC +#define OV0_FOUR_TAP_COEF_4 0x04C0 +#define OV0_FLAG_CNTRL 0x04DC +#define OV0_SLICE_CNTL 0x04E0 +#define OV0_VID_KEY_CLR_LOW 0x04E4 +#define OV0_VID_KEY_CLR_HIGH 0x04E8 +#define OV0_GRPH_KEY_CLR_LOW 0x04EC +#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +#define OV0_TEST 0x04F8 +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 +#define DISP_MISC_CNTL 0x0D00 +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL 0x0D64 +#define DISP_LIN_TRANS_GRPH_A 0x0D80 +#define DISP_LIN_TRANS_GRPH_B 0x0D84 +#define DISP_LIN_TRANS_GRPH_C 0x0D88 +#define DISP_LIN_TRANS_GRPH_D 0x0D8C +#define DISP_LIN_TRANS_GRPH_E 0x0D90 +#define DISP_LIN_TRANS_GRPH_F 0x0D94 +#define DISP_LIN_TRANS_VID_A 0x0D98 +#define DISP_LIN_TRANS_VID_B 0x0D9C +#define DISP_LIN_TRANS_VID_C 0x0DA0 +#define DISP_LIN_TRANS_VID_D 0x0DA4 +#define DISP_LIN_TRANS_VID_E 0x0DA8 +#define DISP_LIN_TRANS_VID_F 0x0DAC +#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +#define RMX_HORZ_PHASE 0x0DBC +#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +#define DAC_BROAD_PULSE 0x0DC4 +#define DAC_SKEW_CLKS 0x0DC8 +#define DAC_INCR 0x0DCC +#define DAC_NEG_SYNC_LEVEL 0x0DD0 +#define DAC_POS_SYNC_LEVEL 0x0DD4 +#define DAC_BLANK_LEVEL 0x0DD8 +#define CLOCK_CNTL_INDEX 0x0008 +#define CLOCK_CNTL_DATA 0x000C +#define CP_RB_CNTL 0x0704 +#define CP_RB_BASE 0x0700 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define SCRATCH_REG0 0x15E0 +#define GUI_SCRATCH_REG0 0x15E0 +#define SCRATCH_REG1 0x15E4 +#define GUI_SCRATCH_REG1 0x15E4 +#define SCRATCH_REG2 0x15E8 +#define GUI_SCRATCH_REG2 0x15E8 +#define SCRATCH_REG3 0x15EC +#define GUI_SCRATCH_REG3 0x15EC +#define SCRATCH_REG4 0x15F0 +#define GUI_SCRATCH_REG4 0x15F0 +#define SCRATCH_REG5 0x15F4 +#define GUI_SCRATCH_REG5 0x15F4 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DP_BRUSH_FRGD_CLR 0x147C +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define DST_LINE_PATCOUNT 0x1608 +#define SRC_OFFSET 0x15AC +#define SRC_PITCH 0x15B0 +#define SRC_TILE 0x1704 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define SRC_X_Y 0x1590 +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_HEIGHT_WIDTH 0x143c +#define DST_OFFSET 0x1404 +#define SRC_CLUT_ADDRESS 0x1780 +#define SRC_CLUT_DATA 0x1784 +#define SRC_CLUT_DATA_RD 0x1788 +#define HOST_DATA0 0x17C0 +#define HOST_DATA1 0x17C4 +#define HOST_DATA2 0x17C8 +#define HOST_DATA3 0x17CC +#define HOST_DATA4 0x17D0 +#define HOST_DATA5 0x17D4 +#define HOST_DATA6 0x17D8 +#define HOST_DATA7 0x17DC +#define HOST_DATA_LAST 0x17E0 +#define DP_SRC_ENDIAN 0x15D4 +#define DP_SRC_FRGD_CLR 0x15D8 +#define DP_SRC_BKGD_CLR 0x15DC +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164C +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165C +#define DP_CNTL 0x16C0 +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +#define DP_DATATYPE 0x16C4 +#define DP_MIX 0x16C8 +#define DP_WRITE_MSK 0x16CC +#define DP_XOP 0x17F8 +#define CLR_CMP_CLR_SRC 0x15C4 +#define CLR_CMP_CLR_DST 0x15C8 +#define CLR_CMP_CNTL 0x15C0 +#define CLR_CMP_MSK 0x15CC +#define DSTCACHE_MODE 0x1710 +#define DSTCACHE_CTLSTAT 0x1714 +#define DEFAULT_PITCH_OFFSET 0x16E0 +#define DEFAULT_OFFSET 0x16e0 +#define DEFAULT_PITCH 0x16e4 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +#define DEFAULT_SC_TOP_LEFT 0x16EC +#define SRC_PITCH_OFFSET 0x1428 +#define DST_PITCH_OFFSET 0x142C +#define DP_GUI_MASTER_CNTL 0x146C +#define SC_TOP_LEFT 0x16EC +#define SC_BOTTOM_RIGHT 0x16F0 +#define SRC_SC_BOTTOM_RIGHT 0x16F4 +#define RB2D_DSTCACHE_MODE 0x3428 +#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define LVDS_GEN_CNTL 0x02d0 +#define LVDS_PLL_CNTL 0x02d4 +#define FP2_GEN_CNTL 0x0288 +#define TMDS_CNTL 0x0294 +#define TMDS_CRC 0x02a0 +#define TMDS_TRANSMITTER_CNTL 0x02a4 +#define MPP_TB_CONFIG 0x01c0 +#define PAMAC0_DLY_CNTL 0x0a94 +#define PAMAC1_DLY_CNTL 0x0a98 +#define PAMAC2_DLY_CNTL 0x0a9c +#define FW_CNTL 0x0118 +#define FCP_CNTL 0x0910 +#define VGA_DDA_ON_OFF 0x02ec +#define TV_MASTER_CNTL 0x0800 + +#define BIOS_0_SCRATCH 0x0010 +#define BIOS_1_SCRATCH 0x0014 +#define BIOS_2_SCRATCH 0x0018 +#define BIOS_3_SCRATCH 0x001c +#define BIOS_4_SCRATCH 0x0020 +#define BIOS_5_SCRATCH 0x0024 +#define BIOS_6_SCRATCH 0x0028 +#define BIOS_7_SCRATCH 0x002c + +#define HDP_SOFT_RESET (1 << 26) + +#define TV_DAC_CNTL 0x088c +#define GPIOPAD_MASK 0x0198 +#define GPIOPAD_A 0x019c +#define GPIOPAD_EN 0x01a0 +#define GPIOPAD_Y 0x01a4 +#define ZV_LCDPAD_MASK 0x01a8 +#define ZV_LCDPAD_A 0x01ac +#define ZV_LCDPAD_EN 0x01b0 +#define ZV_LCDPAD_Y 0x01b4 + +/* PLL Registers */ +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +#define PPLL_REF_DIV 0x0003 +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +#define HTOTAL_CNTL 0x0009 +#define M_SPLL_REF_FB_DIV 0x000a +#define AGP_PLL_CNTL 0x000b +#define SPLL_CNTL 0x000c +#define SCLK_CNTL 0x000d +#define MPLL_CNTL 0x000e +#define MDLL_CKO 0x000f +#define MDLL_RDCKA 0x0010 +#define MCLK_CNTL 0x0012 +#define AGP_PLL_CNTL 0x000b +#define PLL_TEST_CNTL 0x0013 +#define CLK_PWRMGT_CNTL 0x0014 +#define PLL_PWRMGT_CNTL 0x0015 +#define MCLK_MISC 0x001f +#define P2PLL_CNTL 0x002a +#define P2PLL_REF_DIV 0x002b +#define PIXCLKS_CNTL 0x002d +#define SCLK_MORE_CNTL 0x0035 + +/* MCLK_CNTL bit constants */ +#define FORCEON_MCLKA (1 << 16) +#define FORCEON_MCLKB (1 << 17) +#define FORCEON_YCLKA (1 << 18) +#define FORCEON_YCLKB (1 << 19) +#define FORCEON_MC (1 << 20) +#define FORCEON_AIC (1 << 21) + +/* SCLK_CNTL bit constants */ +#define DYN_STOP_LAT_MASK 0x00007ff8 +#define CP_MAX_DYN_STOP_LAT 0x0008 +#define SCLK_FORCEON_MASK 0xffff8000 + +/* SCLK_MORE_CNTL bit constants */ +#define SCLK_MORE_FORCEON 0x0700 + +/* BUS_CNTL bit constants */ +#define BUS_DBL_RESYNC 0x00000001 +#define BUS_MSTR_RESET 0x00000002 +#define BUS_FLUSH_BUF 0x00000004 +#define BUS_STOP_REQ_DIS 0x00000008 +#define BUS_ROTATION_DIS 0x00000010 +#define BUS_MASTER_DIS 0x00000040 +#define BUS_ROM_WRT_EN 0x00000080 +#define BUS_DIS_ROM 0x00001000 +#define BUS_PCI_READ_RETRY_EN 0x00002000 +#define BUS_AGP_AD_STEPPING_EN 0x00004000 +#define BUS_PCI_WRT_RETRY_EN 0x00008000 +#define BUS_MSTR_RD_MULT 0x00100000 +#define BUS_MSTR_RD_LINE 0x00200000 +#define BUS_SUSPEND 0x00400000 +#define LAT_16X 0x00800000 +#define BUS_RD_DISCARD_EN 0x01000000 +#define BUS_RD_ABORT_EN 0x02000000 +#define BUS_MSTR_WS 0x04000000 +#define BUS_PARKING_DIS 0x08000000 +#define BUS_MSTR_DISCONNECT_EN 0x10000000 +#define BUS_WRT_BURST 0x20000000 +#define BUS_READ_BURST 0x40000000 +#define BUS_RDY_READ_DLY 0x80000000 + +/* PIXCLKS_CNTL */ +#define PIX2CLK_SRC_SEL_MASK 0x03 +#define PIX2CLK_SRC_SEL_CPUCLK 0x00 +#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +#define PIX2CLK_SRC_SEL_BYTECLK 0x02 +#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +#define PIX2CLK_ALWAYS_ONb (1<<6) +#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) +#define PIXCLK_TV_SRC_SEL (1 << 8) +#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) + +/* CLOCK_CNTL_INDEX bit constants */ +#define PLL_WR_EN 0x00000080 + +/* CONFIG_CNTL bit constants */ +#define CFG_VGA_RAM_EN 0x00000100 +#define CFG_ATI_REV_ID_MASK (0xf << 16) +#define CFG_ATI_REV_A11 (0 << 16) +#define CFG_ATI_REV_A12 (1 << 16) +#define CFG_ATI_REV_A13 (2 << 16) + +/* CRTC_EXT_CNTL bit constants */ +#define VGA_ATI_LINEAR 0x00000008 +#define VGA_128KAP_PAGING 0x00000010 +#define XCRT_CNT_EN (1 << 6) +#define CRTC_HSYNC_DIS (1 << 8) +#define CRTC_VSYNC_DIS (1 << 9) +#define CRTC_DISPLAY_DIS (1 << 10) +#define CRTC_CRT_ON (1 << 15) + +/* DSTCACHE_CTLSTAT bit constants */ +#define RB2D_DC_FLUSH (3 << 0) +#define RB2D_DC_FREE (3 << 2) +#define RB2D_DC_FLUSH_ALL 0xf +#define RB2D_DC_BUSY (1 << 31) + +/* CRTC_GEN_CNTL bit constants */ +#define CRTC_DBL_SCAN_EN (1 << 0) +#define CRTC_INTERLACE_EN (1 << 1) +#define CRTC_CSYNC_EN (1 << 4) +#define CRTC_BYPASS_LUT_EN (1 << 14) +#define CRTC_CUR_EN (1 << 16) +#define CRTC_CUR_MODE_MASK (7 << 17) +#define CRTC_ICON_EN (1 << 20) +#define CRTC_EXT_DISP_EN (1 << 24) +#define CRTC_EN (1 << 25) +#define CRTC_DISP_REQ_EN_B (1 << 26) + +/* CRTC2_GEN_CTRL bit constants */ +#define CRTC2_DBL_SCAN_EN (1 << 0) +#define CRTC2_INTERLACE_EN (1 << 1) +#define CRTC2_SYNC_TRISTAT (1 << 4) +#define CRTC2_HSYNC_TRISTAT (1 << 5) +#define CRTC2_VSYNC_TRISTAT (1 << 6) +#define CRTC2_CRT2_ON (1 << 7) +#define CRTC2_ICON_EN (1 << 15) +#define CRTC2_CUR_EN (1 << 16) +#define CRTC2_CUR_MODE_MASK (7 << 20) +#define CRTC2_DISP_DIS (1 << 23) +#define CRTC2_EN (1 << 25) +#define CRTC2_DISP_REQ_EN_B (1 << 26) +#define CRTC2_CSYNC_EN (1 << 27) +#define CRTC2_HSYNC_DIS (1 << 28) +#define CRTC2_VSYNC_DIS (1 << 29) + +/* CRTC_STATUS bit constants */ +#define CRTC_VBLANK 0x00000001 + +/* CRTC2_GEN_CNTL bit constants */ +#define CRT2_ON (1 << 7) +#define CRTC2_DISPLAY_DIS (1 << 23) +#define CRTC2_EN (1 << 25) +#define CRTC2_DISP_REQ_EN_B (1 << 26) + +/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ +#define CUR_LOCK 0x80000000 + +/* GPIO bit constants */ +#define GPIO_A_0 (1 << 0) +#define GPIO_A_1 (1 << 1) +#define GPIO_Y_0 (1 << 8) +#define GPIO_Y_1 (1 << 9) +#define GPIO_EN_0 (1 << 16) +#define GPIO_EN_1 (1 << 17) +#define GPIO_MASK_0 (1 << 24) +#define GPIO_MASK_1 (1 << 25) +#define VGA_DDC_DATA_OUTPUT GPIO_A_0 +#define VGA_DDC_CLK_OUTPUT GPIO_A_1 +#define VGA_DDC_DATA_INPUT GPIO_Y_0 +#define VGA_DDC_CLK_INPUT GPIO_Y_1 +#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 +#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 + +/* FP bit constants */ +#define FP_CRTC_H_TOTAL_MASK 0x000003ff +#define FP_CRTC_H_DISP_MASK 0x01ff0000 +#define FP_CRTC_V_TOTAL_MASK 0x00000fff +#define FP_CRTC_V_DISP_MASK 0x0fff0000 +#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +#define FP_H_SYNC_WID_MASK 0x003f0000 +#define FP_V_SYNC_STRT_MASK 0x00000fff +#define FP_V_SYNC_WID_MASK 0x001f0000 +#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_H_DISP_SHIFT 0x00000010 +#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_V_DISP_SHIFT 0x00000010 +#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +#define FP_H_SYNC_WID_SHIFT 0x00000010 +#define FP_V_SYNC_STRT_SHIFT 0x00000000 +#define FP_V_SYNC_WID_SHIFT 0x00000010 + +/* FP_GEN_CNTL bit constants */ +#define FP_FPON (1 << 0) +#define FP_TMDS_EN (1 << 2) +#define FP_PANEL_FORMAT (1 << 3) +#define FP_EN_TMDS (1 << 7) +#define FP_DETECT_SENSE (1 << 8) +#define R200_FP_SOURCE_SEL_MASK (3 << 10) +#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +#define R200_FP_SOURCE_SEL_RMX (2 << 10) +#define R200_FP_SOURCE_SEL_TRANS (3 << 10) +#define FP_SEL_CRTC1 (0 << 13) +#define FP_SEL_CRTC2 (1 << 13) +#define FP_USE_VGA_HSYNC (1 << 14) +#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +#define FP_CRTC_USE_SHADOW_VEND (1 << 18) +#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +#define FP_DFP_SYNC_SEL (1 << 21) +#define FP_CRTC_LOCK_8DOT (1 << 22) +#define FP_CRT_SYNC_SEL (1 << 23) +#define FP_USE_SHADOW_EN (1 << 24) +#define FP_CRT_SYNC_ALT (1 << 26) + +/* FP2_GEN_CNTL bit constants */ +#define FP2_BLANK_EN (1 << 1) +#define FP2_ON (1 << 2) +#define FP2_PANEL_FORMAT (1 << 3) +#define FP2_SOURCE_SEL_MASK (3 << 10) +#define FP2_SOURCE_SEL_CRTC2 (1 << 10) +#define FP2_SRC_SEL_MASK (3 << 13) +#define FP2_SRC_SEL_CRTC2 (1 << 13) +#define FP2_FP_POL (1 << 16) +#define FP2_LP_POL (1 << 17) +#define FP2_SCK_POL (1 << 18) +#define FP2_LCD_CNTL_MASK (7 << 19) +#define FP2_PAD_FLOP_EN (1 << 22) +#define FP2_CRC_EN (1 << 23) +#define FP2_CRC_READ_EN (1 << 24) +#define FP2_DV0_EN (1 << 25) +#define FP2_DV0_RATE_SEL_SDR (1 << 26) + +/* LVDS_GEN_CNTL bit constants */ +#define LVDS_ON (1 << 0) +#define LVDS_DISPLAY_DIS (1 << 1) +#define LVDS_PANEL_TYPE (1 << 2) +#define LVDS_PANEL_FORMAT (1 << 3) +#define LVDS_EN (1 << 7) +#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 +#define LVDS_BL_MOD_LEVEL_SHIFT 8 +#define LVDS_BL_MOD_EN (1 << 16) +#define LVDS_DIGON (1 << 18) +#define LVDS_BLON (1 << 19) +#define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_STATE_MASK \ + (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) + +/* LVDS_PLL_CNTL bit constatns */ +#define HSYNC_DELAY_SHIFT 0x1c +#define HSYNC_DELAY_MASK (0xf << 0x1c) + +/* TMDS_TRANSMITTER_CNTL bit constants */ +#define TMDS_PLL_EN (1 << 0) +#define TMDS_PLLRST (1 << 1) +#define TMDS_RAN_PAT_RST (1 << 7) +#define TMDS_ICHCSEL (1 << 28) + +/* FP_HORZ_STRETCH bit constants */ +#define HORZ_STRETCH_RATIO_MASK 0xffff +#define HORZ_STRETCH_RATIO_MAX 4096 +#define HORZ_PANEL_SIZE (0x1ff << 16) +#define HORZ_PANEL_SHIFT 16 +#define HORZ_STRETCH_PIXREP (0 << 25) +#define HORZ_STRETCH_BLEND (1 << 26) +#define HORZ_STRETCH_ENABLE (1 << 25) +#define HORZ_AUTO_RATIO (1 << 27) +#define HORZ_FP_LOOP_STRETCH (0x7 << 28) +#define HORZ_AUTO_RATIO_INC (1 << 31) + +/* FP_VERT_STRETCH bit constants */ +#define VERT_STRETCH_RATIO_MASK 0xfff +#define VERT_STRETCH_RATIO_MAX 4096 +#define VERT_PANEL_SIZE (0xfff << 12) +#define VERT_PANEL_SHIFT 12 +#define VERT_STRETCH_LINREP (0 << 26) +#define VERT_STRETCH_BLEND (1 << 26) +#define VERT_STRETCH_ENABLE (1 << 25) +#define VERT_AUTO_RATIO_EN (1 << 27) +#define VERT_FP_LOOP_STRETCH (0x7 << 28) +#define VERT_STRETCH_RESERVED 0xf1000000 + +/* DAC_CNTL bit constants */ +#define DAC_8BIT_EN 0x00000100 +#define DAC_4BPP_PIX_ORDER 0x00000200 +#define DAC_CRC_EN 0x00080000 +#define DAC_MASK_ALL (0xff << 24) +#define DAC_PDWN (1 << 15) +#define DAC_EXPAND_MODE (1 << 14) +#define DAC_VGA_ADR_EN (1 << 13) +#define DAC_RANGE_CNTL (3 << 0) +#define DAC_RANGE_CNTL_MASK 0x03 +#define DAC_BLANKING (1 << 2) +#define DAC_CMP_EN (1 << 3) +#define DAC_CMP_OUTPUT (1 << 7) + +/* DAC_CNTL2 bit constants */ +#define DAC2_EXPAND_MODE (1 << 14) +#define DAC2_CMP_EN (1 << 7) +#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) + +/* DAC_EXT_CNTL bit constants */ +#define DAC_FORCE_BLANK_OFF_EN (1 << 4) +#define DAC_FORCE_DATA_EN (1 << 5) +#define DAC_FORCE_DATA_SEL_MASK (3 << 6) +#define DAC_FORCE_DATA_MASK 0x0003ff00 +#define DAC_FORCE_DATA_SHIFT 8 + +/* GEN_RESET_CNTL bit constants */ +#define SOFT_RESET_GUI 0x00000001 +#define SOFT_RESET_VCLK 0x00000100 +#define SOFT_RESET_PCLK 0x00000200 +#define SOFT_RESET_ECP 0x00000400 +#define SOFT_RESET_DISPENG_XCLK 0x00000800 + +/* MEM_CNTL bit constants */ +#define MEM_CTLR_STATUS_IDLE 0x00000000 +#define MEM_CTLR_STATUS_BUSY 0x00100000 +#define MEM_SEQNCR_STATUS_IDLE 0x00000000 +#define MEM_SEQNCR_STATUS_BUSY 0x00200000 +#define MEM_ARBITER_STATUS_IDLE 0x00000000 +#define MEM_ARBITER_STATUS_BUSY 0x00400000 +#define MEM_REQ_UNLOCK 0x00000000 +#define MEM_REQ_LOCK 0x00800000 +#define MEM_NUM_CHANNELS_MASK 0x00000001 +#define MEM_USE_B_CH_ONLY 0x00000002 +#define RV100_MEM_HALF_MODE 0x00000008 +#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 +#define R300_MEM_USE_CD_CH_ONLY 0x00000004 + +/* RBBM_GUICNTL bit connstants */ +#define HOST_DATA_SWAP_NONE (0 << 0) +#define HOST_DATA_SWAP_16BIT (1 << 0) +#define HOST_DATA_SWAP_32BIT (2 << 0) +#define HOST_DATA_SWAP_HDW (3 << 0) + +/* RBBM_SOFT_RESET bit constants */ +#define SOFT_RESET_CP (1 << 0) +#define SOFT_RESET_HI (1 << 1) +#define SOFT_RESET_SE (1 << 2) +#define SOFT_RESET_RE (1 << 3) +#define SOFT_RESET_PP (1 << 4) +#define SOFT_RESET_E2 (1 << 5) +#define SOFT_RESET_RB (1 << 6) +#define SOFT_RESET_HDP (1 << 7) + +/* RBBM_STATUS bit constants */ +#define RBBM_FIFOCNT_MASK 0x007f +#define RBBM_ACTIVE (1 << 31) + +/* SURFACE_CNTL bit constants */ +#define SURF_TRANSLATION_DIS (1 << 8) +#define NONSURF_AP0_SWP_16BPP (1 << 20) +#define NONSURF_AP0_SWP_32BPP (1 << 21) +#define NONSURF_AP1_SWP_16BPP (1 << 22) +#define NONSURF_AP1_SWP_32BPP (1 << 23) + +/* SURFACE_INFO bit constants */ +#define SURF_TILE_COLOR_MACRO (0 << 16) +#define SURF_TILE_COLOR_BOTH (1 << 16) +#define SURF_TILE_DEPTH_32BPP (2 << 16) +#define SURF_TILE_DEPTH_16BPP (3 << 16) +#define R200_SURF_TILE_NONE (0 << 16) +#define R200_SURF_TILE_COLOR_MACRO (1 << 16) +#define R200_SURF_TILE_COLOR_MICRO (2 << 16) +#define R200_SURF_TILE_COLOR_BOTH (3 << 16) +#define R200_SURF_TILE_DEPTH_32BPP (4 << 16) +#define R200_SURF_TILE_DEPTH_16BPP (5 << 16) +#define R300_SURF_TILE_NONE (0 << 16) +#define R300_SURF_TILE_COLOR_MACRO (1 << 16) +#define R300_SURF_TILE_DEPTH_32BPP (2 << 16) +#define SURF_AP0_SWP_16BPP (1 << 20) +#define SURF_AP0_SWP_32BPP (1 << 21) +#define SURF_AP1_SWP_16BPP (1 << 22) +#define SURF_AP1_SWP_32BPP (1 << 23) + + +/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ +#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) + +/* MM_INDEX bit constants */ +#define MM_APER 0x80000000 + +/* CLR_CMP_CNTL bit constants */ +#define COMPARE_SRC_FALSE 0x00000000 +#define COMPARE_SRC_TRUE 0x00000001 +#define COMPARE_SRC_NOT_EQUAL 0x00000004 +#define COMPARE_SRC_EQUAL 0x00000005 +#define COMPARE_SRC_EQUAL_FLIP 0x00000007 +#define COMPARE_DST_FALSE 0x00000000 +#define COMPARE_DST_TRUE 0x00000100 +#define COMPARE_DST_NOT_EQUAL 0x00000400 +#define COMPARE_DST_EQUAL 0x00000500 +#define COMPARE_DESTINATION 0x00000000 +#define COMPARE_SOURCE 0x01000000 +#define COMPARE_SRC_AND_DST 0x02000000 + +/* CMP_CNTL bit constants */ +#define SRC_CMP_EQ_COLOR (4 << 0) +#define SRC_CMP_NEQ_COLOR (5 << 0) +#define CLR_CMP_SRC_SOURCE (1 << 24) + +/* DP_CNTL bit constants */ +#define DST_X_RIGHT_TO_LEFT 0x00000000 +#define DST_X_LEFT_TO_RIGHT 0x00000001 +#define DST_Y_BOTTOM_TO_TOP 0x00000000 +#define DST_Y_TOP_TO_BOTTOM 0x00000002 +#define DST_X_MAJOR 0x00000000 +#define DST_Y_MAJOR 0x00000004 +#define DST_X_TILE 0x00000008 +#define DST_Y_TILE 0x00000010 +#define DST_LAST_PEL 0x00000020 +#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +#define DST_BRES_SIGN 0x00000100 +#define DST_HOST_BIG_ENDIAN_EN 0x00000200 +#define DST_POLYLINE_NONLAST 0x00008000 +#define DST_RASTER_STALL 0x00010000 +#define DST_POLY_EDGE 0x00040000 + +/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ +#define DST_X_MAJOR_S 0x00000000 +#define DST_Y_MAJOR_S 0x00000001 +#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +#define DST_X_RIGHT_TO_LEFT_S 0x00000000 +#define DST_X_LEFT_TO_RIGHT_S 0x80000000 + +/* SC_TOP_LEFT_C bit contsants */ +#define SC_SIGN_MASK_LO 0x8000 +#define SC_SIGN_MASK_HI 0x80000000 + +/* DST_LINE_PATCOUNT bit constants */ +#define BRES_CNTL_SHIFT 8 + +/* DP_DATATYPE bit constants */ +#define DST_8BPP 0x00000002 +#define DST_15BPP 0x00000003 +#define DST_16BPP 0x00000004 +#define DST_24BPP 0x00000005 +#define DST_32BPP 0x00000006 +#define DST_8BPP_RGB332 0x00000007 +#define DST_8BPP_Y8 0x00000008 +#define DST_8BPP_RGB8 0x00000009 +#define DST_16BPP_VYUY422 0x0000000b +#define DST_16BPP_YVYU422 0x0000000c +#define DST_32BPP_AYUV444 0x0000000e +#define DST_16BPP_ARGB4444 0x0000000f +#define BRUSH_SOLIDCOLOR 0x00000d00 +#define SRC_MONO 0x00000000 +#define SRC_MONO_LBKGD 0x00010000 +#define SRC_DSTCOLOR 0x00030000 +#define BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define BYTE_ORDER_LSB_TO_MSB 0x40000000 +#define DP_CONVERSION_TEMP 0x80000000 +#define HOST_BIG_ENDIAN_EN (1 << 29) + +/* DP_GUI_MASTER_CNTL bit constants */ +#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +#define GMC_SRC_CLIP_DEFAULT 0x00000000 +#define GMC_SRC_CLIP_LEAVE 0x00000004 +#define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_DST_CLIP_LEAVE 0x00000008 +#define GMC_BRUSH_8x8MONO 0x00000000 +#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +#define GMC_BRUSH_8x1MONO 0x00000020 +#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +#define GMC_BRUSH_1x8MONO 0x00000040 +#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +#define GMC_BRUSH_32x1MONO 0x00000060 +#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +#define GMC_BRUSH_32x32MONO 0x00000080 +#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +#define GMC_BRUSH_8x8COLOR 0x000000a0 +#define GMC_BRUSH_8x1COLOR 0x000000b0 +#define GMC_BRUSH_1x8COLOR 0x000000c0 +#define GMC_DST_8BPP 0x00000200 +#define GMC_DST_8BPP_RGB332 0x00000700 +#define GMC_DST_8BPP_Y8 0x00000800 +#define GMC_DST_8BPP_RGB8 0x00000900 +#define GMC_DST_16BPP_VYUY422 0x00000b00 +#define GMC_DST_16BPP_YVYU422 0x00000c00 +#define GMC_DST_32BPP_AYUV444 0x00000e00 +#define GMC_DST_16BPP_ARGB4444 0x00000f00 +#define GMC_SRC_MONO 0x00000000 +#define GMC_SRC_MONO_LBKGD 0x00001000 +#define GMC_SRC_DSTCOLOR 0x00003000 +#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +#define GMC_DP_SRC_RECT 0x02000000 +#define GMC_DP_SRC_HOST 0x03000000 +#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +#define GMC_3D_FCN_EN_CLR 0x00000000 +#define GMC_3D_FCN_EN_SET 0x08000000 +#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +#define GMC_AUX_CLIP_LEAVE 0x00000000 +#define GMC_AUX_CLIP_CLEAR 0x20000000 +#define GMC_WRITE_MASK_LEAVE 0x00000000 +#define GMC_WRITE_MASK_SET 0x40000000 +#define GMC_CLR_CMP_CNTL_DIS (1 << 28) +#define GMC_SRC_DATATYPE_COLOR (3 << 12) +#define DP_SRC_SOURCE_MASK (7 << 24) +#define GMC_BRUSH_NONE (15 << 4) +#define DP_SRC_SOURCE_MEMORY (2 << 24) +#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +#define GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +#define GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +#define GMC_SRC_CLIPPING (1 << 2) +#define GMC_DST_CLIPPING (1 << 3) +#define GMC_BRUSH_DATATYPE_MASK (0x0f << 4) +#define GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) +#define GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) +#define GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) +#define GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) +#define GMC_BRUSH_32X1_MONO_FG_BG (6 << 4) +#define GMC_BRUSH_32X1_MONO_FG_LA (7 << 4) +#define GMC_BRUSH_32X32_MONO_FG_BG (8 << 4) +#define GMC_BRUSH_32X32_MONO_FG_LA (9 << 4) +#define GMC_BRUSH_8X8_COLOR (10 << 4) +#define GMC_BRUSH_1X8_COLOR (12 << 4) +#define GMC_BRUSH_SOLID_COLOR (13 << 4) +#define GMC_BRUSH_NONE (15 << 4) +#define GMC_DST_8BPP_CI (2 << 8) +#define GMC_DST_15BPP (3 << 8) +#define GMC_DST_16BPP (4 << 8) +#define GMC_DST_24BPP (5 << 8) +#define GMC_DST_32BPP (6 << 8) +#define GMC_DST_8BPP_RGB (7 << 8) +#define GMC_DST_Y8 (8 << 8) +#define GMC_DST_RGB8 (9 << 8) +#define GMC_DST_VYUY (11 << 8) +#define GMC_DST_YVYU (12 << 8) +#define GMC_DST_AYUV444 (14 << 8) +#define GMC_DST_ARGB4444 (15 << 8) +#define GMC_DST_DATATYPE_MASK (0x0f << 8) +#define GMC_DST_DATATYPE_SHIFT 8 +#define GMC_SRC_DATATYPE_MASK (3 << 12) +#define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) +#define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) +#define GMC_SRC_DATATYPE_COLOR (3 << 12) +#define GMC_BYTE_PIX_ORDER (1 << 14) +#define GMC_BYTE_MSB_TO_LSB (0 << 14) +#define GMC_BYTE_LSB_TO_MSB (1 << 14) +#define GMC_CONVERSION_TEMP (1 << 15) +#define GMC_CONVERSION_TEMP_6500 (0 << 15) +#define GMC_CONVERSION_TEMP_9300 (1 << 15) +#define GMC_ROP3_MASK (0xff << 16) +#define DP_SRC_SOURCE_MASK (7 << 24) +#define DP_SRC_SOURCE_MEMORY (2 << 24) +#define DP_SRC_SOURCE_HOST_DATA (3 << 24) +#define GMC_3D_FCN_EN (1 << 27) +#define GMC_CLR_CMP_CNTL_DIS (1 << 28) +#define GMC_AUX_CLIP_DIS (1 << 29) +#define GMC_WR_MSK_DIS (1 << 30) +#define GMC_LD_BRUSH_Y_X (1 << 31) +#define ROP3_ZERO 0x00000000 +#define ROP3_DSa 0x00880000 +#define ROP3_SDna 0x00440000 +#define ROP3_S 0x00cc0000 +#define ROP3_SRCCOPY 0x00cc0000 +#define ROP3_DSna 0x00220000 +#define ROP3_D 0x00aa0000 +#define ROP3_DSx 0x00660000 +#define ROP3_DSo 0x00ee0000 +#define ROP3_DSon 0x00110000 +#define ROP3_DSxn 0x00990000 +#define ROP3_Dn 0x00550000 +#define ROP3_SDno 0x00dd0000 +#define ROP3_Sn 0x00330000 +#define ROP3_DSno 0x00bb0000 +#define ROP3_DSan 0x00770000 +#define ROP3_ONE 0x00ff0000 +#define ROP3_DPa 0x00a00000 +#define ROP3_PDna 0x00500000 +#define ROP3_P 0x00f00000 +#define ROP3_PATCOPY 0x00f00000 +#define ROP3_DPna 0x000a0000 +#define ROP3_D 0x00aa0000 +#define ROP3_DPx 0x005a0000 +#define ROP3_DPo 0x00fa0000 +#define ROP3_DPon 0x00050000 +#define ROP3_PDxn 0x00a50000 +#define ROP3_PDno 0x00f50000 +#define ROP3_Pn 0x000f0000 +#define ROP3_DPno 0x00af0000 +#define ROP3_DPan 0x005f0000 + +/* DP_MIX bit constants */ +#define DP_SRC_RECT 0x00000200 +#define DP_SRC_HOST 0x00000300 +#define DP_SRC_HOST_BYTEALIGN 0x00000400 + +/* MPLL_CNTL bit constants */ +#define MPLL_RESET 0x00000001 + +/* MDLL_CKO bit constants */ +#define MCKOA_SLEEP 0x00000001 +#define MCKOA_RESET 0x00000002 +#define MCKOA_REF_SKEW_MASK 0x00000700 +#define MCKOA_FB_SKEW_MASK 0x00007000 + +/* MDLL_RDCKA bit constants */ +#define MRDCKA0_SLEEP 0x00000001 +#define MRDCKA0_RESET 0x00000002 +#define MRDCKA1_SLEEP 0x00010000 +#define MRDCKA1_RESET 0x00020000 + +/* VCLK_ECP_CNTL constants */ +#define VCLK_SRC_SEL_MASK 0x03 +#define VCLK_SRC_SEL_CPUCLK 0x00 +#define VCLK_SRC_SEL_PSCANCLK 0x01 +#define VCLK_SRC_SEL_BYTECLK 0x02 +#define VCLK_SRC_SEL_PPLLCLK 0x03 +#define PIXCLK_ALWAYS_ONb 0x00000040 +#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 + +/* BUS_CNTL1 constants */ +#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 +#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 +#define BUS_CNTL1_AGPCLK_VALID 0x80000000 + +/* PLL_PWRMGT_CNTL constants */ +#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 +#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 +#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 +#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 +#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 +#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 +#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 + +/* TV_DAC_CNTL constants */ +#define TV_DAC_CNTL_BGSLEEP 0x00000040 +#define TV_DAC_CNTL_DETECT 0x00000010 +#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 +#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 +#define TV_DAC_CNTL_BGADJ__SHIFT 16 +#define TV_DAC_CNTL_DACADJ__SHIFT 20 +#define TV_DAC_CNTL_RDACPD 0x01000000 +#define TV_DAC_CNTL_GDACPD 0x02000000 +#define TV_DAC_CNTL_BDACPD 0x04000000 + +/* DISP_MISC_CNTL constants */ +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) +#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) +#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) +#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) +#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) + +/* DISP_PWR_MAN constants */ +#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) +#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) +#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) +#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) +#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) +#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) +#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) +#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) +#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) +#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) +#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) +#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) +#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) + +/* DST_PITCH_OFFSET bit constants */ +#define PITCH_SHIFT 21 +#define DST_TILE_LINEAR (0 << 30) +#define DST_TILE_MACRO (1 << 30) +#define DST_TILE_MICRO (2 << 30) +#define DST_TILE_BOTH (3 << 30) + +/* masks */ +#define CONFIG_MEMSIZE_MASK 0x1f000000 +#define MEM_CFG_TYPE 0x40000000 +#define DST_OFFSET_MASK 0x003fffff +#define DST_PITCH_MASK 0x3fc00000 +#define DEFAULT_TILE_MASK 0xc0000000 +#define PPLL_DIV_SEL_MASK 0x00000300 +#define PPLL_RESET 0x00000001 +#define PPLL_SLEEP 0x00000002 +#define PPLL_ATOMIC_UPDATE_EN 0x00010000 +#define PPLL_REF_DIV_MASK 0x000003ff +#define PPLL_FB3_DIV_MASK 0x000007ff +#define PPLL_POST3_DIV_MASK 0x00070000 +#define PPLL_ATOMIC_UPDATE_R 0x00008000 +#define PPLL_ATOMIC_UPDATE_W 0x00008000 +#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 +#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +#define R300_PPLL_REF_DIV_ACC_SHIFT 18 + +#define GUI_ACTIVE 0x80000000 + +#define MC_IND_INDEX 0x01F8 +#define MC_IND_DATA 0x01FC + +/* PAD_CTLR_STRENGTH */ +#define PAD_MANUAL_OVERRIDE 0x80000000 + +/* pllCLK_PIN_CNTL */ +#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L +#define CLK_PIN_CNTL__OSC_EN 0x00000001L +#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L +#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L +#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L +#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L +#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L +#define CLK_PIN_CNTL__CG_SPARE 0x00004000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L +#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L +#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L + +/* pllCLK_PWRMGT_CNTL */ +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 +#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 +#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c +#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f +#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 +#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 +#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 +#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 +#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 +#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 +#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f + +/* pllP2PLL_CNTL */ +#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L +#define P2PLL_CNTL__P2PLL_RESET 0x00000001L +#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L +#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L +#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L +#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L +#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L +#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L +#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L +#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L +#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L +#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L +#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L + +/* pllPIXCLKS_CNTL */ +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 +#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f + +/* pllPIXCLKS_CNTL */ +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L +#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L +#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) +#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) +#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) +#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) + +/* pllP2PLL_DIV_0 */ +#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L +#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L + +/* pllSCLK_CNTL */ +#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L +#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L +#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L +#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L +#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L +#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L +#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L +#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L +#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L +#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L +#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L +#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L +#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L +#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 +#define SCLK_CNTL__FORCE_DISP2 0x00008000L +#define SCLK_CNTL__FORCE_CP 0x00010000L +#define SCLK_CNTL__FORCE_HDP 0x00020000L +#define SCLK_CNTL__FORCE_DISP1 0x00040000L +#define SCLK_CNTL__FORCE_TOP 0x00080000L +#define SCLK_CNTL__FORCE_E2 0x00100000L +#define SCLK_CNTL__FORCE_SE 0x00200000L +#define SCLK_CNTL__FORCE_IDCT 0x00400000L +#define SCLK_CNTL__FORCE_VIP 0x00800000L +#define SCLK_CNTL__FORCE_RE 0x01000000L +#define SCLK_CNTL__FORCE_PB 0x02000000L +#define SCLK_CNTL__FORCE_TAM 0x04000000L +#define SCLK_CNTL__FORCE_TDM 0x08000000L +#define SCLK_CNTL__FORCE_RB 0x10000000L +#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L +#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L +#define SCLK_CNTL__FORCE_OV0 0x80000000L +#define SCLK_CNTL__R300_FORCE_VAP (1<<21) +#define SCLK_CNTL__R300_FORCE_SR (1<<25) +#define SCLK_CNTL__R300_FORCE_PX (1<<26) +#define SCLK_CNTL__R300_FORCE_TX (1<<27) +#define SCLK_CNTL__R300_FORCE_US (1<<28) +#define SCLK_CNTL__R300_FORCE_SU (1<<30) +#define SCLK_CNTL__FORCEON_MASK 0xffff8000L + +/* pllSCLK_CNTL2 */ +#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) +#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) +#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) +#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) +#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) +#define SCLK_CNTL2__R300_FORCE_GA (1<<15) + +/* SCLK_MORE_CNTL */ +#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L +#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L +#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L +#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L +#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L +#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L +#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L +#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L +#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L +#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L +#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L +#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L +#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L +#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L +#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L +#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L +#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L +#define SCLK_MORE_CNTL__FORCEON 0x00000700L + +/* MCLK_CNTL */ +#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L +#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L +#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L +#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L +#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L +#define MCLK_CNTL__FORCE_MCLKA 0x00010000L +#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L +#define MCLK_CNTL__FORCE_MCLKB 0x00020000L +#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L +#define MCLK_CNTL__FORCE_YCLKA 0x00040000L +#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L +#define MCLK_CNTL__FORCE_YCLKB 0x00080000L +#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L +#define MCLK_CNTL__FORCE_MC 0x00100000L +#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L +#define MCLK_CNTL__FORCE_AIC 0x00200000L +#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L +#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L +#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L +#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L +#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) +#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) + +/* MCLK_MISC */ +#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L +#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L +#define MCLK_MISC__DLL_READY_LAT 0x00000100L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L +#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L +#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L +#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L +#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L +#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L + +/* VCLK_ECP_CNTL */ +#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L +#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L +#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L +#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L +#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L +#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L +#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L +#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L +#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) + +/* PLL_PWRMGT_CNTL */ +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L +#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L +#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L +#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L +#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L +#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L +#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L + +/* CLK_PWRMGT_CNTL */ +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L +#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L +#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L +#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L +#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L +#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L +#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L +#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L +#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L +#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L +#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L +#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L +#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L +#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L +#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L +#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L +#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L +#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L + +/* BUS_CNTL1 */ +#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L +#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L +#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L +#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L +#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L +#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L +#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L +#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L +#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L +#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L +#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L +#define BUS_CNTL1__AGPCLK_VALID 0x80000000L + +/* BUS_CNTL1 */ +#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 +#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 +#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 +#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b +#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a +#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c +#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f + +/* CRTC_OFFSET_CNTL */ +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L +#define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) +#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) +#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) +#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) +#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) +#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) +#define R300_CRTC_X_Y_MODE_EN (1 << 9) +#define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) +#define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) +#define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) +#define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) +#define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) +#define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) +#define R300_CRTC_MICRO_TILE_EN (1 << 13) +#define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) +#define R300_CRTC_MACRO_TILE_EN (1 << 15) + +/* CRTC_GEN_CNTL */ +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L +#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L +#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L +#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L +#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L +#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L +#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L + +/* CRTC2_GEN_CNTL */ +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L +#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L +#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L +#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L + +/* AGP_CNTL */ +#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL +#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L +#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L +#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L +#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L +#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L +#define AGP_CNTL__EN_2X_STBB 0x00000400L +#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L +#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L +#define AGP_CNTL__SBA_DIS_MASK 0x00001000L +#define AGP_CNTL__SBA_DIS 0x00001000L +#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L +#define AGP_CNTL__AGP_REV_ID 0x00002000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L +#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L +#define AGP_CNTL__FORCE_INT_VREF 0x00010000L +#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L +#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L +#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L +#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L +#define AGP_CNTL__EN_RBFCALM 0x00800000L +#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L +#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L +#define AGP_CNTL__DIS_RBF_MASK 0x02000000L +#define AGP_CNTL__DIS_RBF 0x02000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L +#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L + +/* AGP_CNTL */ +#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 +#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 +#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 +#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a +#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b +#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c +#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d +#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f +#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 +#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 +#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 +#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 +#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 +#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 +#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 +#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a +#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b +#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e + +/* DISP_MISC_CNTL */ +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L +#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L +#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L +#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L +#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L +#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L + +/* DISP_PWR_MAN */ +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L +#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L +#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L +#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L +#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L +#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L +#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L +#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L + +/* MC_IND_INDEX */ +#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL +#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L +#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L + +/* MC_IND_DATA */ +#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL + +/* MC_CHP_IO_CNTL_A1 */ +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f + +/* MC_CHP_IO_CNTL_B1 */ +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f + +/* MC_CHP_IO_CNTL_A1 */ +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L + +/* MC_CHP_IO_CNTL_B1 */ +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L + +/* MEM_SDRAM_MODE_REG */ +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L + +/* MEM_SDRAM_MODE_REG */ +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f + +/* MEM_REFRESH_CNTL */ +#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L +#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L + +/* MC_STATUS */ +#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L +#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L +#define MC_STATUS__MC_IDLE_MASK 0x00000004L +#define MC_STATUS__MC_IDLE 0x00000004L +#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L +#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L +#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L +#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L +#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L +#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L +#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L +#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L +#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L +#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L + +/* MDLL_CKO */ +#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L +#define MDLL_CKO__MCKOA_SLEEP 0x00000001L +#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L +#define MDLL_CKO__MCKOA_RESET 0x00000002L +#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL +#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L +#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L +#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L +#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L +#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L +#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L +#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L +#define MDLL_CKO__MCKOB_SLEEP 0x00010000L +#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L +#define MDLL_CKO__MCKOB_RESET 0x00020000L +#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L +#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L +#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L +#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L +#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L +#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L +#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L + +/* MDLL_RDCKA */ +#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L +#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L +#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L +#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L +#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L +#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L + +/* MDLL_RDCKB */ +#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L +#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L +#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L +#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L +#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L +#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L + +#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L +#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L +#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L +#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L +#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L +#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L +#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L +#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L + +#define pllCLK_PIN_CNTL 0x0001 +#define pllPPLL_CNTL 0x0002 +#define pllPPLL_REF_DIV 0x0003 +#define pllPPLL_DIV_0 0x0004 +#define pllPPLL_DIV_1 0x0005 +#define pllPPLL_DIV_2 0x0006 +#define pllPPLL_DIV_3 0x0007 +#define pllVCLK_ECP_CNTL 0x0008 +#define pllHTOTAL_CNTL 0x0009 +#define pllM_SPLL_REF_FB_DIV 0x000A +#define pllAGP_PLL_CNTL 0x000B +#define pllSPLL_CNTL 0x000C +#define pllSCLK_CNTL 0x000D +#define pllMPLL_CNTL 0x000E +#define pllMDLL_CKO 0x000F +#define pllMDLL_RDCKA 0x0010 +#define pllMDLL_RDCKB 0x0011 +#define pllMCLK_CNTL 0x0012 +#define pllPLL_TEST_CNTL 0x0013 +#define pllCLK_PWRMGT_CNTL 0x0014 +#define pllPLL_PWRMGT_CNTL 0x0015 +#define pllCG_TEST_MACRO_RW_WRITE 0x0016 +#define pllCG_TEST_MACRO_RW_READ 0x0017 +#define pllCG_TEST_MACRO_RW_DATA 0x0018 +#define pllCG_TEST_MACRO_RW_CNTL 0x0019 +#define pllDISP_TEST_MACRO_RW_WRITE 0x001A +#define pllDISP_TEST_MACRO_RW_READ 0x001B +#define pllDISP_TEST_MACRO_RW_DATA 0x001C +#define pllDISP_TEST_MACRO_RW_CNTL 0x001D +#define pllSCLK_CNTL2 0x001E +#define pllMCLK_MISC 0x001F +#define pllTV_PLL_FINE_CNTL 0x0020 +#define pllTV_PLL_CNTL 0x0021 +#define pllTV_PLL_CNTL1 0x0022 +#define pllTV_DTO_INCREMENTS 0x0023 +#define pllSPLL_AUX_CNTL 0x0024 +#define pllMPLL_AUX_CNTL 0x0025 +#define pllP2PLL_CNTL 0x002A +#define pllP2PLL_REF_DIV 0x002B +#define pllP2PLL_DIV_0 0x002C +#define pllPIXCLKS_CNTL 0x002D +#define pllHTOTAL2_CNTL 0x002E +#define pllSSPLL_CNTL 0x0030 +#define pllSSPLL_REF_DIV 0x0031 +#define pllSSPLL_DIV_0 0x0032 +#define pllSS_INT_CNTL 0x0033 +#define pllSS_TST_CNTL 0x0034 +#define pllSCLK_MORE_CNTL 0x0035 + +#define ixMC_PERF_CNTL 0x0000 +#define ixMC_PERF_SEL 0x0001 +#define ixMC_PERF_REGION_0 0x0002 +#define ixMC_PERF_REGION_1 0x0003 +#define ixMC_PERF_COUNT_0 0x0004 +#define ixMC_PERF_COUNT_1 0x0005 +#define ixMC_PERF_COUNT_2 0x0006 +#define ixMC_PERF_COUNT_3 0x0007 +#define ixMC_PERF_COUNT_MEMCH_A 0x0008 +#define ixMC_PERF_COUNT_MEMCH_B 0x0009 +#define ixMC_IMP_CNTL 0x000A +#define ixMC_CHP_IO_CNTL_A0 0x000B +#define ixMC_CHP_IO_CNTL_A1 0x000C +#define ixMC_CHP_IO_CNTL_B0 0x000D +#define ixMC_CHP_IO_CNTL_B1 0x000E +#define ixMC_IMP_CNTL_0 0x000F +#define ixTC_MISMATCH_1 0x0010 +#define ixTC_MISMATCH_2 0x0011 +#define ixMC_BIST_CTRL 0x0012 +#define ixREG_COLLAR_WRITE 0x0013 +#define ixREG_COLLAR_READ 0x0014 +#define ixR300_MC_IMP_CNTL 0x0018 +#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 +#define ixR300_MC_CHP_IO_CNTL_A1 0x001a +#define ixR300_MC_CHP_IO_CNTL_B0 0x001b +#define ixR300_MC_CHP_IO_CNTL_B1 0x001c +#define ixR300_MC_CHP_IO_CNTL_C0 0x001d +#define ixR300_MC_CHP_IO_CNTL_C1 0x001e +#define ixR300_MC_CHP_IO_CNTL_D0 0x001f +#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 +#define ixR300_MC_IMP_CNTL_0 0x0021 +#define ixR300_MC_ELPIDA_CNTL 0x0022 +#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 +#define ixR300_MC_READ_CNTL_CD 0x0024 +#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 +#define ixR300_MC_DEBUG_CNTL 0x0026 +#define ixR300_MC_BIST_CNTL_0 0x0028 +#define ixR300_MC_BIST_CNTL_1 0x0029 +#define ixR300_MC_BIST_CNTL_2 0x002a +#define ixR300_MC_BIST_CNTL_3 0x002b +#define ixR300_MC_BIST_CNTL_4 0x002c +#define ixR300_MC_BIST_CNTL_5 0x002d +#define ixR300_MC_IMP_STATUS 0x002e +#define ixR300_MC_DLL_CNTL 0x002f +#define NB_TOM 0x15C + +/****************** for VIDIX **************************/ + +/* BUS_CNTL bit constants */ +#define BUS_DBL_RESYNC 0x00000001 +#define BUS_MSTR_RESET 0x00000002 +#define BUS_FLUSH_BUF 0x00000004 +#define BUS_STOP_REQ_DIS 0x00000008 +#define BUS_ROTATION_DIS 0x00000010 +#define BUS_MASTER_DIS 0x00000040 +#define BUS_ROM_WRT_EN 0x00000080 +#define BUS_DIS_ROM 0x00001000 +#define BUS_PCI_READ_RETRY_EN 0x00002000 +#define BUS_AGP_AD_STEPPING_EN 0x00004000 +#define BUS_PCI_WRT_RETRY_EN 0x00008000 +#define BUS_MSTR_RD_MULT 0x00100000 +#define BUS_MSTR_RD_LINE 0x00200000 +#define BUS_SUSPEND 0x00400000 +#define LAT_16X 0x00800000 +#define BUS_RD_DISCARD_EN 0x01000000 +#define BUS_RD_ABORT_EN 0x02000000 +#define BUS_MSTR_WS 0x04000000 +#define BUS_PARKING_DIS 0x08000000 +#define BUS_MSTR_DISCONNECT_EN 0x10000000 +#define BUS_WRT_BURST 0x20000000 +#define BUS_READ_BURST 0x40000000 +#define BUS_RDY_READ_DLY 0x80000000 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +#define BUS_WAIT_ON_LOCK_EN (1 << 4) +#define I2C_CNTL_0 0x0090 +#define I2C_DONE (1<<0) +#define I2C_NACK (1<<1) +#define I2C_HALT (1<<2) +#define I2C_SOFT_RST (1<<5) +#define I2C_DRIVE_EN (1<<6) +#define I2C_DRIVE_SEL (1<<7) +#define I2C_START (1<<8) +#define I2C_STOP (1<<9) +#define I2C_RECEIVE (1<<10) +#define I2C_ABORT (1<<11) +#define I2C_GO (1<<12) +#define I2C_SEL (1<<16) +#define I2C_EN (1<<17) +#define I2C_CNTL_1 0x0094 +#define I2C_DATA 0x0098 +#define CONFIG_CNTL 0x00E0 +/* CONFIG_CNTL bit constants */ +#define CFG_VGA_RAM_EN 0x00000100 +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define AGP_CNTL 0x0174 +#define AGP_APER_SIZE_256MB (0x00 << 0) +#define AGP_APER_SIZE_128MB (0x20 << 0) +#define AGP_APER_SIZE_64MB (0x30 << 0) +#define AGP_APER_SIZE_32MB (0x38 << 0) +#define AGP_APER_SIZE_16MB (0x3c << 0) +#define AGP_APER_SIZE_8MB (0x3e << 0) +#define AGP_APER_SIZE_4MB (0x3f << 0) +#define AGP_APER_SIZE_MASK (0x3f << 0) +#define AMCGPIO_A_REG 0x01a0 +#define AMCGPIO_EN_REG 0x01a8 +#define AMCGPIO_MASK 0x0194 +#define AMCGPIO_Y_REG 0x01a4 +#define MPP_TB_CONFIG 0x01c0 /* ? */ +#define MPP_GP_CONFIG 0x01c8 /* ? */ +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +#define AGP_1X_MODE 0x01 +#define AGP_2X_MODE 0x02 +#define AGP_4X_MODE 0x04 +#define AGP_MODE_MASK 0x07 +#define AGP_COMMAND 0x0F60 + +/* Video muxer unit */ +#define VIDEOMUX_CNTL 0x0190 +#define VIPPAD_MASK 0x0198 +#define VIPPAD1_A 0x01AC +#define VIPPAD1_EN 0x01B0 +#define VIPPAD1_Y 0x01B4 + +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +/* DAC_CNTL bit constants */ +#define DAC_8BIT_EN 0x00000100 +#define DAC_4BPP_PIX_ORDER 0x00000200 +#define DAC_CRC_EN 0x00080000 +#define DAC_MASK_ALL (0xff << 24) +#define DAC_VGA_ADR_EN (1 << 13) +#define DAC_RANGE_CNTL (3 << 0) +#define DAC_BLANKING (1 << 2) +#define DAC_CNTL2 0x007c +/* DAC_CNTL2 bit constants */ +#define DAC2_DAC_CLK_SEL (1 << 0) +#define DAC2_DAC2_CLK_SEL (1 << 1) +#define DAC2_PALETTE_ACC_CTL (1 << 5) +#define TV_DAC_CNTL 0x088c +/* TV_DAC_CNTL bit constants */ +#define TV_DAC_STD_MASK 0x0300 +#define TV_DAC_RDACPD (1 << 24) +#define TV_DAC_GDACPD (1 << 25) +#define TV_DAC_BDACPD (1 << 26) +#define CRTC_GEN_CNTL 0x0050 +/* CRTC_GEN_CNTL bit constants */ +//#define CRTC_DBL_SCAN_EN 0x00000001 +#define CRTC_INTERLACE_EN (1 << 1) +#define CRTC_CSYNC_EN (1 << 4) +//#define CRTC_CUR_EN 0x00010000 +#define CRTC_CUR_MODE_MASK (7 << 17) +#define CRTC_ICON_EN (1 << 20) +#define CRTC_EXT_DISP_EN (1 << 24) +#define CRTC_EN (1 << 25) +#define CRTC_DISP_REQ_EN_B (1 << 26) +#define CRTC2_GEN_CNTL 0x03f8 +/* CRTC2_GEN_CNTL bit constants */ +#define CRTC2_DBL_SCAN_EN (1 << 0) +#define CRTC2_INTERLACE_EN (1 << 1) +#define CRTC2_SYNC_TRISTAT (1 << 4) +#define CRTC2_HSYNC_TRISTAT (1 << 5) +#define CRTC2_VSYNC_TRISTAT (1 << 6) +#define CRTC2_CRT2_ON (1 << 7) +#define CRTC2_ICON_EN (1 << 15) +#define CRTC2_CUR_EN (1 << 16) +#define CRTC2_CUR_MODE_MASK (7 << 20) +#define CRTC2_DISP_DIS (1 << 23) +#define CRTC2_EN (1 << 25) +#define CRTC2_DISP_REQ_EN_B (1 << 26) +#define CRTC2_HSYNC_DIS (1 << 28) +#define CRTC2_VSYNC_DIS (1 << 29) +#define MEM_CNTL 0x0140 +/* MEM_CNTL bit constants */ +#define MEM_CTLR_STATUS_IDLE 0x00000000 +#define MEM_CTLR_STATUS_BUSY 0x00100000 +#define MEM_SEQNCR_STATUS_IDLE 0x00000000 +#define MEM_SEQNCR_STATUS_BUSY 0x00200000 +#define MEM_ARBITER_STATUS_IDLE 0x00000000 +#define MEM_ARBITER_STATUS_BUSY 0x00400000 +#define MEM_REQ_UNLOCK 0x00000000 +#define MEM_REQ_LOCK 0x00800000 +#define EXT_MEM_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#define MEM_IO_CNTL_A1 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_DEBUG 0x0188 +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_FB_LOCATION 0x0148 +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define SURFACE_CNTL 0x0B00 +/* SURFACE_CNTL bit constants */ +# define SURF_TRANSLATION_DIS (1 << 8) +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +#define VSYNC_INT_AK (1 << 2) +#define VSYNC_INT (1 << 2) +#define CRTC_EXT_CNTL 0x0054 +/* CRTC_EXT_CNTL bit constants */ +#define CRTC_VGA_XOVERSCAN (1 << 0) +#define VGA_ATI_LINEAR 0x00000008 +#define VGA_128KAP_PAGING 0x00000010 +#define XCRT_CNT_EN (1 << 6) +#define CRTC_HSYNC_DIS (1 << 8) +#define CRTC_VSYNC_DIS (1 << 9) +#define CRTC_DISPLAY_DIS (1 << 10) +#define CRTC_SYNC_TRISTAT (1 << 11) +#define CRTC_CRT_ON (1 << 15) +#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +#define CRTC_HSYNC_DIS_BYTE (1 << 0) +#define CRTC_VSYNC_DIS_BYTE (1 << 1) +#define CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define WAIT_UNTIL 0x1720 +#define WAIT_CRTC_PFLIP (1 << 0) +#define WAIT_2D_IDLECLEAN (1 << 16) +#define WAIT_3D_IDLECLEAN (1 << 17) +#define WAIT_HOST_IDLECLEAN (1 << 18) +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +#define RBBM_FIFOCNT_MASK 0x007f +#define RBBM_ACTIVE (1 << 31) +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +/* RBBM_SOFT_RESET bit constants */ +#define SOFT_RESET_CP (1 << 0) +#define SOFT_RESET_HI (1 << 1) +#define SOFT_RESET_SE (1 << 2) +#define SOFT_RESET_RE (1 << 3) +#define SOFT_RESET_PP (1 << 4) +#define SOFT_RESET_E2 (1 << 5) +#define SOFT_RESET_RB (1 << 6) +#define SOFT_RESET_HDP (1 << 7) +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +/* CRTC_STATUS bit constants */ +#define CRTC_VBLANK 0x00000001 +#define CRTC_VBLANK_SAVE ( 1 << 1) +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +#define CRTC_H_TOTAL (0x03ff << 0) +#define CRTC_H_TOTAL_SHIFT 0 +#define CRTC_H_DISP (0x01ff << 16) +#define CRTC_H_DISP_SHIFT 16 +#define CRTC2_H_TOTAL_DISP 0x0300 +#define CRTC2_H_TOTAL (0x03ff << 0) +#define CRTC2_H_TOTAL_SHIFT 0 +#define CRTC2_H_DISP (0x01ff << 16) +#define CRTC2_H_DISP_SHIFT 16 +#define CRTC_H_SYNC_STRT_WID 0x0204 +#define CRTC_H_SYNC_STRT_PIX (0x07 << 0) +#define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +#define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +#define CRTC_H_SYNC_WID (0x3f << 16) +#define CRTC_H_SYNC_WID_SHIFT 16 +#define CRTC_H_SYNC_POL (1 << 23) +#define CRTC2_H_SYNC_STRT_WID 0x0304 +#define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +#define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +#define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +#define CRTC2_H_SYNC_WID (0x3f << 16) +#define CRTC2_H_SYNC_WID_SHIFT 16 +#define CRTC2_H_SYNC_POL (1 << 23) +#define CRTC_V_TOTAL_DISP 0x0208 +#define CRTC_V_TOTAL (0x07ff << 0) +#define CRTC_V_TOTAL_SHIFT 0 +#define CRTC_V_DISP (0x07ff << 16) +#define CRTC_V_DISP_SHIFT 16 +#define CRTC2_V_TOTAL_DISP 0x0308 +#define CRTC2_V_TOTAL (0x07ff << 0) +#define CRTC2_V_TOTAL_SHIFT 0 +#define CRTC2_V_DISP (0x07ff << 16) +#define CRTC2_V_DISP_SHIFT 16 +#define CRTC_V_SYNC_STRT_WID 0x020C +#define CRTC_V_SYNC_STRT (0x7ff << 0) +#define CRTC_V_SYNC_STRT_SHIFT 0 +#define CRTC_V_SYNC_WID (0x1f << 16) +#define CRTC_V_SYNC_WID_SHIFT 16 +#define CRTC_V_SYNC_POL (1 << 23) +#define CRTC2_V_SYNC_STRT_WID 0x030C +#define CRTC2_V_SYNC_STRT (0x7ff << 0) +#define CRTC2_V_SYNC_STRT_SHIFT 0 +#define CRTC2_V_SYNC_WID (0x1f << 16) +#define CRTC2_V_SYNC_WID_SHIFT 16 +#define CRTC2_V_SYNC_POL (1 << 23) +#define CRTC_VLINE_CRNT_VLINE 0x0210 +#define CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define CRTC2_VLINE_CRNT_VLINE 0x0310 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC2_CRNT_FRAME 0x0314 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC2_GUI_TRIG_VLINE 0x0318 +#define CRTC_DEBUG 0x021C +#define CRTC2_DEBUG 0x031C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC2_OFFSET 0x0324 +#define CRTC_OFFSET_CNTL 0x0228 +#define CRTC_TILE_EN (1 << 15) +#define CRTC2_OFFSET_CNTL 0x0328 +#define CRTC2_TILE_EN (1 << 15) +#define CRTC_PITCH 0x022C +#define CRTC2_PITCH 0x032C +#define TMDS_CRC 0x02a0 +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC2_H_TOTAL_DISP 0x0350 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define FP_CRTC2_V_TOTAL_DISP 0x0354 +#define FP_CRTC_H_TOTAL_MASK 0x000003ff +#define FP_CRTC_H_DISP_MASK 0x01ff0000 +#define FP_CRTC_V_TOTAL_MASK 0x00000fff +#define FP_CRTC_V_DISP_MASK 0x0fff0000 +#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +#define FP_H_SYNC_WID_MASK 0x003f0000 +#define FP_V_SYNC_STRT_MASK 0x00000fff +#define FP_V_SYNC_WID_MASK 0x001f0000 +#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_H_DISP_SHIFT 0x00000010 +#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_V_DISP_SHIFT 0x00000010 +#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +#define FP_H_SYNC_WID_SHIFT 0x00000010 +#define FP_V_SYNC_STRT_SHIFT 0x00000000 +#define FP_V_SYNC_WID_SHIFT 0x00000010 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ +#define CUR_LOCK 0x80000000 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define CUR2_OFFSET 0x0360 +#define CUR2_HORZ_VERT_POSN 0x0364 +#define CUR2_HORZ_VERT_OFF 0x0368 +#define CUR2_LOCK (1 << 31) +#define CUR2_CLR0 0x036c +#define CUR2_CLR1 0x0370 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +/* FP_GEN_CNTL bit constants */ +#define FP_FPON (1 << 0) +#define FP_TMDS_EN (1 << 2) +#define FP_EN_TMDS (1 << 7) +#define FP_DETECT_SENSE (1 << 8) +#define FP_SEL_CRTC2 (1 << 13) +#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +#define FP_CRTC_USE_SHADOW_VEND (1 << 18) +#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +#define FP_DFP_SYNC_SEL (1 << 21) +#define FP_CRTC_LOCK_8DOT (1 << 22) +#define FP_CRT_SYNC_SEL (1 << 23) +#define FP_USE_SHADOW_EN (1 << 24) +#define FP_CRT_SYNC_ALT (1 << 26) +#define FP2_GEN_CNTL 0x0288 +/* FP2_GEN_CNTL bit constants */ +#define FP2_FPON (1 << 0) +#define FP2_TMDS_EN (1 << 2) +#define FP2_EN_TMDS (1 << 7) +#define FP2_DETECT_SENSE (1 << 8) +#define FP2_SEL_CRTC2 (1 << 13) +#define FP2_FP_POL (1 << 16) +#define FP2_LP_POL (1 << 17) +#define FP2_SCK_POL (1 << 18) +#define FP2_LCD_CNTL_MASK (7 << 19) +#define FP2_PAD_FLOP_EN (1 << 22) +#define FP2_CRC_EN (1 << 23) +#define FP2_CRC_READ_EN (1 << 24) +#define FP_HORZ_STRETCH 0x028C +#define FP_HORZ2_STRETCH 0x038C +#define HORZ_STRETCH_RATIO_MASK 0xffff +#define HORZ_STRETCH_RATIO_MAX 4096 +#define HORZ_PANEL_SIZE (0x1ff << 16) +#define HORZ_PANEL_SHIFT 16 +#define HORZ_STRETCH_PIXREP (0 << 25) +#define HORZ_STRETCH_BLEND (1 << 26) +#define HORZ_STRETCH_ENABLE (1 << 25) +#define HORZ_AUTO_RATIO (1 << 27) +#define HORZ_FP_LOOP_STRETCH (0x7 << 28) +#define HORZ_AUTO_RATIO_INC (1 << 31) +#define FP_VERT_STRETCH 0x0290 +#define FP_VERT2_STRETCH 0x0390 +#define VERT_PANEL_SIZE (0xfff << 12) +#define VERT_PANEL_SHIFT 12 +#define VERT_STRETCH_RATIO_MASK 0xfff +#define VERT_STRETCH_RATIO_SHIFT 0 +#define VERT_STRETCH_RATIO_MAX 4096 +#define VERT_STRETCH_ENABLE (1 << 25) +#define VERT_STRETCH_LINEREP (0 << 26) +#define VERT_STRETCH_BLEND (1 << 26) +#define VERT_AUTO_RATIO_EN (1 << 27) +#define VERT_STRETCH_RESERVED 0xf1000000 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_H2_SYNC_STRT_WID 0x03C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define FP_V2_SYNC_STRT_WID 0x03C8 +#define LVDS_GEN_CNTL 0x02d0 +#define LVDS_ON (1 << 0) +#define LVDS_DISPLAY_DIS (1 << 1) +#define LVDS_PANEL_TYPE (1 << 2) +#define LVDS_PANEL_FORMAT (1 << 3) +#define LVDS_EN (1 << 7) +#define LVDS_DIGON (1 << 18) +#define LVDS_BLON (1 << 19) +#define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_PLL_CNTL 0x02d4 +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +#define DDA_CONFIG 0x02e0 +#define DDA_ON_OFF 0x02e4 + +#define GRPH_BUFFER_CNTL 0x02F0 +#define VGA_BUFFER_CNTL 0x02F4 + +/* first overlay unit (there is only one) */ + +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_EXCLUSIVE_HORZ 0x0408 +#define EXCL_HORZ_START_MASK 0x000000ff +#define EXCL_HORZ_END_MASK 0x0000ff00 +#define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +#define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define OV0_EXCLUSIVE_VERT 0x040C +#define EXCL_VERT_START_MASK 0x000003ff +#define EXCL_VERT_END_MASK 0x03ff0000 +#define OV0_REG_LOAD_CNTL 0x0410 +#define REG_LD_CTL_LOCK 0x00000001L +#define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +#define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +#define REG_LD_CTL_LOCK_READBACK 0x00000008L +#define OV0_SCALE_CNTL 0x0420 +#define SCALER_PIX_EXPAND 0x00000001L +#define SCALER_Y2R_TEMP 0x00000002L +#define SCALER_HORZ_PICK_NEAREST 0x00000004L +#define SCALER_VERT_PICK_NEAREST 0x00000008L +#define SCALER_SIGNED_UV 0x00000010L +#define SCALER_GAMMA_SEL_MASK 0x00000060L +#define SCALER_GAMMA_SEL_BRIGHT 0x00000000L +#define SCALER_GAMMA_SEL_G22 0x00000020L +#define SCALER_GAMMA_SEL_G18 0x00000040L +#define SCALER_GAMMA_SEL_G14 0x00000060L +#define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +#define SCALER_SURFAC_FORMAT 0x00000f00L +#define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */ +#define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */ +#define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */ +#define SCALER_SOURCE_15BPP 0x00000300L +#define SCALER_SOURCE_16BPP 0x00000400L +/*# define SCALER_SOURCE_24BPP 0x00000500L*/ +#define SCALER_SOURCE_32BPP 0x00000600L +#define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */ +#define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */ +#define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */ +#define SCALER_SOURCE_YUV12 0x00000A00L +#define SCALER_SOURCE_VYUY422 0x00000B00L +#define SCALER_SOURCE_YVYU422 0x00000C00L +#define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */ +#define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */ +#define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */ +#define SCALER_ADAPTIVE_DEINT 0x00001000L +#define R200_SCALER_TEMPORAL_DEINT 0x00002000L +#define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */ +#define SCALER_SMART_SWITCH 0x00008000L +#define SCALER_BURST_PER_PLANE 0x007f0000L +#define SCALER_DOUBLE_BUFFER 0x01000000L +#define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */ +#define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */ +#define SCALER_DIS_LIMIT 0x08000000L +#define SCALER_PRG_LOAD_START 0x10000000L +#define SCALER_INT_EMU 0x20000000L +#define SCALER_ENABLE 0x40000000L +#define SCALER_SOFT_RESET 0x80000000L +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +#define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +#define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P23_V_ACCUM_INIT 0x042C +#define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L +#define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +#define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +#define P1_ACTIVE_LINES_M1 0x0fff0000L +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +#define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +#define P23_ACTIVE_LINES_M1 0x07ff0000L +#define OV0_BASE_ADDR 0x043C +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +#define VIF_BUF0_PITCH_SEL 0x00000001L +#define VIF_BUF0_TILE_ADRS 0x00000002L +#define VIF_BUF0_BASE_ADRS_MASK 0xfffffff0L +#define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +#define VIF_BUF1_PITCH_SEL 0x00000001L +#define VIF_BUF1_TILE_ADRS 0x00000002L +#define VIF_BUF1_BASE_ADRS_MASK 0xfffffff0L +#define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +#define VIF_BUF2_PITCH_SEL 0x00000001L +#define VIF_BUF2_TILE_ADRS 0x00000002L +#define VIF_BUF2_BASE_ADRS_MASK 0xfffffff0L +#define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF3_BASE_ADRS 0x044C +#define VIF_BUF3_PITCH_SEL 0x00000001L +#define VIF_BUF3_TILE_ADRS 0x00000002L +#define VIF_BUF3_BASE_ADRS_MASK 0xfffffff0L +#define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +#define VIF_BUF4_PITCH_SEL 0x00000001L +#define VIF_BUF4_TILE_ADRS 0x00000002L +#define VIF_BUF4_BASE_ADRS_MASK 0xfffffff0L +#define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +#define VIF_BUF5_PITCH_SEL 0x00000001L +#define VIF_BUF5_TILE_ADRS 0x00000002L +#define VIF_BUF5_BASE_ADRS_MASK 0xfffffff0L +#define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTL 0x0470 +#define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +#define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +#define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +#define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +#define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +#define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +#define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +#define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +#define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +#define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +#define FILTER_PROGRAMMABLE_COEF 0x00000000 +#define FILTER_HARD_SCALE_HORZ_Y 0x00000001 +#define FILTER_HARD_SCALE_HORZ_UV 0x00000002 +#define FILTER_HARD_SCALE_VERT_Y 0x00000004 +#define FILTER_HARD_SCALE_VERT_UV 0x00000008 +#define FILTER_HARDCODED_COEF 0x0000000F +#define FILTER_COEF_MASK 0x0000000F +/* When bit is set hard coded coefficients are used. */ + +/* + Top quality 4x4-tap filtered vertical and horizontal scaler. + It allows up to 64:1 upscaling and downscaling without + performance or quality degradation. +*/ +#define OV0_FOUR_TAP_COEF_0 0x04B0 +#define OV0_FOUR_TAP_PHASE_0_TAP_0 0x0000000F +#define OV0_FOUR_TAP_PHASE_0_TAP_1 0x00007F00 +#define OV0_FOUR_TAP_PHASE_0_TAP_2 0x007F0000 +#define OV0_FOUR_TAP_PHASE_0_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +#define OV0_FOUR_TAP_PHASE_1_5_TAP_0 0x0000000F +#define OV0_FOUR_TAP_PHASE_1_5_TAP_1 0x00007F00 +#define OV0_FOUR_TAP_PHASE_1_5_TAP_2 0x007F0000 +#define OV0_FOUR_TAP_PHASE_1_5_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +#define OV0_FOUR_TAP_PHASE_2_6_TAP_0 0x0000000F +#define OV0_FOUR_TAP_PHASE_2_6_TAP_1 0x00007F00 +#define OV0_FOUR_TAP_PHASE_2_6_TAP_2 0x007F0000 +#define OV0_FOUR_TAP_PHASE_2_6_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_3 0x04BC +#define OV0_FOUR_TAP_PHASE_3_7_TAP_0 0x0000000F +#define OV0_FOUR_TAP_PHASE_3_7_TAP_1 0x00007F00 +#define OV0_FOUR_TAP_PHASE_3_7_TAP_2 0x007F0000 +#define OV0_FOUR_TAP_PHASE_3_7_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_4 0x04C0 +#define OV0_FOUR_TAP_PHASE_4_TAP_0 0x0000000F +#define OV0_FOUR_TAP_PHASE_4_TAP_1 0x00007F00 +#define OV0_FOUR_TAP_PHASE_4_TAP_2 0x007F0000 +#define OV0_FOUR_TAP_PHASE_4_TAP_3 0x0F000000 +/* 0th_tap means that the left most of top most pixel in a set of four will + be multiplied by this coefficient. */ + +#define OV0_FLAG_CNTL 0x04DC +#define OV0_SLICE_CNTL 0x04E0 +#define SLICE_CNTL_DISABLE 0x40000000 +/* Video and graphics keys allow alpha blending, color correction + and many other video effects */ +#define OV0_VID_KEY_CLR 0x04E4 +#define OV0_VID_KEY_MSK 0x04E8 +#define OV0_GRAPHICS_KEY_CLR 0x04EC +#define OV0_GRAPHICS_KEY_MSK 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +#define VIDEO_KEY_FN_MASK 0x00000003L +#define VIDEO_KEY_FN_FALSE 0x00000000L +#define VIDEO_KEY_FN_TRUE 0x00000001L +#define VIDEO_KEY_FN_EQ 0x00000002L +#define VIDEO_KEY_FN_NE 0x00000003L +#define GRAPHIC_KEY_FN_MASK 0x00000030L +#define GRAPHIC_KEY_FN_FALSE 0x00000000L +#define GRAPHIC_KEY_FN_TRUE 0x00000010L +#define GRAPHIC_KEY_FN_EQ 0x00000020L +#define GRAPHIC_KEY_FN_NE 0x00000030L +#define CMP_MIX_MASK 0x00000100L +#define CMP_MIX_OR 0x00000000L +#define CMP_MIX_AND 0x00000100L +#define OV0_TEST 0x04F8 +#define OV0_SCALER_Y2R_DISABLE 0x00000001L +#define OV0_SUBPIC_ONLY 0x00000008L +#define OV0_EXTENSE 0x00000010L +#define OV0_SWAP_UV 0x00000020L +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +/* These registers exist on R200 only */ +#define OV0_GAMMA_80_BF 0x0E00 +#define OV0_GAMMA_C0_FF 0x0E04 +#define OV0_GAMMA_100_13F 0x0E08 +#define OV0_GAMMA_140_17F 0x0E0C +#define OV0_GAMMA_180_1BF 0x0E10 +#define OV0_GAMMA_1C0_1FF 0x0E14 +#define OV0_GAMMA_200_23F 0x0E18 +#define OV0_GAMMA_240_27F 0x0E1C +#define OV0_GAMMA_280_2BF 0x0E20 +#define OV0_GAMMA_2C0_2FF 0x0E24 +#define OV0_GAMMA_300_33F 0x0E28 +#define OV0_GAMMA_340_37F 0x0E2C +/* End of R200 specific definitions */ +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 + +/* + IDCT ENGINE: + It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag + and IDCT into an IDCT engine to complement the motion compensation engine. +*/ +#define IDCT_RUNS 0x1F80 +#define IDCT_LEVELS 0x1F84 +#define IDCT_AUTH_CONTROL 0x1F88 +#define IDCT_AUTH 0x1F8C +#define IDCT_CONTROL 0x1FBC + +#define SE_MC_SRC2_CNTL 0x19D4 +#define SE_MC_SRC1_CNTL 0x19D8 +#define SE_MC_DST_CNTL 0x19DC +#define SE_MC_CNTL_START 0x19E0 +#define SE_MC_BUF_BASE 0x19E4 +#define PP_MC_CONTEXT 0x19E8 + +/* + SUBPICTURE UNIT: + Decompressing, scaling and alpha blending the compressed bitmap on the fly. + Provide optimal DVD subpicture qualtity. +*/ +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 + +#define CP_RB_BASE 0x0700 +#define CP_RB_CNTL 0x0704 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define CP_CSQ_CNTL 0x0740 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DMA_GUI_TABLE_ADDR 0x0780 +#define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff +#define DMA_GUI_COMMAND__INTDIS 0x40000000 +#define DMA_GUI_COMMAND__EOL 0x80000000 +#define DMA_GUI_SRC_ADDR 0x0784 +#define DMA_GUI_DST_ADDR 0x0788 +#define DMA_GUI_COMMAND 0x078C +#define DMA_GUI_STATUS 0x0790 +#define DMA_GUI_ACT_DSCRPTR 0x0794 +#define DMA_VID_TABLE_ADDR 0x07A0 +#define DMA_VID_SRC_ADDR 0x07A4 +#define DMA_VID_DST_ADDR 0x07A8 +#define DMA_VID_COMMAND 0x07AC +#define DMA_VID_STATUS 0x07B0 +#define DMA_VID_ACT_DSCRPTR 0x07B4 +#define CP_ME_CNTL 0x07D0 +#define CP_ME_RAM_ADDR 0x07D4 +#define CP_ME_RAM_RADDR 0x07D8 +#define CP_ME_RAM_DATAH 0x07DC +#define CP_ME_RAM_DATAL 0x07E0 +#define CP_CSQ_ADDR 0x07F0 +#define CP_CSQ_DATA 0x07F4 +#define CP_CSQ_STAT 0x07F8 + +#define DISP_MISC_CNTL 0x0D00 +#define SOFT_RESET_GRPH_PP (1 << 0) +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C + +/* first capture unit */ + +#define VID_BUFFER_CONTROL 0x0900 +#define CAP_INT_CNTL 0x0908 +#define CAP_INT_STATUS 0x090C +#define FCP_CNTL 0x0910 +#define FCP0_SRC_PCICLK 0 +#define FCP0_SRC_PCLK 1 +#define FCP0_SRC_PCLKb 2 +#define FCP0_SRC_HREF 3 +#define FCP0_SRC_GND 4 +#define FCP0_SRC_HREFb 5 +#define CAP0_BUF0_OFFSET 0x0920 +#define CAP0_BUF1_OFFSET 0x0924 +#define CAP0_BUF0_EVEN_OFFSET 0x0928 +#define CAP0_BUF1_EVEN_OFFSET 0x092C +#define CAP0_BUF_PITCH 0x0930 +#define CAP0_V_WINDOW 0x0934 +#define CAP0_H_WINDOW 0x0938 +#define CAP0_VBI0_OFFSET 0x093C +#define CAP0_VBI1_OFFSET 0x0940 +#define CAP0_VBI_V_WINDOW 0x0944 +#define CAP0_VBI_H_WINDOW 0x0948 +#define CAP0_PORT_MODE_CNTL 0x094C +#define CAP0_TRIG_CNTL 0x0950 +#define CAP0_DEBUG 0x0954 +#define CAP0_CONFIG 0x0958 +#define CAP0_CONFIG_CONTINUOS 0x00000001 +#define CAP0_CONFIG_START_FIELD_EVEN 0x00000002 +#define CAP0_CONFIG_START_BUF_GET 0x00000004 +#define CAP0_CONFIG_START_BUF_SET 0x00000008 +#define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 +#define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 +#define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 +#define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 +#define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 +#define CAP0_CONFIG_MIRROR_EN 0x00000200 +#define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 +#define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 +#define CAP0_CONFIG_ANC_DECODE_EN 0x00001000 +#define CAP0_CONFIG_VBI_EN 0x00002000 +#define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 +#define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 +#define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 +#define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 +#define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 +#define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 +#define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 +#define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 +#define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 +#define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 +#define CAP0_CONFIG_FORMAT_CCIR656 0x00800000 +#define CAP0_CONFIG_FORMAT_ZV 0x01000000 +#define CAP0_CONFIG_FORMAT_VIP 0x01800000 +#define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 +#define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 +#define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 +#define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 +#define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 +#define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 +#define CAP0_ANC_ODD_OFFSET 0x095C +#define CAP0_ANC_EVEN_OFFSET 0x0960 +#define CAP0_ANC_H_WINDOW 0x0964 +#define CAP0_VIDEO_SYNC_TEST 0x0968 +#define CAP0_ONESHOT_BUF_OFFSET 0x096C +#define CAP0_BUF_STATUS 0x0970 +/* #define CAP0_DWNSC_XRATIO 0x0978 */ +/* #define CAP0_XSHARPNESS 0x097C */ +#define CAP0_VBI2_OFFSET 0x0980 +#define CAP0_VBI3_OFFSET 0x0984 +#define CAP0_ANC2_OFFSET 0x0988 +#define CAP0_ANC3_OFFSET 0x098C + +/* second capture unit */ + +#define CAP1_BUF0_OFFSET 0x0990 +#define CAP1_BUF1_OFFSET 0x0994 +#define CAP1_BUF0_EVEN_OFFSET 0x0998 +#define CAP1_BUF1_EVEN_OFFSET 0x099C + +#define CAP1_BUF_PITCH 0x09A0 +#define CAP1_V_WINDOW 0x09A4 +#define CAP1_H_WINDOW 0x09A8 +#define CAP1_VBI_ODD_OFFSET 0x09AC +#define CAP1_VBI_EVEN_OFFSET 0x09B0 +#define CAP1_VBI_V_WINDOW 0x09B4 +#define CAP1_VBI_H_WINDOW 0x09B8 +#define CAP1_PORT_MODE_CNTL 0x09BC +#define CAP1_DEBUG 0x09C4 +#define CAP1_CONFIG 0x09C8 +#define CAP1_ANC_ODD_OFFSET 0x09CC +#define CAP1_ANC_EVEN_OFFSET 0x09D0 +#define CAP1_ANC_H_WINDOW 0x09D4 +#define CAP1_VIDEO_SYNC_TEST 0x09D8 +#define CAP1_ONESHOT_BUF_OFFSET 0x09DC +#define CAP1_BUF_STATUS 0x09E0 +#define CAP1_DWNSC_XRATIO 0x09E8 +#define CAP1_XSHARPNESS 0x09EC + +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL 0x0D64 +#define DISP_DAC_SOURCE_MASK 0x03 +#define DISP_DAC_SOURCE_CRTC2 0x01 +#define DISP_LIN_TRANS_GRPH_A 0x0D80 +#define DISP_LIN_TRANS_GRPH_B 0x0D84 +#define DISP_LIN_TRANS_GRPH_C 0x0D88 +#define DISP_LIN_TRANS_GRPH_D 0x0D8C +#define DISP_LIN_TRANS_GRPH_E 0x0D90 +#define DISP_LIN_TRANS_GRPH_F 0x0D94 +#define DISP_LIN_TRANS_VID_A 0x0D98 +#define DISP_LIN_TRANS_VID_B 0x0D9C +#define DISP_LIN_TRANS_VID_C 0x0DA0 +#define DISP_LIN_TRANS_VID_D 0x0DA4 +#define DISP_LIN_TRANS_VID_E 0x0DA8 +#define DISP_LIN_TRANS_VID_F 0x0DAC +#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +#define RMX_HORZ_PHASE 0x0DBC +#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +#define DAC_BROAD_PULSE 0x0DC4 +#define DAC_SKEW_CLKS 0x0DC8 +#define DAC_INCR 0x0DCC +#define DAC_NEG_SYNC_LEVEL 0x0DD0 +#define DAC_POS_SYNC_LEVEL 0x0DD4 +#define DAC_BLANK_LEVEL 0x0DD8 +#define CLOCK_CNTL_INDEX 0x0008 +/* CLOCK_CNTL_INDEX bit constants */ +#define PLL_WR_EN 0x00000080 +#define PLL_DIV_SEL (3 << 8) +#define PLL2_DIV_SEL_MASK ~(3 << 8) +#define CLOCK_CNTL_DATA 0x000C +#define CP_RB_CNTL 0x0704 +#define CP_RB_BASE 0x0700 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define SCRATCH_REG0 0x15E0 +#define GUI_SCRATCH_REG0 0x15E0 +#define SCRATCH_REG1 0x15E4 +#define GUI_SCRATCH_REG1 0x15E4 +#define SCRATCH_REG2 0x15E8 +#define GUI_SCRATCH_REG2 0x15E8 +#define SCRATCH_REG3 0x15EC +#define GUI_SCRATCH_REG3 0x15EC +#define SCRATCH_REG4 0x15F0 +#define GUI_SCRATCH_REG4 0x15F0 +#define SCRATCH_REG5 0x15F4 +#define GUI_SCRATCH_REG5 0x15F4 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DP_BRUSH_FRGD_CLR 0x147C +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define SRC_OFFSET 0x15AC +#define SRC_PITCH 0x15B0 +#define SRC_TILE 0x1704 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define DST_WIDTH_X 0x1588 +#define DST_HEIGHT_WIDTH_8 0x158C +#define SRC_X_Y 0x1590 +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_HEIGHT_WIDTH 0x143c +#define SRC_CLUT_ADDRESS 0x1780 +#define SRC_CLUT_DATA 0x1784 +#define SRC_CLUT_DATA_RD 0x1788 +#define HOST_DATA0 0x17C0 +#define HOST_DATA1 0x17C4 +#define HOST_DATA2 0x17C8 +#define HOST_DATA3 0x17CC +#define HOST_DATA4 0x17D0 +#define HOST_DATA5 0x17D4 +#define HOST_DATA6 0x17D8 +#define HOST_DATA7 0x17DC +#define HOST_DATA_LAST 0x17E0 +#define DP_SRC_ENDIAN 0x15D4 +#define DP_SRC_FRGD_CLR 0x15D8 +#define DP_SRC_BKGD_CLR 0x15DC +#define DP_WRITE_MASK 0x16cc +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164C +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165C +#define DP_CNTL 0x16C0 +/* DP_CNTL bit constants */ +#define DST_X_RIGHT_TO_LEFT 0x00000000 +#define DST_X_LEFT_TO_RIGHT 0x00000001 +#define DST_Y_BOTTOM_TO_TOP 0x00000000 +#define DST_Y_TOP_TO_BOTTOM 0x00000002 +#define DST_X_MAJOR 0x00000000 +#define DST_Y_MAJOR 0x00000004 +#define DST_X_TILE 0x00000008 +#define DST_Y_TILE 0x00000010 +#define DST_LAST_PEL 0x00000020 +#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +#define DST_BRES_SIGN 0x00000100 +#define DST_HOST_BIG_ENDIAN_EN 0x00000200 +#define DST_POLYLINE_NONLAST 0x00008000 +#define DST_RASTER_STALL 0x00010000 +#define DST_POLY_EDGE 0x00040000 +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */ +#define DST_X_MAJOR_S 0x00000000 +#define DST_Y_MAJOR_S 0x00000001 +#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +#define DST_X_RIGHT_TO_LEFT_S 0x00000000 +#define DST_X_LEFT_TO_RIGHT_S 0x80000000 +#define DP_DATATYPE 0x16C4 +/* DP_DATATYPE bit constants */ +#define DST_8BPP 0x00000002 +#define DST_15BPP 0x00000003 +#define DST_16BPP 0x00000004 +#define DST_24BPP 0x00000005 +#define DST_32BPP 0x00000006 +#define DST_8BPP_RGB332 0x00000007 +#define DST_8BPP_Y8 0x00000008 +#define DST_8BPP_RGB8 0x00000009 +#define DST_16BPP_VYUY422 0x0000000b +#define DST_16BPP_YVYU422 0x0000000c +#define DST_32BPP_AYUV444 0x0000000e +#define DST_16BPP_ARGB4444 0x0000000f +#define BRUSH_SOLIDCOLOR 0x00000d00 +#define SRC_MONO 0x00000000 +#define SRC_MONO_LBKGD 0x00010000 +#define SRC_DSTCOLOR 0x00030000 +#define BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define BYTE_ORDER_LSB_TO_MSB 0x40000000 +#define DP_CONVERSION_TEMP 0x80000000 +#define HOST_BIG_ENDIAN_EN (1 << 29) +#define DP_MIX 0x16C8 +/* DP_MIX bit constants */ +#define DP_SRC_RECT 0x00000200 +#define DP_SRC_HOST 0x00000300 +#define DP_SRC_HOST_BYTEALIGN 0x00000400 +#define DP_WRITE_MSK 0x16CC +#define DP_XOP 0x17F8 +#define CLR_CMP_CLR_SRC 0x15C4 +#define CLR_CMP_CLR_DST 0x15C8 +#define CLR_CMP_CNTL 0x15C0 +/* CLR_CMP_CNTL bit constants */ +#define COMPARE_SRC_FALSE 0x00000000 +#define COMPARE_SRC_TRUE 0x00000001 +#define COMPARE_SRC_NOT_EQUAL 0x00000004 +#define COMPARE_SRC_EQUAL 0x00000005 +#define COMPARE_SRC_EQUAL_FLIP 0x00000007 +#define COMPARE_DST_FALSE 0x00000000 +#define COMPARE_DST_TRUE 0x00000100 +#define COMPARE_DST_NOT_EQUAL 0x00000400 +#define COMPARE_DST_EQUAL 0x00000500 +#define COMPARE_DESTINATION 0x00000000 +#define COMPARE_SOURCE 0x01000000 +#define COMPARE_SRC_AND_DST 0x02000000 +#define CLR_CMP_MSK 0x15CC +#define DSTCACHE_MODE 0x1710 +#define DSTCACHE_CTLSTAT 0x1714 +/* DSTCACHE_CTLSTAT bit constants */ +#define RB2D_DC_FLUSH (3 << 0) +#define RB2D_DC_FLUSH_ALL 0xf +#define RB2D_DC_BUSY (1 << 31) +#define DEFAULT_OFFSET 0x16e0 +#define DEFAULT_PITCH_OFFSET 0x16E0 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ +#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define DP_GUI_MASTER_CNTL 0x146C +/* DP_GUI_MASTER_CNTL bit constants */ +#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +#define GMC_SRC_CLIP_DEFAULT 0x00000000 +#define GMC_SRC_CLIP_LEAVE 0x00000004 +#define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_DST_CLIP_LEAVE 0x00000008 +#define GMC_BRUSH_8x8MONO 0x00000000 +#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +#define GMC_BRUSH_8x1MONO 0x00000020 +#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +#define GMC_BRUSH_1x8MONO 0x00000040 +#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +#define GMC_BRUSH_32x1MONO 0x00000060 +#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +#define GMC_BRUSH_32x32MONO 0x00000080 +#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +#define GMC_BRUSH_8x8COLOR 0x000000a0 +#define GMC_BRUSH_8x1COLOR 0x000000b0 +#define GMC_BRUSH_1x8COLOR 0x000000c0 +//#define GMC_BRUSH_SOLID_COLOR 0x000000d0 +//#define GMC_DST_8BPP 0x00000200 +//#define GMC_DST_15BPP 0x00000300 +//#define GMC_DST_16BPP 0x00000400 +//#define GMC_DST_24BPP 0x00000500 +//#define GMC_DST_32BPP 0x00000600 +//#define GMC_DST_8BPP_RGB332 0x00000700 +//#define GMC_DST_8BPP_Y8 0x00000800 +//#define GMC_DST_8BPP_RGB8 0x00000900 +//#define GMC_DST_16BPP_VYUY422 0x00000b00 +//#define GMC_DST_16BPP_YVYU422 0x00000c00 +//#define GMC_DST_32BPP_AYUV444 0x00000e00 +//#define GMC_DST_16BPP_ARGB4444 0x00000f00 +#define GMC_SRC_MONO 0x00000000 +#define GMC_SRC_MONO_LBKGD 0x00001000 +#define GMC_SRC_DSTCOLOR 0x00003000 +#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +#define GMC_DP_SRC_RECT 0x02000000 +#define GMC_DP_SRC_HOST 0x03000000 +#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +#define GMC_3D_FCN_EN_CLR 0x00000000 +#define GMC_3D_FCN_EN_SET 0x08000000 +#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +#define GMC_AUX_CLIP_LEAVE 0x00000000 +#define GMC_AUX_CLIP_CLEAR 0x20000000 +#define GMC_WRITE_MASK_LEAVE 0x00000000 +#define GMC_WRITE_MASK_SET 0x40000000 +#define GMC_CLR_CMP_CNTL_DIS (1 << 28) +#define GMC_SRC_DATATYPE_COLOR (3 << 12) +#define ROP3_S 0x00cc0000 +#define ROP3_SRCCOPY 0x00cc0000 +#define ROP3_P 0x00f00000 +#define ROP3_PATCOPY 0x00f00000 +#define DP_SRC_SOURCE_MASK (7 << 24) +#define GMC_BRUSH_NONE (15 << 4) +#define DP_SRC_SOURCE_MEMORY (2 << 24) +#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +#define SC_TOP_LEFT 0x16EC +#define SC_BOTTOM_RIGHT 0x16F0 +#define SRC_SC_BOTTOM_RIGHT 0x16F4 +#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define RB2D_DSTCACHE_MODE 0x3428 + +#define RADEON_BIOS_0_SCRATCH 0x0010 +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +#define RADEON_BIOS_5_SCRATCH 0x0024 +#define RADEON_BIOS_6_SCRATCH 0x0028 +#define RADEON_BIOS_7_SCRATCH 0x002c + +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +//#define PPLL_RESET (1 << 0) +//#define PPLL_SLEEP (1 << 1) +//#define PPLL_ATOMIC_UPDATE_EN (1 << 16) +//#define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +//#define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +//#define PPLL_REF_DIV 0x0003 +//#define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +//#define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +#define VCLK_SRC_SEL_MASK 0x03 +#define VCLK_SRC_SEL_CPUCLK 0x00 +#define VCLK_SRC_SEL_PSCANCLK 0x01 +#define VCLK_SRC_SEL_BYTECLK 0x02 +#define VCLK_SRC_SEL_PPLLCLK 0x03 +#define HTOTAL_CNTL 0x0009 +#define HTOTAL2_CNTL 0x002e /* PLL */ +#define M_SPLL_REF_FB_DIV 0x000a +#define AGP_PLL_CNTL 0x000b +#define SPLL_CNTL 0x000c +#define SCLK_CNTL 0x000d +#define DYN_STOP_LAT_MASK 0x00007ff8 +#define CP_MAX_DYN_STOP_LAT 0x0008 +#define SCLK_FORCEON_MASK 0xffff8000 +#define SCLK_MORE_CNTL 0x0035 /* PLL */ +#define SCLK_MORE_FORCEON 0x0700 +#define MPLL_CNTL 0x000e +#define MCLK_CNTL 0x0012 +/* MCLK_CNTL bit constants */ +#define FORCEON_MCLKA (1 << 16) +#define FORCEON_MCLKB (1 << 17) +#define FORCEON_YCLKA (1 << 18) +#define FORCEON_YCLKB (1 << 19) +#define FORCEON_MC (1 << 20) +#define FORCEON_AIC (1 << 21) +#define PLL_TEST_CNTL 0x0013 +#define P2PLL_CNTL 0x002a /* P2PLL */ +#define P2PLL_RESET (1 << 0) +#define P2PLL_SLEEP (1 << 1) +#define P2PLL_ATOMIC_UPDATE_EN (1 << 16) +#define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +#define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define P2PLL_DIV_0 0x002c +#define P2PLL_FB0_DIV_MASK 0x07ff +#define P2PLL_POST0_DIV_MASK 0x00070000 +#define P2PLL_REF_DIV_MASK 0x03ff +#define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +#define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define PIXCLKS_CNTL 0x002d +#define PIX2CLK_SRC_SEL_MASK 0x03 +#define PIX2CLK_SRC_SEL_CPUCLK 0x00 +#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +#define PIX2CLK_SRC_SEL_BYTECLK 0x02 +#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 + +/* masks */ + +#define CONFIG_MEMSIZE_MASK 0x1f000000 +#define MEM_CFG_TYPE 0x40000000 +#define DST_OFFSET_MASK 0x003fffff +#define DST_PITCH_MASK 0x3fc00000 +#define DEFAULT_TILE_MASK 0xc0000000 +#define PPLL_DIV_SEL_MASK 0x00000300 +#define PPLL_FB3_DIV_MASK 0x000007ff +#define PPLL_POST3_DIV_MASK 0x00070000 + +/* Registers for 3D/TCL */ + +#define PP_BORDER_COLOR_0 0x1d40 +#define PP_BORDER_COLOR_1 0x1d44 +#define PP_BORDER_COLOR_2 0x1d48 +#define PP_CNTL 0x1c38 +#define STIPPLE_ENABLE (1 << 0) +#define SCISSOR_ENABLE (1 << 1) +#define PATTERN_ENABLE (1 << 2) +#define SHADOW_ENABLE (1 << 3) +#define TEX_ENABLE_MASK (0xf << 4) +#define TEX_0_ENABLE (1 << 4) +#define TEX_1_ENABLE (1 << 5) +#define TEX_2_ENABLE (1 << 6) +#define TEX_3_ENABLE (1 << 7) +#define TEX_BLEND_ENABLE_MASK (0xf << 12) +#define TEX_BLEND_0_ENABLE (1 << 12) +#define TEX_BLEND_1_ENABLE (1 << 13) +#define TEX_BLEND_2_ENABLE (1 << 14) +#define TEX_BLEND_3_ENABLE (1 << 15) +#define PLANAR_YUV_ENABLE (1 << 20) +#define SPECULAR_ENABLE (1 << 21) +#define FOG_ENABLE (1 << 22) +#define ALPHA_TEST_ENABLE (1 << 23) +#define ANTI_ALIAS_NONE (0 << 24) +#define ANTI_ALIAS_LINE (1 << 24) +#define ANTI_ALIAS_POLY (2 << 24) +#define ANTI_ALIAS_LINE_POLY (3 << 24) +#define BUMP_MAP_ENABLE (1 << 26) +#define BUMPED_MAP_T0 (0 << 27) +#define BUMPED_MAP_T1 (1 << 27) +#define BUMPED_MAP_T2 (2 << 27) +#define TEX_3D_ENABLE_0 (1 << 29) +#define TEX_3D_ENABLE_1 (1 << 30) +#define MC_ENABLE (1 << 31) +#define PP_FOG_COLOR 0x1c18 +#define FOG_COLOR_MASK 0x00ffffff +#define FOG_VERTEX (0 << 24) +#define FOG_TABLE (1 << 24) +#define FOG_USE_DEPTH (0 << 25) +#define FOG_USE_DIFFUSE_ALPHA (2 << 25) +#define FOG_USE_SPEC_ALPHA (3 << 25) +#define PP_LUM_MATRIX 0x1d00 +#define PP_MISC 0x1c14 +#define REF_ALPHA_MASK 0x000000ff +#define ALPHA_TEST_FAIL (0 << 8) +#define ALPHA_TEST_LESS (1 << 8) +#define ALPHA_TEST_LEQUAL (2 << 8) +#define ALPHA_TEST_EQUAL (3 << 8) +#define ALPHA_TEST_GEQUAL (4 << 8) +#define ALPHA_TEST_GREATER (5 << 8) +#define ALPHA_TEST_NEQUAL (6 << 8) +#define ALPHA_TEST_PASS (7 << 8) +#define ALPHA_TEST_OP_MASK (7 << 8) +#define CHROMA_FUNC_FAIL (0 << 16) +#define CHROMA_FUNC_PASS (1 << 16) +#define CHROMA_FUNC_NEQUAL (2 << 16) +#define CHROMA_FUNC_EQUAL (3 << 16) +#define CHROMA_KEY_NEAREST (0 << 18) +#define CHROMA_KEY_ZERO (1 << 18) +#define SHADOW_ID_AUTO_INC (1 << 20) +#define SHADOW_FUNC_EQUAL (0 << 21) +#define SHADOW_FUNC_NEQUAL (1 << 21) +#define SHADOW_PASS_1 (0 << 22) +#define SHADOW_PASS_2 (1 << 22) +#define RIGHT_HAND_CUBE_D3D (0 << 24) +#define RIGHT_HAND_CUBE_OGL (1 << 24) +#define PP_ROT_MATRIX_0 0x1d58 +#define PP_ROT_MATRIX_1 0x1d5c +#define PP_TXFILTER_0 0x1c54 +#define PP_TXFILTER_1 0x1c6c +#define PP_TXFILTER_2 0x1c84 +#define MAG_FILTER_NEAREST (0 << 0) +#define MAG_FILTER_LINEAR (1 << 0) +#define MAG_FILTER_MASK (1 << 0) +#define MIN_FILTER_NEAREST (0 << 1) +#define MIN_FILTER_LINEAR (1 << 1) +#define MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +#define MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +#define MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +#define MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +#define MIN_FILTER_ANISO_NEAREST (8 << 1) +#define MIN_FILTER_ANISO_LINEAR (9 << 1) +#define MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +#define MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +#define MIN_FILTER_MASK (15 << 1) +#define MAX_ANISO_1_TO_1 (0 << 5) +#define MAX_ANISO_2_TO_1 (1 << 5) +#define MAX_ANISO_4_TO_1 (2 << 5) +#define MAX_ANISO_8_TO_1 (3 << 5) +#define MAX_ANISO_16_TO_1 (4 << 5) +#define MAX_ANISO_MASK (7 << 5) +#define LOD_BIAS_MASK (0xff << 8) +#define LOD_BIAS_SHIFT 8 +#define MAX_MIP_LEVEL_MASK (0x0f << 16) +#define MAX_MIP_LEVEL_SHIFT 16 +#define YUV_TO_RGB (1 << 20) +#define YUV_TEMPERATURE_COOL (0 << 21) +#define YUV_TEMPERATURE_HOT (1 << 21) +#define YUV_TEMPERATURE_MASK (1 << 21) +#define WRAPEN_S (1 << 22) +#define CLAMP_S_WRAP (0 << 23) +#define CLAMP_S_MIRROR (1 << 23) +#define CLAMP_S_CLAMP_LAST (2 << 23) +#define CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +#define CLAMP_S_CLAMP_BORDER (4 << 23) +#define CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +#define CLAMP_S_CLAMP_GL (6 << 23) +#define CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +#define CLAMP_S_MASK (7 << 23) +#define WRAPEN_T (1 << 26) +#define CLAMP_T_WRAP (0 << 27) +#define CLAMP_T_MIRROR (1 << 27) +#define CLAMP_T_CLAMP_LAST (2 << 27) +#define CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +#define CLAMP_T_CLAMP_BORDER (4 << 27) +#define CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +#define CLAMP_T_CLAMP_GL (6 << 27) +#define CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +#define CLAMP_T_MASK (7 << 27) +#define BORDER_MODE_OGL (0 << 31) +#define BORDER_MODE_D3D (1 << 31) +#define PP_TXFORMAT_0 0x1c58 +#define PP_TXFORMAT_1 0x1c70 +#define PP_TXFORMAT_2 0x1c88 +#define TXFORMAT_I8 (0 << 0) +#define TXFORMAT_AI88 (1 << 0) +#define TXFORMAT_RGB332 (2 << 0) +#define TXFORMAT_ARGB1555 (3 << 0) +#define TXFORMAT_RGB565 (4 << 0) +#define TXFORMAT_ARGB4444 (5 << 0) +#define TXFORMAT_ARGB8888 (6 << 0) +#define TXFORMAT_RGBA8888 (7 << 0) +#define TXFORMAT_Y8 (8 << 0) +#define TXFORMAT_VYUY422 (10 << 0) +#define TXFORMAT_YVYU422 (11 << 0) +#define TXFORMAT_DXT1 (12 << 0) +#define TXFORMAT_DXT23 (14 << 0) +#define TXFORMAT_DXT45 (15 << 0) +#define TXFORMAT_FORMAT_MASK (31 << 0) +#define TXFORMAT_FORMAT_SHIFT 0 +#define TXFORMAT_APPLE_YUV_MODE (1 << 5) +#define TXFORMAT_ALPHA_IN_MAP (1 << 6) +#define TXFORMAT_NON_POWER2 (1 << 7) +#define TXFORMAT_WIDTH_MASK (15 << 8) +#define TXFORMAT_WIDTH_SHIFT 8 +#define TXFORMAT_HEIGHT_MASK (15 << 12) +#define TXFORMAT_HEIGHT_SHIFT 12 +#define TXFORMAT_F5_WIDTH_MASK (15 << 16) +#define TXFORMAT_F5_WIDTH_SHIFT 16 +#define TXFORMAT_F5_HEIGHT_MASK (15 << 20) +#define TXFORMAT_F5_HEIGHT_SHIFT 20 +#define TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +#define TXFORMAT_ST_ROUTE_MASK (3 << 24) +#define TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +#define TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +#define TXFORMAT_ENDIAN_NO_SWAP (0 << 26) +#define TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) +#define TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) +#define TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) +#define TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +#define TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +#define TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +#define TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) +#define PP_CUBIC_FACES_0 0x1d24 +#define PP_CUBIC_FACES_1 0x1d28 +#define PP_CUBIC_FACES_2 0x1d2c +#define FACE_WIDTH_1_SHIFT 0 +#define FACE_HEIGHT_1_SHIFT 4 +#define FACE_WIDTH_1_MASK (0xf << 0) +#define FACE_HEIGHT_1_MASK (0xf << 4) +#define FACE_WIDTH_2_SHIFT 8 +#define FACE_HEIGHT_2_SHIFT 12 +#define FACE_WIDTH_2_MASK (0xf << 8) +#define FACE_HEIGHT_2_MASK (0xf << 12) +#define FACE_WIDTH_3_SHIFT 16 +#define FACE_HEIGHT_3_SHIFT 20 +#define FACE_WIDTH_3_MASK (0xf << 16) +#define FACE_HEIGHT_3_MASK (0xf << 20) +#define FACE_WIDTH_4_SHIFT 24 +#define FACE_HEIGHT_4_SHIFT 28 +#define FACE_WIDTH_4_MASK (0xf << 24) +#define FACE_HEIGHT_4_MASK (0xf << 28) + +#define PP_TXOFFSET_0 0x1c5c +#define PP_TXOFFSET_1 0x1c74 +#define PP_TXOFFSET_2 0x1c8c +#define TXO_ENDIAN_NO_SWAP (0 << 0) +#define TXO_ENDIAN_BYTE_SWAP (1 << 0) +#define TXO_ENDIAN_WORD_SWAP (2 << 0) +#define TXO_ENDIAN_HALFDW_SWAP (3 << 0) +#define TXO_MACRO_LINEAR (0 << 2) +#define TXO_MACRO_TILE (1 << 2) +#define TXO_MICRO_LINEAR (0 << 3) +#define TXO_MICRO_TILE_X2 (1 << 3) +#define TXO_MICRO_TILE_OPT (2 << 3) +#define TXO_OFFSET_MASK 0xffffffe0 +#define TXO_OFFSET_SHIFT 5 + +#define PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ +#define PP_CUBIC_OFFSET_T0_1 0x1dd4 +#define PP_CUBIC_OFFSET_T0_2 0x1dd8 +#define PP_CUBIC_OFFSET_T0_3 0x1ddc +#define PP_CUBIC_OFFSET_T0_4 0x1de0 +#define PP_CUBIC_OFFSET_T1_0 0x1e00 +#define PP_CUBIC_OFFSET_T1_1 0x1e04 +#define PP_CUBIC_OFFSET_T1_2 0x1e08 +#define PP_CUBIC_OFFSET_T1_3 0x1e0c +#define PP_CUBIC_OFFSET_T1_4 0x1e10 +#define PP_CUBIC_OFFSET_T2_0 0x1e14 +#define PP_CUBIC_OFFSET_T2_1 0x1e18 +#define PP_CUBIC_OFFSET_T2_2 0x1e1c +#define PP_CUBIC_OFFSET_T2_3 0x1e20 +#define PP_CUBIC_OFFSET_T2_4 0x1e24 + +#define PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define PP_TEX_SIZE_1 0x1d0c +#define PP_TEX_SIZE_2 0x1d14 +#define TEX_USIZE_MASK (0x7ff << 0) +#define TEX_USIZE_SHIFT 0 +#define TEX_VSIZE_MASK (0x7ff << 16) +#define TEX_VSIZE_SHIFT 16 +#define SIGNED_RGB_MASK (1 << 30) +#define SIGNED_RGB_SHIFT 30 +#define SIGNED_ALPHA_MASK (1 << 31) +#define SIGNED_ALPHA_SHIFT 31 +#define PP_TEX_PITCH_0 0x1d08 /* NPOT */ +#define PP_TEX_PITCH_1 0x1d10 /* NPOT */ +#define PP_TEX_PITCH_2 0x1d18 /* NPOT */ +/* note: bits 13-5: 32 byte aligned stride of texture map */ + +#define PP_TXCBLEND_0 0x1c60 +#define PP_TXCBLEND_1 0x1c78 +#define PP_TXCBLEND_2 0x1c90 +#define COLOR_ARG_A_SHIFT 0 +#define COLOR_ARG_A_MASK (0x1f << 0) +#define COLOR_ARG_A_ZERO (0 << 0) +#define COLOR_ARG_A_CURRENT_COLOR (2 << 0) +#define COLOR_ARG_A_CURRENT_ALPHA (3 << 0) +#define COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) +#define COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) +#define COLOR_ARG_A_SPECULAR_COLOR (6 << 0) +#define COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) +#define COLOR_ARG_A_TFACTOR_COLOR (8 << 0) +#define COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) +#define COLOR_ARG_A_T0_COLOR (10 << 0) +#define COLOR_ARG_A_T0_ALPHA (11 << 0) +#define COLOR_ARG_A_T1_COLOR (12 << 0) +#define COLOR_ARG_A_T1_ALPHA (13 << 0) +#define COLOR_ARG_A_T2_COLOR (14 << 0) +#define COLOR_ARG_A_T2_ALPHA (15 << 0) +#define COLOR_ARG_A_T3_COLOR (16 << 0) +#define COLOR_ARG_A_T3_ALPHA (17 << 0) +#define COLOR_ARG_B_SHIFT 5 +#define COLOR_ARG_B_MASK (0x1f << 5) +#define COLOR_ARG_B_ZERO (0 << 5) +#define COLOR_ARG_B_CURRENT_COLOR (2 << 5) +#define COLOR_ARG_B_CURRENT_ALPHA (3 << 5) +#define COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) +#define COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) +#define COLOR_ARG_B_SPECULAR_COLOR (6 << 5) +#define COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) +#define COLOR_ARG_B_TFACTOR_COLOR (8 << 5) +#define COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) +#define COLOR_ARG_B_T0_COLOR (10 << 5) +#define COLOR_ARG_B_T0_ALPHA (11 << 5) +#define COLOR_ARG_B_T1_COLOR (12 << 5) +#define COLOR_ARG_B_T1_ALPHA (13 << 5) +#define COLOR_ARG_B_T2_COLOR (14 << 5) +#define COLOR_ARG_B_T2_ALPHA (15 << 5) +#define COLOR_ARG_B_T3_COLOR (16 << 5) +#define COLOR_ARG_B_T3_ALPHA (17 << 5) +#define COLOR_ARG_C_SHIFT 10 +#define COLOR_ARG_C_MASK (0x1f << 10) +#define COLOR_ARG_C_ZERO (0 << 10) +#define COLOR_ARG_C_CURRENT_COLOR (2 << 10) +#define COLOR_ARG_C_CURRENT_ALPHA (3 << 10) +#define COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) +#define COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) +#define COLOR_ARG_C_SPECULAR_COLOR (6 << 10) +#define COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) +#define COLOR_ARG_C_TFACTOR_COLOR (8 << 10) +#define COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) +#define COLOR_ARG_C_T0_COLOR (10 << 10) +#define COLOR_ARG_C_T0_ALPHA (11 << 10) +#define COLOR_ARG_C_T1_COLOR (12 << 10) +#define COLOR_ARG_C_T1_ALPHA (13 << 10) +#define COLOR_ARG_C_T2_COLOR (14 << 10) +#define COLOR_ARG_C_T2_ALPHA (15 << 10) +#define COLOR_ARG_C_T3_COLOR (16 << 10) +#define COLOR_ARG_C_T3_ALPHA (17 << 10) +#define COMP_ARG_A (1 << 15) +#define COMP_ARG_A_SHIFT 15 +#define COMP_ARG_B (1 << 16) +#define COMP_ARG_B_SHIFT 16 +#define COMP_ARG_C (1 << 17) +#define COMP_ARG_C_SHIFT 17 +#define BLEND_CTL_MASK (7 << 18) +#define BLEND_CTL_ADD (0 << 18) +#define BLEND_CTL_SUBTRACT (1 << 18) +#define BLEND_CTL_ADDSIGNED (2 << 18) +#define BLEND_CTL_BLEND (3 << 18) +#define BLEND_CTL_DOT3 (4 << 18) +#define SCALE_SHIFT 21 +#define SCALE_MASK (3 << 21) +#define SCALE_1X (0 << 21) +#define SCALE_2X (1 << 21) +#define SCALE_4X (2 << 21) +#define CLAMP_TX (1 << 23) +#define T0_EQ_TCUR (1 << 24) +#define T1_EQ_TCUR (1 << 25) +#define T2_EQ_TCUR (1 << 26) +#define T3_EQ_TCUR (1 << 27) +#define COLOR_ARG_MASK 0x1f +#define COMP_ARG_SHIFT 15 +#define PP_TXABLEND_0 0x1c64 +#define PP_TXABLEND_1 0x1c7c +#define PP_TXABLEND_2 0x1c94 +#define ALPHA_ARG_A_SHIFT 0 +#define ALPHA_ARG_A_MASK (0xf << 0) +#define ALPHA_ARG_A_ZERO (0 << 0) +#define ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) +#define ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) +#define ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) +#define ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) +#define ALPHA_ARG_A_T0_ALPHA (5 << 0) +#define ALPHA_ARG_A_T1_ALPHA (6 << 0) +#define ALPHA_ARG_A_T2_ALPHA (7 << 0) +#define ALPHA_ARG_A_T3_ALPHA (8 << 0) +#define ALPHA_ARG_B_SHIFT 4 +#define ALPHA_ARG_B_MASK (0xf << 4) +#define ALPHA_ARG_B_ZERO (0 << 4) +#define ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) +#define ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) +#define ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) +#define ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) +#define ALPHA_ARG_B_T0_ALPHA (5 << 4) +#define ALPHA_ARG_B_T1_ALPHA (6 << 4) +#define ALPHA_ARG_B_T2_ALPHA (7 << 4) +#define ALPHA_ARG_B_T3_ALPHA (8 << 4) +#define ALPHA_ARG_C_SHIFT 8 +#define ALPHA_ARG_C_MASK (0xf << 8) +#define ALPHA_ARG_C_ZERO (0 << 8) +#define ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) +#define ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) +#define ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) +#define ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) +#define ALPHA_ARG_C_T0_ALPHA (5 << 8) +#define ALPHA_ARG_C_T1_ALPHA (6 << 8) +#define ALPHA_ARG_C_T2_ALPHA (7 << 8) +#define ALPHA_ARG_C_T3_ALPHA (8 << 8) +#define DOT_ALPHA_DONT_REPLICATE (1 << 9) +#define ALPHA_ARG_MASK 0xf + +#define PP_TFACTOR_0 0x1c68 +#define PP_TFACTOR_1 0x1c80 +#define PP_TFACTOR_2 0x1c98 + +#define RB3D_BLENDCNTL 0x1c20 +#define COMB_FCN_MASK (3 << 12) +#define COMB_FCN_ADD_CLAMP (0 << 12) +#define COMB_FCN_ADD_NOCLAMP (1 << 12) +#define COMB_FCN_SUB_CLAMP (2 << 12) +#define COMB_FCN_SUB_NOCLAMP (3 << 12) +#define SRC_BLEND_GL_ZERO (32 << 16) +#define SRC_BLEND_GL_ONE (33 << 16) +#define SRC_BLEND_GL_SRC_COLOR (34 << 16) +#define SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) +#define SRC_BLEND_GL_DST_COLOR (36 << 16) +#define SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) +#define SRC_BLEND_GL_SRC_ALPHA (38 << 16) +#define SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) +#define SRC_BLEND_GL_DST_ALPHA (40 << 16) +#define SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) +#define SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) +#define SRC_BLEND_MASK (63 << 16) +#define DST_BLEND_GL_ZERO (32 << 24) +#define DST_BLEND_GL_ONE (33 << 24) +#define DST_BLEND_GL_SRC_COLOR (34 << 24) +#define DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) +#define DST_BLEND_GL_DST_COLOR (36 << 24) +#define DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) +#define DST_BLEND_GL_SRC_ALPHA (38 << 24) +#define DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) +#define DST_BLEND_GL_DST_ALPHA (40 << 24) +#define DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) +#define DST_BLEND_MASK (63 << 24) +#define RB3D_CNTL 0x1C3C +#define ALPHA_BLEND_ENABLE (1 << 0) +#define PLANE_MASK_ENABLE (1 << 1) +#define DITHER_ENABLE (1 << 2) +#define ROUND_ENABLE (1 << 3) +#define SCALE_DITHER_ENABLE (1 << 4) +#define DITHER_INIT (1 << 5) +#define ROP_ENABLE (1 << 6) +#define STENCIL_ENABLE (1 << 7) +#define Z_ENABLE (1 << 8) +#define DEPTH_XZ_OFFEST_ENABLE (1 << 9) +#define COLOR_FORMAT_ARGB1555 (3 << 10) +#define COLOR_FORMAT_RGB565 (4 << 10) +#define COLOR_FORMAT_ARGB8888 (6 << 10) +#define COLOR_FORMAT_RGB332 (7 << 10) +#define COLOR_FORMAT_Y8 (8 << 10) +#define COLOR_FORMAT_RGB8 (9 << 10) +#define COLOR_FORMAT_YUV422_VYUY (11 << 10) +#define COLOR_FORMAT_YUV422_YVYU (12 << 10) +#define COLOR_FORMAT_aYUV444 (14 << 10) +#define COLOR_FORMAT_ARGB4444 (15 << 10) +#define CLRCMP_FLIP_ENABLE (1 << 14) +#define RB3D_COLOROFFSET 0x1c40 +#define COLOROFFSET_MASK 0xfffffff0 +#define RB3D_COLORPITCH 0x1c48 +#define COLORPITCH_MASK 0x000001ff8 +#define COLOR_TILE_ENABLE (1 << 16) +#define COLOR_MICROTILE_ENABLE (1 << 17) +#define COLOR_ENDIAN_NO_SWAP (0 << 18) +#define COLOR_ENDIAN_WORD_SWAP (1 << 18) +#define COLOR_ENDIAN_DWORD_SWAP (2 << 18) +#define RB3D_DEPTHOFFSET 0x1c24 +#define RB3D_DEPTHPITCH 0x1c28 +#define DEPTHPITCH_MASK 0x00001ff8 +#define DEPTH_ENDIAN_NO_SWAP (0 << 18) +#define DEPTH_ENDIAN_WORD_SWAP (1 << 18) +#define DEPTH_ENDIAN_DWORD_SWAP (2 << 18) +#define RB3D_PLANEMASK 0x1d84 +#define RB3D_ROPCNTL 0x1d80 +#define ROP_MASK (15 << 8) +#define ROP_CLEAR (0 << 8) +#define ROP_NOR (1 << 8) +#define ROP_AND_INVERTED (2 << 8) +#define ROP_COPY_INVERTED (3 << 8) +#define ROP_AND_REVERSE (4 << 8) +#define ROP_INVERT (5 << 8) +#define ROP_XOR (6 << 8) +#define ROP_NAND (7 << 8) +#define ROP_AND (8 << 8) +#define ROP_EQUIV (9 << 8) +#define ROP_NOOP (10 << 8) +#define ROP_OR_INVERTED (11 << 8) +#define ROP_COPY (12 << 8) +#define ROP_OR_REVERSE (13 << 8) +#define ROP_OR (14 << 8) +#define ROP_SET (15 << 8) +#define RB3D_STENCILREFMASK 0x1d7c +#define STENCIL_REF_SHIFT 0 +#define STENCIL_REF_MASK (0xff << 0) +#define STENCIL_MASK_SHIFT 16 +#define STENCIL_VALUE_MASK (0xff << 16) +#define STENCIL_WRITEMASK_SHIFT 24 +#define STENCIL_WRITE_MASK (0xff << 24) +#define RB3D_ZSTENCILCNTL 0x1c2c +#define DEPTH_FORMAT_MASK (0xf << 0) +#define DEPTH_FORMAT_16BIT_INT_Z (0 << 0) +#define DEPTH_FORMAT_24BIT_INT_Z (2 << 0) +#define DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) +#define DEPTH_FORMAT_32BIT_INT_Z (4 << 0) +#define DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) +#define DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) +#define DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) +#define DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) +#define Z_TEST_NEVER (0 << 4) +#define Z_TEST_LESS (1 << 4) +#define Z_TEST_LEQUAL (2 << 4) +#define Z_TEST_EQUAL (3 << 4) +#define Z_TEST_GEQUAL (4 << 4) +#define Z_TEST_GREATER (5 << 4) +#define Z_TEST_NEQUAL (6 << 4) +#define Z_TEST_ALWAYS (7 << 4) +#define Z_TEST_MASK (7 << 4) +#define STENCIL_TEST_NEVER (0 << 12) +#define STENCIL_TEST_LESS (1 << 12) +#define STENCIL_TEST_LEQUAL (2 << 12) +#define STENCIL_TEST_EQUAL (3 << 12) +#define STENCIL_TEST_GEQUAL (4 << 12) +#define STENCIL_TEST_GREATER (5 << 12) +#define STENCIL_TEST_NEQUAL (6 << 12) +#define STENCIL_TEST_ALWAYS (7 << 12) +#define STENCIL_TEST_MASK (0x7 << 12) +#define STENCIL_FAIL_KEEP (0 << 16) +#define STENCIL_FAIL_ZERO (1 << 16) +#define STENCIL_FAIL_REPLACE (2 << 16) +#define STENCIL_FAIL_INC (3 << 16) +#define STENCIL_FAIL_DEC (4 << 16) +#define STENCIL_FAIL_INVERT (5 << 16) +#define STENCIL_FAIL_MASK (0x7 << 16) +#define STENCIL_ZPASS_KEEP (0 << 20) +#define STENCIL_ZPASS_ZERO (1 << 20) +#define STENCIL_ZPASS_REPLACE (2 << 20) +#define STENCIL_ZPASS_INC (3 << 20) +#define STENCIL_ZPASS_DEC (4 << 20) +#define STENCIL_ZPASS_INVERT (5 << 20) +#define STENCIL_ZPASS_MASK (0x7 << 20) +#define STENCIL_ZFAIL_KEEP (0 << 24) +#define STENCIL_ZFAIL_ZERO (1 << 24) +#define STENCIL_ZFAIL_REPLACE (2 << 24) +#define STENCIL_ZFAIL_INC (3 << 24) +#define STENCIL_ZFAIL_DEC (4 << 24) +#define STENCIL_ZFAIL_INVERT (5 << 24) +#define STENCIL_ZFAIL_MASK (0x7 << 24) +#define Z_COMPRESSION_ENABLE (1 << 28) +#define FORCE_Z_DIRTY (1 << 29) +#define Z_WRITE_ENABLE (1 << 30) +#define RE_LINE_PATTERN 0x1cd0 +#define LINE_PATTERN_MASK 0x0000ffff +#define LINE_REPEAT_COUNT_SHIFT 16 +#define LINE_PATTERN_START_SHIFT 24 +#define LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) +#define LINE_PATTERN_BIG_BIT_ORDER (1 << 28) +#define LINE_PATTERN_AUTO_RESET (1 << 29) +#define RE_LINE_STATE 0x1cd4 +#define LINE_CURRENT_PTR_SHIFT 0 +#define LINE_CURRENT_COUNT_SHIFT 8 +#define RE_MISC 0x26c4 +#define STIPPLE_COORD_MASK 0x1f +#define STIPPLE_X_OFFSET_SHIFT 0 +#define STIPPLE_X_OFFSET_MASK (0x1f << 0) +#define STIPPLE_Y_OFFSET_SHIFT 8 +#define STIPPLE_Y_OFFSET_MASK (0x1f << 8) +#define STIPPLE_LITTLE_BIT_ORDER (0 << 16) +#define STIPPLE_BIG_BIT_ORDER (1 << 16) +#define RE_SOLID_COLOR 0x1c1c +#define RE_TOP_LEFT 0x26c0 +#define RE_LEFT_SHIFT 0 +#define RE_TOP_SHIFT 16 +#define RE_WIDTH_HEIGHT 0x1c44 +#define RE_WIDTH_SHIFT 0 +#define RE_HEIGHT_SHIFT 16 + +#define SE_CNTL 0x1c4c +#define FFACE_CULL_CW (0 << 0) +#define FFACE_CULL_CCW (1 << 0) +#define FFACE_CULL_DIR_MASK (1 << 0) +#define BFACE_CULL (0 << 1) +#define BFACE_SOLID (3 << 1) +#define FFACE_CULL (0 << 3) +#define FFACE_SOLID (3 << 3) +#define FFACE_CULL_MASK (3 << 3) +#define BADVTX_CULL_DISABLE (1 << 5) +#define FLAT_SHADE_VTX_0 (0 << 6) +#define FLAT_SHADE_VTX_1 (1 << 6) +#define FLAT_SHADE_VTX_2 (2 << 6) +#define FLAT_SHADE_VTX_LAST (3 << 6) +#define DIFFUSE_SHADE_SOLID (0 << 8) +#define DIFFUSE_SHADE_FLAT (1 << 8) +#define DIFFUSE_SHADE_GOURAUD (2 << 8) +#define DIFFUSE_SHADE_MASK (3 << 8) +#define ALPHA_SHADE_SOLID (0 << 10) +#define ALPHA_SHADE_FLAT (1 << 10) +#define ALPHA_SHADE_GOURAUD (2 << 10) +#define ALPHA_SHADE_MASK (3 << 10) +#define SPECULAR_SHADE_SOLID (0 << 12) +#define SPECULAR_SHADE_FLAT (1 << 12) +#define SPECULAR_SHADE_GOURAUD (2 << 12) +#define SPECULAR_SHADE_MASK (3 << 12) +#define FOG_SHADE_SOLID (0 << 14) +#define FOG_SHADE_FLAT (1 << 14) +#define FOG_SHADE_GOURAUD (2 << 14) +#define FOG_SHADE_MASK (3 << 14) +#define ZBIAS_ENABLE_POINT (1 << 16) +#define ZBIAS_ENABLE_LINE (1 << 17) +#define ZBIAS_ENABLE_TRI (1 << 18) +#define WIDELINE_ENABLE (1 << 20) +#define VPORT_XY_XFORM_ENABLE (1 << 24) +#define VPORT_Z_XFORM_ENABLE (1 << 25) +#define VTX_PIX_CENTER_D3D (0 << 27) +#define VTX_PIX_CENTER_OGL (1 << 27) +#define ROUND_MODE_TRUNC (0 << 28) +#define ROUND_MODE_ROUND (1 << 28) +#define ROUND_MODE_ROUND_EVEN (2 << 28) +#define ROUND_MODE_ROUND_ODD (3 << 28) +#define ROUND_PREC_16TH_PIX (0 << 30) +#define ROUND_PREC_8TH_PIX (1 << 30) +#define ROUND_PREC_4TH_PIX (2 << 30) +#define ROUND_PREC_HALF_PIX (3 << 30) +#define R200_RE_CNTL 0x1c50 +#define R200_STIPPLE_ENABLE 0x1 +#define R200_SCISSOR_ENABLE 0x2 +#define R200_PATTERN_ENABLE 0x4 +#define R200_PERSPECTIVE_ENABLE 0x8 +#define R200_POINT_SMOOTH 0x20 +#define R200_VTX_STQ0_D3D 0x00010000 +#define R200_VTX_STQ1_D3D 0x00040000 +#define R200_VTX_STQ2_D3D 0x00100000 +#define R200_VTX_STQ3_D3D 0x00400000 +#define R200_VTX_STQ4_D3D 0x01000000 +#define R200_VTX_STQ5_D3D 0x04000000 +#define SE_CNTL_STATUS 0x2140 +#define VC_NO_SWAP (0 << 0) +#define VC_16BIT_SWAP (1 << 0) +#define VC_32BIT_SWAP (2 << 0) +#define VC_HALF_DWORD_SWAP (3 << 0) +#define TCL_BYPASS (1 << 8) +#define SE_COORD_FMT 0x1c50 +#define VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) +#define VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) +#define VTX_ST0_NONPARAMETRIC (1 << 8) +#define VTX_ST1_NONPARAMETRIC (1 << 9) +#define VTX_ST2_NONPARAMETRIC (1 << 10) +#define VTX_ST3_NONPARAMETRIC (1 << 11) +#define VTX_W0_NORMALIZE (1 << 12) +#define VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) +#define VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) +#define VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) +#define VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) +#define VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) +#define TEX1_W_ROUTING_USE_W0 (0 << 26) +#define TEX1_W_ROUTING_USE_Q1 (1 << 26) +#define SE_LINE_WIDTH 0x1db8 +#define SE_TCL_LIGHT_MODEL_CTL 0x226c +#define LIGHTING_ENABLE (1 << 0) +#define LIGHT_IN_MODELSPACE (1 << 1) +#define LOCAL_VIEWER (1 << 2) +#define NORMALIZE_NORMALS (1 << 3) +#define RESCALE_NORMALS (1 << 4) +#define SPECULAR_LIGHTS (1 << 5) +#define DIFFUSE_SPECULAR_COMBINE (1 << 6) +#define LIGHT_ALPHA (1 << 7) +#define LOCAL_LIGHT_VEC_GL (1 << 8) +#define LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) +#define LM_SOURCE_STATE_PREMULT 0 +#define LM_SOURCE_STATE_MULT 1 +#define LM_SOURCE_VERTEX_DIFFUSE 2 +#define LM_SOURCE_VERTEX_SPECULAR 3 +#define EMISSIVE_SOURCE_SHIFT 16 +#define AMBIENT_SOURCE_SHIFT 18 +#define DIFFUSE_SOURCE_SHIFT 20 +#define SPECULAR_SOURCE_SHIFT 22 +#define SE_TCL_MATERIAL_AMBIENT_RED 0x2220 +#define SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 +#define SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 +#define SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c +#define SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 +#define SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 +#define SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 +#define SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c +#define SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 +#define SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 +#define SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 +#define SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c +#define SE_TCL_MATERIAL_SPECULAR_RED 0x2240 +#define SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 +#define SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 +#define SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c +#define SE_TCL_MATRIX_SELECT_0 0x225c +#define MODELVIEW_0_SHIFT 0 +#define MODELVIEW_1_SHIFT 4 +#define MODELVIEW_2_SHIFT 8 +#define MODELVIEW_3_SHIFT 12 +#define IT_MODELVIEW_0_SHIFT 16 +#define IT_MODELVIEW_1_SHIFT 20 +#define IT_MODELVIEW_2_SHIFT 24 +#define IT_MODELVIEW_3_SHIFT 28 +#define SE_TCL_MATRIX_SELECT_1 0x2260 +#define MODELPROJECT_0_SHIFT 0 +#define MODELPROJECT_1_SHIFT 4 +#define MODELPROJECT_2_SHIFT 8 +#define MODELPROJECT_3_SHIFT 12 +#define TEXMAT_0_SHIFT 16 +#define TEXMAT_1_SHIFT 20 +#define TEXMAT_2_SHIFT 24 +#define TEXMAT_3_SHIFT 28 + +#define SE_TCL_OUTPUT_VTX_FMT 0x2254 +#define TCL_VTX_W0 (1 << 0) +#define TCL_VTX_FP_DIFFUSE (1 << 1) +#define TCL_VTX_FP_ALPHA (1 << 2) +#define TCL_VTX_PK_DIFFUSE (1 << 3) +#define TCL_VTX_FP_SPEC (1 << 4) +#define TCL_VTX_FP_FOG (1 << 5) +#define TCL_VTX_PK_SPEC (1 << 6) +#define TCL_VTX_ST0 (1 << 7) +#define TCL_VTX_ST1 (1 << 8) +#define TCL_VTX_Q1 (1 << 9) +#define TCL_VTX_ST2 (1 << 10) +#define TCL_VTX_Q2 (1 << 11) +#define TCL_VTX_ST3 (1 << 12) +#define TCL_VTX_Q3 (1 << 13) +#define TCL_VTX_Q0 (1 << 14) +#define TCL_VTX_WEIGHT_COUNT_SHIFT 15 +#define TCL_VTX_NORM0 (1 << 18) +#define TCL_VTX_XY1 (1 << 27) +#define TCL_VTX_Z1 (1 << 28) +#define TCL_VTX_W1 (1 << 29) +#define TCL_VTX_NORM1 (1 << 30) +#define TCL_VTX_Z0 (1 << 31) + +#define SE_TCL_OUTPUT_VTX_SEL 0x2258 +#define TCL_COMPUTE_XYZW (1 << 0) +#define TCL_COMPUTE_DIFFUSE (1 << 1) +#define TCL_COMPUTE_SPECULAR (1 << 2) +#define TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) +#define TCL_FORCE_INORDER_PROC (1 << 4) +#define TCL_TEX_INPUT_TEX_0 0 +#define TCL_TEX_INPUT_TEX_1 1 +#define TCL_TEX_INPUT_TEX_2 2 +#define TCL_TEX_INPUT_TEX_3 3 +#define TCL_TEX_COMPUTED_TEX_0 8 +#define TCL_TEX_COMPUTED_TEX_1 9 +#define TCL_TEX_COMPUTED_TEX_2 10 +#define TCL_TEX_COMPUTED_TEX_3 11 +#define TCL_TEX_0_OUTPUT_SHIFT 16 +#define TCL_TEX_1_OUTPUT_SHIFT 20 +#define TCL_TEX_2_OUTPUT_SHIFT 24 +#define TCL_TEX_3_OUTPUT_SHIFT 28 + +#define SE_TCL_PER_LIGHT_CTL_0 0x2270 +#define LIGHT_0_ENABLE (1 << 0) +#define LIGHT_0_ENABLE_AMBIENT (1 << 1) +#define LIGHT_0_ENABLE_SPECULAR (1 << 2) +#define LIGHT_0_IS_LOCAL (1 << 3) +#define LIGHT_0_IS_SPOT (1 << 4) +#define LIGHT_0_DUAL_CONE (1 << 5) +#define LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) +#define LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) +#define LIGHT_0_SHIFT 0 +#define LIGHT_1_ENABLE (1 << 16) +#define LIGHT_1_ENABLE_AMBIENT (1 << 17) +#define LIGHT_1_ENABLE_SPECULAR (1 << 18) +#define LIGHT_1_IS_LOCAL (1 << 19) +#define LIGHT_1_IS_SPOT (1 << 20) +#define LIGHT_1_DUAL_CONE (1 << 21) +#define LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) +#define LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) +#define LIGHT_1_SHIFT 16 +#define SE_TCL_PER_LIGHT_CTL_1 0x2274 +#define LIGHT_2_SHIFT 0 +#define LIGHT_3_SHIFT 16 +#define SE_TCL_PER_LIGHT_CTL_2 0x2278 +#define LIGHT_4_SHIFT 0 +#define LIGHT_5_SHIFT 16 +#define SE_TCL_PER_LIGHT_CTL_3 0x227c +#define LIGHT_6_SHIFT 0 +#define LIGHT_7_SHIFT 16 + +#define SE_TCL_SHININESS 0x2250 + +#define SE_TCL_TEXTURE_PROC_CTL 0x2268 +#define TEXGEN_TEXMAT_0_ENABLE (1 << 0) +#define TEXGEN_TEXMAT_1_ENABLE (1 << 1) +#define TEXGEN_TEXMAT_2_ENABLE (1 << 2) +#define TEXGEN_TEXMAT_3_ENABLE (1 << 3) +#define TEXMAT_0_ENABLE (1 << 4) +#define TEXMAT_1_ENABLE (1 << 5) +#define TEXMAT_2_ENABLE (1 << 6) +#define TEXMAT_3_ENABLE (1 << 7) +#define TEXGEN_INPUT_MASK 0xf +#define TEXGEN_INPUT_TEXCOORD_0 0 +#define TEXGEN_INPUT_TEXCOORD_1 1 +#define TEXGEN_INPUT_TEXCOORD_2 2 +#define TEXGEN_INPUT_TEXCOORD_3 3 +#define TEXGEN_INPUT_OBJ 4 +#define TEXGEN_INPUT_EYE 5 +#define TEXGEN_INPUT_EYE_NORMAL 6 +#define TEXGEN_INPUT_EYE_REFLECT 7 +#define TEXGEN_INPUT_EYE_NORMALIZED 8 +#define TEXGEN_0_INPUT_SHIFT 16 +#define TEXGEN_1_INPUT_SHIFT 20 +#define TEXGEN_2_INPUT_SHIFT 24 +#define TEXGEN_3_INPUT_SHIFT 28 + +#define SE_TCL_UCP_VERT_BLEND_CTL 0x2264 +#define UCP_IN_CLIP_SPACE (1 << 0) +#define UCP_IN_MODEL_SPACE (1 << 1) +#define UCP_ENABLE_0 (1 << 2) +#define UCP_ENABLE_1 (1 << 3) +#define UCP_ENABLE_2 (1 << 4) +#define UCP_ENABLE_3 (1 << 5) +#define UCP_ENABLE_4 (1 << 6) +#define UCP_ENABLE_5 (1 << 7) +#define TCL_FOG_MASK (3 << 8) +#define TCL_FOG_DISABLE (0 << 8) +#define TCL_FOG_EXP (1 << 8) +#define TCL_FOG_EXP2 (2 << 8) +#define TCL_FOG_LINEAR (3 << 8) +#define RNG_BASED_FOG (1 << 10) +#define LIGHT_TWOSIDE (1 << 11) +#define BLEND_OP_COUNT_MASK (7 << 12) +#define BLEND_OP_COUNT_SHIFT 12 +#define POSITION_BLEND_OP_ENABLE (1 << 16) +#define NORMAL_BLEND_OP_ENABLE (1 << 17) +#define VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) +#define VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) +#define VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) +#define VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) +#define VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) +#define VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) +#define VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) +#define VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) +#define VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) +#define CULL_FRONT_IS_CW (0 << 28) +#define CULL_FRONT_IS_CCW (1 << 28) +#define CULL_FRONT (1 << 29) +#define CULL_BACK (1 << 30) +#define FORCE_W_TO_ONE (1 << 31) + +#define SE_VPORT_XSCALE 0x1d98 +#define SE_VPORT_XOFFSET 0x1d9c +#define SE_VPORT_YSCALE 0x1da0 +#define SE_VPORT_YOFFSET 0x1da4 +#define SE_VPORT_ZSCALE 0x1da8 +#define SE_VPORT_ZOFFSET 0x1dac +#define SE_ZBIAS_FACTOR 0x1db0 +#define SE_ZBIAS_CONSTANT 0x1db4 + +#define SE_VTX_FMT 0x2080 +#define SE_VTX_FMT_XY 0x00000000 +#define SE_VTX_FMT_W0 0x00000001 +#define SE_VTX_FMT_FPCOLOR 0x00000002 +#define SE_VTX_FMT_FPALPHA 0x00000004 +#define SE_VTX_FMT_PKCOLOR 0x00000008 +#define SE_VTX_FMT_FPSPEC 0x00000010 +#define SE_VTX_FMT_FPFOG 0x00000020 +#define SE_VTX_FMT_PKSPEC 0x00000040 +#define SE_VTX_FMT_ST0 0x00000080 +#define SE_VTX_FMT_ST1 0x00000100 +#define SE_VTX_FMT_Q1 0x00000200 +#define SE_VTX_FMT_ST2 0x00000400 +#define SE_VTX_FMT_Q2 0x00000800 +#define SE_VTX_FMT_ST3 0x00001000 +#define SE_VTX_FMT_Q3 0x00002000 +#define SE_VTX_FMT_Q0 0x00004000 +#define SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 +#define SE_VTX_FMT_N0 0x00040000 +#define SE_VTX_FMT_XY1 0x08000000 +#define SE_VTX_FMT_Z1 0x10000000 +#define SE_VTX_FMT_W1 0x20000000 +#define SE_VTX_FMT_N1 0x40000000 +#define SE_VTX_FMT_Z 0x80000000 + +#define SE_VF_CNTL 0x2084 +#define VF_PRIM_TYPE_POINT_LIST 1 +#define VF_PRIM_TYPE_LINE_LIST 2 +#define VF_PRIM_TYPE_LINE_STRIP 3 +#define VF_PRIM_TYPE_TRIANGLE_LIST 4 +#define VF_PRIM_TYPE_TRIANGLE_FAN 5 +#define VF_PRIM_TYPE_TRIANGLE_STRIP 6 +#define VF_PRIM_TYPE_TRIANGLE_FLAG 7 +#define VF_PRIM_TYPE_RECTANGLE_LIST 8 +#define VF_PRIM_TYPE_POINT_LIST_3 9 +#define VF_PRIM_TYPE_LINE_LIST_3 10 +#define VF_PRIM_TYPE_SPIRIT_LIST 11 +#define VF_PRIM_TYPE_LINE_LOOP 12 +#define VF_PRIM_TYPE_QUAD_LIST 13 +#define VF_PRIM_TYPE_QUAD_STRIP 14 +#define VF_PRIM_TYPE_POLYGON 15 +#define VF_PRIM_WALK_STATE (0<<4) +#define VF_PRIM_WALK_INDEX (1<<4) +#define VF_PRIM_WALK_LIST (2<<4) +#define VF_PRIM_WALK_DATA (3<<4) +#define VF_COLOR_ORDER_RGBA (1<<6) +#define VF_RADEON_MODE (1<<8) +#define VF_TCL_OUTPUT_CTL_ENA (1<<9) +#define VF_PROG_STREAM_ENA (1<<10) +#define VF_INDEX_SIZE_SHIFT 11 +#define VF_NUM_VERTICES_SHIFT 16 + +#define SE_PORT_DATA0 0x2000 + +#define R200_SE_VAP_CNTL 0x2080 +#define R200_VAP_TCL_ENABLE 0x00000001 +#define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 +#define R200_VAP_FORCE_W_TO_ONE 0x00010000 +#define R200_VAP_D3D_TEX_DEFAULT 0x00020000 +#define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 +#define R200_VAP_VF_MAX_VTX_NUM (9 << 18) +#define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 +#define R200_VF_MAX_VTX_INDX 0x210c +#define R200_VF_MIN_VTX_INDX 0x2110 +#define R200_SE_VTE_CNTL 0x20b0 +#define R200_VPORT_X_SCALE_ENA 0x00000001 +#define R200_VPORT_X_OFFSET_ENA 0x00000002 +#define R200_VPORT_Y_SCALE_ENA 0x00000004 +#define R200_VPORT_Y_OFFSET_ENA 0x00000008 +#define R200_VPORT_Z_SCALE_ENA 0x00000010 +#define R200_VPORT_Z_OFFSET_ENA 0x00000020 +#define R200_VTX_XY_FMT 0x00000100 +#define R200_VTX_Z_FMT 0x00000200 +#define R200_VTX_W0_FMT 0x00000400 +#define R200_VTX_W0_NORMALIZE 0x00000800 +#define R200_VTX_ST_DENORMALIZED 0x00001000 +#define R200_SE_VAP_CNTL_STATUS 0x2140 +#define R200_VC_NO_SWAP (0 << 0) +#define R200_VC_16BIT_SWAP (1 << 0) +#define R200_VC_32BIT_SWAP (2 << 0) +#define R200_PP_TXFILTER_0 0x2c00 +#define R200_MAG_FILTER_NEAREST (0 << 0) +#define R200_MAG_FILTER_LINEAR (1 << 0) +#define R200_MAG_FILTER_MASK (1 << 0) +#define R200_MIN_FILTER_NEAREST (0 << 1) +#define R200_MIN_FILTER_LINEAR (1 << 1) +#define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +#define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +#define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +#define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +#define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) +#define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) +#define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +#define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +#define R200_MIN_FILTER_MASK (15 << 1) +#define R200_MAX_ANISO_1_TO_1 (0 << 5) +#define R200_MAX_ANISO_2_TO_1 (1 << 5) +#define R200_MAX_ANISO_4_TO_1 (2 << 5) +#define R200_MAX_ANISO_8_TO_1 (3 << 5) +#define R200_MAX_ANISO_16_TO_1 (4 << 5) +#define R200_MAX_ANISO_MASK (7 << 5) +#define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) +#define R200_MAX_MIP_LEVEL_SHIFT 16 +#define R200_YUV_TO_RGB (1 << 20) +#define R200_YUV_TEMPERATURE_COOL (0 << 21) +#define R200_YUV_TEMPERATURE_HOT (1 << 21) +#define R200_YUV_TEMPERATURE_MASK (1 << 21) +#define R200_WRAPEN_S (1 << 22) +#define R200_CLAMP_S_WRAP (0 << 23) +#define R200_CLAMP_S_MIRROR (1 << 23) +#define R200_CLAMP_S_CLAMP_LAST (2 << 23) +#define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +#define R200_CLAMP_S_CLAMP_BORDER (4 << 23) +#define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +#define R200_CLAMP_S_CLAMP_GL (6 << 23) +#define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +#define R200_CLAMP_S_MASK (7 << 23) +#define R200_WRAPEN_T (1 << 26) +#define R200_CLAMP_T_WRAP (0 << 27) +#define R200_CLAMP_T_MIRROR (1 << 27) +#define R200_CLAMP_T_CLAMP_LAST (2 << 27) +#define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +#define R200_CLAMP_T_CLAMP_BORDER (4 << 27) +#define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +#define R200_CLAMP_T_CLAMP_GL (6 << 27) +#define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +#define R200_CLAMP_T_MASK (7 << 27) +#define R200_KILL_LT_ZERO (1 << 30) +#define R200_BORDER_MODE_OGL (0 << 31) +#define R200_BORDER_MODE_D3D (1 << 31) +#define R200_PP_TXFORMAT_0 0x2c04 +#define R200_TXFORMAT_I8 (0 << 0) +#define R200_TXFORMAT_AI88 (1 << 0) +#define R200_TXFORMAT_RGB332 (2 << 0) +#define R200_TXFORMAT_ARGB1555 (3 << 0) +#define R200_TXFORMAT_RGB565 (4 << 0) +#define R200_TXFORMAT_ARGB4444 (5 << 0) +#define R200_TXFORMAT_ARGB8888 (6 << 0) +#define R200_TXFORMAT_RGBA8888 (7 << 0) +#define R200_TXFORMAT_Y8 (8 << 0) +#define R200_TXFORMAT_AVYU4444 (9 << 0) +#define R200_TXFORMAT_VYUY422 (10 << 0) +#define R200_TXFORMAT_YVYU422 (11 << 0) +#define R200_TXFORMAT_DXT1 (12 << 0) +#define R200_TXFORMAT_DXT23 (14 << 0) +#define R200_TXFORMAT_DXT45 (15 << 0) +#define R200_TXFORMAT_FORMAT_MASK (31 << 0) +#define R200_TXFORMAT_FORMAT_SHIFT 0 +#define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) +#define R200_TXFORMAT_NON_POWER2 (1 << 7) +#define R200_TXFORMAT_WIDTH_MASK (15 << 8) +#define R200_TXFORMAT_WIDTH_SHIFT 8 +#define R200_TXFORMAT_HEIGHT_MASK (15 << 12) +#define R200_TXFORMAT_HEIGHT_SHIFT 12 +#define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ +#define R200_TXFORMAT_F5_WIDTH_SHIFT 16 +#define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +#define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 +#define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +#define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +#define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +#define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) +#define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) +#define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) +#define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) +#define R200_TXFORMAT_ST_ROUTE_SHIFT 24 +#define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +#define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +#define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +#define R200_PP_TXFORMAT_X_0 0x2c08 +#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ +#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ +#define R200_PP_TXOFFSET_0 0x2d00 +#define R200_TXO_ENDIAN_NO_SWAP (0 << 0) +#define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) +#define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) +#define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +#define R200_TXO_OFFSET_MASK 0xffffffe0 +#define R200_TXO_OFFSET_SHIFT 5 + +#define R200_PP_TFACTOR_0 0x2ee0 +#define R200_PP_TFACTOR_1 0x2ee4 +#define R200_PP_TFACTOR_2 0x2ee8 +#define R200_PP_TFACTOR_3 0x2eec +#define R200_PP_TFACTOR_4 0x2ef0 +#define R200_PP_TFACTOR_5 0x2ef4 + +#define R200_PP_TXCBLEND_0 0x2f00 +#define R200_TXC_ARG_A_ZERO (0) +#define R200_TXC_ARG_A_CURRENT_COLOR (2) +#define R200_TXC_ARG_A_CURRENT_ALPHA (3) +#define R200_TXC_ARG_A_DIFFUSE_COLOR (4) +#define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) +#define R200_TXC_ARG_A_SPECULAR_COLOR (6) +#define R200_TXC_ARG_A_SPECULAR_ALPHA (7) +#define R200_TXC_ARG_A_TFACTOR_COLOR (8) +#define R200_TXC_ARG_A_TFACTOR_ALPHA (9) +#define R200_TXC_ARG_A_R0_COLOR (10) +#define R200_TXC_ARG_A_R0_ALPHA (11) +#define R200_TXC_ARG_A_R1_COLOR (12) +#define R200_TXC_ARG_A_R1_ALPHA (13) +#define R200_TXC_ARG_A_R2_COLOR (14) +#define R200_TXC_ARG_A_R2_ALPHA (15) +#define R200_TXC_ARG_A_R3_COLOR (16) +#define R200_TXC_ARG_A_R3_ALPHA (17) +#define R200_TXC_ARG_A_R4_COLOR (18) +#define R200_TXC_ARG_A_R4_ALPHA (19) +#define R200_TXC_ARG_A_R5_COLOR (20) +#define R200_TXC_ARG_A_R5_ALPHA (21) +#define R200_TXC_ARG_A_TFACTOR1_COLOR (26) +#define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) +#define R200_TXC_ARG_A_MASK (31 << 0) +#define R200_TXC_ARG_A_SHIFT 0 +#define R200_TXC_ARG_B_ZERO (0 << 5) +#define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) +#define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) +#define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) +#define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) +#define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) +#define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) +#define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) +#define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) +#define R200_TXC_ARG_B_R0_COLOR (10 << 5) +#define R200_TXC_ARG_B_R0_ALPHA (11 << 5) +#define R200_TXC_ARG_B_R1_COLOR (12 << 5) +#define R200_TXC_ARG_B_R1_ALPHA (13 << 5) +#define R200_TXC_ARG_B_R2_COLOR (14 << 5) +#define R200_TXC_ARG_B_R2_ALPHA (15 << 5) +#define R200_TXC_ARG_B_R3_COLOR (16 << 5) +#define R200_TXC_ARG_B_R3_ALPHA (17 << 5) +#define R200_TXC_ARG_B_R4_COLOR (18 << 5) +#define R200_TXC_ARG_B_R4_ALPHA (19 << 5) +#define R200_TXC_ARG_B_R5_COLOR (20 << 5) +#define R200_TXC_ARG_B_R5_ALPHA (21 << 5) +#define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) +#define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) +#define R200_TXC_ARG_B_MASK (31 << 5) +#define R200_TXC_ARG_B_SHIFT 5 +#define R200_TXC_ARG_C_ZERO (0 << 10) +#define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) +#define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) +#define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) +#define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) +#define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) +#define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) +#define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) +#define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) +#define R200_TXC_ARG_C_R0_COLOR (10 << 10) +#define R200_TXC_ARG_C_R0_ALPHA (11 << 10) +#define R200_TXC_ARG_C_R1_COLOR (12 << 10) +#define R200_TXC_ARG_C_R1_ALPHA (13 << 10) +#define R200_TXC_ARG_C_R2_COLOR (14 << 10) +#define R200_TXC_ARG_C_R2_ALPHA (15 << 10) +#define R200_TXC_ARG_C_R3_COLOR (16 << 10) +#define R200_TXC_ARG_C_R3_ALPHA (17 << 10) +#define R200_TXC_ARG_C_R4_COLOR (18 << 10) +#define R200_TXC_ARG_C_R4_ALPHA (19 << 10) +#define R200_TXC_ARG_C_R5_COLOR (20 << 10) +#define R200_TXC_ARG_C_R5_ALPHA (21 << 10) +#define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) +#define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) +#define R200_TXC_ARG_C_MASK (31 << 10) +#define R200_TXC_ARG_C_SHIFT 10 +#define R200_TXC_COMP_ARG_A (1 << 16) +#define R200_TXC_COMP_ARG_A_SHIFT (16) +#define R200_TXC_BIAS_ARG_A (1 << 17) +#define R200_TXC_SCALE_ARG_A (1 << 18) +#define R200_TXC_NEG_ARG_A (1 << 19) +#define R200_TXC_COMP_ARG_B (1 << 20) +#define R200_TXC_COMP_ARG_B_SHIFT (20) +#define R200_TXC_BIAS_ARG_B (1 << 21) +#define R200_TXC_SCALE_ARG_B (1 << 22) +#define R200_TXC_NEG_ARG_B (1 << 23) +#define R200_TXC_COMP_ARG_C (1 << 24) +#define R200_TXC_COMP_ARG_C_SHIFT (24) +#define R200_TXC_BIAS_ARG_C (1 << 25) +#define R200_TXC_SCALE_ARG_C (1 << 26) +#define R200_TXC_NEG_ARG_C (1 << 27) +#define R200_TXC_OP_MADD (0 << 28) +#define R200_TXC_OP_CND0 (2 << 28) +#define R200_TXC_OP_LERP (3 << 28) +#define R200_TXC_OP_DOT3 (4 << 28) +#define R200_TXC_OP_DOT4 (5 << 28) +#define R200_TXC_OP_CONDITIONAL (6 << 28) +#define R200_TXC_OP_DOT2_ADD (7 << 28) +#define R200_TXC_OP_MASK (7 << 28) +#define R200_PP_TXCBLEND2_0 0x2f04 +#define R200_TXC_TFACTOR_SEL_SHIFT 0 +#define R200_TXC_TFACTOR_SEL_MASK 0x7 +#define R200_TXC_TFACTOR1_SEL_SHIFT 4 +#define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) +#define R200_TXC_SCALE_SHIFT 8 +#define R200_TXC_SCALE_MASK (7 << 8) +#define R200_TXC_SCALE_1X (0 << 8) +#define R200_TXC_SCALE_2X (1 << 8) +#define R200_TXC_SCALE_4X (2 << 8) +#define R200_TXC_SCALE_8X (3 << 8) +#define R200_TXC_SCALE_INV2 (5 << 8) +#define R200_TXC_SCALE_INV4 (6 << 8) +#define R200_TXC_SCALE_INV8 (7 << 8) +#define R200_TXC_CLAMP_SHIFT 12 +#define R200_TXC_CLAMP_MASK (3 << 12) +#define R200_TXC_CLAMP_WRAP (0 << 12) +#define R200_TXC_CLAMP_0_1 (1 << 12) +#define R200_TXC_CLAMP_8_8 (2 << 12) +#define R200_TXC_OUTPUT_REG_MASK (7 << 16) +#define R200_TXC_OUTPUT_REG_NONE (0 << 16) +#define R200_TXC_OUTPUT_REG_R0 (1 << 16) +#define R200_TXC_OUTPUT_REG_R1 (2 << 16) +#define R200_TXC_OUTPUT_REG_R2 (3 << 16) +#define R200_TXC_OUTPUT_REG_R3 (4 << 16) +#define R200_TXC_OUTPUT_REG_R4 (5 << 16) +#define R200_TXC_OUTPUT_REG_R5 (6 << 16) +#define R200_TXC_OUTPUT_MASK_MASK (7 << 20) +#define R200_TXC_OUTPUT_MASK_RGB (0 << 20) +#define R200_TXC_OUTPUT_MASK_RG (1 << 20) +#define R200_TXC_OUTPUT_MASK_RB (2 << 20) +#define R200_TXC_OUTPUT_MASK_R (3 << 20) +#define R200_TXC_OUTPUT_MASK_GB (4 << 20) +#define R200_TXC_OUTPUT_MASK_G (5 << 20) +#define R200_TXC_OUTPUT_MASK_B (6 << 20) +#define R200_TXC_OUTPUT_MASK_NONE (7 << 20) +#define R200_TXC_REPL_NORMAL 0 +#define R200_TXC_REPL_RED 1 +#define R200_TXC_REPL_GREEN 2 +#define R200_TXC_REPL_BLUE 3 +#define R200_TXC_REPL_ARG_A_SHIFT 26 +#define R200_TXC_REPL_ARG_A_MASK (3 << 26) +#define R200_TXC_REPL_ARG_B_SHIFT 28 +#define R200_TXC_REPL_ARG_B_MASK (3 << 28) +#define R200_TXC_REPL_ARG_C_SHIFT 30 +#define R200_TXC_REPL_ARG_C_MASK (3 << 30) +#define R200_PP_TXABLEND_0 0x2f08 +#define R200_TXA_ARG_A_ZERO (0) +#define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ +#define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ +#define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) +#define R200_TXA_ARG_A_DIFFUSE_BLUE (5) +#define R200_TXA_ARG_A_SPECULAR_ALPHA (6) +#define R200_TXA_ARG_A_SPECULAR_BLUE (7) +#define R200_TXA_ARG_A_TFACTOR_ALPHA (8) +#define R200_TXA_ARG_A_TFACTOR_BLUE (9) +#define R200_TXA_ARG_A_R0_ALPHA (10) +#define R200_TXA_ARG_A_R0_BLUE (11) +#define R200_TXA_ARG_A_R1_ALPHA (12) +#define R200_TXA_ARG_A_R1_BLUE (13) +#define R200_TXA_ARG_A_R2_ALPHA (14) +#define R200_TXA_ARG_A_R2_BLUE (15) +#define R200_TXA_ARG_A_R3_ALPHA (16) +#define R200_TXA_ARG_A_R3_BLUE (17) +#define R200_TXA_ARG_A_R4_ALPHA (18) +#define R200_TXA_ARG_A_R4_BLUE (19) +#define R200_TXA_ARG_A_R5_ALPHA (20) +#define R200_TXA_ARG_A_R5_BLUE (21) +#define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) +#define R200_TXA_ARG_A_TFACTOR1_BLUE (27) +#define R200_TXA_ARG_A_MASK (31 << 0) +#define R200_TXA_ARG_A_SHIFT 0 +#define R200_TXA_ARG_B_ZERO (0 << 5) +#define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ +#define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ +#define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) +#define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) +#define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) +#define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) +#define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) +#define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) +#define R200_TXA_ARG_B_R0_ALPHA (10 << 5) +#define R200_TXA_ARG_B_R0_BLUE (11 << 5) +#define R200_TXA_ARG_B_R1_ALPHA (12 << 5) +#define R200_TXA_ARG_B_R1_BLUE (13 << 5) +#define R200_TXA_ARG_B_R2_ALPHA (14 << 5) +#define R200_TXA_ARG_B_R2_BLUE (15 << 5) +#define R200_TXA_ARG_B_R3_ALPHA (16 << 5) +#define R200_TXA_ARG_B_R3_BLUE (17 << 5) +#define R200_TXA_ARG_B_R4_ALPHA (18 << 5) +#define R200_TXA_ARG_B_R4_BLUE (19 << 5) +#define R200_TXA_ARG_B_R5_ALPHA (20 << 5) +#define R200_TXA_ARG_B_R5_BLUE (21 << 5) +#define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) +#define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) +#define R200_TXA_ARG_B_MASK (31 << 5) +#define R200_TXA_ARG_B_SHIFT 5 +#define R200_TXA_ARG_C_ZERO (0 << 10) +#define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ +#define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ +#define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) +#define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) +#define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) +#define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) +#define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) +#define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) +#define R200_TXA_ARG_C_R0_ALPHA (10 << 10) +#define R200_TXA_ARG_C_R0_BLUE (11 << 10) +#define R200_TXA_ARG_C_R1_ALPHA (12 << 10) +#define R200_TXA_ARG_C_R1_BLUE (13 << 10) +#define R200_TXA_ARG_C_R2_ALPHA (14 << 10) +#define R200_TXA_ARG_C_R2_BLUE (15 << 10) +#define R200_TXA_ARG_C_R3_ALPHA (16 << 10) +#define R200_TXA_ARG_C_R3_BLUE (17 << 10) +#define R200_TXA_ARG_C_R4_ALPHA (18 << 10) +#define R200_TXA_ARG_C_R4_BLUE (19 << 10) +#define R200_TXA_ARG_C_R5_ALPHA (20 << 10) +#define R200_TXA_ARG_C_R5_BLUE (21 << 10) +#define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) +#define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) +#define R200_TXA_ARG_C_MASK (31 << 10) +#define R200_TXA_ARG_C_SHIFT 10 +#define R200_TXA_COMP_ARG_A (1 << 16) +#define R200_TXA_COMP_ARG_A_SHIFT (16) +#define R200_TXA_BIAS_ARG_A (1 << 17) +#define R200_TXA_SCALE_ARG_A (1 << 18) +#define R200_TXA_NEG_ARG_A (1 << 19) +#define R200_TXA_COMP_ARG_B (1 << 20) +#define R200_TXA_COMP_ARG_B_SHIFT (20) +#define R200_TXA_BIAS_ARG_B (1 << 21) +#define R200_TXA_SCALE_ARG_B (1 << 22) +#define R200_TXA_NEG_ARG_B (1 << 23) +#define R200_TXA_COMP_ARG_C (1 << 24) +#define R200_TXA_COMP_ARG_C_SHIFT (24) +#define R200_TXA_BIAS_ARG_C (1 << 25) +#define R200_TXA_SCALE_ARG_C (1 << 26) +#define R200_TXA_NEG_ARG_C (1 << 27) +#define R200_TXA_OP_MADD (0 << 28) +#define R200_TXA_OP_CND0 (2 << 28) +#define R200_TXA_OP_LERP (3 << 28) +#define R200_TXA_OP_CONDITIONAL (6 << 28) +#define R200_TXA_OP_MASK (7 << 28) +#define R200_PP_TXABLEND2_0 0x2f0c +#define R200_TXA_TFACTOR_SEL_SHIFT 0 +#define R200_TXA_TFACTOR_SEL_MASK 0x7 +#define R200_TXA_TFACTOR1_SEL_SHIFT 4 +#define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) +#define R200_TXA_SCALE_SHIFT 8 +#define R200_TXA_SCALE_MASK (7 << 8) +#define R200_TXA_SCALE_1X (0 << 8) +#define R200_TXA_SCALE_2X (1 << 8) +#define R200_TXA_SCALE_4X (2 << 8) +#define R200_TXA_SCALE_8X (3 << 8) +#define R200_TXA_SCALE_INV2 (5 << 8) +#define R200_TXA_SCALE_INV4 (6 << 8) +#define R200_TXA_SCALE_INV8 (7 << 8) +#define R200_TXA_CLAMP_SHIFT 12 +#define R200_TXA_CLAMP_MASK (3 << 12) +#define R200_TXA_CLAMP_WRAP (0 << 12) +#define R200_TXA_CLAMP_0_1 (1 << 12) +#define R200_TXA_CLAMP_8_8 (2 << 12) +#define R200_TXA_OUTPUT_REG_MASK (7 << 16) +#define R200_TXA_OUTPUT_REG_NONE (0 << 16) +#define R200_TXA_OUTPUT_REG_R0 (1 << 16) +#define R200_TXA_OUTPUT_REG_R1 (2 << 16) +#define R200_TXA_OUTPUT_REG_R2 (3 << 16) +#define R200_TXA_OUTPUT_REG_R3 (4 << 16) +#define R200_TXA_OUTPUT_REG_R4 (5 << 16) +#define R200_TXA_OUTPUT_REG_R5 (6 << 16) +#define R200_TXA_DOT_ALPHA (1 << 20) +#define R200_TXA_REPL_NORMAL 0 +#define R200_TXA_REPL_RED 1 +#define R200_TXA_REPL_GREEN 2 +#define R200_TXA_REPL_ARG_A_SHIFT 26 +#define R200_TXA_REPL_ARG_A_MASK (3 << 26) +#define R200_TXA_REPL_ARG_B_SHIFT 28 +#define R200_TXA_REPL_ARG_B_MASK (3 << 28) +#define R200_TXA_REPL_ARG_C_SHIFT 30 +#define R200_TXA_REPL_ARG_C_MASK (3 << 30) + +#define R200_SE_VTX_FMT_0 0x2088 +#define R200_VTX_XY 0 /* always have xy */ +#define R200_VTX_Z0 (1<<0) +#define R200_VTX_W0 (1<<1) +#define R200_VTX_WEIGHT_COUNT_SHIFT (2) +#define R200_VTX_PV_MATRIX_SEL (1<<5) +#define R200_VTX_N0 (1<<6) +#define R200_VTX_POINT_SIZE (1<<7) +#define R200_VTX_DISCRETE_FOG (1<<8) +#define R200_VTX_SHININESS_0 (1<<9) +#define R200_VTX_SHININESS_1 (1<<10) +#define R200_VTX_COLOR_NOT_PRESENT 0 +#define R200_VTX_PK_RGBA 1 +#define R200_VTX_FP_RGB 2 +#define R200_VTX_FP_RGBA 3 +#define R200_VTX_COLOR_MASK 3 +#define R200_VTX_COLOR_0_SHIFT 11 +#define R200_VTX_COLOR_1_SHIFT 13 +#define R200_VTX_COLOR_2_SHIFT 15 +#define R200_VTX_COLOR_3_SHIFT 17 +#define R200_VTX_COLOR_4_SHIFT 19 +#define R200_VTX_COLOR_5_SHIFT 21 +#define R200_VTX_COLOR_6_SHIFT 23 +#define R200_VTX_COLOR_7_SHIFT 25 +#define R200_VTX_XY1 (1<<28) +#define R200_VTX_Z1 (1<<29) +#define R200_VTX_W1 (1<<30) +#define R200_VTX_N1 (1<<31) +#define R200_SE_VTX_FMT_1 0x208c +#define R200_VTX_TEX0_COMP_CNT_SHIFT 0 +#define R200_VTX_TEX1_COMP_CNT_SHIFT 3 +#define R200_VTX_TEX2_COMP_CNT_SHIFT 6 +#define R200_VTX_TEX3_COMP_CNT_SHIFT 9 +#define R200_VTX_TEX4_COMP_CNT_SHIFT 12 +#define R200_VTX_TEX5_COMP_CNT_SHIFT 15 + +#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 +#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 +#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 +#define R200_OUTPUT_XYZW (1<<0) +#define R200_OUTPUT_COLOR_0 (1<<8) +#define R200_OUTPUT_COLOR_1 (1<<9) +#define R200_OUTPUT_TEX_0 (1<<16) +#define R200_OUTPUT_TEX_1 (1<<17) +#define R200_OUTPUT_TEX_2 (1<<18) +#define R200_OUTPUT_TEX_3 (1<<19) +#define R200_OUTPUT_TEX_4 (1<<20) +#define R200_OUTPUT_TEX_5 (1<<21) +#define R200_OUTPUT_TEX_MASK (0x3f<<16) +#define R200_OUTPUT_DISCRETE_FOG (1<<24) +#define R200_OUTPUT_PT_SIZE (1<<25) +#define R200_FORCE_INORDER_PROC (1<<31) +#define R200_PP_CNTL_X 0x2cc4 +#define R200_PP_TXMULTI_CTL_0 0x2c1c +#define R200_SE_VTX_STATE_CNTL 0x2180 +#define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) + +/* BUS MASTERING */ + +#define BM_FRAME_BUF_OFFSET 0xA00 +#define BM_SYSTEM_MEM_ADDR 0xA04 +#define BM_COMMAND 0xA08 +#define BM_INTERRUPT_DIS 0x08000000 +#define BM_TRANSFER_DEST_REG 0x10000000 +#define BM_FORCE_TO_PCI 0x20000000 +#define BM_FRAME_OFFSET_HOLD 0x40000000 +#define BM_END_OF_LIST 0x80000000 +//#define BM_STATUS 0xA0c // !!!!!! already used +#define BM_QUEUE_STATUS 0xA10 +#define BM_QUEUE_FREE_STATUS 0xA14 +#define BM_CHUNK_0_VAL 0xA18 +#define BM_PTR_FORCE_TO_PCI 0x00200000 +#define BM_PM4_RD_FORCE_TO_PCI 0x00400000 +#define BM_GLOBAL_FORCE_TO_PCI 0x00800000 +#define BM_VIP3_NOCHUNK 0x10000000 +#define BM_VIP2_NOCHUNK 0x20000000 +#define BM_VIP1_NOCHUNK 0x40000000 +#define BM_VIP0_NOCHUNK 0x80000000 +#define BM_CHUNK_1_VAL 0xA1C +#define BM_VIP0_BUF 0xA20 +#define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 +#define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 +#define BM_VIP0_ACTIVE 0xA24 +#define BM_VIP1_BUF 0xA30 +#define BM_VIP1_ACTIVE 0xA34 +#define BM_VIP2_BUF 0xA40 +#define BM_VIP2_ACTIVE 0xA44 +#define BM_VIP3_BUF 0xA50 +#define BM_VIP3_ACTIVE 0xA54 +#define BM_VIDCAP_BUF0 0xA60 +#define BM_VIDCAP_BUF1 0xA64 +#define BM_VIDCAP_BUF2 0xA68 +#define BM_VIDCAP_ACTIVE 0xA6c +#define BM_GUI 0xA80 + +/* RAGE THEATER REGISTERS */ + +#define DMA_VIPH0_COMMAND 0x0A00 +#define DMA_VIPH1_COMMAND 0x0A04 +#define DMA_VIPH2_COMMAND 0x0A08 +#define DMA_VIPH3_COMMAND 0x0A0C +#define DMA_VIPH_STATUS 0x0A10 +#define DMA_VIPH_CHUNK_0 0x0A18 +#define DMA_VIPH_CHUNK_1_VAL 0x0A1C +#define DMA_VIP0_TABLE_ADDR 0x0A20 +#define DMA_VIPH0_ACTIVE 0x0A24 +#define DMA_VIP1_TABLE_ADDR 0x0A30 +#define DMA_VIPH1_ACTIVE 0x0A34 +#define DMA_VIP2_TABLE_ADDR 0x0A40 +#define DMA_VIPH2_ACTIVE 0x0A44 +#define DMA_VIP3_TABLE_ADDR 0x0A50 +#define DMA_VIPH3_ACTIVE 0x0A54 +#define DMA_VIPH_ABORT 0x0A88 + +#define VIPH_CONTROL 0x0C40 +#define VIPH_CH0_DATA 0x0C00 +#define VIPH_CH1_DATA 0x0C04 +#define VIPH_CH2_DATA 0x0C08 +#define VIPH_CH3_DATA 0x0C0C +#define VIPH_CH0_ADDR 0x0C10 +#define VIPH_CH1_ADDR 0x0C14 +#define VIPH_CH2_ADDR 0x0C18 +#define VIPH_CH3_ADDR 0x0C1C +#define VIPH_CH0_SBCNT 0x0C20 +#define VIPH_CH1_SBCNT 0x0C24 +#define VIPH_CH2_SBCNT 0x0C28 +#define VIPH_CH3_SBCNT 0x0C2C +#define VIPH_CH0_ABCNT 0x0C30 +#define VIPH_CH1_ABCNT 0x0C34 +#define VIPH_CH2_ABCNT 0x0C38 +#define VIPH_CH3_ABCNT 0x0C3C +#define VIPH_DV_LAT 0x0C44 +#define VIPH_BM_CHUNK 0x0C48 +#define VIPH_DV_INT 0x0C4C +#define VIPH_TIMEOUT_STAT 0x0C50 + +#define VIPH_REG_DATA 0x0084 +#define VIPH_REG_ADDR 0x0080 + +/* Address Space Rage Theatre Registers (VIP Access) */ +#define VIP_VIP_VENDOR_DEVICE_ID 0x0000 +#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004 +#define VIP_VIP_COMMAND_STATUS 0x0008 +#define VIP_VIP_REVISION_ID 0x000c +#define VIP_HW_DEBUG 0x0010 +#define VIP_SW_SCRATCH 0x0014 +#define VIP_I2C_CNTL_0 0x0020 +#define VIP_I2C_CNTL_1 0x0024 +#define VIP_I2C_DATA 0x0028 +#define VIP_INT_CNTL 0x002c +#define VIP_INT_CNTL__FB_INT0 0x02000000 +#define VIP_INT_CNTL__FB_INT0_CLR 0x02000000 +#define VIP_GPIO_INOUT 0x0030 +#define VIP_GPIO_CNTL 0x0034 +#define VIP_CLKOUT_GPIO_CNTL 0x0038 +#define VIP_RIPINTF_PORT_CNTL 0x003c +#define VIP_HOSTINTF_PORT_CNTL 0x003c +#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SN 0x00000008 +#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SP 0x00000080 +#define VIP_HOSTINTF_PORT_CNTL__HAD_HCTL_SDA_SR 0x00000100 +#define VIP_HOSTINTF_PORT_CNTL__SUB_SYS_ID_EN 0x00010000 +#define VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE 0x00300000 +#define VIP_HOSTINTF_PORT_CNTL__FIFOA_ENDIAN_SWAP 0x00c00000 +#define VIP_HOSTINTF_PORT_CNTL__FIFOB_ENDIAN_SWAP 0x03000000 +#define VIP_HOSTINTF_PORT_CNTL__FIFOC_ENDIAN_SWAP 0x0c000000 +#define VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP 0x30000000 +#define VIP_HOSTINTF_PORT_CNTL__FIFOE_ENDIAN_SWAP 0xc0000000 +#define VIP_DSP_PLL_CNTL 0x0bc +#define VIP_TC_SOURCE 0x300 +#define VIP_TC_DESTINATION 0x304 +#define VIP_TC_COMMAND 0x308 +#define VIP_TC_STATUS 0x030c +#define VIP_TC_STATUS__TC_CHAN_BUSY 0x00007fff +#define VIP_TC_STATUS__TC_WRITE_PENDING 0x00008000 +#define VIP_TC_STATUS__TC_FIFO_4_EMPTY 0x00040000 +#define VIP_TC_STATUS__TC_FIFO_6_EMPTY 0x00080000 +#define VIP_TC_STATUS__TC_FIFO_8_EMPTY 0x00100000 +#define VIP_TC_STATUS__TC_FIFO_10_EMPTY 0x00200000 +#define VIP_TC_STATUS__TC_FIFO_4_FULL 0x04000000 +#define VIP_TC_STATUS__TC_FIFO_6_FULL 0x08080000 +#define VIP_TC_STATUS__TC_FIFO_8_FULL 0x10080000 +#define VIP_TC_STATUS__TC_FIFO_10_FULL 0x20080000 +#define VIP_TC_STATUS__DSP_ILLEGAL_OP 0x80080000 +#define VIP_TC_DOWNLOAD 0x0310 +#define VIP_TC_DOWNLOAD__TC_DONE_MASK 0x00003fff +#define VIP_TC_DOWNLOAD__TC_RESET_MODE 0x00060000 +#define VIP_FB_INT 0x0314 +#define VIP_FB_INT__INT_7 0x00000080 +#define VIP_FB_SCRATCH0 0x0318 +#define VIP_FB_SCRATCH1 0x031c +#define VIP_ADC_CNTL 0x0400 +#define VIP_ADC_DEBUG 0x0404 +#define VIP_STANDARD_SELECT 0x0408 +#define VIP_THERMO2BIN_STATUS 0x040c +#define VIP_COMB_CNTL0 0x0440 +#define VIP_COMB_CNTL1 0x0444 +#define VIP_COMB_CNTL2 0x0448 +#define VIP_COMB_LINE_LENGTH 0x044c +#define VIP_NOISE_CNTL0 0x0450 +#define VIP_HS_PLINE 0x0480 +#define VIP_HS_DTOINC 0x0484 +#define VIP_HS_PLLGAIN 0x0488 +#define VIP_HS_MINMAXWIDTH 0x048c +#define VIP_HS_GENLOCKDELAY 0x0490 +#define VIP_HS_WINDOW_LIMIT 0x0494 +#define VIP_HS_WINDOW_OC_SPEED 0x0498 +#define VIP_HS_PULSE_WIDTH 0x049c +#define VIP_HS_PLL_ERROR 0x04a0 +#define VIP_HS_PLL_FS_PATH 0x04a4 +#define VIP_SG_BLACK_GATE 0x04c0 +#define VIP_SG_SYNCTIP_GATE 0x04c4 +#define VIP_SG_UVGATE_GATE 0x04c8 +#define VIP_LP_AGC_CLAMP_CNTL0 0x0500 +#define VIP_LP_AGC_CLAMP_CNTL1 0x0504 +#define VIP_LP_BRIGHTNESS 0x0508 +#define VIP_LP_CONTRAST 0x050c +#define VIP_LP_SLICE_LIMIT 0x0510 +#define VIP_LP_WPA_CNTL0 0x0514 +#define VIP_LP_WPA_CNTL1 0x0518 +#define VIP_LP_BLACK_LEVEL 0x051c +#define VIP_LP_SLICE_LEVEL 0x0520 +#define VIP_LP_SYNCTIP_LEVEL 0x0524 +#define VIP_LP_VERT_LOCKOUT 0x0528 +#define VIP_VS_DETECTOR_CNTL 0x0540 +#define VIP_VS_BLANKING_CNTL 0x0544 +#define VIP_VS_FIELD_ID_CNTL 0x0548 +#define VIP_VS_COUNTER_CNTL 0x054c +#define VIP_VS_FRAME_TOTAL 0x0550 +#define VIP_VS_LINE_COUNT 0x0554 +#define VIP_CP_PLL_CNTL0 0x0580 +#define VIP_CP_PLL_CNTL1 0x0584 +#define VIP_CP_HUE_CNTL 0x0588 +#define VIP_CP_BURST_GAIN 0x058c +#define VIP_CP_AGC_CNTL 0x0590 +#define VIP_CP_ACTIVE_GAIN 0x0594 +#define VIP_CP_PLL_STATUS0 0x0598 +#define VIP_CP_PLL_STATUS1 0x059c +#define VIP_CP_PLL_STATUS2 0x05a0 +#define VIP_CP_PLL_STATUS3 0x05a4 +#define VIP_CP_PLL_STATUS4 0x05a8 +#define VIP_CP_PLL_STATUS5 0x05ac +#define VIP_CP_PLL_STATUS6 0x05b0 +#define VIP_CP_PLL_STATUS7 0x05b4 +#define VIP_CP_DEBUG_FORCE 0x05b8 +#define VIP_CP_VERT_LOCKOUT 0x05bc +#define VIP_H_ACTIVE_WINDOW 0x05c0 +#define VIP_V_ACTIVE_WINDOW 0x05c4 +#define VIP_H_VBI_WINDOW 0x05c8 +#define VIP_V_VBI_WINDOW 0x05cc +#define VIP_VBI_CONTROL 0x05d0 +#define VIP_DECODER_DEBUG_CNTL 0x05d4 +#define VIP_SINGLE_STEP_DATA 0x05d8 +#define VIP_MASTER_CNTL 0x0040 +#define VIP_RGB_CNTL 0x0048 +#define VIP_CLKOUT_CNTL 0x004c +#define VIP_SYNC_CNTL 0x0050 +#define VIP_I2C_CNTL 0x0054 +#define VIP_HTOTAL 0x0080 +#define VIP_HDISP 0x0084 +#define VIP_HSIZE 0x0088 +#define VIP_HSTART 0x008c +#define VIP_HCOUNT 0x0090 +#define VIP_VTOTAL 0x0094 +#define VIP_VDISP 0x0098 +#define VIP_VCOUNT 0x009c +#define VIP_VFTOTAL 0x00a0 +#define VIP_DFCOUNT 0x00a4 +#define VIP_DFRESTART 0x00a8 +#define VIP_DHRESTART 0x00ac +#define VIP_DVRESTART 0x00b0 +#define VIP_SYNC_SIZE 0x00b4 +#define VIP_TV_PLL_FINE_CNTL 0x00b8 +#define VIP_CRT_PLL_FINE_CNTL 0x00bc +#define VIP_TV_PLL_CNTL 0x00c0 +#define VIP_CRT_PLL_CNTL 0x00c4 +#define VIP_PLL_CNTL0 0x00c8 +#define VIP_PLL_TEST_CNTL 0x00cc +#define VIP_CLOCK_SEL_CNTL 0x00d0 +#define VIP_VIN_PLL_CNTL 0x00d4 +#define VIP_VIN_PLL_FINE_CNTL 0x00d8 +#define VIP_AUD_PLL_CNTL 0x00e0 +#define VIP_AUD_PLL_FINE_CNTL 0x00e4 +#define VIP_AUD_CLK_DIVIDERS 0x00e8 +#define VIP_AUD_DTO_INCREMENTS 0x00ec +#define VIP_L54_PLL_CNTL 0x00f0 +#define VIP_L54_PLL_FINE_CNTL 0x00f4 +#define VIP_L54_DTO_INCREMENTS 0x00f8 +#define VIP_PLL_CNTL1 0x00fc +#define VIP_FRAME_LOCK_CNTL 0x0100 +#define VIP_SYNC_LOCK_CNTL 0x0104 +#define VIP_TVO_SYNC_PAT_ACCUM 0x0108 +#define VIP_TVO_SYNC_THRESHOLD 0x010c +#define VIP_TVO_SYNC_PAT_EXPECT 0x0110 +#define VIP_DELAY_ONE_MAP_A 0x0114 +#define VIP_DELAY_ONE_MAP_B 0x0118 +#define VIP_DELAY_ZERO_MAP_A 0x011c +#define VIP_DELAY_ZERO_MAP_B 0x0120 +#define VIP_TVO_DATA_DELAY_A 0x0140 +#define VIP_TVO_DATA_DELAY_B 0x0144 +#define VIP_HOST_READ_DATA 0x0180 +#define VIP_HOST_WRITE_DATA 0x0184 +#define VIP_HOST_RD_WT_CNTL 0x0188 +#define VIP_VSCALER_CNTL1 0x01c0 +#define VIP_TIMING_CNTL 0x01c4 +#define VIP_VSCALER_CNTL2 0x01c8 +#define VIP_Y_FALL_CNTL 0x01cc +#define VIP_Y_RISE_CNTL 0x01d0 +#define VIP_Y_SAW_TOOTH_CNTL 0x01d4 +#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0 +#define VIP_GAIN_LIMIT_SETTINGS 0x01e4 +#define VIP_LINEAR_GAIN_SETTINGS 0x01e8 +#define VIP_MODULATOR_CNTL1 0x0200 +#define VIP_MODULATOR_CNTL2 0x0204 +#define VIP_MV_MODE_CNTL 0x0208 +#define VIP_MV_STRIPE_CNTL 0x020c +#define VIP_MV_LEVEL_CNTL1 0x0210 +#define VIP_MV_LEVEL_CNTL2 0x0214 +#define VIP_PRE_DAC_MUX_CNTL 0x0240 +#define VIP_TV_DAC_CNTL 0x0280 +#define VIP_CRC_CNTL 0x02c0 +#define VIP_VIDEO_PORT_SIG 0x02c4 +#define VIP_VBI_CC_CNTL 0x02c8 +#define VIP_VBI_EDS_CNTL 0x02cc +#define VIP_VBI_20BIT_CNTL 0x02d0 +#define VIP_VBI_DTO_CNTL 0x02d4 +#define VIP_VBI_LEVEL_CNTL 0x02d8 +#define VIP_UV_ADR 0x0300 +#define VIP_MV_STATUS 0x0330 +#define VIP_UPSAMP_COEFF0_0 0x0340 +#define VIP_UPSAMP_COEFF0_1 0x0344 +#define VIP_UPSAMP_COEFF0_2 0x0348 +#define VIP_UPSAMP_COEFF1_0 0x034c +#define VIP_UPSAMP_COEFF1_1 0x0350 +#define VIP_UPSAMP_COEFF1_2 0x0354 +#define VIP_UPSAMP_COEFF2_0 0x0358 +#define VIP_UPSAMP_COEFF2_1 0x035c +#define VIP_UPSAMP_COEFF2_2 0x0360 +#define VIP_UPSAMP_COEFF3_0 0x0364 +#define VIP_UPSAMP_COEFF3_1 0x0368 +#define VIP_UPSAMP_COEFF3_2 0x036c +#define VIP_UPSAMP_COEFF4_0 0x0370 +#define VIP_UPSAMP_COEFF4_1 0x0374 +#define VIP_UPSAMP_COEFF4_2 0x0378 +#define VIP_TV_DTO_INCREMENTS 0x0390 +#define VIP_CRT_DTO_INCREMENTS 0x0394 +#define VIP_VSYNC_DIFF_CNTL 0x03a0 +#define VIP_VSYNC_DIFF_LIMITS 0x03a4 +#define VIP_VSYNC_DIFF_RD_DATA 0x03a8 +#define VIP_SCALER_IN_WINDOW 0x0618 +#define VIP_SCALER_OUT_WINDOW 0x061c +#define VIP_H_SCALER_CONTROL 0x0600 +#define VIP_V_SCALER_CONTROL 0x0604 +#define VIP_V_DEINTERLACE_CONTROL 0x0608 +#define VIP_VBI_SCALER_CONTROL 0x060c +#define VIP_DVS_PORT_CTRL 0x0610 +#define VIP_DVS_PORT_READBACK 0x0614 +#define VIP_FIFOA_CONFIG 0x0800 +#define VIP_FIFOB_CONFIG 0x0804 +#define VIP_FIFOC_CONFIG 0x0808 +#define VIP_SPDIF_PORT_CNTL 0x080c +#define VIP_SPDIF_CHANNEL_STAT 0x0810 +#define VIP_SPDIF_AC3_PREAMBLE 0x0814 +#define VIP_I2S_TRANSMIT_CNTL 0x0818 +#define VIP_I2S_RECEIVE_CNTL 0x081c +#define VIP_SPDIF_TX_CNT_REG 0x0820 +#define VIP_IIS_TX_CNT_REG 0x0824 + +/* Status defines */ +#define VIP_BUSY 0 +#define VIP_IDLE 1 +#define VIP_RESET 2 + +#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_STAT 0x00000001 +#define VIPH_TIMEOUT_STAT__VIPH_FIFO0_AK 0x00000001 +#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_STAT 0x00000002 +#define VIPH_TIMEOUT_STAT__VIPH_FIFO1_AK 0x00000002 +#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_STAT 0x00000004 +#define VIPH_TIMEOUT_STAT__VIPH_FIFO2_AK 0x00000004 +#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_STAT 0x00000008 +#define VIPH_TIMEOUT_STAT__VIPH_FIFO3_AK 0x00000008 + +#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 +#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 +#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 +#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 + +#define RT100_ATI_ID 0x4D541002 +#define RT200_ATI_ID 0x4D4A1002 + +/* Register/Field values: */ +#define RT_COMP0 0x0 +#define RT_COMP1 0x1 +#define RT_COMP2 0x2 +#define RT_YF_COMP3 0x3 +#define RT_YR_COMP3 0x4 +#define RT_YCF_COMP4 0x5 +#define RT_YCR_COMP4 0x6 + +/* Video standard defines */ +#define RT_NTSC 0x0 +#define RT_PAL 0x1 +#define RT_SECAM 0x2 +#define extNONE 0x0000 +#define extNTSC 0x0100 +#define extRsvd 0x0200 +#define extPAL 0x0300 +#define extPAL_M 0x0400 +#define extPAL_N 0x0500 +#define extSECAM 0x0600 +#define extPAL_NCOMB 0x0700 +#define extNTSC_J 0x0800 +#define extNTSC_443 0x0900 +#define extPAL_BGHI 0x0A00 +#define extPAL_60 0x0B00 + /* these are used in MSP3430 */ +#define extPAL_DK1 0x0C00 +#define extPAL_AUTO 0x0D00 + /* these are used in RT200. Some are defined above */ +#define extPAL_B 0x0E00 +#define extPAL_D 0x0F00 +#define extPAL_G 0x1000 +#define extPAL_H 0x1100 +#define extPAL_I 0x1200 +#define extSECAM_B 0x1300 +#define extSECAM_D 0x1400 +#define extSECAM_G 0x1500 +#define extSECAM_H 0x1600 +#define extSECAM_K 0x1700 +#define extSECAM_K1 0x1800 +#define extSECAM_L 0x1900 +#define extSECAM_L1 0x1A00 + +#define RT_FREF_2700 6 +#define RT_FREF_2950 5 + +#define RT_COMPOSITE 0x0 +#define RT_SVIDEO 0x1 + +#define RT_NORM_SHARPNESS 0x03 +#define RT_HIGH_SHARPNESS 0x0F + +#define RT_HUE_PAL_DEF 0x00 + +#define RT_DECINTERLACED 0x1 +#define RT_DECNONINTERLACED 0x0 + +#define NTSC_LINES 525 +#define PAL_SECAM_LINES 625 + +#define RT_ASYNC_ENABLE 0x0 +#define RT_ASYNC_DISABLE 0x1 +#define RT_ASYNC_RESET 0x1 + +#define RT_VINRST_ACTIVE 0x0 +#define RT_VINRST_RESET 0x1 +#define RT_L54RST_RESET 0x1 + +#define RT_REF_CLK 0x0 +#define RT_PLL_VIN_CLK 0x1 + +#define RT_VIN_ASYNC_RST 0x20 +#define RT_DVS_ASYNC_RST 0x80 + +#define RT_ADC_ENABLE 0x0 +#define RT_ADC_DISABLE 0x1 + +#define RT_DVSDIR_IN 0x0 +#define RT_DVSDIR_OUT 0x1 + +#define RT_DVSCLK_HIGH 0x0 +#define RT_DVSCLK_LOW 0x1 + +#define RT_DVSCLK_SEL_8FS 0x0 +#define RT_DVSCLK_SEL_27MHZ 0x1 + +#define RT_DVS_CONTSTREAM 0x1 +#define RT_DVS_NONCONTSTREAM 0x0 + +#define RT_DVSDAT_HIGH 0x0 +#define RT_DVSDAT_LOW 0x1 + +#define RT_ADC_CNTL_DEFAULT 0x03252338 + +/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 /* was 0x09438090 */ +#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000 + +#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090 + +#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/ +#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090 + +#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090 + +#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090 +/* End of filter settings. */ + +/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081 + +#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1 + +#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091 +#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081 + +#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1 + +#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1 +/* End of filter settings. */ + +/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010 +#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF + +#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */ +#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */ +#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102 +#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102 +#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102 +/* End of filter settings. */ + +/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A +#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A + +#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B +#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B + +#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A +#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A + +#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391 +#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391 + +#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389 +#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389 +/* End of filter settings. */ + +/* LP_AGC_CLAMP_CNTL0 */ +#define RT_NTSCM_SYNCTIP_REF0 0x00000037 +#define RT_NTSCM_SYNCTIP_REF1 0x00000029 +#define RT_NTSCM_CLAMP_REF 0x0000003B +#define RT_NTSCM_PEAKWHITE 0x000000FF +#define RT_NTSCM_VBI_PEAKWHITE 0x000000D2 /* was 0xc2 - docs say d2 */ + +#define RT_NTSCM_WPA_THRESHOLD 0x00000406 +#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3 + +#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B + +#define RT_NTSCM_LP_LOCKOUT_START 0x00000206 +#define RT_NTSCM_LP_LOCKOUT_END 0x00000021 +#define RT_NTSCM_CH_DTO_INC 0x00400000 +#define RT_NTSCM_CH_PLL_SGAIN 0x00000001 +#define RT_NTSCM_CH_PLL_FGAIN 0x00000002 + +#define RT_NTSCM_CR_BURST_GAIN 0x0000007A +#define RT_NTSCM_CB_BURST_GAIN 0x000000AC + +#define RT_NTSCM_CH_HEIGHT 0x000000CD +#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0 +#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002 +#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000 +#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A +#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC + +#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207 +#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E + +#define RT_NTSCJ_SYNCTIP_REF0 0x00000004 +#define RT_NTSCJ_SYNCTIP_REF1 0x00000012 +#define RT_NTSCJ_CLAMP_REF 0x0000003B +#define RT_NTSCJ_PEAKWHITE 0x000000CB +#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2 +#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0 +#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4 +#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C +#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206 +#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021 + +#define RT_NTSCJ_CR_BURST_GAIN 0x00000071 +#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F +#define RT_NTSCJ_CH_HEIGHT 0x000000CD +#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0 +#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002 +#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000 +#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071 +#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F +#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207 +#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E + +#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ +#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ +#define RT_PAL_CLAMP_REF 0x0000003B +#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ +#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ +#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */ + +#define RT_PAL_WPA_TRIGGER_LO 0x00000096 +#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2 +#define RT_PAL_LP_LOCKOUT_START 0x00000263 +#define RT_PAL_LP_LOCKOUT_END 0x0000002C + +#define RT_PAL_CH_DTO_INC 0x00400000 +#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */ +#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */ +#define RT_PAL_CR_BURST_GAIN 0x0000007A +#define RT_PAL_CB_BURST_GAIN 0x000000AB +#define RT_PAL_CH_HEIGHT 0x0000009C +#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */ +#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */ +#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */ +#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */ +#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */ +#define RT_PAL_VERT_LOCKOUT_START 0x00000269 +#define RT_PAL_VERT_LOCKOUT_END 0x00000012 + +#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ +#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ +#define RT_SECAM_CLAMP_REF 0x0000003B +#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ +#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ +#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/ + +#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */ +#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2 +#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */ +#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */ + +#define RT_SECAM_CH_DTO_INC 0x003E7A28 +#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 - Volodya */ +#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */ + +#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ +#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ +#define RT_SECAM_CH_HEIGHT 0x00000066 +#define RT_SECAM_CH_KILL_LEVEL 0x00000060 +#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003 +#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000 +#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */ +#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */ +#define RT_SECAM_VERT_LOCKOUT_START 0x00000269 +#define RT_SECAM_VERT_LOCKOUT_END 0x00000012 + +#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/ +#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000a + +#define RT_NTSCM_FIELD_IDLOCATION 0x00000105 +#define RT_PAL_FIELD_IDLOCATION 0x00000137 + +#define RT_NTSCM_H_ACTIVE_START 0x00000070 +#define RT_NTSCM_H_ACTIVE_END 0x00000363 + +#define RT_PAL_H_ACTIVE_START 0x0000009A +#define RT_PAL_H_ACTIVE_END 0x00000439 + +#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1) +#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1) + +#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */ +#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */ + +/* VBI */ +#define RT_NTSCM_H_VBI_WIND_START 0x32 /* instead of 0x00000049 - V.D. */ +#define RT_NTSCM_H_VBI_WIND_END 0x367 /* instead of 0x00000366 - V.D. */ + +#define RT_PAL_H_VBI_WIND_START 0x00000084 +#define RT_PAL_H_VBI_WIND_END 0x0000041F + +#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def +#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def + +#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */ +#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */ + +#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */ +#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */ +#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */ + +#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA +#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353 + +#define RT_NTSCM_VSYNC_INT_HOLD 0x17 +#define RT_PALSEM_VSYNC_INT_HOLD 0x1C + +#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 +#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */ + +#define RT_FIELD_FLIP_EN 0x4 +#define RT_V_FIELD_FLIP_INVERTED 0x2000 + +#define RT_NTSCM_H_IN_START 0x70 +#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */ +#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */ +#define RT_NTSC_H_ACTIVE_SIZE 744 +#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */ +#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */ +#define RT_NTSCM_V_IN_START (0x23) +#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */ +#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */ +#define RT_NTSCM_V_ACTIVE_SIZE 480 +#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */ +#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */ + +#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D +#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D +#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F +#define RT_PALM_WIN_CLOSE_LIMIT 0x4D +#define RT_PALN_WIN_CLOSE_LIMIT 0x5F +#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */ + +#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 + +#define RT_NTSCM_HS_PLL_SGAIN 0x5 +#define RT_NTSCM_HS_PLL_FGAIN 0x7 + +#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4 +#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0 + +#define TV 0x1 +#define LINEIN 0x2 +#define MUTE 0x3 + +#define DEC_COMPOSITE 0 +#define DEC_SVIDEO 1 +#define DEC_TUNER 2 + +#define DEC_NTSC 0 +#define DEC_PAL 1 +#define DEC_SECAM 2 +#define DEC_NTSC_J 8 + +#define DEC_SMOOTH 0 +#define DEC_SHARP 1 + +/* RT Register Field Defaults: */ +#define fld_tmpReg1_def (unsigned long) 0x00000000 +#define fld_tmpReg2_def (unsigned long) 0x00000001 +#define fld_tmpReg3_def (unsigned long) 0x00000002 + +#define fld_LP_CONTRAST_def (unsigned long) 0x0000006e +#define fld_LP_BRIGHTNESS_def (unsigned long) 0x00003ff0 +#define fld_CP_HUE_CNTL_def (unsigned long) 0x00000000 +#define fld_LUMA_FILTER_def (unsigned long) 0x00000001 +#define fld_H_SCALE_RATIO_def (unsigned long) 0x00010000 +#define fld_H_SHARPNESS_def (unsigned long) 0x00000000 + +#define fld_V_SCALE_RATIO_def (unsigned long) 0x00000800 +#define fld_V_DEINTERLACE_ON_def (unsigned long) 0x00000001 +#define fld_V_BYPSS_def (unsigned long) 0x00000000 +#define fld_V_DITHER_ON_def (unsigned long) 0x00000001 +#define fld_EVENF_OFFSET_def (unsigned long) 0x00000000 +#define fld_ODDF_OFFSET_def (unsigned long) 0x00000000 + +#define fld_INTERLACE_DETECTED_def (unsigned long) 0x00000000 + +#define fld_VS_LINE_COUNT_def (unsigned long) 0x00000000 +#define fld_VS_DETECTED_LINES_def (unsigned long) 0x00000000 +#define fld_VS_ITU656_VB_def (unsigned long) 0x00000000 + +#define fld_VBI_CC_DATA_def (unsigned long) 0x00000000 +#define fld_VBI_CC_WT_def (unsigned long) 0x00000000 +#define fld_VBI_CC_WT_ACK_def (unsigned long) 0x00000000 +#define fld_VBI_CC_HOLD_def (unsigned long) 0x00000000 +#define fld_VBI_DECODE_EN_def (unsigned long) 0x00000000 + +#define fld_VBI_CC_DTO_P_def (unsigned long) 0x00001802 +#define fld_VBI_20BIT_DTO_P_def (unsigned long) 0x0000155c + +#define fld_VBI_CC_LEVEL_def (unsigned long) 0x0000003f +#define fld_VBI_20BIT_LEVEL_def (unsigned long) 0x00000059 +#define fld_VBI_CLK_RUNIN_GAIN_def (unsigned long) 0x0000010f + +#define fld_H_VBI_WIND_START_def (unsigned long) 0x00000041 +#define fld_H_VBI_WIND_END_def (unsigned long) 0x00000366 + +#define fld_V_VBI_WIND_START_def (unsigned long) 0x0B /* instead of 0x0D - V.D. */ +#define fld_V_VBI_WIND_END_def (unsigned long) 0x24 + +#define fld_VBI_20BIT_DATA0_def (unsigned long) 0x00000000 +#define fld_VBI_20BIT_DATA1_def (unsigned long) 0x00000000 +#define fld_VBI_20BIT_WT_def (unsigned long) 0x00000000 +#define fld_VBI_20BIT_WT_ACK_def (unsigned long) 0x00000000 +#define fld_VBI_20BIT_HOLD_def (unsigned long) 0x00000000 + +#define fld_VBI_CAPTURE_ENABLE_def (unsigned long) 0x00000000 + +#define fld_VBI_EDS_DATA_def (unsigned long) 0x00000000 +#define fld_VBI_EDS_WT_def (unsigned long) 0x00000000 +#define fld_VBI_EDS_WT_ACK_def (unsigned long) 0x00000000 +#define fld_VBI_EDS_HOLD_def (unsigned long) 0x00000000 + +#define fld_VBI_SCALING_RATIO_def (unsigned long) 0x00010000 +#define fld_VBI_ALIGNER_ENABLE_def (unsigned long) 0x00000000 + +#define fld_H_ACTIVE_START_def (unsigned long) 0x00000070 +#define fld_H_ACTIVE_END_def (unsigned long) 0x000002f0 + +#define fld_V_ACTIVE_START_def (unsigned long) ((22-4)*2+1) +#define fld_V_ACTIVE_END_def (unsigned long) ((22+240-4)*2+2) + +#define fld_CH_HEIGHT_def (unsigned long) 0x000000CD +#define fld_CH_KILL_LEVEL_def (unsigned long) 0x000000C0 +#define fld_CH_AGC_ERROR_LIM_def (unsigned long) 0x00000002 +#define fld_CH_AGC_FILTER_EN_def (unsigned long) 0x00000000 +#define fld_CH_AGC_LOOP_SPEED_def (unsigned long) 0x00000000 + +#define fld_HUE_ADJ_def (unsigned long) 0x00000000 + +#define fld_STANDARD_SEL_def (unsigned long) 0x00000000 +#define fld_STANDARD_YC_def (unsigned long) 0x00000000 + +#define fld_ADC_PDWN_def (unsigned long) 0x00000001 +#define fld_INPUT_SELECT_def (unsigned long) 0x00000000 + +#define fld_ADC_PREFLO_def (unsigned long) 0x00000003 +#define fld_H_SYNC_PULSE_WIDTH_def (unsigned long) 0x00000000 +#define fld_HS_GENLOCKED_def (unsigned long) 0x00000000 +#define fld_HS_SYNC_IN_WIN_def (unsigned long) 0x00000000 + +#define fld_VIN_ASYNC_RST_def (unsigned long) 0x00000001 +#define fld_DVS_ASYNC_RST_def (unsigned long) 0x00000001 + +/* Vendor IDs: */ +#define fld_VIP_VENDOR_ID_def (unsigned long) 0x00001002 +#define fld_VIP_DEVICE_ID_def (unsigned long) 0x00004d54 +#define fld_VIP_REVISION_ID_def (unsigned long) 0x00000001 + +/* AGC Delay Register */ +#define fld_BLACK_INT_START_def (unsigned long) 0x00000031 +#define fld_BLACK_INT_LENGTH_def (unsigned long) 0x0000000f + +#define fld_UV_INT_START_def (unsigned long) 0x0000003b +#define fld_U_INT_LENGTH_def (unsigned long) 0x0000000f +#define fld_V_INT_LENGTH_def (unsigned long) 0x0000000f +#define fld_CRDR_ACTIVE_GAIN_def (unsigned long) 0x0000007a +#define fld_CBDB_ACTIVE_GAIN_def (unsigned long) 0x000000ac + +#define fld_DVS_DIRECTION_def (unsigned long) 0x00000000 +#define fld_DVS_VBI_CARD8_SWAP_def (unsigned long) 0x00000000 +#define fld_DVS_CLK_SELECT_def (unsigned long) 0x00000000 +#define fld_CONTINUOUS_STREAM_def (unsigned long) 0x00000000 +#define fld_DVSOUT_CLK_DRV_def (unsigned long) 0x00000001 +#define fld_DVSOUT_DATA_DRV_def (unsigned long) 0x00000001 + +#define fld_COMB_CNTL0_def (unsigned long) 0x09438090 +#define fld_COMB_CNTL1_def (unsigned long) 0x00000010 + +#define fld_COMB_CNTL2_def (unsigned long) 0x16161010 +#define fld_COMB_LENGTH_def (unsigned long) 0x0718038A + +#define fld_SYNCTIP_REF0_def (unsigned long) 0x00000037 +#define fld_SYNCTIP_REF1_def (unsigned long) 0x00000029 +#define fld_CLAMP_REF_def (unsigned long) 0x0000003B +#define fld_AGC_PEAKWHITE_def (unsigned long) 0x000000FF +#define fld_VBI_PEAKWHITE_def (unsigned long) 0x000000D2 + +#define fld_WPA_THRESHOLD_def (unsigned long) 0x000003B0 + +#define fld_WPA_TRIGGER_LO_def (unsigned long) 0x000000B4 +#define fld_WPA_TRIGGER_HIGH_def (unsigned long) 0x0000021C + +#define fld_LOCKOUT_START_def (unsigned long) 0x00000206 +#define fld_LOCKOUT_END_def (unsigned long) 0x00000021 + +#define fld_CH_DTO_INC_def (unsigned long) 0x00400000 +#define fld_PLL_SGAIN_def (unsigned long) 0x00000001 +#define fld_PLL_FGAIN_def (unsigned long) 0x00000002 + +#define fld_CR_BURST_GAIN_def (unsigned long) 0x0000007a +#define fld_CB_BURST_GAIN_def (unsigned long) 0x000000ac + +#define fld_VERT_LOCKOUT_START_def (unsigned long) 0x00000207 +#define fld_VERT_LOCKOUT_END_def (unsigned long) 0x0000000E + +#define fld_H_IN_WIND_START_def (unsigned long) 0x00000070 +#define fld_V_IN_WIND_START_def (unsigned long) 0x00000027 + +#define fld_H_OUT_WIND_WIDTH_def (unsigned long) 0x000002f4 + +#define fld_V_OUT_WIND_WIDTH_def (unsigned long) 0x000000f0 + +#define fld_HS_LINE_TOTAL_def (unsigned long) 0x0000038E + +#define fld_MIN_PULSE_WIDTH_def (unsigned long) 0x0000002F +#define fld_MAX_PULSE_WIDTH_def (unsigned long) 0x00000046 + +#define fld_WIN_CLOSE_LIMIT_def (unsigned long) 0x0000004D +#define fld_WIN_OPEN_LIMIT_def (unsigned long) 0x000001B7 + +#define fld_VSYNC_INT_TRIGGER_def (unsigned long) 0x000002AA + +#define fld_VSYNC_INT_HOLD_def (unsigned long) 0x0000001D + +#define fld_VIN_M0_def (unsigned long) 0x00000039 +#define fld_VIN_N0_def (unsigned long) 0x0000014c +#define fld_MNFLIP_EN_def (unsigned long) 0x00000000 +#define fld_VIN_P_def (unsigned long) 0x00000006 +#define fld_REG_CLK_SEL_def (unsigned long) 0x00000000 + +#define fld_VIN_M1_def (unsigned long) 0x00000000 +#define fld_VIN_N1_def (unsigned long) 0x00000000 +#define fld_VIN_DRIVER_SEL_def (unsigned long) 0x00000000 +#define fld_VIN_MNFLIP_REQ_def (unsigned long) 0x00000000 +#define fld_VIN_MNFLIP_DONE_def (unsigned long) 0x00000000 +#define fld_TV_LOCK_TO_VIN_def (unsigned long) 0x00000000 +#define fld_TV_P_FOR_WINCLK_def (unsigned long) 0x00000004 + +#define fld_VINRST_def (unsigned long) 0x00000001 +#define fld_VIN_CLK_SEL_def (unsigned long) 0x00000000 + +#define fld_VS_FIELD_BLANK_START_def (unsigned long) 0x00000206 + +#define fld_VS_FIELD_BLANK_END_def (unsigned long) 0x0000000A + +/*#define fld_VS_FIELD_IDLOCATION_def (unsigned long) 0x00000105 */ +#define fld_VS_FIELD_IDLOCATION_def (unsigned long) 0x00000001 +#define fld_VS_FRAME_TOTAL_def (unsigned long) 0x00000217 + +#define fld_SYNC_TIP_START_def (unsigned long) 0x00000372 +#define fld_SYNC_TIP_LENGTH_def (unsigned long) 0x0000000F + +#define fld_GAIN_FORCE_DATA_def (unsigned long) 0x00000000 +#define fld_GAIN_FORCE_EN_def (unsigned long) 0x00000000 +#define fld_I_CLAMP_SEL_def (unsigned long) 0x00000003 +#define fld_I_AGC_SEL_def (unsigned long) 0x00000001 +#define fld_EXT_CLAMP_CAP_def (unsigned long) 0x00000001 +#define fld_EXT_AGC_CAP_def (unsigned long) 0x00000001 +#define fld_DECI_DITHER_EN_def (unsigned long) 0x00000001 +#define fld_ADC_PREFHI_def (unsigned long) 0x00000000 +#define fld_ADC_CH_GAIN_SEL_def (unsigned long) 0x00000001 + +#define fld_HS_PLL_SGAIN_def (unsigned long) 0x00000003 + +#define fld_NREn_def (unsigned long) 0x00000000 +#define fld_NRGainCntl_def (unsigned long) 0x00000000 +#define fld_NRBWTresh_def (unsigned long) 0x00000000 +#define fld_NRGCTresh_def (unsigned long) 0x00000000 +#define fld_NRCoefDespeclMode_def (unsigned long) 0x00000000 + +#define fld_GPIO_5_OE_def (unsigned long) 0x00000000 +#define fld_GPIO_6_OE_def (unsigned long) 0x00000000 + +#define fld_GPIO_5_OUT_def (unsigned long) 0x00000000 +#define fld_GPIO_6_OUT_def (unsigned long) 0x00000000 +/* End of field default values. */ + +#endif /* _RADEON_H */ + diff --git a/BaS_gcc/include/radeonfb.h b/BaS_gcc/include/radeonfb.h new file mode 100644 index 0000000..37e1499 --- /dev/null +++ b/BaS_gcc/include/radeonfb.h @@ -0,0 +1,690 @@ +#ifndef __RADEONFB_H__ +#define __RADEONFB_H__ + +//#include "config.h" +#include +#include "pci.h" +#include "mod_devicetable.h" +#include "pci_ids.h" +#include "fb.h" +#include "i2c.h" +#include "i2c-algo-bit.h" +//#include "radeon_theatre.h" +#include "radeon_reg.h" + +#ifndef point32_ter +#define point32_ter void* +#endif +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif + +/* Buffer are aligned on 4096 byte boundaries */ +#define RADEON_BUFFER_ALIGN 0x00000fff + +#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ +#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ +#define RADEON_MMIOSIZE 0x80000 + +#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) + +#define ATY_RADEON_LCD_ON 0x00000001 +#define ATY_RADEON_CRT_ON 0x00000002 + +#define FBIO_RADEON_GET_MIRROR 0x80044003 +#define FBIO_RADEON_SET_MIRROR 0xC0044004 + +/*************************************************************** + * Most of the definitions here are adapted right from XFree86 * + ***************************************************************/ + +/* + * Chip families. Must fit in the low 16 bits of a int32_t word + */ +enum radeon_family +{ + CHIP_FAMILY_UNKNOW, + CHIP_FAMILY_LEGACY, + CHIP_FAMILY_RADEON, + CHIP_FAMILY_RV100, + CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ + CHIP_FAMILY_RV200, + CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ + CHIP_FAMILY_R200, + CHIP_FAMILY_RV250, + CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ + CHIP_FAMILY_RV280, + CHIP_FAMILY_R300, + CHIP_FAMILY_R350, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ + CHIP_FAMILY_R420, /* R420/R423/M18 */ + CHIP_FAMILY_LAST, +}; + +#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ + ((rinfo)->family == CHIP_FAMILY_RV200) || \ + ((rinfo)->family == CHIP_FAMILY_RS100) || \ + ((rinfo)->family == CHIP_FAMILY_RS200) || \ + ((rinfo)->family == CHIP_FAMILY_RV250) || \ + ((rinfo)->family == CHIP_FAMILY_RV280) || \ + ((rinfo)->family == CHIP_FAMILY_RS300)) + + +#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ + ((rinfo)->family == CHIP_FAMILY_RV350) || \ + ((rinfo)->family == CHIP_FAMILY_R350) || \ + ((rinfo)->family == CHIP_FAMILY_RV380) || \ + ((rinfo)->family == CHIP_FAMILY_R420)) + +/* + * Chip flags + */ +enum radeon_chip_flags +{ + CHIP_FAMILY_MASK = 0x0000ffffUL, + CHIP_FLAGS_MASK = 0xffff0000UL, + CHIP_IS_MOBILITY = 0x00010000UL, + CHIP_IS_IGP = 0x00020000UL, + CHIP_HAS_CRTC2 = 0x00040000UL, +}; + +/* + * Errata workarounds + */ +enum radeon_errata +{ + CHIP_ERRATA_R300_CG = 0x00000001, + CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, + CHIP_ERRATA_PLL_DELAY = 0x00000004, +}; + + +/* + * Monitor types + */ +enum radeon_montype +{ + MT_NONE = 0, + MT_CRT, /* CRT */ + MT_LCD, /* LCD */ + MT_DFP, /* DVI */ + MT_CTV, /* composite TV */ + MT_STV /* S-Video out */ +}; + +/* + * DDC i2c ports + */ +enum ddc_type +{ + ddc_none, + ddc_monid, + ddc_dvi, + ddc_vga, + ddc_crt2, +}; + +/* + * Connector types + */ +enum conn_type +{ + conn_none, + conn_proprietary, + conn_crt, + conn_DVI_I, + conn_DVI_D, +}; + + +/* + * PLL infos + */ +struct pll_info +{ + int32_t ppll_max; + int32_t ppll_min; + int32_t sclk, mclk; + int32_t ref_div; + int32_t ref_clk; +}; + + +/* + * This structure contains the various registers manipulated by this + * driver for setting or restoring a mode. It's mostly copied from + * XFree's RADEONSaveRec structure. A few chip settings might still be + * tweaked without beeing reflected or saved in these registers though + */ +struct radeon_regs +{ + /* Common registers */ + uint32_t ovr_clr; + uint32_t ovr_wid_left_right; + uint32_t ovr_wid_top_bottom; + uint32_t ov0_scale_cntl; + uint32_t mpp_tb_config; + uint32_t mpp_gp_config; + uint32_t subpic_cntl; + uint32_t viph_control; + uint32_t i2c_cntl_1; + uint32_t gen_int32_t_cntl; + uint32_t cap0_trig_cntl; + uint32_t cap1_trig_cntl; + uint32_t bus_cntl; + uint32_t surface_cntl; + uint32_t bios_5_scratch; + + /* Other registers to save for VT switches or driver load/unload */ + uint32_t dp_datatype; + uint32_t rbbm_soft_reset; + uint32_t clock_cntl_index; + uint32_t amcgpio_en_reg; + uint32_t amcgpio_mask; + + /* Surface/tiling registers */ + uint32_t surf_lower_bound[8]; + uint32_t surf_upper_bound[8]; + uint32_t surf_info[8]; + + /* CRTC registers */ + uint32_t crtc_gen_cntl; + uint32_t crtc_ext_cntl; + uint32_t dac_cntl; + uint32_t crtc_h_total_disp; + uint32_t crtc_h_sync_strt_wid; + uint32_t crtc_v_total_disp; + uint32_t crtc_v_sync_strt_wid; + uint32_t crtc_offset; + uint32_t crtc_offset_cntl; + uint32_t crtc_pitch; + uint32_t disp_merge_cntl; + uint32_t grph_buffer_cntl; + uint32_t crtc_more_cntl; + + /* CRTC2 registers */ + uint32_t crtc2_gen_cntl; + uint32_t dac2_cntl; + uint32_t disp_output_cntl; + uint32_t disp_hw_debug; + uint32_t disp2_merge_cntl; + uint32_t grph2_buffer_cntl; + uint32_t crtc2_h_total_disp; + uint32_t crtc2_h_sync_strt_wid; + uint32_t crtc2_v_total_disp; + uint32_t crtc2_v_sync_strt_wid; + uint32_t crtc2_offset; + uint32_t crtc2_offset_cntl; + uint32_t crtc2_pitch; + + /* Flat panel regs */ + uint32_t fp_crtc_h_total_disp; + uint32_t fp_crtc_v_total_disp; + uint32_t fp_gen_cntl; + uint32_t fp2_gen_cntl; + uint32_t fp_h_sync_strt_wid; + uint32_t fp2_h_sync_strt_wid; + uint32_t fp_horz_stretch; + uint32_t fp_panel_cntl; + uint32_t fp_v_sync_strt_wid; + uint32_t fp2_v_sync_strt_wid; + uint32_t fp_vert_stretch; + uint32_t lvds_gen_cntl; + uint32_t lvds_pll_cntl; + uint32_t tmds_crc; + uint32_t tmds_transmitter_cntl; + + /* Computed values for PLL */ + uint32_t dot_clock_freq; + uint32_t pll_output_freq; + int32_t feedback_div; + int32_t post_div; + + /* PLL registers */ + uint32_t ppll_div_3; + uint32_t ppll_ref_div; + uint32_t vclk_ecp_cntl; + uint32_t clk_cntl_index; + uint32_t htotal_cntl; + + /* Computed values for PLL2 */ + uint32_t dot_clock_freq_2; + uint32_t pll_output_freq_2; + int32_t feedback_div_2; + int32_t post_div_2; + + /* PLL2 registers */ + uint32_t p2pll_ref_div; + uint32_t p2pll_div_0; + uint32_t htotal_cntl2; +}; + +struct panel_info +{ + int32_t xres, yres; + int32_t valid; + int32_t clock; + int32_t hOver_plus, hSync_width, hblank; + int32_t vOver_plus, vSync_width, vblank; + int32_t hAct_high, vAct_high, int32_terlaced; + int32_t pwr_delay; + int32_t use_bios_dividers; + int32_t ref_divider; + int32_t post_divider; + int32_t fbk_divider; +}; + +struct radeonfb_info; + +#ifdef CONFIG_FB_RADEON_I2C +struct radeon_i2c_chan +{ + struct radeonfb_info *rinfo; + uint32_t ddc_reg; + struct i2c_adapter adapter; + struct i2c_algo_bit_data algo; +}; +#endif + +enum radeon_pm_mode { + radeon_pm_none = 0, /* Nothing supported */ + radeon_pm_d2 = 0x00000001, /* Can do D2 state */ + radeon_pm_off = 0x00000002, /* Can resume from D3 cold */ +}; + +typedef struct +{ + uint8_t table_revision; + uint8_t table_size; + uint8_t tuner_type; + uint8_t audio_chip; + uint8_t product_id; + uint8_t tuner_voltage_teletext_fm; + uint8_t i2s_config; /* configuration of the sound chip */ + uint8_t video_decoder_type; + uint8_t video_decoder_host_config; + uint8_t input[5]; +} _MM_TABLE; + +struct radeonfb_info +{ + int32_t handle; /* PCI BIOS, must be 1st place */ + int32_t big_endian; /* PCI BIOS */ + + uint32_t cursor_x; + uint32_t cursor_y; + int32_t cursor_show; + uint32_t cursor_start; + uint32_t cursor_end; + int32_t cursor_fg; + int32_t cursor_bg; + + int32_t fifo_slots; /* Free slots in the FIFO (64 max) */ + + /* Computed values for Radeon */ + uint32_t dp_gui_master_cntl_clip; + uint32_t trans_color; + + /* Saved values for ScreenToScreenCopy */ + int32_t xdir; + int32_t ydir; + + /* ScanlineScreenToScreenColorExpand support */ + int32_t scanline_h; + int32_t scanline_words; + int32_t scanline_bpp; /* Only used for ImageWrite */ + + /* Saved values for DashedTwoPoint32_tLine */ + int32_t dashLen; + uint32_t dashPattern; + int32_t dash_fg; + int32_t dash_bg; + + struct fb_info *info; + + struct radeon_regs state; + struct radeon_regs init_state; + + uint8_t name[50]; + + uint32_t io_base_phys; + uint32_t mmio_base_phys; + uint32_t fb_base_phys; + + void *io_base; + void *mmio_base; + void *fb_base; + + uint32_t fb_local_base; + uint32_t fb_offset; + + uint32_t bios_seg_phys; + void *bios_seg; + int32_t fp_bios_start; + + struct + { + uint8_t red, green, blue, pad; + } palette[256]; + + int32_t chipset; + uint8_t family; + uint8_t rev; + int32_t errata; + uint32_t video_ram; + uint32_t mapped_vram; + int32_t vram_width; + int32_t vram_ddr; + + int32_t pitch, bpp, depth; + + int32_t has_CRTC2; + int32_t is_mobility; + int32_t is_IGP; + int32_t reversed_DAC; + int32_t reversed_TMDS; + struct panel_info panel_info; + int32_t mon1_type; + uint8_t *mon1_EDID; + struct fb_videomode *mon1_modedb; + int32_t mon1_dbsize; + int32_t mon2_type; + uint8_t *mon2_EDID; + + uint32_t dp_gui_master_cntl; + + struct pll_info bios_pll; + struct pll_info pll; + + uint32_t save_regs[100]; + int32_t asleep; + int32_t lock_blank; + int32_t dynclk; + int32_t no_schedule; + enum radeon_pm_mode pm_mode; + + /* Timer used for delayed LVDS operations */ + int32_t lvds_timer; + uint32_t pending_lvds_gen_cntl; + +#ifdef CONFIG_FB_RADEON_I2C + struct radeon_i2c_chan i2c[4]; +#endif + + /* Texture */ + + int32_t RenderInited3D; + int32_t tilingEnabled; + void *RenderTex; + uint32_t RenderTexOffset; + int32_t RenderTexSize; + void (*RenderCallback)(struct radeonfb_info *rinfo); + uint32_t RenderTimeout; + uint32_t dst_pitch_offset; + + +#ifdef _NOT_USED_ + /* Video & theatre */ + + TheatrePtr theatre; + + int32_t MM_TABLE_valid; + _MM_TABLE MM_TABLE; + + int32_t RageTheatreCrystal; + int32_t RageTheatreTunerPort; + int32_t RageTheatreCompositePort; + int32_t RageTheatreSVideoPort; + int32_t tunerType; + + int32_t videoStatus; + int32_t encoding; + int32_t overlay_deint32_terlacing_method; + int32_t video_stream_active; + int32_t capture_vbi_data; + int32_t v; + void *videoLinear; + int32_t videoLinearSize; + struct + { + uint32_t y,u,v; + } videoLinearOffset; +#endif /* _NOT_USED_ */ + + int32_t dec_hue; + int32_t dec_saturation; + int32_t dec_contrast; + int32_t dec_brightness; +}; + +#define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type) + +/* + * IO macros + */ + +/* Note about this function: we have some rare cases where we must not schedule, + * this typically happen with our special "wake up early" hook which allows us to + * wake up the graphic chip (and thus get the console back) before everything else + * on some machines that support that mecanism. At this point32_t, int32_terrupts are off + * and scheduling is not permitted + */ +static inline void _radeon_msleep(struct radeonfb_info *rinfo, uint32_t ms) +{ + mdelay(ms); +} + +#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) + +extern void _OUTREGP(struct radeonfb_info *rinfo, uint32_t addr, uint32_t val, uint32_t mask); +extern void radeon_pll_errata_after_index(struct radeonfb_info *rinfo); +extern void radeon_pll_errata_after_data(struct radeonfb_info *rinfo); +extern uint32_t __INPLL(struct radeonfb_info *rinfo, uint32_t addr); +extern void __OUTPLL(struct radeonfb_info *rinfo, uint32_t index, uint32_t val); +extern void __OUTPLLP(struct radeonfb_info *rinfo, uint32_t index, uint32_t val, uint32_t mask); + +extern uint16_t _swap_int16_t(uint16_t val); +extern uint32_t _swap_int32_t(uint32_t val); + +#define INREG8(addr) *((uint8_t *)(rinfo->mmio_base+addr)) +#define INREG16(addr) _swap_int16_t(*(uint16_t *)(rinfo->mmio_base+addr)) +#define INREG(addr) _swap_int32_t(*(uint32_t *)(rinfo->mmio_base+addr)) +#define OUTREG8(addr,val) (*((uint8_t *)(rinfo->mmio_base+addr)) = val) +#define OUTREG16(addr,val) (*((uint16_t *)(rinfo->mmio_base+addr)) = _swap_int16_t(val)) +#define OUTREG(addr,val) (*((uint32_t *)(rinfo->mmio_base+addr)) = _swap_int32_t(val)) + +extern int32_t *tab_funcs_pci; + +#define BIOS_IN8(v) (Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v)) +#define BIOS_IN16(v) ((uint16_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v) | \ + ((uint16_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+1) << 8)) +#define BIOS_IN32(v) ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v) | \ + ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+1) << 8) | \ + ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+2) << 16) | \ + ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+3) << 24)) + +#define ADDRREG(addr) ((volatile uint32_t *)(rinfo->mmio_base + (addr))) +#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val, mask) +#define INPLL(addr) __INPLL(rinfo, addr) +#define OUTPLL(index,val) __OUTPLL(rinfo, index, val) +#define OUTPLLP(index,val,mask) __OUTPLLP(rinfo, index, val, mask) + +/* + * Inline utilities + */ + +static inline uint32_t radeon_get_dstbpp(uint16_t depth) +{ + switch(depth) + { + case 8: return DST_8BPP; + case 15: return DST_15BPP; + case 16: return DST_16BPP; + case 32: return DST_32BPP; + default: return 0; + } +} + +/* I2C Functions */ +extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo); +extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo); +extern int32_t radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int32_t conn, uint8_t **out_edid); + +/* PM Functions */ +/* extern int32_t radeonfb_pci_suspend(struct pci_dev *pdev, uint32_t state); +extern int32_t radeonfb_pci_resume(struct pci_dev *pdev); */ +extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int32_t dynclk); +extern void radeonfb_pm_exit(struct radeonfb_info *rinfo); + +/* Monitor probe functions */ +extern void radeon_probe_screens(struct radeonfb_info *rinfo, + const uint8_t *monitor_layout, int32_t ignore_edid); +extern void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolution); +extern int32_t radeon_match_mode(struct radeonfb_info *rinfo, + struct fb_var_screeninfo *dest, + const struct fb_var_screeninfo *src); + +/* Video functions */ +void RADEONResetVideo(struct radeonfb_info *rinfo); +int32_t RADEONVIP_read(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer); +int32_t RADEONVIP_fifo_read(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer); +int32_t RADEONVIP_write(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer); +int32_t RADEONVIP_fifo_write(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer); +void RADEONVIP_reset(struct radeonfb_info *rinfo); + +void RADEONInitVideo(struct radeonfb_info *rinfo); +void RADEONShutdownVideo(struct radeonfb_info *rinfo); +int32_t RADEONPutVideo(struct radeonfb_info *rinfo, int32_t src_x, int32_t src_y, int32_t src_w, int32_t src_h, + int32_t drw_x, int32_t drw_y, int32_t drw_w, int32_t drw_h); +void RADEONStopVideo(struct radeonfb_info *rinfo, int32_t cleanup); + +/* Theatre functions */ +//extern TheatrePtr DetectTheatre(struct radeonfb_info *rinfo); +//extern void RT_SetTint32_t(TheatrePtr t, int32_t hue); +//extern void RT_SetSaturation(TheatrePtr t, int32_t Saturation); +//extern void RT_SetBrightness(TheatrePtr t, int32_t Brightness); +//extern void RT_SetSharpness(TheatrePtr t, uint16_t wSharpness); +//extern void RT_SetContrast(TheatrePtr t, int32_t Contrast); +//extern void RT_SetInterlace(TheatrePtr t, uint8_t bInterlace); +//extern void RT_SetStandard(TheatrePtr t, uint16_t wStandard); +//extern void RT_SetCombFilter(TheatrePtr t, uint16_t wStandard, uint16_t wConnector); +//extern void RT_SetOutputVideoSize(TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On); +//extern void RT_SetConnector(TheatrePtr t, uint16_t wConnector, int32_t tunerFlag); +//extern void InitTheatre(TheatrePtr t); +//extern void ShutdownTheatre(TheatrePtr t); +//extern void ResetTheatreRegsForNoTVout(TheatrePtr t); +//extern void ResetTheatreRegsForTVout(TheatrePtr t); +extern void RADEONVIP_reset(struct radeonfb_info *rinfo); + +/* Accel functions */ + +extern void RADEONWaitForFifoFunction(struct radeonfb_info *rinfo, int32_t entries); +extern void RADEONEngineFlush(struct radeonfb_info *rinfo); +extern void RADEONEngineReset(struct radeonfb_info *rinfo); +extern void RADEONEngineRestore(struct radeonfb_info *rinfo); +extern void RADEONEngineInit(struct radeonfb_info *rinfo); +extern void RADEONWaitForIdleMMIO(struct radeonfb_info *rinfo); + +#define RADEONWaitForFifo(rinfo, entries) \ +do { \ + if(rinfo->fifo_slots < entries) \ + RADEONWaitForFifoFunction(rinfo, entries); \ + rinfo->fifo_slots -= entries; \ +} while(0) + +#define radeon_fifo_wait(entries) RADEONWaitForFifo(rinfo, entries) +#define radeon_engine_flush(rinfo) RADEONEngineFlush(rinfo) +#define radeonfb_engine_reset(rinfo) RADEONEngineReset(rinfo) +#define radeonfb_engine_init(rinfo) RADEONEngineInit(rinfo) +#define radeon_engine_idle() RADEONWaitForIdleMMIO(rinfo) + +static inline int32_t radeonfb_sync(struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + radeon_engine_idle(); + return 0; +} + +extern void RADEONRestoreAccelStateMMIO(struct fb_info *info); +extern void RADEONSetupForSolidFillMMIO(struct fb_info *info, int32_t color, int32_t rop, int32_t planemask); +extern void RADEONSubsequentSolidFillRectMMIO(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h); +extern void RADEONSetupForSolidLineMMIO(struct fb_info *info, int32_t color, int32_t rop, int32_t planemask); +extern void RADEONSubsequentSolidHorVertLineMMIO(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir); + +extern void RADEONSubsequentSolidTwoPointLineMMIO(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, + int32_t yb, int32_t flags); +extern void RADEONSetupForDashedLineMMIO(struct fb_info *info, int32_t fg, int32_t bg, + int32_t rop, int32_t planemask, int32_t length, uint8_t *pattern); +extern void RADEONSubsequentDashedTwoPointLineMMIO(struct fb_info *info, + int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase); +extern void RADEONSetupForScreenToScreenCopyMMIO(struct fb_info *info, + int32_t xdir, int32_t ydir, int32_t rop, int32_t planemask, int32_t trans_color); +extern void RADEONSubsequentScreenToScreenCopyMMIO(struct fb_info *info, + int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h); +extern void RADEONScreenToScreenCopyMMIO(struct fb_info *info, + int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop); +extern void RADEONSetupForMono8x8PatternFillMMIO(struct fb_info *info, + int32_t patternx, int32_t patterny, int32_t fg, int32_t bg, int32_t rop, int32_t planemask); +extern void RADEONSubsequentMono8x8PatternFillRectMMIO(struct fb_info *info, + int32_t patternx, int32_t patterny, int32_t x, int32_t y, int32_t w, int32_t h); +extern void RADEONSetupForScanlineCPUToScreenColorExpandFillMMIO(struct fb_info *info, + int32_t fg, int32_t bg, int32_t rop, int32_t planemask); +extern void RADEONSubsequentScanlineCPUToScreenColorExpandFillMMIO(struct fb_info *info, + int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft); +extern void RADEONSubsequentScanlineMMIO(struct fb_info *info, uint32_t *buf); +extern void RADEONSetupForScanlineImageWriteMMIO(struct fb_info *info, + int32_t rop, int32_t planemask, int32_t trans_color, int32_t bpp); +extern void RADEONSubsequentScanlineImageWriteRectMMIO(struct fb_info *info, + int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft); +extern void RADEONSetClippingRectangleMMIO(struct fb_info *info, + int32_t xa, int32_t ya, int32_t xb, int32_t yb); +extern void RADEONDisableClippingMMIO(struct fb_info *info); + +#ifndef MCF5445X +extern int32_t RADEONSetupForCPUToScreenAlphaTextureMMIO(struct fb_info *info, + int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha, uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch, int32_t width, int32_t height, int32_t flags); +extern int32_t RADEONSetupForCPUToScreenTextureMMIO(struct fb_info *info, + int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags); +extern void RADEONSubsequentCPUToScreenTextureMMIO(struct fb_info *info, + int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height); +#else +static __inline__ int32_t RADEONSetupForCPUToScreenAlphaTextureMMIO(struct fb_info *info, + int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha, uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch, int32_t width, int32_t height, int32_t flags) +{ return FALSE; } +static __inline__ int32_t RADEONSetupForCPUToScreenTextureMMIO(struct fb_info *info, + int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags) +{ return FALSE; } +static __inline__ void RADEONSubsequentCPUToScreenTextureMMIO(struct fb_info *info, + int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height) { } +#endif /* MCF5445X */ + +/* Cursor functions */ +extern void RADEONSetCursorColors(struct fb_info *info, int32_t bg, int32_t fg); +extern void RADEONSetCursorPosition(struct fb_info *info, int32_t x, int32_t y); +extern void RADEONLoadCursorImage(struct fb_info *info, uint16_t *mask, uint16_t *data, int32_t zoom); +extern void RADEONHideCursor(struct fb_info *info); +extern void RADEONShowCursor(struct fb_info *info); +extern int32_t RADEONCursorInit(struct fb_info *info); + +/* Other functions */ +extern int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t mode_switch); +extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t reg_only); +int32_t radeonfb_setcolreg(uint32_t regno, uint32_t red, uint32_t green, + uint32_t blue, uint32_t transp, struct fb_info *info); +extern int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent); +extern void radeonfb_pci_unregister(void); + +/* global */ +extern uint8_t monitor_layout[]; +extern int16_t default_dynclk; +extern int16_t ignore_edid; +extern int16_t mirror; +extern int16_t virtual; +extern int16_t force_measure_pll; +extern int16_t zoom_mouse; + +#endif /* __RADEONFB_H__ */ diff --git a/BaS_gcc/include/videl.h b/BaS_gcc/include/videl.h index 8c4bf4c..61b2063 100644 --- a/BaS_gcc/include/videl.h +++ b/BaS_gcc/include/videl.h @@ -75,23 +75,23 @@ typedef struct { uint16_t vss; /* V SS */ } VMODE_ENTRY; -void initialise_falcon_palette(int16_t mode); -const VMODE_ENTRY *lookup_videl_mode(int16_t mode,int16_t monitor); +extern void initialise_falcon_palette(int16_t mode); +extern const VMODE_ENTRY *lookup_videl_mode(int16_t mode,int16_t monitor); /* Public XBIOS functions */ -int16_t vsetmode(int16_t mode); -int16_t vmontype(void); -int16_t vsetsync(int16_t external); -int32_t vgetsize(int16_t mode); -int16_t vsetrgb(int16_t index,int16_t count,int32_t *rgb); -int16_t vgetrgb(int16_t index,int16_t count,int32_t *rgb); +extern int16_t vsetmode(int16_t mode); +extern int16_t vmontype(void); +extern int16_t vsetsync(int16_t external); +extern int32_t vgetsize(int16_t mode); +extern int16_t vsetrgb(int16_t index,int16_t count,int32_t *rgb); +extern int16_t vgetrgb(int16_t index,int16_t count,int32_t *rgb); /* misc routines */ -int16_t get_videl_mode(void); -int16_t vfixmode(int16_t mode); -int16_t videl_check_moderez(int16_t moderez); -uint32_t videl_vram_size(void); -void videl_get_current_mode_info(uint16_t *planes, uint16_t *hz_rez, uint16_t *vt_rez); +extern int16_t get_videl_mode(void); +extern int16_t vfixmode(int16_t mode); +extern int16_t videl_check_moderez(int16_t moderez); +extern uint32_t videl_vram_size(void); +extern void videl_get_current_mode_info(uint16_t *planes, uint16_t *hz_rez, uint16_t *vt_rez); extern int16_t current_video_mode; diff --git a/BaS_gcc/net/arp.c b/BaS_gcc/net/arp.c index e9669e1..0b3caf0 100644 --- a/BaS_gcc/net/arp.c +++ b/BaS_gcc/net/arp.c @@ -9,7 +9,7 @@ #include #include -#define TIMER_NETWORK 0 +#define TIMER_NETWORK 3 static uint8_t *arp_find_pair(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa) { diff --git a/BaS_gcc/net/bootp.c b/BaS_gcc/net/bootp.c index 3858299..419eba2 100644 --- a/BaS_gcc/net/bootp.c +++ b/BaS_gcc/net/bootp.c @@ -11,7 +11,7 @@ #include #include "bas_printf.h" -#define TIMER_NETWORK 0 +#define TIMER_NETWORK 3 static struct bootp_connection connection; #define XID 0x1234 /* this is arbitrary */ diff --git a/BaS_gcc/net/nbuf.c b/BaS_gcc/net/nbuf.c index 8419770..1b6fc28 100644 --- a/BaS_gcc/net/nbuf.c +++ b/BaS_gcc/net/nbuf.c @@ -41,7 +41,7 @@ int nbuf_init(void) } #ifdef DEBUG_PRINT - printf("Creating %d net buffers of %d bytes\n",NBUF_MAX,NBUF_SZ); + printf("Creating %d net buffers of %d bytes\r\n",NBUF_MAX,NBUF_SZ); #endif for (i = 0; i < NBUF_MAX; ++i) @@ -70,7 +70,7 @@ int nbuf_init(void) queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf); } - xprintf("NBUF allocation complete\n"); + xprintf("NBUF allocation complete\r\n"); return 0; } diff --git a/BaS_gcc/net/nif.c b/BaS_gcc/net/nif.c index a2d6194..545daa7 100644 --- a/BaS_gcc/net/nif.c +++ b/BaS_gcc/net/nif.c @@ -50,7 +50,7 @@ void nif_protocol_handler(NIF *nif, uint16_t protocol, NBUF *pNbuf) } } -void *nif_get_protocol_info (NIF *nif, uint16_t protocol) +void *nif_get_protocol_info(NIF *nif, uint16_t protocol) { /* * This function searches the list of supported protocols @@ -67,9 +67,8 @@ void *nif_get_protocol_info (NIF *nif, uint16_t protocol) return (void *)0; } -int nif_bind_protocol (NIF *nif, uint16_t protocol, - void (*handler)(NIF *,NBUF *), - void *info) +int nif_bind_protocol(NIF *nif, uint16_t protocol, void (*handler)(NIF *,NBUF *), + void *info) { /* * This function registers 'protocol' as a supported diff --git a/BaS_gcc/net/tftp.c b/BaS_gcc/net/tftp.c index 89022b4..43b85f2 100644 --- a/BaS_gcc/net/tftp.c +++ b/BaS_gcc/net/tftp.c @@ -18,7 +18,7 @@ #include "net.h" #include "net_timer.h" -#define TIMER_NETWORK 0 +#define TIMER_NETWORK 3 /* The one and only TFTP connection */ static TFTP_Connection tcxn; diff --git a/BaS_gcc/net/udp.c b/BaS_gcc/net/udp.c index 25c9428..b12f201 100644 --- a/BaS_gcc/net/udp.c +++ b/BaS_gcc/net/udp.c @@ -135,10 +135,8 @@ int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf) /* Add the length of the UDP packet to the total length of the packet */ pNbuf->length += 8; - return (ip_send(nif, dest, - ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP)), - IP_PROTO_UDP, - pNbuf)); + return (ip_send(nif, dest, ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP)), + IP_PROTO_UDP, pNbuf)); } void udp_handler(NIF *nif, NBUF *pNbuf) diff --git a/BaS_gcc/radeon/radeon_base.c b/BaS_gcc/radeon/radeon_base.c new file mode 100644 index 0000000..0003bf1 --- /dev/null +++ b/BaS_gcc/radeon/radeon_base.c @@ -0,0 +1,2260 @@ +/* + * radeon_base.c + * + * framebuffer driver for ATI Radeon chipset video boards + * + * Copyright 2003 Ben. Herrenschmidt + * Copyright 2000 Ani Joshi + * + * i2c bits from Luca Tettamanti + * + * Special thanks to ATI DevRel team for their hardware donations. + * + * ...Insert GPL boilerplate here... + * + * Significant portions of this driver apdated from XFree86 Radeon + * driver which has the following copyright notice: + * + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * XFree86 driver authors: + * + * Kevin E. Martin + * Rickard E. Faith + * Alan Hourihane + * + */ + +#define RADEON_VERSION "0.2.0" + +#include "fb.h" +#include "i2c.h" +#include "pci.h" +#include "radeonfb.h" +#include "edid.h" +#include "ati_ids.h" + +#ifdef DRIVER_IN_ROM +extern void run_bios(struct radeonfb_info *rinfo); +#endif +extern void mdelay(int32_t msec); +extern void udelay(int32_t usec); + +#define MAX_MAPPED_VRAM (2048*2048*4) +#define MIN_MAPPED_VRAM (1024*768*4) + +#define CHIP_DEF(id, family, flags) \ + { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) } + +struct pci_device_id radeonfb_pci_table[] = +{ + /* Mobility M6 */ + CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + /* Radeon VE/7000 */ + CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2), + /* Radeon IGP320M (U1) */ + CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), + /* Radeon IGP320 (A3) */ + CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP), + /* IGP330M/340M/350M (U2) */ + CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), + /* IGP330/340/350 (A4) */ + CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), + /* Mobility 7000 IGP */ + CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), + /* 7000 IGP (A4+) */ + CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), + /* 8500 AIW */ + CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2), + /* 8700/8800 */ + CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2), + /* 8500 */ + CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2), + /* 9100 */ + CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2), + /* Mobility M7 */ + CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + /* 7500 */ + CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2), + /* Mobility M9 */ + CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + /* 9000/Pro */ + CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2), + /* Mobility 9100 IGP (U3) */ + CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), + /* 9100 IGP (A5) */ + CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), + CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), + /* Mobility 9200 (M9+) */ + CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + /* 9200 */ + CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2), + /* 9500 */ + CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2), + /* 9600TX / FireGL Z1 */ + CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2), + /* 9700/9500/Pro/FireGL X1 */ + CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2), + /* Mobility M10/M11 */ + CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + /* 9600/FireGL T2 */ + CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2), + /* 9800/Pro/FileGL X2 */ + CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2), + /* Newer stuff */ + CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), + CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2), + CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2), + /* Original Radeon/7200 */ + CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0), + CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0), + CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0), + CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0), + { 0, 0, 0, 0, 0, 0, 0 } +}; + + +typedef struct +{ + uint16_t reg; + uint32_t val; +} reg_val; + + +/* these common regs are cleared before mode setting so they do not + * interfere with anything + */ +static reg_val common_regs[] = { + { OVR_CLR, 0 }, + { OVR_WID_LEFT_RIGHT, 0 }, + { OVR_WID_TOP_BOTTOM, 0 }, + { OV0_SCALE_CNTL, 0 }, + { SUBPIC_CNTL, 0 }, + { VIPH_CONTROL, 0 }, + { I2C_CNTL_1, 0 }, + { GEN_INT_CNTL, 0 }, + { CAP0_TRIG_CNTL, 0 }, + { CAP1_TRIG_CNTL, 0 }, +}; + +#define rinfo ((struct radeonfb_info *)info_fvdi->par) + +static uint32_t inreg(uint32_t addr) +{ + return(INREG(addr)); +} + +static void outreg(uint32_t addr, uint32_t val) +{ + OUTREG(addr,val); +} + +#undef rinfo +#undef INREG +#define INREG inreg +#undef OUTREG +#define OUTREG outreg + +void _OUTREGP(struct radeonfb_info *rinfo, uint32_t addr, uint32_t val, uint32_t mask) +{ + uint32_t tmp; + tmp = INREG(addr); + tmp &= (mask); + tmp |= (val); + OUTREG(addr, tmp); +} + +/* + * Note about PLL register accesses: + * + * I have removed the spinlock on them on purpose. The driver now + * expects that it will only manipulate the PLL registers in normal + * task environment, where radeon_msleep() will be called, protected + * by a semaphore (currently the console semaphore) so that no conflict + * will happen on the PLL register index. + * + * With the latest changes to the VT layer, this is guaranteed for all + * calls except the actual drawing/blits which aren't supposed to use + * the PLL registers anyway + * + * This is very important for the workarounds to work properly. The only + * possible exception to this rule is the call to unblank(), which may + * be done at irq time if an oops is in progress. + */ +void radeon_pll_errata_after_index(struct radeonfb_info *rinfo) +{ + if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS)) + return; + (void)INREG(CLOCK_CNTL_DATA); + (void)INREG(CRTC_GEN_CNTL); +} + +void radeon_pll_errata_after_data(struct radeonfb_info *rinfo) +{ + if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) + { + /* we can't deal with posted writes here ... */ + radeon_msleep(5); + } + + if (rinfo->errata & CHIP_ERRATA_R300_CG) + { + uint32_t save, tmp; + save = INREG(CLOCK_CNTL_INDEX); + tmp = save & ~(0x3f | PLL_WR_EN); + OUTREG(CLOCK_CNTL_INDEX, tmp); + tmp = INREG(CLOCK_CNTL_DATA); + OUTREG(CLOCK_CNTL_INDEX, save); + } +} + +uint32_t __INPLL(struct radeonfb_info *rinfo, uint32_t addr) +{ + uint32_t data; + + OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); + radeon_pll_errata_after_index(rinfo); + data = INREG(CLOCK_CNTL_DATA); + radeon_pll_errata_after_data(rinfo); + return data; +} + +void __OUTPLL(struct radeonfb_info *rinfo, uint32_t index, uint32_t val) +{ + OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); + radeon_pll_errata_after_index(rinfo); + OUTREG(CLOCK_CNTL_DATA, val); + radeon_pll_errata_after_data(rinfo); +} + +void __OUTPLLP(struct radeonfb_info *rinfo, uint32_t index, uint32_t val, uint32_t mask) +{ + uint32_t tmp; + + tmp = __INPLL(rinfo, index); + tmp &= (mask); + tmp |= (val); + __OUTPLL(rinfo, index, tmp); +} + +static int round_div(int num, int den) +{ + return(num + (den / 2)) / den; +} + +#ifndef MCF5445X +static uint32_t read_vline_crnt(struct radeonfb_info *rinfo) +{ + return((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3FF); +} +#endif + +static int radeon_map_ROM(struct radeonfb_info *rinfo) +{ + uint16_t dptr; + uint8_t rom_type; + + /* If this is a primary card, there is a shadow copy of the + * ROM somewhere in the first meg. We will just ignore the copy + * and use the ROM directly. + */ + /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */ + + uint32_t temp; + + temp = INREG(MPP_TB_CONFIG); + temp &= 0x00ffffffu; + temp |= 0x04 << 24; + OUTREG(MPP_TB_CONFIG, temp); + temp = INREG(MPP_TB_CONFIG); + if (rinfo->bios_seg == NULL) + { + DPRINT("radeonfb: ROM failed to map\r\n"); + return -1; + } + + /* Very simple test to make sure it appeared */ + if (BIOS_IN16(0) != 0xaa55) + { + DPRINT("radeonfb: Invalid ROM signature"); + goto failed; + } + + /* Look for the PCI data to check the ROM type */ + dptr = BIOS_IN16(0x18); + + /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM + * for now, until I've verified this works everywhere. The goal here is more + * to phase out Open Firmware images. + * + * Currently, we only look at the first PCI data, we could iteratre and deal with + * them all, and we should use fb_bios_start relative to start of image and not + * relative start of ROM, but so far, I never found a dual-image ATI card + * + * typedef struct { + * u32 signature; + 0x00 + * u16 vendor; + 0x04 + * u16 device; + 0x06 + * u16 reserved_1; + 0x08 + * u16 dlen; + 0x0a + * u8 drevision; + 0x0c + * u8 class_hi; + 0x0d + * u16 class_lo; + 0x0e + * u16 ilen; + 0x10 + * u16 irevision; + 0x12 + * u8 type; + 0x14 + * u8 indicator; + 0x15 + * u16 reserved_2; + 0x16 + * } pci_data_t; + */ + if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) + { + DPRINTVALHEX("radeonfb: PCI DATA signature in ROM incorrect: ", BIOS_IN32(dptr)); + DPRINT("\r\n"); + goto anyway; + } + rom_type = BIOS_IN8(dptr + 0x14); + switch(rom_type) + { + case 0: + DPRINT("radeonfb: Found Intel x86 BIOS ROM Image\r\n"); + break; + case 1: + DPRINT("radeonfb: Found Open Firmware ROM Image\r\n"); + goto failed; + case 2: + DPRINT("radeonfb: Found HP PA-RISC ROM Image\r\n"); + goto failed; + default: + DPRINTVAL("radeonfb: Found unknown type ", rom_type); + DPRINT(" ROM Image\r\n"); + goto failed; + } +anyway: + /* Locate the flat panel infos, do some sanity checking !!! */ + rinfo->fp_bios_start = BIOS_IN16(0x48); + +// DPRINTVALHEX("radeonfb: BIOS start offset: ", BIOS_IN16(0x48)); +// DPRINT("\r\n"); + +#ifdef DRIVER_IN_ROM // problem if BIOS ROM is invalid after run_bios() + /* Save BIOS PLL informations */ + { + uint16_t pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); + +// DPRINTVALHEX("radeonfb: BIOS PLL info block offset: ", BIOS_IN16(rinfo->fp_bios_start + 0x30)); +// DPRINT("\r\n"); + rinfo->bios_pll.sclk = BIOS_IN16(pll_info_block + 0x08); + rinfo->bios_pll.mclk = BIOS_IN16(pll_info_block + 0x0a); + rinfo->bios_pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); + rinfo->bios_pll.ref_div = BIOS_IN16(pll_info_block + 0x10); + rinfo->bios_pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); + rinfo->bios_pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); + } +#endif + return 0; + +failed: + rinfo->bios_seg = NULL; + return -1; //-ENXIO; +} + +/* + * Read PLL infos from chip registers + */ +static int radeon_probe_pll_params(struct radeonfb_info *rinfo) +{ +#ifdef MCF5445X /* MCF5445X has mo FPU */ + if (rinfo); + return(-1); /* to do ... */ +#else /* MCF548X or ATARI */ + uint8_t ppll_div_sel; + unsigned Ns, Nm, M; + unsigned sclk, mclk, tmp, ref_div; + int hTotal, vTotal, num, denom, m, n; + double hz, vclk; + int32_t xtal; + uint32_t start_tv, stop_tv; + int timeout=0; + + /* + * Ugh, we cut interrupts, bad bad bad, but we want some precision + * here, so... --BenH + */ + DPRINT("radeonfb: radeon_probe_pll_params\r\n"); + + /* Flush PCI buffers ? */ + tmp = INREG16(DEVICE_ID); + +#ifdef __mcoldfire__ + asm volatile ( + " move.l D0,-(SP)\n\t" + " move.w SR,D0\n\t" + " move.w D0,save_d0\n\t" + " or.l #0x700,D0\n\t" /* disable interrupts */ + " move.w D0,SR\n\t" + " move.l (SP)+,D0\n\t" ); +#else + asm volatile ( + " move.w SR,save_d0\n\t" + " or.w #0x700,SR\n\t" ); /* disable interrupts */ +#endif + + start_tv = get_timer(); + while(read_vline_crnt(rinfo) != 0) + { + if ((get_timer() - start_tv) > US_TO_TIMER(10000000UL)) /* 10 sec */ + { + timeout=1; + break; + } + } + + if (!timeout) + { + start_tv = get_timer(); + while(read_vline_crnt(rinfo) == 0) + { + if ((get_timer() - start_tv) > US_TO_TIMER(1000000UL)) /* 1 sec */ + { + timeout=1; + break; + } + } + if (!timeout) + { + while(read_vline_crnt(rinfo) != 0) + { + if ((get_timer() - start_tv) > US_TO_TIMER(10000000UL)) /* 10 sec */ + { + timeout=1; + break; + } + } + } + } + stop_tv = get_timer(); + +#ifdef __mcoldfire__ + asm volatile ( + " move.w D0,-(SP)\n\t" + " move.w save_d0,D0\n\t" + " move.w D0,SR\n\t" + " move.w (SP)+,D0\n\t" ); + if (timeout) /* 10 sec */ + return -1; /* error */ +#else + asm volatile ( + "move.w save_d0,SR\n\t" ); + if (timeout) /* 10 sec */ + return -1; /* error */ +#endif + + hz = US_TO_TIMER(1000000.0) / (double)(stop_tv - start_tv); + DPRINTVAL("radeonfb: radeon_probe_pll_params hz ", (int32_t)hz); + hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; + vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1); + DPRINTVAL(" hTotal ",hTotal); + DPRINTVAL(" vTotal ",vTotal); + vclk = (double)hTotal * (double)vTotal * hz; + DPRINTVAL(" vclk ", (int32_t)vclk); + DPRINT("\r\n"); + switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) + { + case 1: + n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff); + m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); + num = 2*n; + denom = 2*m; + break; + case 2: + n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff); + m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); + num = 2*n; + denom = 2*m; + break; + case 0: + default: + num = 1; + denom = 1; + break; + } + ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; + radeon_pll_errata_after_index(rinfo); + n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff); + m = (INPLL(PPLL_REF_DIV) & 0x3ff); + num *= n; + denom *= m; + switch((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) + { + case 1: + denom *= 2; + break; + case 2: + denom *= 4; + break; + case 3: + denom *= 8; + break; + case 4: + denom *= 3; + break; + case 6: + denom *= 6; + break; + case 7: + denom *= 12; + break; + } + vclk *= (double)denom; + vclk /= (double)(1000 * num); + xtal = (int32_t)vclk; + if ((xtal > 26900) && (xtal < 27100)) + xtal = 2700; /* 27 MHz */ + else if ((xtal > 14200) && (xtal < 14400)) + xtal = 1432; + else if ((xtal > 29400) && (xtal < 29600)) + xtal = 2950; + else + { + DPRINTVAL("radeonfb: xtal calculation failed: ",xtal); + DPRINT("\r\n"); + return -1; /* error */ + } + tmp = INPLL(M_SPLL_REF_FB_DIV); + ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; + Ns = (tmp & 0xff0000) >> 16; + Nm = (tmp & 0xff00) >> 8; + M = (tmp & 0xff); + sclk = round_div((2 * Ns * xtal), (2 * M)); + mclk = round_div((2 * Nm * xtal), (2 * M)); + /* we're done, hopefully these are sane values */ + rinfo->pll.ref_clk = xtal; + rinfo->pll.ref_div = ref_div; + rinfo->pll.sclk = sclk; + rinfo->pll.mclk = mclk; + return 0; +#endif /* MCF5445X */ +} + +/* + * Retreive PLL infos by register probing... + */ +static void radeon_get_pllinfo(struct radeonfb_info *rinfo) +{ + /* + * In the case nothing works, these are defaults; they are mostly + * incomplete, however. It does provide ppll_max and _min values + * even for most other methods, however. + */ + DPRINT("radeonfb: radeon_get_pllinfo\r\n"); + switch(rinfo->chipset) + { + case PCI_DEVICE_ID_ATI_RADEON_QW: + case PCI_DEVICE_ID_ATI_RADEON_QX: + rinfo->pll.ppll_max = 35000; + rinfo->pll.ppll_min = 12000; + rinfo->pll.mclk = 23000; + rinfo->pll.sclk = 23000; + rinfo->pll.ref_clk = 2700; + break; + case PCI_DEVICE_ID_ATI_RADEON_QL: + case PCI_DEVICE_ID_ATI_RADEON_QN: + case PCI_DEVICE_ID_ATI_RADEON_QO: + case PCI_DEVICE_ID_ATI_RADEON_Ql: + case PCI_DEVICE_ID_ATI_RADEON_BB: + rinfo->pll.ppll_max = 35000; + rinfo->pll.ppll_min = 12000; + rinfo->pll.mclk = 27500; + rinfo->pll.sclk = 27500; + rinfo->pll.ref_clk = 2700; + break; + case PCI_DEVICE_ID_ATI_RADEON_Id: + case PCI_DEVICE_ID_ATI_RADEON_Ie: + case PCI_DEVICE_ID_ATI_RADEON_If: + case PCI_DEVICE_ID_ATI_RADEON_Ig: + rinfo->pll.ppll_max = 35000; + rinfo->pll.ppll_min = 12000; + rinfo->pll.mclk = 25000; + rinfo->pll.sclk = 25000; + rinfo->pll.ref_clk = 2700; + break; + case PCI_DEVICE_ID_ATI_RADEON_ND: + case PCI_DEVICE_ID_ATI_RADEON_NE: + case PCI_DEVICE_ID_ATI_RADEON_NF: + case PCI_DEVICE_ID_ATI_RADEON_NG: + rinfo->pll.ppll_max = 40000; + rinfo->pll.ppll_min = 20000; + rinfo->pll.mclk = 27000; + rinfo->pll.sclk = 27000; + rinfo->pll.ref_clk = 2700; + break; + case PCI_DEVICE_ID_ATI_RADEON_QD: + case PCI_DEVICE_ID_ATI_RADEON_QE: + case PCI_DEVICE_ID_ATI_RADEON_QF: + case PCI_DEVICE_ID_ATI_RADEON_QG: + default: + rinfo->pll.ppll_max = 35000; + rinfo->pll.ppll_min = 12000; + rinfo->pll.mclk = 16600; + rinfo->pll.sclk = 16600; + rinfo->pll.ref_clk = 2700; + break; + } + rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; + /* + * Check out if we have an X86 which gave us some PLL informations + * and if yes, retreive them + */ + if (!force_measure_pll && (rinfo->bios_seg != NULL)) + { +#ifdef DRIVER_IN_ROM // problem if BIOS ROM is invalid after run_bios() + rinfo->pll.sclk = rinfo->bios_pll.sclk; + rinfo->pll.mclk = rinfo->bios_pll.mclk; + rinfo->pll.ref_clk = rinfo->bios_pll.ref_clk; + rinfo->pll.ref_div = rinfo->bios_pll.ref_div; + rinfo->pll.ppll_min = rinfo->bios_pll.ppll_min; + rinfo->pll.ppll_max = rinfo->bios_pll.ppll_max; +#else + uint16_t pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); + rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); + rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); + rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); + rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); + rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); + rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); +#endif + DPRINT("radeonfb: Retreived PLL infos from BIOS\r\n"); + goto found; + } + /* + * We didn't get PLL parameters from either OF or BIOS, we try to + * probe them + */ + if (radeon_probe_pll_params(rinfo) == 0) + { + DPRINT("radeonfb: Retreived PLL infos from registers\r\n"); + goto found; + } + /* + * Fall back to already-set defaults... + */ + DPRINT("radeonfb: Used default PLL infos\r\n"); +found: + /* + * Some methods fail to retreive SCLK and MCLK values, we apply default + * settings in this case (200Mhz). If that really happne often, we could + * fetch from registers instead... + */ + if (rinfo->pll.mclk == 0) + rinfo->pll.mclk = 20000; + if (rinfo->pll.sclk == 0) + rinfo->pll.sclk = 20000; + DPRINTVAL("radeonfb: Reference=",rinfo->pll.ref_clk / 100); + DPRINTVAL(" MHz (RefDiv=",rinfo->pll.ref_div); + DPRINTVAL(") Memory=",rinfo->pll.mclk / 100); + DPRINTVAL(" Mhz, System=",rinfo->pll.sclk / 100); + DPRINT(" MHz\r\n"); + DPRINTVAL("radeonfb: PLL min ",rinfo->pll.ppll_min); + DPRINTVAL(" max ", rinfo->pll.ppll_max); + DPRINT("\r\n"); +} + +static int var_to_depth(const struct fb_var_screeninfo *var) +{ + if (var->bits_per_pixel != 16) + return var->bits_per_pixel; + return(var->green.length == 5) ? 15 : 16; +} + +int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + struct fb_var_screeninfo v; + int nom, den; + uint32_t pitch; +// DPRINT("radeonfb: radeonfb_check_var\r\n"); + /* clocks over 135 MHz have heat isues with DVI on RV100 */ + if ((rinfo->mon1_type == MT_DFP) && (rinfo->family == CHIP_FAMILY_RV100) && ((100000000 / var->pixclock) > 13500)) + { + DPRINTVAL("radeonfb: mode ",var->xres); + DPRINTVAL("x",var->yres); + DPRINTVAL("x",var->bits_per_pixel); + DPRINT(" rejected, RV100 DVI clock over 135 MHz\r\n"); + + return -1; //-EINVAL; + } + + if (radeon_match_mode(rinfo, &v, var)) + return -1; //-EINVAL; + + switch (v.bits_per_pixel) + { + case 0 ... 8: + v.bits_per_pixel = 8; + break; + case 9 ... 16: + v.bits_per_pixel = 16; + break; +#if 0 /* Doesn't seem to work */ + case 17 ... 24: + v.bits_per_pixel = 24; + break; +#endif + case 25 ... 32: + v.bits_per_pixel = 32; + break; + default: + return -1; //-EINVAL; + } + + switch (var_to_depth(&v)) + { + case 8: + nom = den = 1; + v.red.offset = v.green.offset = v.blue.offset = 0; + v.red.length = v.green.length = v.blue.length = 8; + v.transp.offset = v.transp.length = 0; + break; + case 15: + nom = 2; + den = 1; + v.red.offset = 10; + v.green.offset = 5; + v.blue.offset = 0; + v.red.length = v.green.length = v.blue.length = 5; + v.transp.offset = v.transp.length = 0; + break; + case 16: + nom = 2; + den = 1; + v.red.offset = 11; + v.green.offset = 5; + v.blue.offset = 0; + v.red.length = 5; + v.green.length = 6; + v.blue.length = 5; + v.transp.offset = v.transp.length = 0; + break; + case 24: + nom = 4; + den = 1; + v.red.offset = 16; + v.green.offset = 8; + v.blue.offset = 0; + v.red.length = v.blue.length = v.green.length = 8; + v.transp.offset = v.transp.length = 0; + break; + case 32: + nom = 4; + den = 1; + v.red.offset = 16; + v.green.offset = 8; + v.blue.offset = 0; + v.red.length = v.blue.length = v.green.length = 8; + v.transp.offset = 24; + v.transp.length = 8; + break; + default: + DPRINTVAL("radeonfb: mode ",var->xres); + DPRINTVAL("x",var->yres); + DPRINTVAL("x",var->bits_per_pixel); + DPRINT(" rejected, color depth invalid\r\n"); + return -1; //-EINVAL; + } + + if (v.yres_virtual < v.yres) + v.yres_virtual = v.yres; + if (v.xres_virtual < v.xres) + v.xres_virtual = v.xres; + /* + * XXX I'm adjusting xres_virtual to the pitch, that may help XFree + * with some panels, though I don't quite like this solution + */ + pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f) & ~(0x3f)) >> 6; + v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8); + + if (((v.xres_virtual * v.yres_virtual * nom) / den) > info->screen_size) + return -1; //-EINVAL; + if (v.xres_virtual < v.xres) + v.xres = v.xres_virtual; + if (v.xoffset < 0) + v.xoffset = 0; + if (v.yoffset < 0) + v.yoffset = 0; + if (v.xoffset > v.xres_virtual - v.xres) + v.xoffset = v.xres_virtual - v.xres - 1; + if (v.yoffset > v.yres_virtual - v.yres) + v.yoffset = v.yres_virtual - v.yres - 1; + v.red.msb_right = v.green.msb_right = v.blue.msb_right = 0; + v.transp.offset = v.transp.length = v.transp.msb_right = 0; + + memcpy(var, &v, sizeof(v)); + return 0; +} + +int radeonfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; +// DPRINT("radeonfb: radeonfb_pan_display\r\n"); + if ((var->xoffset + var->xres) > var->xres_virtual) + return -1; //-EINVAL; + if (((var->yoffset * var->xres_virtual) + var->xoffset) >= + (rinfo->mapped_vram - (var->yres * var->xres * (var->bits_per_pixel / 8)))) + return -1; //-EINVAL; + if (rinfo->asleep) + return 0; + radeon_fifo_wait(2); + rinfo->fb_offset = ((var->yoffset * var->xres_virtual + var->xoffset) * var->bits_per_pixel / 8) & ~7; + rinfo->dst_pitch_offset = (rinfo->pitch << 22) | ((rinfo->fb_local_base + rinfo->fb_offset) >> 10); + OUTREG(CRTC_OFFSET, rinfo->fb_offset); + return 0; +} + +int radeonfb_ioctl(uint32_t cmd, uint32_t arg, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + uint32_t tmp; + uint32_t value = 0; + switch(cmd) + { + /* + * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's + * and do something better using 2nd CRTC instead of just hackish + * routing to second output + */ + case FBIO_RADEON_SET_MIRROR: + if (!rinfo->is_mobility) + return -1; //-EINVAL; + radeon_fifo_wait(2); + if (value & 0x01) + { + tmp = INREG(LVDS_GEN_CNTL); + tmp |= (LVDS_ON | LVDS_BLON); + } + else + { + tmp = INREG(LVDS_GEN_CNTL); + tmp &= ~(LVDS_ON | LVDS_BLON); + } + OUTREG(LVDS_GEN_CNTL, tmp); + if (value & 0x02) + { + tmp = INREG(CRTC_EXT_CNTL); + tmp |= CRTC_CRT_ON; + mirror = 1; + } + else + { + tmp = INREG(CRTC_EXT_CNTL); + tmp &= ~CRTC_CRT_ON; + mirror = 0; + } + OUTREG(CRTC_EXT_CNTL, tmp); + return 0; + case FBIO_RADEON_GET_MIRROR: + if (!rinfo->is_mobility) + return -1; //-EINVAL; + tmp = INREG(LVDS_GEN_CNTL); + if ((LVDS_ON | LVDS_BLON) & tmp) + value |= 0x01; + tmp = INREG(CRTC_EXT_CNTL); + if (CRTC_CRT_ON & tmp) + value |= 0x02; + return 0; + default: + return -1; //-EINVAL; + } + return -1; //-EINVAL; +} + +int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t mode_switch) +{ + uint32_t val; + uint32_t tmp_pix_clks; + int unblank = 0; + + if (rinfo->lock_blank) + return 0; + DPRINT("radeonfb: radeon_screen_blank\r\n"); + radeon_engine_idle(); + val = INREG(CRTC_EXT_CNTL); + val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS); + switch(blank) + { + case FB_BLANK_VSYNC_SUSPEND: + val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS); + break; + case FB_BLANK_HSYNC_SUSPEND: + val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS); + break; + case FB_BLANK_POWERDOWN: + val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | CRTC_HSYNC_DIS); + break; + case FB_BLANK_NORMAL: + val |= CRTC_DISPLAY_DIS; + break; + case FB_BLANK_UNBLANK: + default: + unblank = 1; + break; + } + OUTREG(CRTC_EXT_CNTL, val); + + switch(rinfo->mon1_type) + { + case MT_DFP: + if (unblank) + OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN), ~(FP_FPON | FP_TMDS_EN)); + else + { + if (mode_switch || blank == FB_BLANK_NORMAL) + break; + OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN)); + } + break; + case MT_LCD: + rinfo->lvds_timer = 0; + val = INREG(LVDS_GEN_CNTL); + if (unblank) + { + uint32_t target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON + | LVDS_EN | (rinfo->init_state.lvds_gen_cntl & (LVDS_DIGON | LVDS_BL_MOD_EN)); + if ((val ^ target_val) == LVDS_DISPLAY_DIS) + OUTREG(LVDS_GEN_CNTL, target_val); + else if ((val ^ target_val) != 0) + { + OUTREG(LVDS_GEN_CNTL, target_val & ~(LVDS_ON | LVDS_BL_MOD_EN)); + rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; + rinfo->init_state.lvds_gen_cntl |= target_val & LVDS_STATE_MASK; + if (mode_switch) + { + radeon_msleep(rinfo->panel_info.pwr_delay); + OUTREG(LVDS_GEN_CNTL, target_val); + } + else + { + rinfo->pending_lvds_gen_cntl = target_val; + rinfo->lvds_timer = (int32_t)rinfo->panel_info.pwr_delay; + } + } + } + else + { + val |= LVDS_DISPLAY_DIS; + OUTREG(LVDS_GEN_CNTL, val); + /* We don't do a full switch-off on a simple mode switch */ + if (mode_switch || blank == FB_BLANK_NORMAL) + break; + /* Asic bug, when turning off LVDS_ON, we have to make sure + * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off + */ + tmp_pix_clks = INPLL(PIXCLKS_CNTL); + if (rinfo->is_mobility || rinfo->is_IGP) + OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb); + val &= ~(LVDS_BL_MOD_EN); + OUTREG(LVDS_GEN_CNTL, val); + udelay(100); + val &= ~(LVDS_ON | LVDS_EN); + OUTREG(LVDS_GEN_CNTL, val); + val &= ~LVDS_DIGON; + rinfo->pending_lvds_gen_cntl = val; + rinfo->lvds_timer = (int32_t)rinfo->panel_info.pwr_delay; + rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; + rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; + if (rinfo->is_mobility || rinfo->is_IGP) + OUTPLL(PIXCLKS_CNTL, tmp_pix_clks); + } + break; + case MT_CRT: + // todo: powerdown DAC + default: + break; + } + /* let fbcon do a soft blank for us */ + return(blank == FB_BLANK_NORMAL) ? -1 /* -EINVAL */ : 0; +} + +int radeonfb_blank(int blank, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + if (rinfo->asleep) + return 0; + return radeon_screen_blank(rinfo, blank, 0); +} + +static int radeon_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, struct radeonfb_info *rinfo) +{ + uint32_t pindex; + if (regno > 255) + return 1; + red >>= 8; + green >>= 8; + blue >>= 8; + rinfo->palette[regno].red = red; + rinfo->palette[regno].green = green; + rinfo->palette[regno].blue = blue; + /* default */ + pindex = regno; + if (!rinfo->asleep) + { + radeon_fifo_wait(9); + if (rinfo->bpp == 16) + { + pindex = regno * 8; + if (rinfo->depth == 16 && regno > 63) + return 1; + if (rinfo->depth == 15 && regno > 31) + return 1; + /* For 565, the green component is mixed one order + * below + */ + if (rinfo->depth == 16) + { + OUTREG(PALETTE_INDEX, pindex>>1); + OUTREG(PALETTE_DATA,(rinfo->palette[regno>>1].red << 16) + | (green << 8) | (rinfo->palette[regno>>1].blue)); + green = rinfo->palette[regno<<1].green; + } + } + if (rinfo->depth != 16 || regno < 32) + { + OUTREG(PALETTE_INDEX, pindex); + OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue); + } + } + return 0; +} + +int32_t radeonfb_setcolreg(uint32_t regno, uint32_t red, uint32_t green, + uint32_t blue, uint32_t transp, struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + uint32_t dac_cntl2, vclk_cntl = 0; + int rc; + if (!rinfo->asleep) + { + if (rinfo->is_mobility) + { + vclk_cntl = INPLL(VCLK_ECP_CNTL); + OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); + } + /* Make sure we are on first palette */ + if (rinfo->has_CRTC2) + { + dac_cntl2 = INREG(DAC_CNTL2); + dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; + OUTREG(DAC_CNTL2, dac_cntl2); + } + } + rc = radeon_setcolreg(regno, red, green, blue, transp, rinfo); + if (!rinfo->asleep && rinfo->is_mobility) + OUTPLL(VCLK_ECP_CNTL, vclk_cntl); + return rc; +} + +static void radeon_save_state(struct radeonfb_info *rinfo, struct radeon_regs *save) +{ + /* CRTC regs */ + save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); + save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); + save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); + save->dac_cntl = INREG(DAC_CNTL); + save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); + save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); + save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); + save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); + save->crtc_pitch = INREG(CRTC_PITCH); + save->surface_cntl = INREG(SURFACE_CNTL); + /* FP regs */ + save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); + save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); + save->fp_gen_cntl = INREG(FP_GEN_CNTL); + save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); + save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); + save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); + save->fp_vert_stretch = INREG(FP_VERT_STRETCH); + save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); + save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); + save->tmds_crc = INREG(TMDS_CRC); + save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); + save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); + /* PLL regs */ + save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; + radeon_pll_errata_after_index(rinfo); + save->ppll_div_3 = INPLL(PPLL_DIV_3); + save->ppll_ref_div = INPLL(PPLL_REF_DIV); +} + +static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) +{ + int i; + DPRINT("radeonfb: radeon_write_pll_regs\r\n"); + radeon_fifo_wait(20); +#if 0 + /* Workaround from XFree */ + if (rinfo->is_mobility) + { + /* A temporal workaround for the occational blanking on certain laptop + * panels. This appears to related to the PLL divider registers + * (fail to lock?). It occurs even when all dividers are the same + * with their old settings. In this case we really don't need to + * fiddle with PLL registers. By doing this we can avoid the blanking + * problem with some panels. + */ + if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) + && (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) + { + /* We still have to force a switch to selected PPLL div thanks to + * an XFree86 driver bug which will switch it away in some cases + * even when using UseFDev */ + OUTREGP(CLOCK_CNTL_INDEX, + mode->clk_cntl_index & PPLL_DIV_SEL_MASK, + ~PPLL_DIV_SEL_MASK); + radeon_pll_errata_after_index(rinfo); + radeon_pll_errata_after_data(rinfo); + return; + } + } +#endif + /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ + OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); + /* Reset PPLL & enable atomic update */ + OUTPLLP(PPLL_CNTL, PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, + ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); + /* Switch to selected PPLL divider */ + OUTREGP(CLOCK_CNTL_INDEX, mode->clk_cntl_index & PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK); + radeon_pll_errata_after_index(rinfo); + radeon_pll_errata_after_data(rinfo); + /* Set PPLL ref. div */ + if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_RS300 + || rinfo->family == CHIP_FAMILY_R350 || rinfo->family == CHIP_FAMILY_RV350) + { + if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) + { + /* When restoring console mode, use saved PPLL_REF_DIV + * setting. + */ + OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); + } + else + { + /* R300 uses ref_div_acc field as real ref divider */ + OUTPLLP(PPLL_REF_DIV,(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),~R300_PPLL_REF_DIV_ACC_MASK); + } + } + else + OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); + /* Set PPLL divider 3 & post divider*/ + OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); + OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); + /* Write update */ + while(INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); + OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); + /* Wait read update complete */ + /* FIXME: Certain revisions of R300 can't recover here. Not sure of + the cause yet, but this workaround will mask the problem for now. + Other chips usually will pass at the very first test, so the + workaround shouldn't have any effect on them. */ + for(i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++); + OUTPLL(HTOTAL_CNTL, 0); + /* Clear reset & atomic update */ + OUTPLLP(PPLL_CNTL, 0, ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); + /* We may want some locking ... oh well */ + radeon_msleep(5); + /* Switch back VCLK source to PPLL */ + OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); +} + +static void radeon_wait_vbl(struct fb_info *info) +{ + uint32_t cnt = INREG(CRTC_CRNT_FRAME); + while(cnt == INREG(CRTC_CRNT_FRAME)); +} + +static void radeon_timer_func(void) +{ + struct fb_info *info = info_fvdi; + struct radeonfb_info *rinfo = info->par; + static int32_t start_timer; + struct fb_var_screeninfo var; + uint32_t x, y; + int chg, disp; + + /* delayed LVDS panel power up/down */ + if (rinfo->lvds_timer) + { +#ifdef FIXME_LATER + if (!start_timer) + start_timer = *_hz_200; + + if (((*_hz_200 - start_timer) * 5) >= (int32_t)rinfo->lvds_timer) + { + rinfo->lvds_timer = 0; + radeon_engine_idle(); + OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); + } +#endif + } + else + start_timer = 0; + + if (rinfo->RenderCallback != NULL) + rinfo->RenderCallback(rinfo); + if ((info->screen_mono != NULL) && info->update_mono) + { + int32_t foreground = 255, background = 0; + uint8_t *src_buf = (uint8_t *)info->screen_mono; + int skipleft = ((int)src_buf & 3) << 3; + int dst_x = 0; + int w = (int)info->var.xres_virtual; + int h = (int)info->var.yres_virtual; +// info->fbops->SetClippingRectangle(info,0,0,w-1,h-1); + src_buf = (uint8_t*)((int32_t)src_buf & ~3); + dst_x -= (int32_t)skipleft; + w += (int32_t)skipleft; + info->fbops->SetupForScanlineCPUToScreenColorExpandFill(info,(int)foreground,(int)background,3,0xffffffff); + info->fbops->SubsequentScanlineCPUToScreenColorExpandFill(info,(int)dst_x,0,w,h,skipleft); + while(--h >= 0) + { + info->fbops->SubsequentScanline(info, (uint32_t *)src_buf); + src_buf += (info->var.xres_virtual >> 3); + } +// info->fbops->DisableClipping(info); + if (info->update_mono > 0) + info->update_mono = 0; + } + if ((info->var.xres_virtual != info->var.xres) + || (info->var.yres_virtual != info->var.yres)) + { +#ifdef __mcoldfire__ + asm volatile ( + " clr.l -(SP)\n\t" + " move.l D0,-(SP)\n\t" + " move.w SR,D0\n\t" + " move.l D0,4(SP)\n\t" + " or.l #0x700,D0\n\t" /* disable interrupts */ + " move.w D0,SR\n\t" + " move.l (SP)+,D0\n\t" ); +#else + asm volatile ( + " move.w SR,-(SP)\n\t" + " or.w #0x700,SR\n\t" ); /* disable interrupts */ +#endif + chg = 0; + x = info->var.xoffset; + y = info->var.yoffset; + if (((x + info->var.xres) < info->var.xres_virtual) + && (rinfo->cursor_x >= (info->var.xres - 8))) + { + x += 8; + chg = 1; + } + else if ((x >= 8) && (rinfo->cursor_x <= 8)) + { + x -= 8; + chg = 1; + } + if (((y + info->var.yres) < info->var.yres_virtual) + && (rinfo->cursor_y >= (info->var.yres - 8))) + { + y += 8; + chg = 1; + } + else if ((y >=8) && (rinfo->cursor_y <= 8)) + { + y -= 8; + chg = 1; + } + if (chg) + { + memcpy(&var, &info->var, sizeof(struct fb_var_screeninfo)); + var.xoffset = x; + var.yoffset = y; + disp = rinfo->cursor_show; + if (disp) + RADEONHideCursor(info); + fb_pan_display(info,&var); + if (disp) + RADEONShowCursor(info); + } +#ifdef __mcoldfire__ + asm volatile ( + " move.l D0,-(SP)\n\t" + " move.l 4(SP),D0\n\t" + " move.w D0,SR\n\t" + " move.l (SP)+,D0\n\t" + " addq.l #4,SP\n\t" ); +#else + asm volatile ( + " move.w (SP)+,SR\n\r" ); +#endif + } +} + +/* + * Apply a video mode. This will apply the whole register set, including + * the PLL registers, to the card + */ +void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t regs_only) +{ + int i; + int primary_mon = PRIMARY_MONITOR(rinfo); + DPRINT("radeonfb: radeon_write_mode\r\n"); + if (!regs_only) + radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); + radeon_fifo_wait(31); + for(i=0; i<10; i++) + OUTREG(common_regs[i].reg, common_regs[i].val); + /* Apply surface registers */ + for(i=0; i<8; i++) + { + OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]); + OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]); + OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]); + } + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); + OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); + OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); + OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); + OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); + OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); + rinfo->fb_offset = 0; + rinfo->dst_pitch_offset = (rinfo->pitch << 22) | ((rinfo->fb_local_base + rinfo->fb_offset) >> 10); + OUTREG(CRTC_OFFSET, rinfo->fb_offset); +#ifdef RADEON_TILING + if (rinfo->tilingEnabled) + { + if (rinfo->family >= CHIP_FAMILY_R300) + OUTREG(CRTC_OFFSET_CNTL, R300_CRTC_X_Y_MODE_EN | R300_CRTC_MICRO_TILE_BUFFER_DIS | R300_CRTC_MACRO_TILE_EN); + else + OUTREG(CRTC_OFFSET_CNTL, CRTC_OFFSET_CNTL__CRTC_TILE_EN); + } + else +#endif + OUTREG(CRTC_OFFSET_CNTL, 0); + OUTREG(CRTC_PITCH, mode->crtc_pitch); + OUTREG(SURFACE_CNTL, mode->surface_cntl); + radeon_write_pll_regs(rinfo, mode); + if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) + { + radeon_fifo_wait(10); + OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); + OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); + OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); + OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); + OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); + OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); + OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); + OUTREG(TMDS_CRC, mode->tmds_crc); + OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); + } + if (!regs_only) + radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); + radeon_fifo_wait(2); + OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); +} + +/* + * Calculate the PLL values for a given mode + */ +static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs, uint32_t freq) +{ + static const struct { + int divider; + int bitvalue; + } *post_div, + post_divs[] = { + { 1, 0 }, + { 2, 1 }, + { 4, 2 }, + { 8, 3 }, + { 3, 4 }, + { 16, 5 }, + { 6, 6 }, + { 12, 7 }, + { 0, 0 }, + }; + int fb_div, pll_output_freq = 0; + int uses_dvo = 0; + /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm + * not sure which model starts having FP2_GEN_CNTL, I assume anything more + * recent than an r(v)100... + */ +#if 1 + /* XXX I had reports of flicker happening with the cinema display + * on TMDS1 that seem to be fixed if I also forbit odd dividers in + * this case. This could just be a bandwidth calculation issue, I + * haven't implemented the bandwidth code yet, but in the meantime, + * forcing uses_dvo to 1 fixes it and shouln't have bad side effects, + * I haven't seen a case were were absolutely needed an odd PLL + * divider. I'll find a better fix once I have more infos on the + * real cause of the problem. + */ + while(rinfo->has_CRTC2) + { + uint32_t fp2_gen_cntl = INREG(FP2_GEN_CNTL); + uint32_t disp_output_cntl; + int source; + /* FP2 path not enabled */ + if ((fp2_gen_cntl & FP2_ON) == 0) + break; + /* Not all chip revs have the same format for this register, + * extract the source selection + */ + if (rinfo->family == CHIP_FAMILY_R200 || rinfo->family == CHIP_FAMILY_R300 + || rinfo->family == CHIP_FAMILY_R350 || rinfo->family == CHIP_FAMILY_RV350) + { + source = (fp2_gen_cntl >> 10) & 0x3; + /* sourced from transform unit, check for transform unit + * own source + */ + if (source == 3) + { + disp_output_cntl = INREG(DISP_OUTPUT_CNTL); + source = (disp_output_cntl >> 12) & 0x3; + } + } + else + source = (fp2_gen_cntl >> 13) & 0x1; + /* sourced from CRTC2 -> exit */ + if (source == 1) + break; + /* so we end up on CRTC1, let's set uses_dvo to 1 now */ + uses_dvo = 1; + break; + } +#else + uses_dvo = 1; +#endif + if (freq > rinfo->pll.ppll_max) + freq = rinfo->pll.ppll_max; + if (freq*12 < rinfo->pll.ppll_min) + freq = rinfo->pll.ppll_min / 12; + for(post_div = &post_divs[0]; post_div->divider; ++post_div) + { + pll_output_freq = post_div->divider * freq; + /* If we output to the DVO port (external TMDS), we don't allow an + * odd PLL divider as those aren't supported on this path + */ + if (uses_dvo && (post_div->divider & 1)) + continue; + if (pll_output_freq >= rinfo->pll.ppll_min && + pll_output_freq <= rinfo->pll.ppll_max) + break; + } + /* If we fall through the bottom, try the "default value" + given by the terminal post_div->bitvalue */ + if ( !post_div->divider ) + { + post_div = &post_divs[post_div->bitvalue]; + pll_output_freq = post_div->divider * freq; + } + /* If we fall through the bottom, try the "default value" + given by the terminal post_div->bitvalue */ + if ( !post_div->divider ) + { + post_div = &post_divs[post_div->bitvalue]; + pll_output_freq = post_div->divider * freq; + } + fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,rinfo->pll.ref_clk); + regs->ppll_ref_div = rinfo->pll.ref_div; + regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); +} + +int radeonfb_set_par(struct fb_info *info) +{ + struct radeonfb_info *rinfo = info->par; + struct fb_var_screeninfo *mode = &info->var; + struct radeon_regs *newmode; + int hTotal, vTotal, hSyncStart, hSyncEnd, hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync; + static uint8_t hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5}; + static uint8_t hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5}; + uint32_t sync, h_sync_pol, v_sync_pol, dotClock, pixClock; + int i, freq; + int format = 0; + int nopllcalc = 0; + int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid; + int primary_mon = PRIMARY_MONITOR(rinfo); + int depth = var_to_depth(mode); + int use_rmx = 0; + newmode = (struct radeon_regs *)Funcs_malloc(sizeof(struct radeon_regs),3); + if (!newmode) + return -1; //-ENOMEM; + /* We always want engine to be idle on a mode switch, even + * if we won't actually change the mode + */ + DPRINT("radeonfb: radeonfb_set_par\r\n"); + radeon_engine_idle(); + hSyncStart = mode->xres + mode->right_margin; + hSyncEnd = hSyncStart + mode->hsync_len; + hTotal = hSyncEnd + mode->left_margin; + + vSyncStart = mode->yres + mode->lower_margin; + vSyncEnd = vSyncStart + mode->vsync_len; + vTotal = vSyncEnd + mode->upper_margin; + + pixClock = mode->pixclock; + sync = mode->sync; + + h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; + v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; + + if (primary_mon == MT_DFP || primary_mon == MT_LCD) + { + if (rinfo->panel_info.xres < mode->xres) + mode->xres = rinfo->panel_info.xres; + + if (rinfo->panel_info.yres < mode->yres) + mode->yres = rinfo->panel_info.yres; + + hTotal = mode->xres + rinfo->panel_info.hblank; + hSyncStart = mode->xres + rinfo->panel_info.hOver_plus; + hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width; + + vTotal = mode->yres + rinfo->panel_info.vblank; + vSyncStart = mode->yres + rinfo->panel_info.vOver_plus; + vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width; + + h_sync_pol = !rinfo->panel_info.hAct_high; + v_sync_pol = !rinfo->panel_info.vAct_high; + + pixClock = 100000000 / rinfo->panel_info.clock; + + if (rinfo->panel_info.use_bios_dividers) + { + nopllcalc = 1; + newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | (rinfo->panel_info.post_divider << 16); + newmode->ppll_ref_div = rinfo->panel_info.ref_divider; + } + } + dotClock = 1000000000 / pixClock; + freq = dotClock / 10; /* x100 */ + hsync_wid = (hSyncEnd - hSyncStart) / 8; + if (hsync_wid == 0) + hsync_wid = 1; + else if (hsync_wid > 0x3f) /* max */ + hsync_wid = 0x3f; + if (mode->vmode & FB_VMODE_DOUBLE) + { + vSyncStart <<= 1; + vSyncEnd <<= 1; + vTotal <<= 1; + } + vsync_wid = vSyncEnd - vSyncStart; + if (vsync_wid == 0) + vsync_wid = 1; + else if (vsync_wid > 0x1f) /* max */ + vsync_wid = 0x1f; + hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; + vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; + cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; + format = radeon_get_dstbpp(depth); + bytpp = mode->bits_per_pixel >> 3; + if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) + hsync_fudge = hsync_fudge_fp[format-1]; + else + hsync_fudge = hsync_adj_tab[format-1]; + if (mode->vmode & FB_VMODE_DOUBLE) + hsync_fudge = 0; /* todo: need adjust */ + hsync_start = hSyncStart - 8 + hsync_fudge; + newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | (format << 8); + if (mode->vmode & FB_VMODE_DOUBLE) + newmode->crtc_gen_cntl |= CRTC_DBL_SCAN_EN; + if (mode->vmode & FB_VMODE_INTERLACED) + newmode->crtc_gen_cntl |= CRTC_INTERLACE_EN; + /* Clear auto-center etc... */ + newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl; + newmode->crtc_more_cntl &= 0xfffffff0; + if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) + { + newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN; + if (mirror) + newmode->crtc_ext_cntl |= CRTC_CRT_ON; + newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN | CRTC_INTERLACE_EN); + } + else + newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; + newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; + newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | (((mode->xres / 8) - 1) << 16)); + newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | (hsync_wid << 16) | (h_sync_pol << 23)); + if (mode->vmode & FB_VMODE_DOUBLE) + newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | (((mode->yres << 1) - 1) << 16); + else + newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | ((mode->yres - 1) << 16); + newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | (vsync_wid << 16) | (v_sync_pol << 23)); + /* We first calculate the engine pitch */ + rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) & ~(0x3f)) >> 6; + /* Then, re-multiply it to get the CRTC pitch */ + newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8); + newmode->crtc_pitch |= (newmode->crtc_pitch << 16); + /* + * It looks like recent chips have a problem with SURFACE_CNTL, + * setting SURF_TRANSLATION_DIS completely disables the + * swapper as well, so we leave it unset now. + */ + newmode->surface_cntl = 0; + if (rinfo->big_endian) + { + /* Setup swapping on both apertures, though we currently + * only use aperture 0, enabling swapper on aperture 1 + * won't harm + */ + switch(mode->bits_per_pixel) + { + case 16: + newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP; + newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP; + break; + case 24: + case 32: + newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP; + newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP; + break; + } + } + /* Clear surface registers */ + for(i=0; i<8; i++) + { + newmode->surf_lower_bound[i] = 0; + newmode->surf_upper_bound[i] = 0x1f; + newmode->surf_info[i] = 0; + } + rinfo->bpp = mode->bits_per_pixel; + rinfo->depth = depth; + /* We use PPLL_DIV_3 */ + newmode->clk_cntl_index = 0x300; + /* Calculate PPLL value if necessary */ + if (!nopllcalc) + radeon_calc_pll_regs(rinfo, newmode, freq); + newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl; + if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) + { + uint32_t hRatio, vRatio; + if (mode->xres > rinfo->panel_info.xres) + mode->xres = rinfo->panel_info.xres; + if (mode->yres > rinfo->panel_info.yres) + mode->yres = rinfo->panel_info.yres; + newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1) << HORZ_PANEL_SHIFT); + newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1) << VERT_PANEL_SHIFT); + if (mode->xres != rinfo->panel_info.xres) + { + hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX, rinfo->panel_info.xres); + newmode->fp_horz_stretch = (((((uint32_t)hRatio) & HORZ_STRETCH_RATIO_MASK)) + | (newmode->fp_horz_stretch & (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH | HORZ_AUTO_RATIO_INC))); + newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND | HORZ_STRETCH_ENABLE); + use_rmx = 1; + } + newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO; + if (mode->yres != rinfo->panel_info.yres) + { + vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX, rinfo->panel_info.yres); + newmode->fp_vert_stretch = (((((uint32_t)vRatio) & VERT_STRETCH_RATIO_MASK)) + | (newmode->fp_vert_stretch & (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED))); + newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND | VERT_STRETCH_ENABLE); + use_rmx = 1; + } + newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN; + newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl + & (uint32_t) ~(FP_SEL_CRTC2 | FP_RMX_HVSYNC_CONTROL_EN | FP_DFP_SYNC_SEL | FP_CRT_SYNC_SEL + | FP_CRTC_LOCK_8DOT | FP_USE_SHADOW_EN | FP_CRTC_USE_SHADOW_VEND | FP_CRT_SYNC_ALT)); + newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | FP_CRTC_DONT_SHADOW_HEND | FP_PANEL_FORMAT); + if (IS_R300_VARIANT(rinfo) || (rinfo->family == CHIP_FAMILY_R200)) + { + newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; + if (use_rmx) + newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; + else + newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; + } + else + newmode->fp_gen_cntl |= FP_SEL_CRTC1; + newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; + newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; + newmode->tmds_crc = rinfo->init_state.tmds_crc; + newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl; + if (primary_mon == MT_LCD) + { + newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); + newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN); + } + else + { + /* DFP */ + newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); + newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST); + /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */ + if (IS_R300_VARIANT(rinfo) || (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2) + newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN; + else + newmode->tmds_transmitter_cntl |= TMDS_PLL_EN; + newmode->crtc_ext_cntl &= ~CRTC_CRT_ON; + } + newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | (((mode->xres / 8) - 1) << 16)); + newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | ((mode->yres - 1) << 16); + newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | (hsync_wid << 16) | (h_sync_pol << 23)); + newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | (vsync_wid << 16) | (v_sync_pol << 23)); + } + /* do it! */ + if (!rinfo->asleep) + { +#if 0 + if (debug) + { + DPRINT("Press a key for write the video mode...\r\n"); + Bconin(2); + } +#endif + memcpy(&rinfo->state, newmode, sizeof(*newmode)); +#ifdef RADEON_TILING + rinfo->tilingEnabled = (mode->vmode & (FB_VMODE_DOUBLE | FB_VMODE_INTERLACED)) ? FALSE : TRUE; +#endif + radeon_write_mode(rinfo, newmode, 0); + /* (re)initialize the engine */ + radeonfb_engine_init(rinfo); + } + /* Update fix */ + info->fix.line_length = rinfo->pitch*64; + info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; + Funcs_free(newmode); + return 0; +} + +static void radeonfb_check_modes(struct fb_info *info, struct mode_option *resolution) +{ + struct radeonfb_info *rinfo = info->par; + radeon_check_modes(rinfo, resolution); +} + +static struct fb_ops radeonfb_ops = +{ + .fb_check_var = radeonfb_check_var, + .fb_setcolreg = radeonfb_setcolreg, + .fb_set_par = radeonfb_set_par, + .fb_pan_display = radeonfb_pan_display, + .fb_blank = radeonfb_blank, + .fb_sync = radeonfb_sync, + .fb_ioctl = radeonfb_ioctl, + .fb_check_modes = radeonfb_check_modes, + .SetupForSolidFill = RADEONSetupForSolidFillMMIO, + .SubsequentSolidFillRect = RADEONSubsequentSolidFillRectMMIO, + .SetupForSolidLine = RADEONSetupForSolidLineMMIO, + .SubsequentSolidHorVertLine = RADEONSubsequentSolidHorVertLineMMIO, + .SubsequentSolidTwoPointLine = RADEONSubsequentSolidTwoPointLineMMIO, + .SetupForDashedLine = RADEONSetupForDashedLineMMIO, + .SubsequentDashedTwoPointLine = RADEONSubsequentDashedTwoPointLineMMIO, + .SetupForScreenToScreenCopy = RADEONSetupForScreenToScreenCopyMMIO, + .SubsequentScreenToScreenCopy = RADEONSubsequentScreenToScreenCopyMMIO, + .ScreenToScreenCopy = RADEONScreenToScreenCopyMMIO, + .SetupForMono8x8PatternFill = RADEONSetupForMono8x8PatternFillMMIO, + .SubsequentMono8x8PatternFillRect = RADEONSubsequentMono8x8PatternFillRectMMIO, + .SetupForScanlineCPUToScreenColorExpandFill = RADEONSetupForScanlineCPUToScreenColorExpandFillMMIO, + .SubsequentScanlineCPUToScreenColorExpandFill = RADEONSubsequentScanlineCPUToScreenColorExpandFillMMIO, + .SubsequentScanline = RADEONSubsequentScanlineMMIO, + .SetupForScanlineImageWrite = RADEONSetupForScanlineImageWriteMMIO, + .SubsequentScanlineImageWriteRect = RADEONSubsequentScanlineImageWriteRectMMIO, + .SetClippingRectangle = RADEONSetClippingRectangleMMIO, + .DisableClipping = RADEONDisableClippingMMIO, +#ifdef RADEON_RENDER + .SetupForCPUToScreenAlphaTexture = RADEONSetupForCPUToScreenAlphaTextureMMIO, + .SetupForCPUToScreenTexture = RADEONSetupForCPUToScreenTextureMMIO, + .SubsequentCPUToScreenTexture = RADEONSubsequentCPUToScreenTextureMMIO, +#else + .SetupForCPUToScreenAlphaTexture = NULL, + .SetupForCPUToScreenTexture = NULL, + .SubsequentCPUToScreenTexture = NULL, +#endif /* RADEON_RENDER */ + .SetCursorColors = RADEONSetCursorColors, + .SetCursorPosition = RADEONSetCursorPosition, + .LoadCursorImage = RADEONLoadCursorImage, + .HideCursor = RADEONHideCursor, + .ShowCursor = RADEONShowCursor, + .CursorInit = RADEONCursorInit, + .WaitVbl = radeon_wait_vbl, +}; + +static int radeon_set_fbinfo(struct radeonfb_info *rinfo) +{ + struct fb_info *info = rinfo->info; + info->par = rinfo; + info->fbops = &radeonfb_ops; + info->ram_base = info->screen_base = rinfo->fb_base; + info->screen_size = rinfo->mapped_vram; + info->ram_size = rinfo->mapped_vram; + if (info->screen_size > MAX_MAPPED_VRAM) + info->screen_size = MAX_MAPPED_VRAM; + else if (info->screen_size > MIN_MAPPED_VRAM) + info->screen_size = MIN_MAPPED_VRAM; + DPRINTVALHEX("radeonfb: radeon_set_fbinfo: screen_size ",info->screen_size); + DPRINT("\r\n"); + /* Fill fix common fields */ + memcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); + info->fix.smem_start = rinfo->fb_base_phys; + info->fix.smem_len = rinfo->video_ram; + info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.visual = FB_VISUAL_PSEUDOCOLOR; + info->fix.xpanstep = 8; + info->fix.ypanstep = 1; + info->fix.ywrapstep = 0; + info->fix.type_aux = 0; + info->fix.mmio_start = rinfo->mmio_base_phys; + info->fix.mmio_len = RADEON_REGSIZE; + info->fix.accel = FB_ACCEL_ATI_RADEON; + return 0; +} + +static void radeon_identify_vram(struct radeonfb_info *rinfo) +{ + uint32_t tmp; + /* framebuffer size */ + if ((rinfo->family == CHIP_FAMILY_RS100) + || (rinfo->family == CHIP_FAMILY_RS200) + || (rinfo->family == CHIP_FAMILY_RS300)) + { + uint32_t tom = INREG(NB_TOM); + tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); + radeon_fifo_wait(6); + OUTREG(MC_FB_LOCATION, tom); + OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); + /* This is supposed to fix the crtc2 noise problem. */ + OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); + if ((rinfo->family == CHIP_FAMILY_RS100) || (rinfo->family == CHIP_FAMILY_RS200)) + { + /* This is to workaround the asic bug for RMX, some versions + of BIOS dosen't have this register initialized correctly. */ + OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, ~CRTC_H_CUTOFF_ACTIVE_EN); + } + } + else + tmp = INREG(CONFIG_MEMSIZE); + /* mem size is bits [28:0], mask off the rest */ + rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; + /* + * Hack to get around some busted production M6's + * reporting no ram + */ + if (rinfo->video_ram == 0) + { + switch(rinfo->chipset) + { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: rinfo->video_ram = 8192 * 1024; break; + default: break; + } + } + /* + * Now try to identify VRAM type + */ + if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) + || (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) + rinfo->vram_ddr = 1; + else + rinfo->vram_ddr = 0; + tmp = INREG(MEM_CNTL); + if (IS_R300_VARIANT(rinfo)) + { + tmp &= R300_MEM_NUM_CHANNELS_MASK; + switch(tmp) + { + case 0: rinfo->vram_width = 64; break; + case 1: rinfo->vram_width = 128; break; + case 2: rinfo->vram_width = 256; break; + default: rinfo->vram_width = 128; break; + } + } + else if ((rinfo->family == CHIP_FAMILY_RV100) + || (rinfo->family == CHIP_FAMILY_RS100) + || (rinfo->family == CHIP_FAMILY_RS200)) + { + if (tmp & RV100_MEM_HALF_MODE) + rinfo->vram_width = 32; + else + rinfo->vram_width = 64; + } + else + { + if (tmp & MEM_NUM_CHANNELS_MASK) + rinfo->vram_width = 128; + else + rinfo->vram_width = 64; + } + /* This may not be correct, as some cards can have half of channel disabled + * ToDo: identify these cases + */ + DPRINT("radeonfb: "); + switch(rinfo->family) + { + case CHIP_FAMILY_LEGACY: DPRINT("LEGACY"); break; + case CHIP_FAMILY_RADEON: DPRINT("RADEON"); break; + case CHIP_FAMILY_RV100: DPRINT("RV100"); break; + case CHIP_FAMILY_RS100: DPRINT("RS100"); break; + case CHIP_FAMILY_RV200: DPRINT("RV200"); break; + case CHIP_FAMILY_RS200: DPRINT("RS200"); break; + case CHIP_FAMILY_R200: DPRINT("R200"); break; + case CHIP_FAMILY_RV250: DPRINT("RV250"); break; + case CHIP_FAMILY_RS300: DPRINT("RS300"); break; + case CHIP_FAMILY_RV280: DPRINT("RV280"); break; + case CHIP_FAMILY_R300: DPRINT("R300"); break; + case CHIP_FAMILY_R350: DPRINT("R350"); break; + case CHIP_FAMILY_RV350: DPRINT("RV350"); break; + case CHIP_FAMILY_RV380: DPRINT("RV380"); break; + case CHIP_FAMILY_R420: DPRINT("R420"); break; + default: DPRINT("UNKNOW"); break; + } + DPRINTVAL(" found ",rinfo->video_ram / 1024); + DPRINT("KB of "); + DPRINTVAL(rinfo->vram_ddr ? "DDR " : "SDRAM ",rinfo->vram_width); + DPRINT(" bits wide videoram\r\n"); +} + +int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent) +{ +#ifdef DRIVER_IN_ROM + extern short os_magic; +#endif + struct fb_info *info; + struct radeonfb_info *rinfo; + struct pci_rd *pci_rsc_desc; + + info_fvdi = info = framebuffer_alloc(sizeof(struct radeonfb_info)); + if (!info) + return -1; // -ENOMEM; + rinfo = info->par; + rinfo->info = info; + rinfo->handle = handle; + Funcs_copy("ATI Radeon XX ", rinfo->name); + rinfo->name[11] = (char)(ent->device >> 8); + rinfo->name[12] = (char)ent->device; + rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; + rinfo->chipset = ent->device; + rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; + rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0; + rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; + + /* Set base addrs */ + DPRINT("radeonfb: radeonfb_pci_register: Set base addrs\r\n"); + rinfo->fb_base_phys = rinfo->mmio_base_phys = rinfo->io_base_phys = 0xFFFFFFFF; + rinfo->mapped_vram = 0; + rinfo->mmio_base = rinfo->io_base = NULL; + rinfo->bios_seg = NULL; + + pci_rsc_desc = (struct pci_rd *) get_resource(handle); + if ((int32_t)pci_rsc_desc >= 0) + { + uint16_t flags; + do + { + DPRINTVALHEX("radeonfb: flags ", pci_rsc_desc->flags); + DPRINTVALHEX(" start ", pci_rsc_desc->start); + DPRINTVALHEX(" offset ", pci_rsc_desc->offset); + DPRINTVALHEX(" length ", pci_rsc_desc->length); + DPRINT("\r\n"); + if (!(pci_rsc_desc->flags & FLG_IO)) + { + if ((rinfo->fb_base_phys == 0xFFFFFFFF) && (pci_rsc_desc->length >= 0x100000)) + { + rinfo->fb_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start); + rinfo->fb_base_phys = pci_rsc_desc->start; + rinfo->mapped_vram = pci_rsc_desc->length; +// rinfo->dma_offset = pci_rsc_desc->dmaoffset; + if ((pci_rsc_desc->flags & FLG_ENDMASK) == ORD_MOTOROLA) + { + rinfo->big_endian = 0; /* host bridge make swapping intel -> motorola */ + DPRINT("radeonfb: host bridge is big endian\r\n"); + } + else + { + rinfo->big_endian = 1; /* radeon make swapping intel -> motorola */ + DPRINT("radeonfb: host bridge is little endian\r\n"); + } + } + else if ((pci_rsc_desc->length >= RADEON_REGSIZE) + && (pci_rsc_desc->length < 0x100000)) + { + if (pci_rsc_desc->flags & FLG_ROM) + { + if (rinfo->bios_seg == NULL) + { + rinfo->bios_seg_phys = pci_rsc_desc->start; + if (BIOS_IN16(0) == 0xaa55) + rinfo->bios_seg = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start); + else + rinfo->bios_seg_phys = 0; + } + } + else + { + if (rinfo->mmio_base_phys == 0xFFFFFFFF) + { + rinfo->mmio_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start); + rinfo->mmio_base_phys = pci_rsc_desc->start; + } + } + } + } + else + { + if (rinfo->io_base_phys == 0xFFFFFFFF) + { + rinfo->io_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start); + rinfo->io_base_phys = pci_rsc_desc->start; + } + } + flags = pci_rsc_desc->flags; + pci_rsc_desc = (struct pci_rd *)((uint32_t)pci_rsc_desc->next + (uint32_t)pci_rsc_desc); + } + while(!(flags & FLG_LAST)); + } + else + DPRINT("radeonfb: radeonfb_pci_register: get_resource error\r\n"); + + /* map the regions */ + DPRINT("radeonfb: radeonfb_pci_register: map the regions\r\n"); + if (rinfo->mmio_base == NULL) + { + DPRINT("radeonfb: cannot map MMIO\r\n"); + framebuffer_release(info); + return -2; //(-EIO); + } + DPRINTVALHEX("radeonfb: radeonfb_pci_register: mmio_base_phys ", rinfo->mmio_base_phys); + DPRINTVALHEX(" mmio_base ", (uint32_t)rinfo->mmio_base); + DPRINT("\r\n"); + DPRINTVALHEX("radeonfb: radeonfb_pci_register: io_base_phys ", rinfo->io_base_phys); + DPRINTVALHEX(" io_base ", (uint32_t)rinfo->io_base); + DPRINT("\r\n"); + DPRINTVALHEX("radeonfb: radeonfb_pci_register: fb_base_phys ", rinfo->fb_base_phys); + DPRINTVALHEX(" fb_base ", (uint32_t)rinfo->fb_base); + DPRINT("\r\n"); + + /* + * Check for errata + */ + DPRINT("radeonfb: radeonfb_pci_register: check for errata\r\n"); + rinfo->errata = 0; + if (rinfo->family == CHIP_FAMILY_R300 + && (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK) == CFG_ATI_REV_A11) + rinfo->errata |= CHIP_ERRATA_R300_CG; + if (rinfo->family == CHIP_FAMILY_RV200 || rinfo->family == CHIP_FAMILY_RS200) + rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS; + if (rinfo->family == CHIP_FAMILY_RV100 + || rinfo->family == CHIP_FAMILY_RS100 + || rinfo->family == CHIP_FAMILY_RS200) + rinfo->errata |= CHIP_ERRATA_PLL_DELAY; + + /* + * Map the BIOS ROM if any and retreive PLL parameters from + * the BIOS. + */ + DPRINTVALHEX("radeonfb: radeonfb_pci_register: bios_seg_phys ", rinfo->bios_seg_phys); + DPRINTVALHEX(" bios_seg ", (uint32_t)rinfo->bios_seg); + DPRINT("\r\n"); + DPRINT("radeonfb: radeonfb_pci_register: Map the BIOS ROM\r\n"); + radeon_map_ROM(rinfo); + +#ifdef DRIVER_IN_ROM + /* Run VGA BIOS */ + if ((rinfo->bios_seg != NULL) && !os_magic) + { + Cconws("Run VGA BIOS, please wait...\r\n"); + DPRINT("radeonfb: radeonfb_pci_register: run VGA BIOS\r\n"); + run_bios(rinfo); + } +#if defined(COLDFIRE) && defined(LWIP) + else /* abnormal */ + { + extern void uif_cmd_reset(void); + uif_cmd_reset(); + } +#endif +#endif /* DRIVER_IN_ROM */ + +#if 1 + DPRINT("radeonfb: radeonfb_pci_register: fixup display base address\r\n"); + OUTREG(MC_FB_LOCATION, 0x7fff0000); + rinfo->fb_local_base = 0; + /* Fixup the display base addresses & engine offsets while we + * are at it as well + */ + OUTREG(DISPLAY_BASE_ADDR, 0); + if (rinfo->has_CRTC2) + OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0); + OUTREG(OV0_BASE_ADDR, 0); +#else + rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; +#endif + + /* Get VRAM size and type */ + DPRINT("radeonfb: radeonfb_pci_register: get VRAM size\r\n"); + radeon_identify_vram(rinfo); + + if ((rinfo->fb_base == NULL) + || ((rinfo->video_ram > rinfo->mapped_vram) && (rinfo->mapped_vram < MIN_MAPPED_VRAM*2))) + { + DPRINTVAL("radeonfb: cannot map FB, video ram: ",rinfo->mapped_vram / 1024); + DPRINT("KB\r\n"); + framebuffer_release(info); + return -2; //(-EIO); + } + + /* Get informations about the board's PLL */ + DPRINT("radeonfb: radeonfb_pci_register: get informations about the board's PLL\r\n"); + radeon_get_pllinfo(rinfo); + +#ifdef CONFIG_FB_RADEON_I2C + /* Register I2C bus */ + DPRINT("radeonfb: radeonfb_pci_register: register I2C bus\r\n"); + radeon_create_i2c_busses(rinfo); +#endif /* CONFIG_FB_RADEON_I2C */ + + /* set all the vital stuff */ + DPRINT("radeonfb: radeonfb_pci_register: set all the vital stuff\r\n"); + radeon_set_fbinfo(rinfo); + + /* set offscreen memory descriptor */ + DPRINT("radeonfb: radeonfb_pci_register: set offscreen memory descriptor\r\n"); + offscreen_init(info); + + /* Probe screen types */ + DPRINT("radeonfb: radeonfb_pci_register: probe screen types, monitor_layout: "); + DPRINT(monitor_layout); + DPRINT("\r\n"); + radeon_probe_screens(rinfo, monitor_layout, (int)ignore_edid); + + /* Build mode list, check out panel native model */ + DPRINT("radeonfb: radeonfb_pci_register: build mode list\r\n"); + radeon_check_modes(rinfo, &resolution); + + /* save current mode regs before we switch into the new one + * so we can restore this upon exit + */ + DPRINT("radeonfb: radeonfb_pci_register: save current mode\r\n"); + radeon_save_state(rinfo, &rinfo->init_state); + memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); + + /* Setup Power Management capabilities */ +// DPRINT("radeonfb: radeonfb_pci_register: setup power management\r\n"); +// radeonfb_pm_init(rinfo, (int)default_dynclk); + + DPRINT("radeonfb: radeonfb_pci_register: install VBL timer\r\n"); + rinfo->lvds_timer = 0; +#ifndef DRIVER_IN_ROM + install_vbl_timer(radeon_timer_func, 1); /* remove old vector */ +#else + install_vbl_timer(radeon_timer_func, 0); +#endif + //rinfo->RageTheatreCrystal = rinfo->RageTheatreTunerPort=rinfo->RageTheatreCompositePort = rinfo->RageTheatreSVideoPort = -1; + //rinfo->tunerType = -1; + return(0); +} + +#if 0 + +void radeonfb_pci_unregister(void) +{ + struct fb_info *info = info_fvdi; + struct radeonfb_info *rinfo = info->par; +// radeonfb_pm_exit(rinfo); + uninstall_vbl_timer(radeon_timer_func); + if (rinfo->mon1_EDID!=NULL) + Funcs_free(rinfo->mon1_EDID); + if (rinfo->mon2_EDID!=NULL) + Funcs_free(rinfo->mon2_EDID); + if (rinfo->mon1_modedb) + fb_destroy_modedb(rinfo->mon1_modedb); +#ifdef CONFIG_FB_RADEON_I2C + radeon_delete_i2c_busses(rinfo); +#endif + framebuffer_release(info); +} + +#endif + + diff --git a/BaS_gcc/sys/BaS.c b/BaS_gcc/sys/BaS.c index 43027e1..9e629bf 100644 --- a/BaS_gcc/sys/BaS.c +++ b/BaS_gcc/sys/BaS.c @@ -44,6 +44,15 @@ #include "nbuf.h" #include "nif.h" #include "fec.h" +#include "interrupts.h" +#include "exceptions.h" + +#define BAS_DEBUG +#if defined(BAS_DEBUG) +#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif /* imported routines */ extern int mmu_init(); @@ -61,11 +70,6 @@ extern uint8_t _EMUTOS[]; extern uint8_t _EMUTOS_SIZE[]; #define EMUTOS_SIZE ((uint32_t)_EMUTOS_SIZE) /* size of EmuTOS, in bytes */ -NIF nif1; -#ifdef MACHINE_M5484LITE -NIF nif2; -#endif - /* * check if it is possible to transfer data to PIC */ @@ -126,7 +130,7 @@ void pic_init(void) if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!') { - xprintf("PIC initialization failed. Already initialized?\r\n"); + dbg("%s: PIC initialization failed. Already initialized?\r\n", __FUNCTION__); } else { @@ -236,24 +240,47 @@ void disable_coldfire_interrupts() +NIF nif1; +#ifdef MACHINE_M5484LITE +NIF nif2; +#endif +static IP_INFO ip_info; +static ARP_INFO arp_info; + + void network_init(void) { uint8_t mac[6] = {0x00, 0x04, 0x9f, 0x01, 0x01, 0x01}; /* this is a Freescale MAC address */ uint8_t bc[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; /* this is our broadcast MAC address */ - IP_ADDR myip = {0, 0, 0, 0}; - IP_ADDR gateway = {0, 0, 0, 0}; - IP_ADDR netmask = {0, 0, 0, 0}; - IP_INFO info; + IP_ADDR myip = {192, 168, 1, 100}; + IP_ADDR gateway = {192, 168, 1, 1}; + IP_ADDR netmask = {255, 255, 255, 0}; + int vector; + int (*handler)(void *, void *); + + handler = fec0_interrupt_handler; + vector = 103; + + if (!isr_register_handler(ISR_DBUG_ISR, vector, handler, NULL, (void *) &nif1)) + { + dbg("%s: unable to register handler\r\n", __FUNCTION__); + return; + } - fec_eth_setup(0, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac); nif_init(&nif1); nif1.mtu = ETH_MTU; nif1.send = fec0_send; + fec_eth_setup(0, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac); + fec_eth_setup(1, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac); memcpy(nif1.hwa, mac, 6); memcpy(nif1.broadcast, bc, 6); - ip_init(&info, myip, gateway, netmask); - udp_init(); + arp_init(&arp_info); + nif_bind_protocol(&nif1, ETH_FRM_ARP, arp_handler, (void *) &arp_info); + + ip_init(&ip_info, myip, gateway, netmask); + nif_bind_protocol(&nif1, ETH_FRM_IP, ip_handler, (void *) &ip_info); + bootp_request(&nif1, 0); } @@ -324,6 +351,7 @@ void BaS(void) enable_coldfire_interrupts(); +#ifdef _NOT_USED_ screen_init(); /* experimental */ @@ -346,6 +374,7 @@ void BaS(void) } } } +#endif /* _NOT_USED_ */ #endif /* MACHINE_FIREBEE */ @@ -392,7 +421,8 @@ void BaS(void) xprintf("BaS initialization finished, enable interrupts\r\n"); enable_coldfire_interrupts(); - // network_init(); + set_ipl(0); + network_init(); xprintf("call EmuTOS\r\n"); ROM_HEADER* os_header = (ROM_HEADER*)TOS; diff --git a/BaS_gcc/sys/exceptions.S b/BaS_gcc/sys/exceptions.S index 6f66eec..4ac892d 100644 --- a/BaS_gcc/sys/exceptions.S +++ b/BaS_gcc/sys/exceptions.S @@ -295,12 +295,19 @@ init_vec_loop: lea handler_psc3(pc),a1 // PSC3 interrupt source = 32 move.l a1,(INT_SOURCE_PSC3 + 64) * 4(a0) -// timer vectors (used for video page copy on the FireBee) +// timer vectors (triggers when vbashi gets changed, used for video page copy) lea handler_gpt0(pc),a1 // GPT0 interrupt source = 62 move.l a1,(INT_SOURCE_GPT0 + 64) * 4(a0) #endif /* MACHINE_FIREBEE */ + lea _lowlevel_isr_handler,a1 + move.l a1,(INT_SOURCE_GPT1 + 64) * 4(a0) + move.l a1,(INT_SOURCE_GPT2 + 64) * 4(a0) + move.l a1,(INT_SOURCE_GPT3 + 64) * 4(a0) + move.l a1,(INT_SOURCE_FEC0 + 64) * 4(a0) + move.l a1,(INT_SOURCE_FEC1 + 64) * 4(a0) + move.l (sp)+,a2 // Restore registers rts /* @@ -462,7 +469,6 @@ flpoow: halt nop nop - #endif /* _NOT_USED */ irq1: @@ -977,10 +983,10 @@ video_chg_end: * low-level interrupt service routine for routines registered with * isr_register_handler() */ - .global _asm_isr_handler + .global _lowlevel_isr_handler .extern _isr_execute_handler -_asm_isr_handler: +_lowlevel_isr_handler: link a6,#-4*4 movem.l d0-d1/a0-a1,(sp) @@ -991,13 +997,11 @@ _asm_isr_handler: jsr _isr_execute_handler lea 4(sp),sp cmp.l #1,d0 - //beq handled -#ifdef _NOT_USED_ + beq handled nothandled: movem.l (sp),d0-d1/a0-a1 unlk a6 - jmp asm_exception_handler -#endif /* _NOT_USED_ */ + jmp std_exc_vec handled: movem.l (sp),d0-d1/a0-a1 unlk a6 diff --git a/BaS_gcc/sys/interrupts.c b/BaS_gcc/sys/interrupts.c index ec28b77..0851c09 100644 --- a/BaS_gcc/sys/interrupts.c +++ b/BaS_gcc/sys/interrupts.c @@ -34,6 +34,13 @@ extern void (*rt_vbr[])(void); #define VBR rt_vbr +#define IRQ_DEBUG +#if defined(IRQ_DEBUG) +#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0) +#else +#define dbg(format, arg...) do { ; } while (0) +#endif + /* * register an interrupt handler at the Coldfire interrupt controller and add the handler to * the interrupt vector table @@ -113,8 +120,7 @@ void isr_init(void) } -int isr_register_handler ( - int type, int vector, +int isr_register_handler(int type, int vector, int (*handler)(void *, void *), void *hdev, void *harg) { /* @@ -131,7 +137,8 @@ int isr_register_handler ( ((type != ISR_DBUG_ISR) && (type != ISR_USER_ISR)) || (handler == NULL)) { - return true; + dbg("%s: illegal type, vector or handler!\r\n", __FUNCTION__); + return false; } for (index = 0; index < UIF_MAX_ISR_ENTRY; index++) @@ -140,7 +147,8 @@ int isr_register_handler ( (isrtab[index].type == type)) { /* only one entry of each type per vector */ - return 0; + dbg("%s: already set handler with this type and vector (%d, %d)\r\n", __FUNCTION__, type, vector); + return false; } if (isrtab[index].vector == 0) @@ -150,9 +158,10 @@ int isr_register_handler ( isrtab[index].handler = handler; isrtab[index].hdev = hdev; isrtab[index].harg = harg; - return 1; + return true; } } + dbg("%s: no available slots\n\t", __FUNCTION__); return false; /* no available slots */ } diff --git a/BaS_gcc/video/video.c b/BaS_gcc/video/video.c index d1a46fb..a2db339 100644 --- a/BaS_gcc/video/video.c +++ b/BaS_gcc/video/video.c @@ -226,20 +226,20 @@ void screen_init(void) * resolution / video mode appropriately */ monitor_type = MON_COLOR; - xprintf("monitor_type = %d\n", monitor_type); + xprintf("monitor_type = %d\r\n", monitor_type); /* reset VIDEL on boot-up */ /* first set the physbase to a safe memory */ - setphys(0xd00000,0); + setphys(0xd00000, 0); if (!lookup_videl_mode(boot_resolution, monitor_type)) { /* mode isn't in table */ - xprintf("Invalid video mode 0x%04x changed to 0x%04x\n", + xprintf("Invalid video mode 0x%04x changed to 0x%04x\r\n", boot_resolution, FALCON_DEFAULT_BOOT); boot_resolution = FALCON_DEFAULT_BOOT; /* so pick one that is */ } if (!VALID_VDI_BPP(boot_resolution)) { /* mustn't confuse VDI */ - xprintf("VDI doesn't support video mode 0x%04x, changed to 0x%04x\n", + xprintf("VDI doesn't support video mode 0x%04x, changed to 0x%04x\r\n", boot_resolution, FALCON_DEFAULT_BOOT); boot_resolution = FALCON_DEFAULT_BOOT; /* so use default */ }