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rename file and paths to lower case

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This commit is contained in:
Markus Fröschle
2016-07-29 06:29:14 +00:00
parent 31a9e1dd7a
commit 97abde82b9
236 changed files with 133 additions and 131 deletions
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47
video/BLITTER/BLITTER.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity blitter is
port
(
nRSTO : in std_logic;
MAIN_CLK : in std_logic;
FB_ALE : in std_logic;
nFB_WR : in std_logic;
nFB_OE : in std_logic;
FB_SIZE0 : in std_logic;
FB_SIZE1 : in std_logic;
VIDEO_RAM_CTR : in std_logic_vector(15 downto 0);
BLITTER_ON : in std_logic;
FB_ADR : in std_logic_vector(31 downto 0);
nFB_CS1 : in std_logic;
nFB_CS2 : in std_logic;
nFB_CS3 : in std_logic;
DDRCLK0 : in std_logic;
BLITTER_DIN : in std_logic_vector(127 downto 0);
BLITTER_DACK : in std_logic_vector(4 downto 0);
SR_BLITTER_DACK : in std_logic;
blitter_run : out std_logic;
blitter_dout : out std_logic_vector(127 downto 0);
blitter_adr : out std_logic_vector(31 downto 0);
blitter_sig : out std_logic;
blitter_wr : out std_logic;
blitter_ta : out std_logic;
fb_ad_in : in std_logic_vector(31 downto 0);
fb_ad_out : out std_logic_vector(31 downto 0)
);
end BLITTER;
architecture rtl of blitter is
begin
blitter_run <= '0';
blitter_dout <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
blitter_adr <= x"76543210";
blitter_sig <= '0';
blitter_wr <= '0';
blitter_ta <= '0';
fb_ad_out <= (others => 'Z');
end rtl;

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video/BLITTER/altsyncram0.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.cmp"]

6
video/BLITTER/lpm_clshift0.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.cmp"]

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video/altddio_bidir0.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 240 136)
(text "altddio_bidir0" (rect 82 1 171 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 120 25 132)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "datain_h[31..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "datain_l[31..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
(text "datain_l[31..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "oe" (rect 4 43 16 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 0 72)
(input)
(text "inclock" (rect 0 0 38 14)(font "Arial" (font_size 8)))
(text "inclock" (rect 4 59 36 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 88 72)(line_width 1))
)
(port
(pt 0 88)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 75 42 88)(font "Arial" (font_size 8)))
(line (pt 0 88)(pt 88 88)(line_width 1))
)
(port
(pt 240 24)
(output)
(text "dataout_h[31..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
(text "dataout_h[31..0]" (rect 159 11 237 24)(font "Arial" (font_size 8)))
(line (pt 240 24)(pt 144 24)(line_width 3))
)
(port
(pt 240 40)
(output)
(text "dataout_l[31..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
(text "dataout_l[31..0]" (rect 163 27 238 40)(font "Arial" (font_size 8)))
(line (pt 240 40)(pt 144 40)(line_width 3))
)
(port
(pt 240 72)
(output)
(text "combout[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "combout[31..0]" (rect 166 59 237 72)(font "Arial" (font_size 8)))
(line (pt 240 72)(pt 144 72)(line_width 3))
)
(port
(pt 240 56)
(bidir)
(text "padio[31..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
(text "padio[31..0]" (rect 181 43 238 56)(font "Arial" (font_size 8)))
(line (pt 240 56)(pt 144 56)(line_width 3))
)
(drawing
(text "ddio" (rect 108 27 129 40)(font "Arial" (font_size 8)))
(text "bidir" (rect 108 42 129 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 90 129 102)(font "Arial" ))
(text "low" (rect 92 100 105 112)(font "Arial" ))
(line (pt 88 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 112)(line_width 1))
(line (pt 144 112)(pt 88 112)(line_width 1))
(line (pt 88 112)(pt 88 16)(line_width 1))
)
)

29
video/altddio_bidir0.cmp Normal file
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altddio_bidir0
PORT
(
datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
inclock : IN STD_LOGIC ;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;

30
video/altddio_bidir0.inc Normal file
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altddio_bidir0
(
datain_h[31..0],
datain_l[31..0],
inclock,
oe,
outclock
)
RETURNS (
combout[31..0],
dataout_h[31..0],
dataout_l[31..0],
padio[31..0]
);

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video/altddio_bidir0.ppf Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altddio_bidir0" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
<global>
<pin name="datain_h[31..0]" direction="input" scope="external" />
<pin name="datain_l[31..0]" direction="input" scope="external" />
<pin name="inclock" direction="input" scope="external" source="clock" />
<pin name="oe" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="combout[31..0]" direction="output" scope="external" />
<pin name="dataout_h[31..0]" direction="output" scope="external" />
<pin name="dataout_l[31..0]" direction="output" scope="external" />
<pin name="padio[31..0]" direction="bidir" scope="external" />
</global>
</pinplan>

7
video/altddio_bidir0.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"]

172
video/altddio_bidir0.vhd Normal file
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-- megafunction wizard: %ALTDDIO_BIDIR%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altddio_bidir
-- ============================================================
-- File Name: altddio_bidir0.vhd
-- Megafunction Name(s):
-- altddio_bidir
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altddio_bidir0 IS
PORT
(
datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
inclock : IN STD_LOGIC ;
oe : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END altddio_bidir0;
ARCHITECTURE SYN OF altddio_bidir0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altddio_bidir
GENERIC (
extend_oe_disable : STRING;
implement_input_in_lcell : STRING;
intended_device_family : STRING;
invert_output : STRING;
lpm_type : STRING;
oe_reg : STRING;
power_up_high : STRING;
width : NATURAL
);
PORT (
outclock : IN STD_LOGIC ;
padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
inclock : IN STD_LOGIC ;
dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
oe : IN STD_LOGIC ;
datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout_h <= sub_wire0(31 DOWNTO 0);
combout <= sub_wire1(31 DOWNTO 0);
dataout_l <= sub_wire2(31 DOWNTO 0);
altddio_bidir_component : altddio_bidir
GENERIC MAP (
extend_oe_disable => "UNUSED",
implement_input_in_lcell => "ON",
intended_device_family => "Cyclone III",
invert_output => "OFF",
lpm_type => "altddio_bidir",
oe_reg => "UNUSED",
power_up_high => "OFF",
width => 32
)
PORT MAP (
outclock => outclock,
inclock => inclock,
oe => oe,
datain_h => datain_h,
datain_l => datain_l,
dataout_h => sub_wire0,
combout => sub_wire1,
dataout_l => sub_wire2,
padio => padio
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: OE NUMERIC "1"
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1"
-- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1"
-- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH NUMERIC "32"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0]
-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0]
-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0]
-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0]
-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0]
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0]
-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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video/altddio_out0.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
(text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 3))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "high" (rect 92 84 109 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

24
video/altddio_out0.cmp Normal file
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@@ -0,0 +1,24 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altddio_out0
PORT
(
datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end component;

25
video/altddio_out0.inc Normal file
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altddio_out0
(
datain_h[3..0],
datain_l[3..0],
outclock
)
RETURNS (
dataout[3..0]
);

11
video/altddio_out0.ppf Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altddio_out0" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
<global>
<pin name="datain_h[3..0]" direction="input" scope="external" />
<pin name="datain_l[3..0]" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="dataout[3..0]" direction="output" scope="external" />
</global>
</pinplan>

7
video/altddio_out0.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"]

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-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altddio_out
-- ============================================================
-- File Name: altddio_out0.vhd
-- Megafunction Name(s):
-- altddio_out
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altddio_out0 IS
PORT
(
datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END altddio_out0;
ARCHITECTURE SYN OF altddio_out0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altddio_out
GENERIC (
extend_oe_disable : STRING;
intended_device_family : STRING;
invert_output : STRING;
lpm_type : STRING;
oe_reg : STRING;
power_up_high : STRING;
width : NATURAL
);
PORT (
dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
outclock : IN STD_LOGIC ;
datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(3 DOWNTO 0);
altddio_out_component : altddio_out
GENERIC MAP (
extend_oe_disable => "UNUSED",
intended_device_family => "Cyclone III",
invert_output => "ON",
lpm_type => "altddio_out",
oe_reg => "UNUSED",
power_up_high => "ON",
width => 4
)
PORT MAP (
outclock => outclock,
datain_h => datain_h,
datain_l => datain_l,
dataout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: OE NUMERIC "0"
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "1"
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH NUMERIC "4"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
-- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
-- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out1" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 1))
)
(port
(pt 0 40)
(input)
(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 1))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 1))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "low" (rect 92 84 105 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altddio_out1
PORT
(
datain_h : IN STD_LOGIC ;
datain_l : IN STD_LOGIC ;
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC
);
end component;

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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altddio_out1
(
datain_h,
datain_l,
outclock
)
RETURNS (
dataout
);

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altddio_out1" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
<global>
<pin name="datain_h" direction="input" scope="external" />
<pin name="datain_l" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="dataout" direction="output" scope="external" />
</global>
</pinplan>

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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"]

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-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altddio_out
-- ============================================================
-- File Name: altddio_out1.vhd
-- Megafunction Name(s):
-- altddio_out
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altddio_out1 IS
PORT
(
datain_h : IN STD_LOGIC ;
datain_l : IN STD_LOGIC ;
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC
);
END altddio_out1;
ARCHITECTURE SYN OF altddio_out1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altddio_out
GENERIC (
extend_oe_disable : STRING;
intended_device_family : STRING;
invert_output : STRING;
lpm_type : STRING;
oe_reg : STRING;
power_up_high : STRING;
width : NATURAL
);
PORT (
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
outclock : IN STD_LOGIC ;
datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= sub_wire0(0);
dataout <= sub_wire1;
sub_wire2 <= datain_h;
sub_wire3(0) <= sub_wire2;
sub_wire4 <= datain_l;
sub_wire5(0) <= sub_wire4;
altddio_out_component : altddio_out
GENERIC MAP (
extend_oe_disable => "UNUSED",
intended_device_family => "Cyclone III",
invert_output => "OFF",
lpm_type => "altddio_out",
oe_reg => "UNUSED",
power_up_high => "OFF",
width => 1
)
PORT MAP (
outclock => outclock,
datain_h => sub_wire3,
datain_l => sub_wire5,
dataout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: OE NUMERIC "0"
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
(text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 3))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "low" (rect 92 84 105 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

24
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altddio_out2
PORT
(
datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
end component;

25
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altddio_out2
(
datain_h[23..0],
datain_l[23..0],
outclock
)
RETURNS (
dataout[23..0]
);

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altddio_out2" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
<global>
<pin name="datain_h[23..0]" direction="input" scope="external" />
<pin name="datain_l[23..0]" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="dataout[23..0]" direction="output" scope="external" />
</global>
</pinplan>

7
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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"]

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-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altddio_out
-- ============================================================
-- File Name: altddio_out2.vhd
-- Megafunction Name(s):
-- altddio_out
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altddio_out2 IS
PORT
(
datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END altddio_out2;
ARCHITECTURE SYN OF altddio_out2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
COMPONENT altddio_out
GENERIC (
extend_oe_disable : STRING;
intended_device_family : STRING;
invert_output : STRING;
lpm_type : STRING;
oe_reg : STRING;
power_up_high : STRING;
width : NATURAL
);
PORT (
dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
outclock : IN STD_LOGIC ;
datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(23 DOWNTO 0);
altddio_out_component : altddio_out
GENERIC MAP (
extend_oe_disable => "UNUSED",
intended_device_family => "Cyclone III",
invert_output => "OFF",
lpm_type => "altddio_out",
oe_reg => "UNUSED",
power_up_high => "OFF",
width => 24
)
PORT MAP (
outclock => outclock,
datain_h => datain_h,
datain_l => datain_l,
dataout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: OE NUMERIC "0"
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH NUMERIC "24"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "24"
-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0]
-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0]
-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0]
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

173
video/altdpram0.bsf Normal file
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@@ -0,0 +1,173 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 208)
(text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 192 25 204)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data_a[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data_a[2..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "address_a[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_a[3..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 112 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "data_b[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data_b[2..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 112 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "address_b[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_b[3..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 112 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 112 128)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 176 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 181 176)(line_width 1))
)
(port
(pt 256 32)
(output)
(text "q_a[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_a[2..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 192 32)(line_width 3))
)
(port
(pt 256 96)
(output)
(text "q_b[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_b[2..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
(line (pt 256 96)(pt 192 96)(line_width 3))
)
(drawing
(text "16 Word(s)" (rect 136 61 148 107)(font "Arial" )(vertical))
(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
(line (pt 128 24)(pt 168 24)(line_width 1))
(line (pt 168 24)(pt 168 144)(line_width 1))
(line (pt 168 144)(pt 128 144)(line_width 1))
(line (pt 128 144)(pt 128 24)(line_width 1))
(line (pt 112 27)(pt 120 27)(line_width 1))
(line (pt 120 27)(pt 120 39)(line_width 1))
(line (pt 120 39)(pt 112 39)(line_width 1))
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(line (pt 112 135)(pt 112 123)(line_width 1))
(line (pt 112 130)(pt 114 132)(line_width 1))
(line (pt 114 132)(pt 112 134)(line_width 1))
(line (pt 104 132)(pt 112 132)(line_width 1))
(line (pt 120 128)(pt 128 128)(line_width 1))
(line (pt 92 36)(pt 92 161)(line_width 1))
(line (pt 176 36)(pt 176 161)(line_width 1))
(line (pt 104 100)(pt 104 177)(line_width 1))
(line (pt 181 100)(pt 181 177)(line_width 1))
(line (pt 184 27)(pt 192 27)(line_width 1))
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(line (pt 181 100)(pt 184 100)(line_width 1))
(line (pt 168 96)(pt 184 96)(line_width 3))
)
)

30
video/altdpram0.cmp Normal file
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@@ -0,0 +1,30 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altdpram0
PORT
(
address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
end component;

31
video/altdpram0.inc Normal file
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@@ -0,0 +1,31 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altdpram0
(
address_a[3..0],
address_b[3..0],
clock_a,
clock_b,
data_a[2..0],
data_b[2..0],
wren_a,
wren_b
)
RETURNS (
q_a[2..0],
q_b[2..0]
);

6
video/altdpram0.qip Normal file
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@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram0.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.cmp"]

273
video/altdpram0.vhd Normal file
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@@ -0,0 +1,273 @@
-- megafunction wizard: %LPM_RAM_DP+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: altdpram0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altdpram0 IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END altdpram0;
ARCHITECTURE SYN OF altdpram0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(2 DOWNTO 0);
q_b <= sub_wire1(2 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 16,
numwords_b => 16,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "OLD_DATA",
read_during_write_mode_port_b => "OLD_DATA",
widthad_a => 4,
widthad_b => 4,
width_a => 3,
width_b => 3,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "48"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "3"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0]
-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 3 0 INPUT NODEFVAL data_a[2..0]
-- Retrieval info: USED_PORT: data_b 0 0 3 0 INPUT NODEFVAL data_b[2..0]
-- Retrieval info: USED_PORT: q_a 0 0 3 0 OUTPUT NODEFVAL q_a[2..0]
-- Retrieval info: USED_PORT: q_b 0 0 3 0 OUTPUT NODEFVAL q_b[2..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-- Retrieval info: CONNECT: @data_a 0 0 3 0 data_a 0 0 3 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 3 0 @q_a 0 0 3 0
-- Retrieval info: CONNECT: q_b 0 0 3 0 @q_b 0 0 3 0
-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
-- Retrieval info: CONNECT: @data_b 0 0 3 0 data_b 0 0 3 0
-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

173
video/altdpram1.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 208)
(text "altdpram1" (rect 100 1 167 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 192 25 204)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data_a[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data_a[5..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 112 48)(line_width 3))
)
(port
(pt 0 64)
(input)
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(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 1))
)
(port
(pt 0 96)
(input)
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(text "data_b[5..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 112 96)(line_width 3))
)
(port
(pt 0 112)
(input)
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(text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 112 112)(line_width 3))
)
(port
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(input)
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(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 112 128)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 176 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 181 176)(line_width 1))
)
(port
(pt 256 32)
(output)
(text "q_a[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_a[5..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 192 32)(line_width 3))
)
(port
(pt 256 96)
(output)
(text "q_b[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_b[5..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
(line (pt 256 96)(pt 192 96)(line_width 3))
)
(drawing
(text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
(line (pt 128 24)(pt 168 24)(line_width 1))
(line (pt 168 24)(pt 168 144)(line_width 1))
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)
)

30
video/altdpram1.cmp Normal file
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@@ -0,0 +1,30 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altdpram1
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;

31
video/altdpram1.inc Normal file
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@@ -0,0 +1,31 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altdpram1
(
address_a[7..0],
address_b[7..0],
clock_a,
clock_b,
data_a[5..0],
data_b[5..0],
wren_a,
wren_b
)
RETURNS (
q_a[5..0],
q_b[5..0]
);

6
video/altdpram1.qip Normal file
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@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.cmp"]

273
video/altdpram1.vhd Normal file
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@@ -0,0 +1,273 @@
-- megafunction wizard: %LPM_RAM_DP+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: altdpram1.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altdpram1 IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END altdpram1;
ARCHITECTURE SYN OF altdpram1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(5 DOWNTO 0);
q_b <= sub_wire1(5 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "OLD_DATA",
read_during_write_mode_port_b => "OLD_DATA",
widthad_a => 8,
widthad_b => 8,
width_a => 6,
width_b => 6,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "1536"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 6 0 INPUT NODEFVAL data_a[5..0]
-- Retrieval info: USED_PORT: data_b 0 0 6 0 INPUT NODEFVAL data_b[5..0]
-- Retrieval info: USED_PORT: q_a 0 0 6 0 OUTPUT NODEFVAL q_a[5..0]
-- Retrieval info: USED_PORT: q_b 0 0 6 0 OUTPUT NODEFVAL q_b[5..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-- Retrieval info: CONNECT: @data_a 0 0 6 0 data_a 0 0 6 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 6 0 @q_a 0 0 6 0
-- Retrieval info: CONNECT: q_b 0 0 6 0 @q_b 0 0 6 0
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
-- Retrieval info: CONNECT: @data_b 0 0 6 0 data_b 0 0 6 0
-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

173
video/altdpram2.bsf Normal file
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@@ -0,0 +1,173 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 208)
(text "altdpram2" (rect 100 1 167 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 192 25 204)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data_a[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data_a[7..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 112 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 1))
)
(port
(pt 0 96)
(input)
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(text "data_b[7..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 112 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 112 112)(line_width 3))
)
(port
(pt 0 128)
(input)
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(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 112 128)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 176 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 181 176)(line_width 1))
)
(port
(pt 256 32)
(output)
(text "q_a[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_a[7..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 192 32)(line_width 3))
)
(port
(pt 256 96)
(output)
(text "q_b[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_b[7..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
(line (pt 256 96)(pt 192 96)(line_width 3))
)
(drawing
(text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
(line (pt 128 24)(pt 168 24)(line_width 1))
(line (pt 168 24)(pt 168 144)(line_width 1))
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(line (pt 168 96)(pt 184 96)(line_width 3))
)
)

30
video/altdpram2.cmp Normal file
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@@ -0,0 +1,30 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component altdpram2
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

31
video/altdpram2.inc Normal file
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@@ -0,0 +1,31 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION altdpram2
(
address_a[7..0],
address_b[7..0],
clock_a,
clock_b,
data_a[7..0],
data_b[7..0],
wren_a,
wren_b
)
RETURNS (
q_a[7..0],
q_b[7..0]
);

6
video/altdpram2.qip Normal file
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@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram2.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.cmp"]

273
video/altdpram2.vhd Normal file
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@@ -0,0 +1,273 @@
-- megafunction wizard: %LPM_RAM_DP+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: altdpram2.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altdpram2 IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END altdpram2;
ARCHITECTURE SYN OF altdpram2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(7 DOWNTO 0);
q_b <= sub_wire1(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "OLD_DATA",
read_during_write_mode_port_b => "OLD_DATA",
widthad_a => 8,
widthad_b => 8,
width_a => 8,
width_b => 8,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri0" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "tridata[31..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "32" (rect 61 25 71 37)(font "Arial" ))
(text "32" (rect 13 25 23 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 56 28)(pt 64 20)(line_width 1))
(line (pt 8 28)(pt 16 20)(line_width 1))
)
)

23
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri0
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;

24
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_bustri0
(
data[31..0],
enabledt
)
RETURNS (
tridata[31..0]
);

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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri0.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri0.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri0 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_bustri0;
ARCHITECTURE SYN OF lpm_bustri0 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 32
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0]
-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[2..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[2..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "3" (rect 63 25 68 37)(font "Arial" ))
(text "3" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

23
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri1
PORT
(
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
end component;

5
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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri1.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri1 IS
PORT
(
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END lpm_bustri1;
ARCHITECTURE SYN OF lpm_bustri1 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 3
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "3"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL data[2..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 3 0 BIDIR NODEFVAL tridata[2..0]
-- Retrieval info: CONNECT: tridata 0 0 3 0 @tridata 0 0 3 0
-- Retrieval info: CONNECT: @data 0 0 3 0 data 0 0 3 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

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@@ -0,0 +1,56 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "18" (rect 61 25 71 37)(font "Arial" ))
(text "18" (rect 13 25 23 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 56 28)(pt 64 20)(line_width 1))
(line (pt 8 28)(pt 16 20)(line_width 1))
)
)

23
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri2
PORT
(
data : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
end component;

5
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@@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri2.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri2.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri2 IS
PORT
(
data : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
END lpm_bustri2;
ARCHITECTURE SYN OF lpm_bustri2 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 18
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "18"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
-- Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 18 0 BIDIR NODEFVAL tridata[17..0]
-- Retrieval info: CONNECT: tridata 0 0 18 0 @tridata 0 0 18 0
-- Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[5..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[5..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "6" (rect 63 25 68 37)(font "Arial" ))
(text "6" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri3
PORT
(
data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;

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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri3.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri3.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri3 IS
PORT
(
data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END lpm_bustri3;
ARCHITECTURE SYN OF lpm_bustri3 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 6
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "6"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
-- Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL data[5..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 6 0 BIDIR NODEFVAL tridata[5..0]
-- Retrieval info: CONNECT: tridata 0 0 6 0 @tridata 0 0 6 0
-- Retrieval info: CONNECT: @data 0 0 6 0 data 0 0 6 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri4" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[4..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[4..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[4..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[4..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "5" (rect 63 25 68 37)(font "Arial" ))
(text "5" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri4
PORT
(
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
end component;

5
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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri4.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri4.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri4 IS
PORT
(
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END lpm_bustri4;
ARCHITECTURE SYN OF lpm_bustri4 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 5
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 5 0 BIDIR NODEFVAL tridata[4..0]
-- Retrieval info: CONNECT: tridata 0 0 5 0 @tridata 0 0 5 0
-- Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

56
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri5" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[7..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "8" (rect 63 25 68 37)(font "Arial" ))
(text "8" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

23
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri5
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

24
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@@ -0,0 +1,24 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_bustri5
(
data[7..0],
enabledt
)
RETURNS (
tridata[7..0]
);

6
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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri5.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri5.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri5 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_bustri5;
ARCHITECTURE SYN OF lpm_bustri5 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 8
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0]
-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri6" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[23..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[23..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "tridata[23..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "24" (rect 61 25 71 37)(font "Arial" ))
(text "24" (rect 13 25 23 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 56 28)(pt 64 20)(line_width 1))
(line (pt 8 28)(pt 16 20)(line_width 1))
)
)

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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri6
PORT
(
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
end component;

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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri6.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri6.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri6 IS
PORT
(
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END lpm_bustri6;
ARCHITECTURE SYN OF lpm_bustri6 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 24
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "24"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 24 0 BIDIR NODEFVAL tridata[23..0]
-- Retrieval info: CONNECT: tridata 0 0 24 0 @tridata 0 0 24 0
-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

56
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri7" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[3..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[3..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[3..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[3..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "4" (rect 63 25 68 37)(font "Arial" ))
(text "4" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

23
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--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_bustri7
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end component;

5
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set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri7.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.cmp"]

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-- megafunction wizard: %LPM_BUSTRI%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_bustri
-- ============================================================
-- File Name: lpm_bustri7.vhd
-- Megafunction Name(s):
-- lpm_bustri
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_bustri7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
enabledt : IN STD_LOGIC ;
tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_bustri7;
ARCHITECTURE SYN OF lpm_bustri7 IS
COMPONENT lpm_bustri
GENERIC (
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enabledt : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
lpm_bustri_component : lpm_bustri
GENERIC MAP (
lpm_type => "LPM_BUSTRI",
lpm_width => 4
)
PORT MAP (
enabledt => enabledt,
data => data,
tridata => tridata
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
-- Retrieval info: USED_PORT: tridata 0 0 4 0 BIDIR NODEFVAL tridata[3..0]
-- Retrieval info: CONNECT: tridata 0 0 4 0 @tridata 0 0 4 0
-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

54
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 128 96)
(text "lpm_compare1" (rect 22 1 122 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 48)
(input)
(text "dataa[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "dataa[10..0]" (rect 20 42 77 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "datab[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "datab[10..0]" (rect 20 58 77 71)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 128 56)
(output)
(text "agb" (rect 0 0 21 14)(font "Arial" (font_size 8)))
(text "agb" (rect 91 50 109 63)(font "Arial" (font_size 8)))
(line (pt 128 56)(pt 112 56)(line_width 1))
)
(drawing
(text "unsigned compare" (rect 36 17 112 29)(font "Arial" ))
(line (pt 16 16)(pt 112 16)(line_width 1))
(line (pt 112 16)(pt 112 80)(line_width 1))
(line (pt 112 80)(pt 16 80)(line_width 1))
(line (pt 16 80)(pt 16 16)(line_width 1))
)
)

23
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_compare1
PORT
(
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
AgB : OUT STD_LOGIC
);
end component;

24
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@@ -0,0 +1,24 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_compare1
(
dataa[10..0],
datab[10..0]
)
RETURNS (
AgB
);

6
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set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_compare1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.cmp"]

127
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-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: lpm_compare1.vhd
-- Megafunction Name(s):
-- lpm_compare
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare1 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
AgB : OUT STD_LOGIC
);
END lpm_compare1;
ARCHITECTURE SYN OF lpm_compare1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
AgB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
AgB <= sub_wire0;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 11
)
PORT MAP (
dataa => dataa,
datab => datab,
AgB => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "1"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "11"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
-- Retrieval info: USED_PORT: AgB 0 0 0 0 OUTPUT NODEFVAL AgB
-- Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL dataa[10..0]
-- Retrieval info: USED_PORT: datab 0 0 11 0 INPUT NODEFVAL datab[10..0]
-- Retrieval info: CONNECT: AgB 0 0 0 0 @AgB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0
-- Retrieval info: CONNECT: @datab 0 0 11 0 datab 0 0 11 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "0" (rect 75 18 80 30)(font "Arial" ))
(text "5" (rect 87 25 92 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 82 28)(pt 90 20)(line_width 1))
)
)

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@@ -0,0 +1,21 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_constant0
PORT
(
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
end component;

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set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"]

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-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- lpm_constant
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(4 DOWNTO 0);
lpm_constant_component : lpm_constant
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 5
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "0" (rect 75 18 80 30)(font "Arial" ))
(text "2" (rect 87 25 92 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 82 28)(pt 90 20)(line_width 1))
)
)

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@@ -0,0 +1,21 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_constant1
PORT
(
result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
end component;

23
video/lpm_constant1.inc Normal file
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@@ -0,0 +1,23 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_constant1
(
)
RETURNS (
result[1..0]
);

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set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"]

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-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: lpm_constant1.vhd
-- Megafunction Name(s):
-- lpm_constant
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant1 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END lpm_constant1;
ARCHITECTURE SYN OF lpm_constant1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(1 DOWNTO 0);
lpm_constant_component : lpm_constant
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 2
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
-- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL result[1..0]
-- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

42
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@@ -0,0 +1,42 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "0" (rect 75 18 80 30)(font "Arial" ))
(text "8" (rect 87 25 92 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 82 28)(pt 90 20)(line_width 1))
)
)

21
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@@ -0,0 +1,21 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_constant2
PORT
(
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

5
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set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"]

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-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: lpm_constant2.vhd
-- Megafunction Name(s):
-- lpm_constant
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant2 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_constant2;
ARCHITECTURE SYN OF lpm_constant2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(7 DOWNTO 0);
lpm_constant_component : lpm_constant
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 8
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

42
video/lpm_constant3.bsf Normal file
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@@ -0,0 +1,42 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "0" (rect 75 18 80 30)(font "Arial" ))
(text "7" (rect 87 25 92 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 82 28)(pt 90 20)(line_width 1))
)
)

21
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@@ -0,0 +1,21 @@
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component lpm_constant3
PORT
(
result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
end component;

5
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set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"]

108
video/lpm_constant3.vhd Normal file
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@@ -0,0 +1,108 @@
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: lpm_constant3.vhd
-- Megafunction Name(s):
-- lpm_constant
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant3 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END lpm_constant3;
ARCHITECTURE SYN OF lpm_constant3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(6 DOWNTO 0);
lpm_constant_component : lpm_constant
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 7
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "7"
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm

42
video/lpm_constant4.bsf Normal file
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@@ -0,0 +1,42 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant4" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "result[10..0]" (rect 93 -31 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "2040" (rect 60 18 80 30)(font "Arial" ))
(text "11" (rect 85 25 95 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 80 28)(pt 88 20)(line_width 1))
)
)

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