add false paths to design constraints

2015-09-20 16:23:52 +00:00
parent f16d3498c5
commit 967a41de02
12 changed files with 1883 additions and 1864 deletions
--- a/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
+++ b/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
@@ -60,8 +60,8 @@
 --

 library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
+    use ieee.std_logic_1164.all;
+    use ieee.std_logic_unsigned.all;

 entity WF6850IP_TOP_SOC is
  port (