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set fastram end before start of RAM BaS
This commit is contained in:
Markus Fröschle
2013-08-04 18:40:36 +00:00
parent 0ba4a66da0
commit 945082684c
2 changed files with 14 additions and 0 deletions
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3
BaS_gcc/sources/BaS.c
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@@ -215,8 +215,10 @@ void BaS(void)
vec_init(); vec_init();
xprintf("finished\r\n"); xprintf("finished\r\n");
xprintf("enable MMU: ");
MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */ MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */
NOP(); /* force pipeline sync */ NOP(); /* force pipeline sync */
xprintf("finished\r\n");
xprintf("IDE reset: "); xprintf("IDE reset: ");
/* IDE reset */ /* IDE reset */
@@ -276,6 +278,7 @@ void BaS(void)
/* TT-RAM */ /* TT-RAM */
* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */ * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
* (uint32_t *) 0x5a4 = 0x1d000000;
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */ * (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
xprintf("init ACIA: "); xprintf("init ACIA: ");

11
BaS_gcc/sources/mmu.S
View File

@@ -186,7 +186,13 @@ _mmu_init:
* MMU table add on miss * MMU table add on miss
*/ */
_mmutr_miss: _mmutr_miss:
bsr cpusha // clear caches bsr cpusha // clear caches
pea MISS_text
move.l d0,-(sp)
bsr _xprintf
and.l #0xFFF00000,d0 // d0 is the address not found (MMUAR at the time of the exception) and.l #0xFFF00000,d0 // d0 is the address not found (MMUAR at the time of the exception)
or.l #std_mmutr,d0 // mark shared and valid or.l #std_mmutr,d0 // mark shared and valid
move.l d0,MCF_MMU_MMUTR // add to TLB move.l d0,MCF_MMU_MMUTR // add to TLB
@@ -197,5 +203,10 @@ _mmutr_miss:
move.l d0,MCF_MMU_MMUOR // set move.l d0,MCF_MMU_MMUOR // set
moveq.l #mmuord_i,d0 // MMU update instruction moveq.l #mmuord_i,d0 // MMU update instruction
move.l d0,MCF_MMU_MMUOR // set move.l d0,MCF_MMU_MMUOR // set
move.l (sp)+,d0 // restore register saved in acess move.l (sp)+,d0 // restore register saved in acess
rte rte
.data
MISS_text:
.asciz "MMU TLB MISS at %p"
.byte 13, 10, 0