Video/altdpram0.cmp

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+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altdpram0
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+end component;