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aschi54
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FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
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FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
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----------------------------------------------------------------------
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---- ----
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---- WF5380 IP Core ----
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---- ----
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---- Description: ----
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---- This model provides an asynchronous SCSI interface compa- ----
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---- tible to the DP5380 from National Semiconductor and others. ----
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---- ----
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---- This file is the top level file with tree state buses. ----
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---- ----
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---- ----
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---- ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Wolfgang Foerster ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/lgpl.html ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K9A 2009/06/20 WF
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-- Initial Release.
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--
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library work;
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use work.wf5380_pkg.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity WF5380_TOP is
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port (
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-- System controls:
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CLK : in bit;
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RESETn : in bit;
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-- Address and data:
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ADR : in std_logic_vector(2 downto 0);
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DATA : inout std_logic_vector(7 downto 0);
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-- Bus and DMA controls:
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CSn : in bit;
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RDn : in bit;
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WRn : in bit;
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EOPn : in bit;
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DACKn : in bit;
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DRQ : out bit;
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INT : out bit;
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READY : out bit;
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-- SCSI bus:
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DBn : inout std_logic_vector(7 downto 0);
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DBPn : inout std_logic;
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RSTn : inout std_logic;
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BSYn : inout std_logic;
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SELn : inout std_logic;
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ACKn : inout std_logic;
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ATNn : inout std_logic;
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REQn : inout std_logic;
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IOn : inout std_logic;
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CDn : inout std_logic;
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MSGn : inout std_logic
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);
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end entity WF5380_TOP;
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architecture STRUCTURE of WF5380_TOP is
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component WF5380_TOP_SOC
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port (
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-- System controls:
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CLK : in bit;
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RESETn : in bit;
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ADR : in bit_vector(2 downto 0);
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DATA_IN : in bit_vector(7 downto 0);
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DATA_OUT : out bit_vector(7 downto 0);
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DATA_EN : out bit;
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CSn : in bit;
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RDn : in bit;
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WRn : in bit;
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EOPn : in bit;
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DACKn : in bit;
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DRQ : out bit;
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INT : out bit;
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READY : out bit;
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DB_INn : in bit_vector(7 downto 0);
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DB_OUTn : out bit_vector(7 downto 0);
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DB_EN : out bit;
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DBP_INn : in bit;
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DBP_OUTn : out bit;
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DBP_EN : out bit;
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RST_INn : in bit;
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RST_OUTn : out bit;
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RST_EN : out bit;
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BSY_INn : in bit;
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BSY_OUTn : out bit;
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BSY_EN : out bit;
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SEL_INn : in bit;
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SEL_OUTn : out bit;
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SEL_EN : out bit;
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ACK_INn : in bit;
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ACK_OUTn : out bit;
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ACK_EN : out bit;
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ATN_INn : in bit;
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ATN_OUTn : out bit;
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ATN_EN : out bit;
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REQ_INn : in bit;
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REQ_OUTn : out bit;
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REQ_EN : out bit;
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IOn_IN : in bit;
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IOn_OUT : out bit;
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IO_EN : out bit;
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CDn_IN : in bit;
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CDn_OUT : out bit;
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CD_EN : out bit;
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MSG_INn : in bit;
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MSG_OUTn : out bit;
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MSG_EN : out bit
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);
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end component;
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--
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signal ADR_IN : bit_vector(2 downto 0);
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signal DATA_IN : bit_vector(7 downto 0);
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signal DATA_OUT : bit_vector(7 downto 0);
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signal DATA_EN : bit;
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signal DB_INn : bit_vector(7 downto 0);
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signal DB_OUTn : bit_vector(7 downto 0);
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signal DB_EN : bit;
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signal DBP_INn : bit;
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signal DBP_OUTn : bit;
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signal DBP_EN : bit;
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signal RST_INn : bit;
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signal RST_OUTn : bit;
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signal RST_EN : bit;
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signal BSY_INn : bit;
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signal BSY_OUTn : bit;
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signal BSY_EN : bit;
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signal SEL_INn : bit;
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signal SEL_OUTn : bit;
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signal SEL_EN : bit;
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signal ACK_INn : bit;
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signal ACK_OUTn : bit;
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signal ACK_EN : bit;
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signal ATN_INn : bit;
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signal ATN_OUTn : bit;
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signal ATN_EN : bit;
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signal REQ_INn : bit;
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signal REQ_OUTn : bit;
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signal REQ_EN : bit;
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signal IOn_IN : bit;
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signal IOn_OUT : bit;
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signal IO_EN : bit;
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signal CDn_IN : bit;
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signal CDn_OUT : bit;
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signal CD_EN : bit;
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signal MSG_INn : bit;
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signal MSG_OUTn : bit;
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signal MSG_EN : bit;
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begin
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ADR_IN <= To_BitVector(ADR);
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DATA_IN <= To_BitVector(DATA);
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DATA <= To_StdLogicVector(DATA_OUT) when DATA_EN = '1' else (others => 'Z');
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DB_INn <= To_BitVector(DBn);
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DBn <= To_StdLogicVector(DB_OUTn) when DB_EN = '1' else (others => 'Z');
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DBP_INn <= To_Bit(DBPn);
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RST_INn <= To_Bit(RSTn);
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BSY_INn <= To_Bit(BSYn);
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SEL_INn <= To_Bit(SELn);
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ACK_INn <= To_Bit(ACKn);
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ATN_INn <= To_Bit(ATNn);
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REQ_INn <= To_Bit(REQn);
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IOn_IN <= To_Bit(IOn);
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CDn_IN <= To_Bit(CDn);
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MSG_INn <= To_Bit(MSGn);
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DBPn <= '1' when DBP_OUTn = '1' and DBP_EN = '1' else
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'0' when DBP_OUTn = '0' and DBP_EN = '1' else 'Z';
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RSTn <= '1' when RST_OUTn = '1' and RST_EN = '1'else
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'0' when RST_OUTn = '0' and RST_EN = '1' else 'Z';
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BSYn <= '1' when BSY_OUTn = '1' and BSY_EN = '1' else
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'0' when BSY_OUTn = '0' and BSY_EN = '1' else 'Z';
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SELn <= '1' when SEL_OUTn = '1' and SEL_EN = '1' else
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'0' when SEL_OUTn = '0' and SEL_EN = '1' else 'Z';
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ACKn <= '1' when ACK_OUTn = '1' and ACK_EN = '1' else
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'0' when ACK_OUTn = '0' and ACK_EN = '1' else 'Z';
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ATNn <= '1' when ATN_OUTn = '1' and ATN_EN = '1' else
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'0' when ATN_OUTn = '0' and ATN_EN = '1' else 'Z';
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REQn <= '1' when REQ_OUTn = '1' and REQ_EN = '1' else
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'0' when REQ_OUTn = '0' and REQ_EN = '1' else 'Z';
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IOn <= '1' when IOn_OUT = '1' and IO_EN = '1' else
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'0' when IOn_OUT = '0' and IO_EN = '1' else 'Z';
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CDn <= '1' when CDn_OUT = '1' and CD_EN = '1' else
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'0' when CDn_OUT = '0' and CD_EN = '1' else 'Z';
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MSGn <= '1' when MSG_OUTn = '1' and MSG_EN = '1' else
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'0' when MSG_OUTn = '0' and MSG_EN = '1' else 'Z';
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I_5380: WF5380_TOP_SOC
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port map(
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CLK => CLK,
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RESETn => RESETn,
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ADR => ADR_IN,
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DATA_IN => DATA_IN,
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DATA_OUT => DATA_OUT,
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DATA_EN => DATA_EN,
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CSn => CSn,
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RDn => RDn,
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WRn => WRn,
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EOPn => EOPn,
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DACKn => DACKn,
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DRQ => DRQ,
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INT => INT,
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READY => READY,
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DB_INn => DB_INn,
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DB_OUTn => DB_OUTn,
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DB_EN => DB_EN,
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DBP_INn => DBP_INn,
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DBP_OUTn => DBP_OUTn,
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DBP_EN => DBP_EN,
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RST_INn => RST_INn,
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RST_OUTn => RST_OUTn,
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RST_EN => RST_EN,
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BSY_INn => BSY_INn,
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BSY_OUTn => BSY_OUTn,
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BSY_EN => BSY_EN,
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SEL_INn => SEL_INn,
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SEL_OUTn => SEL_OUTn,
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SEL_EN => SEL_EN,
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ACK_INn => ACK_INn,
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ACK_OUTn => ACK_OUTn,
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ACK_EN => ACK_EN,
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ATN_INn => ATN_INn,
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ATN_OUTn => ATN_OUTn,
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ATN_EN => ATN_EN,
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REQ_INn => REQ_INn,
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REQ_OUTn => REQ_OUTn,
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REQ_EN => REQ_EN,
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IOn_IN => IOn_IN,
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IOn_OUT => IOn_OUT,
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IO_EN => IO_EN,
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CDn_IN => CDn_IN,
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CDn_OUT => CDn_OUT,
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CD_EN => CD_EN,
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MSG_INn => MSG_INn,
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MSG_OUTn => MSG_OUTn,
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MSG_EN => MSG_EN
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);
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end STRUCTURE;
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