diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd index c374e2a..0a8054e 100644 --- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd +++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd @@ -1,37 +1,37 @@ ---------------------------------------------------------------------- ---- ---- ----- This file is part of the 'Firebee' project. ---- +---- This file IS part of the 'Firebee' project. ---- ---- http://acp.atari.org ---- ---- ---- ---- Description: ---- ---- This design unit provides the DDR controller of the 'Firebee'---- ----- computer. It is optimized for the use of an Altera Cyclone ---- ----- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- +---- computer. It IS optimized for the use of an Altera Cyclone ---- +---- FPGA (EP3C40F484). This IP-Core IS based on the first edi- ---- ---- tion of the Firebee configware originally provided by Fredi ---- ----- Ashwanden and Wolfgang Förster. This release is in compa- ---- ----- rision to the first edition completely written in VHDL. ---- +---- AshwANDen AND Wolfgang Förster. This release IS IN compa- ---- +---- rision to the first edition completely written IN VHDL. ---- ---- ---- ---- Author(s): ---- ---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ---- ---- ---------------------------------------------------------------------- ---- ---- ----- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- +---- Copyright (C) 2012 Fredi AschwANDen, Wolfgang Förster ---- ---- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General Public ---- +---- This source file IS free software; you can redistribute it ---- +---- AND/OR modify it under the terms of the GNU General Public ---- ---- License as published by the Free Software Foundation; either ---- ----- version 2 of the License, or (at your option) any later ---- +---- version 2 of the License, OR (at your option) any later ---- ---- version. ---- ---- ---- ----- This program is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- This program IS distributed IN the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; WITHout even the implied ---- +---- warranty of MERCHANTABILITY OR FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU General Public ---- ----- License along with this program; if not, write to the Free ---- +---- License along WITH this program; IF NOT, write to the Free ---- ---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ---- Boston, MA 02110-1301, USA. ---- ---- ---- @@ -42,819 +42,822 @@ -- Revision 2K12B 20120801 WF -- Initial Release of the second edition. -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; +LIBRARY IEEE; + USE IEEE.std_logic_1164.ALL; + USE IEEE.numeric_std.ALL; -entity DDR_CTRL_V1 is - port( - CLK_MAIN : in std_logic; - DDR_SYNC_66M : in std_logic; - FB_ADR : in std_logic_vector(31 downto 0); - FB_CS1n : in std_logic; - FB_OEn : in std_logic; - FB_SIZE0 : in std_logic; - FB_SIZE1 : in std_logic; - FB_ALE : in std_logic; - FB_WRn : in std_logic; - FIFO_CLR : in std_logic; - VIDEO_RAM_CTR : in std_logic_vector(15 downto 0); - BLITTER_ADR : in std_logic_vector(31 downto 0); - BLITTER_SIG : in std_logic; - BLITTER_WR : in std_logic; - DDRCLK0 : in std_logic; - CLK_33M : in std_logic; - FIFO_MW : in std_logic_vector(8 downto 0); - - VA : out std_logic_vector(12 downto 0); -- video Adress bus at the DDR chips - VWEn : out std_logic; -- video memory write enable - VRASn : out std_logic; -- video memory RAS - VCSn : out std_logic; -- video memory chip select - VCKE : out std_logic; -- video memory clock enable - VCASn : out std_logic; -- video memory CAS - - FB_LE : out std_logic_vector(3 downto 0); - FB_VDOE : out std_logic_vector(3 downto 0); - - SR_FIFO_WRE : out std_logic; - SR_DDR_FB : out std_logic; - SR_DDR_WR : out std_logic; - SR_DDRWR_D_SEL : out std_logic; - SR_VDMP : out std_logic_vector(7 downto 0); - - VIDEO_DDR_TA : out std_logic; - SR_BLITTER_DACK : out std_logic; - BA : out std_logic_vector(1 downto 0); - DDRWR_D_SEL1 : out std_logic; - VDM_SEL : out std_logic_vector(3 downto 0); - DATA_IN : in std_logic_vector(31 downto 0); - DATA_OUT : out std_logic_vector(31 downto 16); - DATA_EN_H : out std_logic; - DATA_EN_L : out std_logic - ); -end entity DDR_CTRL_V1; +ENTITY DDR_CTRL_V1 IS + PORT( + clk_main : IN STD_LOGIC; + DDR_SYNC_66M : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + FB_CS1n : IN STD_LOGIC; + FB_OEn : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + FB_WRn : IN STD_LOGIC; + FIFO_CLR : IN STD_LOGIC; + video_control_register : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + BLITTER_ADR : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + blitter_sig : IN STD_LOGIC; + BLITTER_WR : IN STD_LOGIC; -architecture BEHAVIOUR of DDR_CTRL_V1 is - -- FIFO WATER MARK: - constant FIFO_LWM : integer := 0; -- low water mark - constant FIFO_MWM : integer := 200; -- medium water mark - constant FIFO_HWM : integer := 500; -- high water mark - - type ACCESS_WIDTH_TYPE is (LONG, WORD, BYTE); - type DDR_ACCESS_TYPE is (CPU, FIFO, BLITTER, NONE); - type FB_REGDDR_TYPE is (FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3); - type DDR_SM_TYPE is (DS_T1, DS_T2A, DS_T2B, DS_T3, DS_N5, DS_N6, DS_N7, DS_N8, -- Start (normal 8 cycles total = 60ns). - DS_C2, DS_C3, DS_C4, DS_C5, DS_C6, DS_C7, -- Configuration. - DS_T4R, DS_T5R, -- Read CPU or BLITTER. - DS_T4W, DS_T5W, DS_T6W, DS_T7W, DS_T8W, DS_T9W, -- Write CPU or BLITTER. - DS_T4F, DS_T5F, DS_T6F, DS_T7F, DS_T8F, DS_T9F, DS_T10F, -- Read FIFO. - DS_CB6, DS_CB8, -- Close FIFO bank. - DS_R2, DS_R3, DS_R4, DS_R5, DS_R6); -- Refresh: 10 x 7.5ns = 75ns. - - signal ACCESS_WIDTH : ACCESS_WIDTH_TYPE; - signal FB_REGDDR : FB_REGDDR_TYPE; - signal FB_REGDDR_NEXT : FB_REGDDR_TYPE; - signal DDR_ACCESS : DDR_ACCESS_TYPE; - signal DDR_STATE : DDR_SM_TYPE; - signal DDR_NEXT_STATE : DDR_SM_TYPE; - signal VCS_In : std_logic; - signal VCKE_I : std_logic; - signal BYTE_SEL : std_logic_vector(3 downto 0); - signal SR_FIFO_WRE_I : std_logic; - signal VCAS : std_logic; - signal VRAS : std_logic; - signal VWE : std_logic; - signal MCS : std_logic_vector(1 downto 0); - signal BUS_CYC : std_logic; - signal BUS_CYC_END : std_logic; - signal BLITTER_REQ : std_logic; - signal BLITTER_ROW_ADR : std_logic_vector(12 downto 0); - signal BLITTER_BA : std_logic_vector(1 downto 0); - signal BLITTER_COL_ADR : std_logic_vector(9 downto 0); - signal CPU_DDR_SYNC : std_logic; - signal CPU_ROW_ADR : std_logic_vector(12 downto 0); - signal CPU_BA : std_logic_vector(1 downto 0); - signal CPU_COL_ADR : std_logic_vector(9 downto 0); - signal CPU_REQ : std_logic; - signal DDR_SEL : std_logic; - signal DDR_CS : std_logic; - signal DDR_CONFIG : std_logic; - signal FIFO_REQ : std_logic; - signal FIFO_ROW_ADR : std_logic_vector(12 downto 0); - signal FIFO_BA : std_logic_vector(1 downto 0); - signal FIFO_COL_ADR : unsigned(9 downto 0); - signal FIFO_ACTIVE : std_logic; - signal FIFO_CLR_SYNC : std_logic; - signal VDM_SEL_I : std_logic_vector(3 downto 0); - signal CLEAR_FIFO_CNT : std_logic; - signal STOP : std_logic; - signal FIFO_BANK_OK : std_logic; - signal DDR_REFRESH_ON : std_logic; - signal DDR_REFRESH_CNT : unsigned(10 downto 0) := "00000000000"; - signal DDR_REFRESH_REQ : std_logic; - signal DDR_REFRESH_SIG : unsigned(3 downto 0); - signal REFRESH_TIME : std_logic; - signal VIDEO_BASE_L_D : std_logic_vector(7 downto 0); - signal VIDEO_BASE_L : std_logic; - signal VIDEO_BASE_M_D : std_logic_vector(7 downto 0); - signal VIDEO_BASE_M : std_logic; - signal VIDEO_BASE_H_D : std_logic_vector(7 downto 0); - signal VIDEO_BASE_H : std_logic; - signal VIDEO_BASE_X_D : std_logic_vector(2 downto 0); - signal VIDEO_ADR_CNT : unsigned(22 downto 0); - signal VIDEO_CNT_L : std_logic; - signal VIDEO_CNT_M : std_logic; - signal VIDEO_CNT_H : std_logic; - signal VIDEO_BASE_ADR : std_logic_vector(22 downto 0); - signal VIDEO_ACT_ADR : std_logic_vector(26 downto 0); - signal FB_ADR_I : std_logic_vector(32 downto 0); - - - signal VA_S : std_logic_vector(12 downto 0); - signal VA_P : std_logic_vector(12 downto 0); - signal BA_S : std_logic_vector(1 downto 0) ; - signal BA_P : std_logic_vector(1 downto 0); - signal TSIZ : std_logic_vector(1 downto 0); -begin - TSIZ <= FB_SIZE1 & FB_SIZE0; - with TSIZ select - ACCESS_WIDTH <= LONG when "11", - WORD when "00", - BYTE when others; + DDRCLK0 : IN STD_LOGIC; + CLK_33M : IN STD_LOGIC; + FIFO_MW : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + + VA : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); -- video Adress bus at the DDR chips + vwen : OUT STD_LOGIC; -- video memory write enable + vrasn : OUT STD_LOGIC; -- video memory RAS + VCSn : OUT STD_LOGIC; -- video memory chip SELECT + VCKE : OUT STD_LOGIC; -- video memory clock enable + vcasn : OUT STD_LOGIC; -- video memory CAS + + FB_LE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + FB_VDOE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + + sr_fifo_wre : OUT STD_LOGIC; + SR_DDR_FB : OUT STD_LOGIC; + SR_DDR_WR : OUT STD_LOGIC; + SR_DDRWR_D_SEL : OUT STD_LOGIC; + SR_VDMP : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + + VIDEO_DDR_TA : OUT STD_LOGIC; + SR_BLITTER_DACK : OUT STD_LOGIC; + BA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + ddrwr_d_sel1 : OUT STD_LOGIC; + VDM_SEL : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + DATA_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 16); + DATA_EN_H : OUT STD_LOGIC; + DATA_EN_L : OUT STD_LOGIC + ); +END ENTITY DDR_CTRL_V1; - -- Byte selectors: - BYTE_SEL(0) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else - '1' when FB_ADR(1 downto 0) = "00" else '0'; -- Byte 0. +ARCHITECTURE BEHAVIOUR of DDR_CTRL_V1 IS + -- FIFO WATER MARK: + CONSTANT FIFO_LWM : INTEGER := 0; -- low water mark + CONSTANT FIFO_MWM : INTEGER := 200; -- medium water mark + CONSTANT FIFO_HWM : INTEGER := 500; -- high water mark + + -- constants for bits IN video_control_register + CONSTANT vrcr_vcke : INTEGER := 0; + CONSTANT vrcr_vcs : INTEGER := 1; + CONSTANT vrcr_refresh_on : INTEGER := 2; + CONSTANT vrcr_config_on : INTEGER := 3; + -- + CONSTANT vrcr_fifo_on : INTEGER := 24; + CONSTANT vrcr_border_on : INTEGER := 25; + + TYPE access_width_t IS (LONG, WORD, BYTE); + TYPE ddr_access_t IS (CPU, FIFO, BLITTER, NONE); + TYPE fb_regddr_t IS (FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3); + TYPE ddr_sm_t IS (DS_T1, DS_T2A, DS_T2B, DS_T3, DS_N5, DS_N6, DS_N7, DS_N8, -- Start (normal 8 cycles total = 60ns). + DS_C2, DS_C3, DS_C4, DS_C5, DS_C6, DS_C7, -- Configuration. + DS_T4R, DS_T5R, -- Read CPU OR BLITTER. + DS_T4W, DS_T5W, DS_T6W, DS_T7W, DS_T8W, DS_T9W, -- Write CPU OR BLITTER. + DS_T4F, DS_T5F, DS_T6F, DS_T7F, DS_T8F, DS_T9F, DS_T10F, -- Read FIFO. + DS_CB6, DS_CB8, -- Close FIFO bank. + DS_R2, DS_R3, DS_R4, DS_R5, DS_R6); -- Refresh: 10 x 7.5ns = 75ns. + + SIGNAL access_width : access_width_t; + SIGNAL fb_regddr : fb_regddr_t; + SIGNAL fb_regddr_next : fb_regddr_t; + SIGNAL ddr_access : ddr_access_t; + SIGNAL ddr_state : ddr_sm_t; + SIGNAL ddr_next_state : ddr_sm_t; + SIGNAL byte_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL sr_fifo_wre_i : STD_LOGIC; + SIGNAL vcas : STD_LOGIC; + SIGNAL vras : STD_LOGIC; + SIGNAL vwe : STD_LOGIC; + SIGNAL mcs : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL bus_cyc : STD_LOGIC; + SIGNAL bus_cyc_end : STD_LOGIC; + SIGNAL blitter_req : STD_LOGIC; + SIGNAL blitter_row_adr : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL blitter_ba : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL blitter_col_adr : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL cpu_ddr_sync : STD_LOGIC; + SIGNAL cpu_row_adr : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL cpu_ba : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL cpu_col_adr : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL cpu_req : STD_LOGIC; + SIGNAL ddr_sel : STD_LOGIC; + SIGNAL ddr_cs : STD_LOGIC; + SIGNAL ddr_config : STD_LOGIC; + SIGNAL fifo_req : STD_LOGIC; + SIGNAL fifo_row_adr : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL fifo_ba : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL fifo_col_adr : UNSIGNED(9 DOWNTO 0); + SIGNAL fifo_active : STD_LOGIC; + SIGNAL fifo_clr_sync : STD_LOGIC; + SIGNAL vdm_sel_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL clear_fifo_cnt : STD_LOGIC; + SIGNAL stop : STD_LOGIC; + SIGNAL fifo_bank_ok : STD_LOGIC; + SIGNAL ddr_refresh_cnt : UNSIGNED(10 DOWNTO 0) := "00000000000"; + SIGNAL ddr_refresh_req : STD_LOGIC; + SIGNAL ddr_refresh_sig : UNSIGNED(3 DOWNTO 0); + SIGNAL refresh_time : STD_LOGIC; + SIGNAL video_base_l_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL video_base_l : STD_LOGIC; + SIGNAL video_base_m_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL video_base_m : STD_LOGIC; + SIGNAL video_base_h_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL video_base_h : STD_LOGIC; + SIGNAL video_base_x_d : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL video_adr_cnt : UNSIGNED(22 DOWNTO 0); + SIGNAL video_cnt_l : STD_LOGIC; + SIGNAL video_cnt_m : STD_LOGIC; + SIGNAL video_cnt_h : STD_LOGIC; + SIGNAL video_base_adr : STD_LOGIC_VECTOR (22 DOWNTO 0); + SIGNAL video_act_adr : STD_LOGIC_VECTOR (26 DOWNTO 0); + SIGNAL fb_adr_i : STD_LOGIC_VECTOR (32 DOWNTO 0); + + + SIGNAL va_s : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL va_p : STD_LOGIC_VECTOR (12 DOWNTO 0); + SIGNAL ba_s : STD_LOGIC_VECTOR (1 DOWNTO 0) ; + SIGNAL ba_p : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL tsiz : STD_LOGIC_VECTOR (1 DOWNTO 0); +BEGIN + tsiz <= FB_SIZE1 & FB_SIZE0; + WITH tsiz SELECT + access_width <= LONG WHEN "11", + WORD WHEN "00", + BYTE WHEN OTHERS; - BYTE_SEL(1) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else - '1' when ACCESS_WIDTH = BYTE and FB_ADR(1) = '0' else -- High word. - '1' when FB_ADR(1 downto 0) = "01" else '0'; -- Byte 1. + -- Byte selectors: + byte_sel(0) <= '1' WHEN access_width = LONG OR access_width = WORD ELSE + '1' WHEN FB_ADR(1 DOWNTO 0) = "00" ELSE '0'; -- Byte 0. + + byte_sel(1) <= '1' WHEN access_width = LONG OR access_width = WORD ELSE + '1' WHEN access_width = BYTE AND FB_ADR(1) = '0' ELSE -- High word. + '1' WHEN FB_ADR(1 DOWNTO 0) = "01" ELSE '0'; -- Byte 1. - BYTE_SEL(2) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else - '1' when FB_ADR(1 downto 0) = "10" else '0'; -- Byte 2. + byte_sel(2) <= '1' WHEN access_width = LONG OR access_width = WORD ELSE + '1' WHEN FB_ADR(1 DOWNTO 0) = "10" ELSE '0'; -- Byte 2. - BYTE_SEL(3) <= '1' when ACCESS_WIDTH = LONG or ACCESS_WIDTH = WORD else - '1' when ACCESS_WIDTH = BYTE and FB_ADR(1) = '1' else -- Low word. - '1' when FB_ADR(1 downto 0) = "11" else '0'; -- Byte 3. + byte_sel(3) <= '1' WHEN access_width = LONG OR access_width = WORD ELSE + '1' WHEN access_width = BYTE AND FB_ADR(1) = '1' ELSE -- Low word. + '1' WHEN FB_ADR(1 DOWNTO 0) = "11" ELSE '0'; -- Byte 3. - --------------------------------------------------------------------------------------------------------------------------------------------------------------- - ------------------------------------ CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------------------------- - FBCTRL_REG: process - begin - wait until rising_edge(CLK_MAIN); - FB_REGDDR <= FB_REGDDR_NEXT; - end process FBCTRL_REG; + --------------------------------------------------------------------------------------------------------------------------------------------------------------- + ------------------------------------ CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------------------------- + fbctrl_reg : PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(clk_main); + fb_regddr <= fb_regddr_next; + END PROCESS FBCTRL_REG; - FBCTRL_DEC: process(FB_REGDDR, BUS_CYC, DDR_SEL, ACCESS_WIDTH, FB_WRn, DDR_CS) - begin - case FB_REGDDR is - when FR_WAIT => - if BUS_CYC = '1' then - FB_REGDDR_NEXT <= FR_S0; - elsif DDR_SEL = '1' and ACCESS_WIDTH = LONG and FB_WRn = '0' then - FB_REGDDR_NEXT <= FR_S0; - else - FB_REGDDR_NEXT <= FR_WAIT; - end if; - - when FR_S0 => - if DDR_CS = '1' and ACCESS_WIDTH = LONG then - FB_REGDDR_NEXT <= FR_S1; - else - FB_REGDDR_NEXT <= FR_WAIT; - end if; - - when FR_S1 => - if DDR_CS = '1' then - FB_REGDDR_NEXT <= FR_S2; - else - FB_REGDDR_NEXT <= FR_WAIT; - end if; - - when FR_S2 => - if DDR_CS = '1' and BUS_CYC = '0' and ACCESS_WIDTH = LONG and FB_WRn = '0' then -- wait during long word access if needed - FB_REGDDR_NEXT <= FR_S2; - elsif DDR_CS = '1' then - FB_REGDDR_NEXT <= FR_S3; - else - FB_REGDDR_NEXT <= FR_WAIT; - end if; - - when FR_S3 => - FB_REGDDR_NEXT <= FR_WAIT; - end case; - end process FBCTRL_DEC; - - -- Coldfire CPU access: - FB_LE(0) <= not FB_WRn when FB_REGDDR = FR_WAIT else - not FB_WRn when FB_REGDDR = FR_S0 and DDR_CS = '1' else '0'; - FB_LE(1) <= not FB_WRn when FB_REGDDR = FR_S1 and DDR_CS = '1' else '0'; - FB_LE(2) <= not FB_WRn when FB_REGDDR = FR_S2 and DDR_CS = '1' else '0'; - FB_LE(3) <= not FB_WRn when FB_REGDDR = FR_S3 and DDR_CS = '1' else '0'; - - -- Video data access: - VIDEO_DDR_TA <= '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' else - '1' when FB_REGDDR = FR_S1 and DDR_CS = '1' else - '1' when FB_REGDDR = FR_S2 and FB_REGDDR_NEXT = FR_S3 else - '1' when FB_REGDDR = FR_S3 and DDR_CS = '1' else '0'; - - -- FB_VDOE # VIDEO_OE. - - -- Write access for video data: - FB_VDOE(0) <= '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and ACCESS_WIDTH = LONG else - '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and ACCESS_WIDTH /= LONG and CLK_MAIN = '0' else '0'; - FB_VDOE(1) <= '1' when FB_REGDDR = FR_S1 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' else '0'; - FB_VDOE(2) <= '1' when FB_REGDDR = FR_S2 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' else '0'; - FB_VDOE(3) <= '1' when FB_REGDDR = FR_S3 and DDR_CS = '1' and FB_OEn = '0' and DDR_CONFIG = '0' and CLK_MAIN = '0' else '0'; - - BUS_CYC_END <= '1' when FB_REGDDR = FR_S0 and DDR_CS = '1' and ACCESS_WIDTH /= LONG else - '1' when FB_REGDDR = FR_S3 and DDR_CS = '1' else '0'; - - --------------------------------------------------------------------------------------------------------------------------------------------------------------- - ------------------------------------------------------ DDR State Machine -------------------------------------------------------------------------------------- - DDR_STATE_REG: process - begin - wait until rising_edge(DDRCLK0); - DDR_STATE <= DDR_NEXT_STATE; - end process DDR_STATE_REG; - - DDR_STATE_DEC: process(DDR_STATE, DDR_REFRESH_REQ, CPU_DDR_SYNC, DDR_CONFIG, FB_WRn, DDR_ACCESS, BLITTER_WR, FIFO_REQ, FIFO_BANK_OK, - FIFO_MW, CPU_REQ, VIDEO_ADR_CNT, DDR_SEL, TSIZ, DATA_IN, FIFO_BA, DDR_REFRESH_SIG) - begin - case DDR_STATE is - when DS_T1 => - if DDR_REFRESH_REQ = '1' then - DDR_NEXT_STATE <= DS_R2; - elsif CPU_DDR_SYNC = '1' and DDR_CONFIG = '1' then -- Synchronous start. - DDR_NEXT_STATE <= DS_C2; - elsif CPU_DDR_SYNC = '1' and CPU_REQ = '1' then -- Synchronous start. - DDR_NEXT_STATE <= DS_T2B; - elsif CPU_DDR_SYNC = '1' then - DDR_NEXT_STATE <= DS_T2A; - else - DDR_NEXT_STATE <= DS_T1; -- Synchronize. - end if; - - when DS_T2A => -- Fast access, in this case page is always not ok. - DDR_NEXT_STATE <= DS_T3; - - when DS_T2B => - DDR_NEXT_STATE <= DS_T3; - - when DS_T3 => - if DDR_ACCESS = CPU and FB_WRn = '0' then - DDR_NEXT_STATE <= DS_T4W; - elsif DDR_ACCESS = BLITTER and BLITTER_WR = '1' then - DDR_NEXT_STATE <= DS_T4W; - elsif DDR_ACCESS = CPU then -- CPU? - DDR_NEXT_STATE <= DS_T4R; - elsif DDR_ACCESS = FIFO then -- FIFO? - DDR_NEXT_STATE <= DS_T4F; - elsif DDR_ACCESS = BLITTER then - DDR_NEXT_STATE <= DS_T4R; - else - DDR_NEXT_STATE <= DS_N8; - end if; + fbctrl_dec : PROCESS(fb_regddr, bus_cyc, ddr_sel, access_width, FB_WRn, ddr_cs) + BEGIN + CASE fb_regddr IS + WHEN FR_WAIT => + IF bus_cyc = '1' THEN + fb_regddr_next <= FR_S0; + ELSIF ddr_sel = '1' AND access_width = LONG AND FB_WRn = '0' THEN + fb_regddr_next <= FR_S0; + ELSE + fb_regddr_next <= FR_WAIT; + END IF; - -- Read: - when DS_T4R => - DDR_NEXT_STATE <= DS_T5R; - - when DS_T5R => - if FIFO_REQ = '1' and FIFO_BANK_OK = '1' then -- Insert FIFO read, when bank ok. - DDR_NEXT_STATE <= DS_T6F; - else - DDR_NEXT_STATE <= DS_CB6; - end if; + WHEN FR_S0 => + IF ddr_cs = '1' AND access_width = LONG THEN + fb_regddr_next <= FR_S1; + ELSE + fb_regddr_next <= FR_WAIT; + END IF; - -- Write: - when DS_T4W => - DDR_NEXT_STATE <= DS_T5W; - - when DS_T5W => - DDR_NEXT_STATE <= DS_T6W; - - when DS_T6W => - DDR_NEXT_STATE <= DS_T7W; - - when DS_T7W => - DDR_NEXT_STATE <= DS_T8W; + WHEN FR_S1 => + IF ddr_cs = '1' THEN + fb_regddr_next <= FR_S2; + ELSE + fb_regddr_next <= FR_WAIT; + END IF; - when DS_T8W => - DDR_NEXT_STATE <= DS_T9W; - - when DS_T9W => - if FIFO_REQ = '1' and FIFO_BANK_OK = '1' then - DDR_NEXT_STATE <= DS_T6F; - else - DDR_NEXT_STATE <= DS_CB6; - end if; - - -- FIFO read: - when DS_T4F => - DDR_NEXT_STATE <= DS_T5F; - - when DS_T5F => - if FIFO_REQ = '1' then - DDR_NEXT_STATE <= DS_T6F; - else - DDR_NEXT_STATE <= DS_CB6; -- Leave open. - end if; - - when DS_T6F => - DDR_NEXT_STATE <= DS_T7F; - - when DS_T7F => - if CPU_REQ = '1' and FIFO_MW > std_logic_vector(to_unsigned(FIFO_LWM, FIFO_MW'length)) then - DDR_NEXT_STATE <= DS_CB8; -- Close bank. - elsif FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then -- New page? - DDR_NEXT_STATE <= DS_CB8; -- Close bank. - elsif FIFO_REQ = '1' then - DDR_NEXT_STATE <= DS_T8F; - else - DDR_NEXT_STATE <= DS_CB8; -- Close bank. - end if; - - when DS_T8F => - if FIFO_MW < std_logic_vector(to_unsigned(FIFO_LWM, FIFO_MW'length)) then -- Emergency? - DDR_NEXT_STATE <= DS_T5F; -- Yes! - else - DDR_NEXT_STATE <= DS_T9F; - end if; - - when DS_T9F => - if FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then -- New page? - DDR_NEXT_STATE <= DS_CB6; -- Close bank. - elsif FIFO_REQ = '1' then - DDR_NEXT_STATE <= DS_T10F; - else - DDR_NEXT_STATE <= DS_CB6; -- Close bank. - end if; - - when DS_T10F => - if DDR_SEL = '1' and (FB_WRn = '1' or TSIZ /= "11") and DATA_IN(13 downto 12) /= FIFO_BA then - DDR_NEXT_STATE <= DS_T3; - else - DDR_NEXT_STATE <= DS_T7F; - end if; - - -- Configuration cycles: - when DS_C2 => - DDR_NEXT_STATE <= DS_C3; - - when DS_C3 => - DDR_NEXT_STATE <= DS_C4; - - when DS_C4 => - if CPU_REQ = '1' then - DDR_NEXT_STATE <= DS_C5; - else - DDR_NEXT_STATE <= DS_T1; - end if; - - when DS_C5 => - DDR_NEXT_STATE <= DS_C6; - - when DS_C6 => - DDR_NEXT_STATE <= DS_C7; - - when DS_C7 => - DDR_NEXT_STATE <= DS_N8; - - -- Close FIFO bank. - when DS_CB6 => - DDR_NEXT_STATE <= DS_N7; - - when DS_CB8 => - DDR_NEXT_STATE <= DS_T1; - - -- Refresh 70ns = ten cycles. - when DS_R2 => - if DDR_REFRESH_SIG = x"9" then -- One cycle delay to close all banks. - DDR_NEXT_STATE <= DS_R4; - else - DDR_NEXT_STATE <= DS_R3; - end if; - - when DS_R3 => - DDR_NEXT_STATE <= DS_R4; - - when DS_R4 => - DDR_NEXT_STATE <= DS_R5; - - when DS_R5 => - DDR_NEXT_STATE <= DS_R6; - - when DS_R6 => - DDR_NEXT_STATE <= DS_N5; - - -- Loop: - when DS_N5 => - DDR_NEXT_STATE <= DS_N6; - - when DS_N6 => - DDR_NEXT_STATE <= DS_N7; - - when DS_N7 => - DDR_NEXT_STATE <= DS_N8; - - when DS_N8 => - DDR_NEXT_STATE <= DS_T1; - end case; - end process DDR_STATE_DEC; - - P_CLK0: process - begin - wait until rising_edge(DDRCLK0); - - -- Default assignments; - DDR_ACCESS <= NONE; - SR_FIFO_WRE_I <= '0'; - SR_VDMP <= x"00"; - SR_DDR_WR <= '0'; - SR_DDRWR_D_SEL <= '0'; - - MCS <= MCS(0) & CLK_MAIN; -- sync on CLK_MAIN - - BLITTER_REQ <= BLITTER_SIG and not DDR_CONFIG and VCKE_I and not VCS_In; - FIFO_CLR_SYNC <= FIFO_CLR; - CLEAR_FIFO_CNT <= FIFO_CLR_SYNC or not FIFO_ACTIVE; - STOP <= FIFO_CLR_SYNC or CLEAR_FIFO_CNT; - - if FIFO_MW < std_logic_vector(to_unsigned(FIFO_MWM, FIFO_MW'length)) then - FIFO_REQ <= '1'; - elsif FIFO_MW < std_logic_vector(to_unsigned(FIFO_HWM, FIFO_MW'length)) and FIFO_REQ = '1' then - FIFO_REQ <= '1'; - elsif FIFO_ACTIVE = '1' and CLEAR_FIFO_CNT = '0' and STOP = '0' and DDR_CONFIG = '0' and VCKE_I = '1' and VCS_In = '0' then - FIFO_REQ <= '1'; - else - FIFO_REQ <= '1'; - end if; - - if CLEAR_FIFO_CNT = '1' then - VIDEO_ADR_CNT <= unsigned(VIDEO_BASE_ADR); - elsif SR_FIFO_WRE_I = '1' then - VIDEO_ADR_CNT <= VIDEO_ADR_CNT + 1; - end if; - - if MCS = "10" and VCKE_I = '1' and VCS_In = '0' then - CPU_DDR_SYNC <= '1'; - else - CPU_DDR_SYNC <= '0'; - end if; - - if DDR_REFRESH_SIG /= x"0" and DDR_REFRESH_ON = '1' and DDR_CONFIG = '0' and REFRESH_TIME = '1' then - DDR_REFRESH_REQ <= '1'; - else - DDR_REFRESH_REQ <= '0'; - end if; - - if DDR_REFRESH_CNT = "00000000000" and CLK_MAIN = '0' then - REFRESH_TIME <= '1'; - else - REFRESH_TIME <= '0'; - end if; - - if REFRESH_TIME = '1' and DDR_REFRESH_ON = '1' and DDR_CONFIG = '0' then - DDR_REFRESH_SIG <= x"9"; - elsif DDR_STATE = DS_R6 and DDR_REFRESH_ON = '1' and DDR_CONFIG = '0' then - DDR_REFRESH_SIG <= DDR_REFRESH_SIG - 1; - else - DDR_REFRESH_SIG <= x"0"; - end if; - - if BUS_CYC_END = '1' then - BUS_CYC <= '0'; - elsif DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and CPU_REQ = '1' then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and ACCESS_WIDTH /= LONG then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_T2B then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_T10F and ACCESS_WIDTH /= LONG and DATA_IN(13 downto 12) = FIFO_BA then - BUS_CYC <= '1'; - elsif DDR_STATE = DS_C3 then - BUS_CYC <= CPU_REQ; - end if; - - if DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and CPU_REQ = '1' then - VA_S <= CPU_ROW_ADR; - BA_S <= CPU_BA; - DDR_ACCESS <= CPU; - elsif DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and FIFO_REQ = '1' then - VA_P <= FIFO_ROW_ADR; - BA_P <= FIFO_BA; - DDR_ACCESS <= FIFO; - elsif DDR_STATE = DS_T1 and CPU_DDR_SYNC = '1' and BLITTER_REQ = '0' then - VA_P <= BLITTER_ROW_ADR; - BA_P <= BLITTER_BA; - DDR_ACCESS <= BLITTER; - elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' then - VA_S(10) <= '1'; - DDR_ACCESS <= CPU; - elsif DDR_STATE = DS_T2A and DDR_SEL = '1' and ACCESS_WIDTH /= LONG then - VA_S(10) <= '1'; - DDR_ACCESS <= CPU; - elsif DDR_STATE = DS_T2A then - -- ?? mfro - VA_S(10) <= not (FIFO_ACTIVE and FIFO_REQ); - DDR_ACCESS <= FIFO; - FIFO_BANK_OK <= FIFO_ACTIVE and FIFO_REQ; - if DDR_ACCESS = BLITTER and BLITTER_REQ = '1' then - DDR_ACCESS <= BLITTER; - end if; - -- ?? mfro BLITTER_AC <= BLITTER_ACTIVE and BLITTER_REQ; - elsif DDR_STATE = DS_T2B then - FIFO_BANK_OK <= '0'; - elsif DDR_STATE = DS_T3 then - VA_S(10) <= VA_S(10); - if (FB_WRn = '0' and DDR_ACCESS = CPU) or (BLITTER_WR = '1' and DDR_ACCESS = BLITTER) then - VA_S(9 downto 0) <= CPU_COL_ADR; - BA_S <= CPU_BA; - elsif FIFO_ACTIVE = '1' then - VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR); - BA_S <= FIFO_BA; - elsif DDR_ACCESS = BLITTER then - VA_S(9 downto 0) <= BLITTER_COL_ADR; - BA_S <= BLITTER_BA; - end if; - elsif DDR_STATE = DS_T4R then - -- mfro change next two statements - if DDR_ACCESS = CPU then - SR_DDR_FB <= '1'; - elsif DDR_ACCESS = BLITTER then - SR_BLITTER_DACK <= '1'; - end if; - elsif DDR_STATE = DS_T5R and FIFO_REQ = '1' and FIFO_BANK_OK = '1' then - VA_S(10) <= '0'; - VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR); - BA_S <= FIFO_BA; - elsif DDR_STATE = DS_T5R then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T4W then - VA_S(10) <= VA_S(10); - -- mfro changed next if - if DDR_ACCESS = BLITTER then - SR_BLITTER_DACK <= '1'; - end if; - elsif DDR_STATE = DS_T5W then - VA_S(10) <= VA_S(10); - if DDR_ACCESS = CPU then - VA_S(9 downto 0) <= CPU_COL_ADR; - BA_S <= CPU_BA; - elsif DDR_ACCESS = BLITTER then - VA_S(9 downto 0) <= BLITTER_COL_ADR; - BA_S <= BLITTER_BA; - end if; - if DDR_ACCESS = BLITTER and ACCESS_WIDTH = LONG then - SR_VDMP <= BYTE_SEL & x"F"; - elsif DDR_ACCESS = BLITTER then - SR_VDMP <= BYTE_SEL & x"0"; - else - SR_VDMP <= BYTE_SEL & x"0"; - end if; - elsif DDR_STATE = DS_T6W then - SR_DDR_WR <= '1'; - SR_DDRWR_D_SEL <= '1'; - if DDR_ACCESS = BLITTER or ACCESS_WIDTH = LONG then - SR_VDMP <= x"FF"; - else - SR_VDMP <= x"00"; - end if; - elsif DDR_STATE = DS_T7W then - SR_DDR_WR <= '1'; - SR_DDRWR_D_SEL <= '1'; - elsif DDR_STATE = DS_T9W and FIFO_REQ = '1' and FIFO_BANK_OK = '1' then - VA_S(10) <= '0'; - VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR); - BA_S <= FIFO_BA; - elsif DDR_STATE = DS_T9W then - VA_S(10) <= '0'; - elsif DDR_STATE = DS_T4F then - SR_FIFO_WRE_I <= '1'; - elsif DDR_STATE = DS_T5F and FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T5F and FIFO_REQ = '1' then - VA_S(10) <= '0'; - VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR + "100"); - BA_S <= FIFO_BA; - elsif DDR_STATE = DS_T5F then - VA_S(10) <= '0'; - elsif DDR_STATE = DS_T6F then - SR_FIFO_WRE_I <= '1'; - elsif DDR_STATE = DS_T7F and CPU_REQ = '1' and FIFO_MW > std_logic_vector(to_unsigned(FIFO_LWM, FIFO_MW'length)) then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T7F and FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T7F and FIFO_REQ = '1' then - VA_S(10) <= '0'; - VA_S(9 downto 0) <= std_logic_vector(FIFO_COL_ADR + "100"); - BA_S <= FIFO_BA; - elsif DDR_STATE = DS_T7F then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T9F and FIFO_REQ = '1' and VIDEO_ADR_CNT(7 downto 0) = x"FF" then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T9F and FIFO_REQ = '1' then - VA_P(10) <= '0'; - VA_P(9 downto 0) <= std_logic_vector(FIFO_COL_ADR + "100"); - BA_P <= FIFO_BA; - elsif DDR_STATE = DS_T9F then - VA_S(10) <= '1'; - elsif DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA then - VA_S(10) <= '1'; - DDR_ACCESS <= CPU; - elsif DDR_STATE = DS_T10F and ACCESS_WIDTH /= LONG and DATA_IN(13 downto 12) = FIFO_BA then - VA_S(10) <= '1'; - DDR_ACCESS <= CPU; - elsif DDR_STATE = DS_T10F then - SR_FIFO_WRE_I <= '1'; - elsif DDR_STATE = DS_C6 then - VA_S <= DATA_IN(12 downto 0); - BA_S <= DATA_IN(14 downto 13); - elsif DDR_STATE = DS_CB6 then - FIFO_BANK_OK <= '0'; - elsif DDR_STATE = DS_CB8 then - FIFO_BANK_OK <= '0'; - elsif DDR_STATE = DS_R2 then - FIFO_BANK_OK <= '0'; - else - end if; - end process P_CLK0; - - DDR_SEL <= '1' when FB_ALE = '1' and DATA_IN(31 downto 30) = "01" else '0'; - - P_DDR_CS: process - begin - wait until rising_edge(CLK_MAIN); - if FB_ALE = '1' then - DDR_CS <= DDR_SEL; - end if; - end process P_DDR_CS; + WHEN FR_S2 => + IF ddr_cs = '1' AND bus_cyc = '0' AND access_width = LONG AND FB_WRn = '0' THEN -- wait during long word access IF needed + fb_regddr_next <= FR_S2; + ELSIF ddr_cs = '1' THEN + fb_regddr_next <= FR_S3; + ELSE + fb_regddr_next <= FR_WAIT; + END IF; - P_CPU_REQ: process - begin - wait until rising_edge(DDR_SYNC_66M); + WHEN FR_S3 => + fb_regddr_next <= FR_WAIT; + END CASE; + END PROCESS FBCTRL_DEC; - if DDR_SEL = '1' and FB_WRn = '1' and DDR_CONFIG = '0' then - CPU_REQ <= '1'; - elsif DDR_SEL = '1' and ACCESS_WIDTH /= LONG and DDR_CONFIG = '0' then -- Start when not config and not long word access. - CPU_REQ <= '1'; - elsif DDR_SEL = '1' and DDR_CONFIG = '1' then -- Config, start immediately. - CPU_REQ <= '1'; - elsif FB_REGDDR = FR_S1 and FB_WRn = '0' then -- Long word write later. - CPU_REQ <= '1'; - elsif FB_REGDDR /= FR_S1 and FB_REGDDR /= FR_S3 and BUS_CYC_END = '0' and BUS_CYC = '0' then -- Halt, bus cycle in progress or ready. - CPU_REQ <= '0'; - end if; - end process P_CPU_REQ; - - P_REFRESH: process - -- Refresh: Always 8 at a time every 7.8us. - -- 7.8us x 8 = 62.4us = 2059 -> 2048 @ 33MHz. - begin - wait until rising_edge(CLK_33M); - DDR_REFRESH_CNT <= DDR_REFRESH_CNT + 1; -- Count 0 to 2047. - end process P_REFRESH; + -- Coldfire CPU access: + FB_LE(0) <= NOT FB_WRn WHEN fb_regddr = FR_WAIT ELSE + NOT FB_WRn WHEN fb_regddr = FR_S0 AND ddr_cs = '1' ELSE '0'; + FB_LE(1) <= NOT FB_WRn WHEN fb_regddr = FR_S1 AND ddr_cs = '1' ELSE '0'; + FB_LE(2) <= NOT FB_WRn WHEN fb_regddr = FR_S2 AND ddr_cs = '1' ELSE '0'; + FB_LE(3) <= NOT FB_WRn WHEN fb_regddr = FR_S3 AND ddr_cs = '1' ELSE '0'; - SR_FIFO_WRE <= SR_FIFO_WRE_I; - - VA <= DATA_IN(26 downto 14) when DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' else - DATA_IN(26 downto 14) when DDR_STATE = DS_T2A and DDR_SEL = '1' and (FB_SIZE0 = '0' or FB_SIZE1= '0') else - VA_P when DDR_STATE = DS_T2A else - DATA_IN(26 downto 14) when DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA else - DATA_IN(26 downto 14) when DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA else - VA_P when DDR_STATE = DS_T10F else - "0010000000000" when DDR_STATE = DS_R2 and DDR_REFRESH_SIG = x"9" else VA_S; + -- Video data access: + VIDEO_DDR_TA <= '1' WHEN fb_regddr = FR_S0 AND ddr_cs = '1' ELSE + '1' WHEN fb_regddr = FR_S1 AND ddr_cs = '1' ELSE + '1' WHEN fb_regddr = FR_S2 AND fb_regddr_next = FR_S3 ELSE + '1' WHEN fb_regddr = FR_S3 AND ddr_cs = '1' ELSE '0'; - BA <= DATA_IN(13 downto 12) when DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' else - DATA_IN(13 downto 12) when DDR_STATE = DS_T2A and DDR_SEL = '1' and (FB_SIZE0 = '0' or FB_SIZE1= '0') else - BA_P when DDR_STATE = DS_T2A else - DATA_IN(13 downto 12) when DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA else - DATA_IN(13 downto 12) when DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA else - BA_P when DDR_STATE = DS_T10F else BA_S; + -- FB_VDOE # VIDEO_OE. + + -- Write access for video data: + FB_VDOE(0) <= '1' WHEN fb_regddr = FR_S0 AND ddr_cs = '1' AND FB_OEn = '0' AND ddr_config = '0' AND access_width = LONG ELSE + '1' WHEN fb_regddr = FR_S0 AND ddr_cs = '1' AND FB_OEn = '0' AND ddr_config = '0' AND access_width /= LONG AND clk_main = '0' ELSE '0'; + FB_VDOE(1) <= '1' WHEN fb_regddr = FR_S1 AND ddr_cs = '1' AND FB_OEn = '0' AND ddr_config = '0' ELSE '0'; + FB_VDOE(2) <= '1' WHEN fb_regddr = FR_S2 AND ddr_cs = '1' AND FB_OEn = '0' AND ddr_config = '0' ELSE '0'; + FB_VDOE(3) <= '1' WHEN fb_regddr = FR_S3 AND ddr_cs = '1' AND FB_OEn = '0' AND ddr_config = '0' AND clk_main = '0' ELSE '0'; + + bus_cyc_end <= '1' WHEN fb_regddr = FR_S0 AND ddr_cs = '1' AND access_width /= LONG ELSE + '1' WHEN fb_regddr = FR_S3 AND ddr_cs = '1' ELSE '0'; + + --------------------------------------------------------------------------------------------------------------------------------------------------------------- + ------------------------------------------------------ DDR State Machine -------------------------------------------------------------------------------------- + ddr_state_REG: PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(DDRCLK0); + ddr_state <= ddr_next_state; + END PROCESS ddr_state_REG; + + ddr_state_DEC: PROCESS(ddr_state, ddr_refresh_req, cpu_ddr_sync, ddr_config, FB_WRn, ddr_access, BLITTER_WR, fifo_req, fifo_bank_ok, + FIFO_MW, cpu_req, video_adr_cnt, ddr_sel, tsiz, data_in, fifo_ba, ddr_refresh_sig) + BEGIN + CASE ddr_state IS + WHEN DS_T1 => + IF ddr_refresh_req = '1' THEN + ddr_next_state <= DS_R2; + ELSIF cpu_ddr_sync = '1' AND ddr_config = '1' THEN -- Synchronous start. + ddr_next_state <= DS_C2; + ELSIF cpu_ddr_sync = '1' AND cpu_req = '1' THEN -- Synchronous start. + ddr_next_state <= DS_T2B; + ELSIF cpu_ddr_sync = '1' THEN + ddr_next_state <= DS_T2A; + ELSE + ddr_next_state <= DS_T1; -- Synchronize. + END IF; - VRAS <= '1' when DDR_STATE = DS_T2A and DDR_SEL = '1' and FB_WRn = '0' else - '1' when DDR_STATE = DS_T2A and DDR_SEL = '1' and (FB_SIZE0 = '0' or FB_SIZE1= '0') else - '1' when DDR_STATE = DS_T2A and DDR_ACCESS = FIFO and FIFO_REQ = '1' else - '1' when DDR_STATE = DS_T2A and DDR_ACCESS = BLITTER and BLITTER_REQ = '1' else - '1' when DDR_STATE = DS_T2B else - '1' when DDR_STATE = DS_T10F and FB_WRn = '0' and DATA_IN(13 downto 12) = FIFO_BA else - '1' when DDR_STATE = DS_T10F and (FB_SIZE0 = '0' or FB_SIZE1= '0') and DATA_IN(13 downto 12) = FIFO_BA else - DATA_IN(18) and not FB_WRn and not FB_SIZE0 and not FB_SIZE1 when DDR_STATE = DS_C7 else - '1' when DDR_STATE = DS_CB6 else - '1' when DDR_STATE = DS_CB8 else - '1' when DDR_STATE = DS_R2 else '0'; + WHEN DS_T2A => -- Fast access, IN this CASE page IS always NOT ok. + ddr_next_state <= DS_T3; + + WHEN DS_T2B => + ddr_next_state <= DS_T3; - VCAS <= '1' when DDR_STATE = DS_T4R else - '1' when DDR_STATE = DS_T6W else - '1' when DDR_STATE = DS_T4F else - '1' when DDR_STATE = DS_T6F else - '1' when DDR_STATE = DS_T8F else - '1' when DDR_STATE = DS_T10F and VRAS = '0' else - DATA_IN(17) and not FB_WRn and not FB_SIZE0 and not FB_SIZE1 when DDR_STATE = DS_C7 else - '1' when DDR_STATE = DS_R2 and DDR_REFRESH_SIG /= x"9" else '0'; + WHEN DS_T3 => + IF ddr_access = CPU AND FB_WRn = '0' THEN + ddr_next_state <= DS_T4W; + ELSIF ddr_access = BLITTER AND BLITTER_WR = '1' THEN + ddr_next_state <= DS_T4W; + ELSIF ddr_access = CPU THEN -- CPU? + ddr_next_state <= DS_T4R; + ELSIF ddr_access = FIFO THEN -- FIFO? + ddr_next_state <= DS_T4F; + ELSIF ddr_access = BLITTER THEN + ddr_next_state <= DS_T4R; + ELSE + ddr_next_state <= DS_N8; + END IF; + + -- Read: + WHEN DS_T4R => + ddr_next_state <= DS_T5R; - VWE <= '1' when DDR_STATE = DS_T6W else - DATA_IN(16) and not FB_WRn and not FB_SIZE0 and not FB_SIZE1 when DDR_STATE = DS_C7 else - '1' when DDR_STATE = DS_CB6 else - '1' when DDR_STATE = DS_CB8 else - '1' when DDR_STATE = DS_R2 and DDR_REFRESH_SIG = x"9" else '0'; + WHEN DS_T5R => + IF fifo_req = '1' AND fifo_bank_ok = '1' THEN -- Insert FIFO read, WHEN bank ok. + ddr_next_state <= DS_T6F; + ELSE + ddr_next_state <= DS_CB6; + END IF; + + -- Write: + WHEN DS_T4W => + ddr_next_state <= DS_T5W; - -- DDR controller: - -- VIDEO RAM CONTROL REGISTER (is in VIDEO_MUX_CTR) - -- $F0000400: BIT 0: VCKE; 1: not nVCS ;2:REFRESH ON , (0=FIFO and CNT CLEAR); - -- 3: CONFIG; 8: FIFO_ACTIVE; - VCKE <= VCKE_I; - VCKE_I <= VIDEO_RAM_CTR(0); - VCSn <= VCS_In; - VCS_In <= not VIDEO_RAM_CTR(1); - DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); - DDR_CONFIG <= VIDEO_RAM_CTR(3); - FIFO_ACTIVE <= VIDEO_RAM_CTR(8); + WHEN DS_T5W => + ddr_next_state <= DS_T6W; - CPU_ROW_ADR <= FB_ADR(26 downto 14); - CPU_BA <= FB_ADR(13 downto 12); - CPU_COL_ADR <= FB_ADR(11 downto 2); - VRASn <= not VRAS; - VCASn <= not VCAS; - VWEn <= not VWE; + WHEN DS_T6W => + ddr_next_state <= DS_T7W; - DDRWR_D_SEL1 <= '1' when DDR_ACCESS = BLITTER else '0'; - - BLITTER_ROW_ADR <= BLITTER_ADR(26 downto 14); - BLITTER_BA <= BLITTER_ADR(13 downto 12); - BLITTER_COL_ADR <= BLITTER_ADR(11 downto 2); + WHEN DS_T7W => + ddr_next_state <= DS_T8W; + + WHEN DS_T8W => + ddr_next_state <= DS_T9W; + + WHEN DS_T9W => + IF fifo_req = '1' AND fifo_bank_ok = '1' THEN + ddr_next_state <= DS_T6F; + ELSE + ddr_next_state <= DS_CB6; + END IF; + + -- FIFO read: + WHEN DS_T4F => + ddr_next_state <= DS_T5F; - FIFO_ROW_ADR <= std_logic_vector(VIDEO_ADR_CNT(22 downto 10)); - FIFO_BA <= std_logic_vector(VIDEO_ADR_CNT(9 downto 8)); - FIFO_COL_ADR <= VIDEO_ADR_CNT(7 downto 0) & "00"; + WHEN DS_T5F => + IF fifo_req = '1' THEN + ddr_next_state <= DS_T6F; + ELSE + ddr_next_state <= DS_CB6; -- Leave open. + END IF; - VIDEO_BASE_ADR(22 downto 20) <= VIDEO_BASE_X_D; - VIDEO_BASE_ADR(19 downto 12) <= VIDEO_BASE_H_D; - VIDEO_BASE_ADR(11 downto 4) <= VIDEO_BASE_M_D; - VIDEO_BASE_ADR(3 downto 0) <= VIDEO_BASE_L_D(7 downto 4); + WHEN DS_T6F => + ddr_next_state <= DS_T7F; + + WHEN DS_T7F => + IF cpu_req = '1' AND FIFO_MW > STD_LOGIC_VECTOR (to_UNSIGNED(FIFO_LWM, FIFO_MW'length)) THEN + ddr_next_state <= DS_CB8; -- Close bank. + ELSIF fifo_req = '1' AND video_adr_cnt(7 DOWNTO 0) = x"FF" THEN -- New page? + ddr_next_state <= DS_CB8; -- Close bank. + ELSIF fifo_req = '1' THEN + ddr_next_state <= DS_T8F; + ELSE + ddr_next_state <= DS_CB8; -- Close bank. + END IF; - VDM_SEL <= VDM_SEL_I; - VDM_SEL_I <= VIDEO_BASE_L_D(3 downto 0); + WHEN DS_T8F => + IF FIFO_MW < STD_LOGIC_VECTOR (to_UNSIGNED(FIFO_LWM, FIFO_MW'length)) THEN -- Emergency? + ddr_next_state <= DS_T5F; -- Yes! + ELSE + ddr_next_state <= DS_T9F; + END IF; - -- Current video address: - VIDEO_ACT_ADR(26 downto 4) <= std_logic_vector(VIDEO_ADR_CNT - unsigned(FIFO_MW)); - VIDEO_ACT_ADR(3 downto 0) <= VDM_SEL_I; + WHEN DS_T9F => + IF fifo_req = '1' AND video_adr_cnt(7 DOWNTO 0) = x"FF" THEN -- New page? + ddr_next_state <= DS_CB6; -- Close bank. + ELSIF fifo_req = '1' THEN + ddr_next_state <= DS_T10F; + ELSE + ddr_next_state <= DS_CB6; -- Close bank. + END IF; - P_VIDEO_REGS: process - -- Video registers. - begin - wait until rising_edge(CLK_MAIN); - if VIDEO_BASE_L = '1' and FB_WRn = '0' and BYTE_SEL(1) = '1' then - VIDEO_BASE_L_D <= DATA_IN(23 downto 16); -- 16 byte boarders. - end if; + WHEN DS_T10F => + IF ddr_sel = '1' AND (FB_WRn = '1' OR tsiz /= "11") AND data_in(13 DOWNTO 12) /= fifo_ba THEN + ddr_next_state <= DS_T3; + ELSE + ddr_next_state <= DS_T7F; + END IF; + + -- Configuration cycles: + WHEN DS_C2 => + ddr_next_state <= DS_C3; + + WHEN DS_C3 => + ddr_next_state <= DS_C4; + + WHEN DS_C4 => + IF cpu_req = '1' THEN + ddr_next_state <= DS_C5; + ELSE + ddr_next_state <= DS_T1; + END IF; + + WHEN DS_C5 => + ddr_next_state <= DS_C6; + + WHEN DS_C6 => + ddr_next_state <= DS_C7; + + WHEN DS_C7 => + ddr_next_state <= DS_N8; + + -- Close FIFO bank. + WHEN DS_CB6 => + ddr_next_state <= DS_N7; + + WHEN DS_CB8 => + ddr_next_state <= DS_T1; + + -- Refresh 70ns = ten cycles. + WHEN DS_R2 => + IF ddr_refresh_sig = x"9" THEN -- One cycle delay to close all banks. + ddr_next_state <= DS_R4; + ELSE + ddr_next_state <= DS_R3; + END IF; + + WHEN DS_R3 => + ddr_next_state <= DS_R4; + + WHEN DS_R4 => + ddr_next_state <= DS_R5; + + WHEN DS_R5 => + ddr_next_state <= DS_R6; + + WHEN DS_R6 => + ddr_next_state <= DS_N5; + + -- Loop: + WHEN DS_N5 => + ddr_next_state <= DS_N6; + + WHEN DS_N6 => + ddr_next_state <= DS_N7; + + WHEN DS_N7 => + ddr_next_state <= DS_N8; + + WHEN DS_N8 => + ddr_next_state <= DS_T1; + END CASE; + END PROCESS ddr_state_DEC; + + P_CLK0: PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(DDRCLK0); + + -- Default assignments; + ddr_access <= NONE; + sr_fifo_wre_i <= '0'; + SR_VDMP <= x"00"; + SR_DDR_WR <= '0'; + SR_DDRWR_D_SEL <= '0'; + + mcs <= mcs(0) & clk_main; -- sync on clk_main + + blitter_req <= blitter_sig AND NOT video_control_register(vrcr_config_on) AND video_control_register(vrcr_vcke) AND video_control_register(vrcr_vcs); + fifo_clr_sync <= FIFO_CLR; + clear_fifo_cnt <= fifo_clr_sync OR NOT fifo_active; + stop <= fifo_clr_sync OR clear_fifo_cnt; + + IF FIFO_MW < STD_LOGIC_VECTOR (to_UNSIGNED(FIFO_MWM, FIFO_MW'length)) THEN + fifo_req <= '1'; + ELSIF FIFO_MW < STD_LOGIC_VECTOR (to_UNSIGNED(FIFO_HWM, FIFO_MW'length)) AND fifo_req = '1' THEN + fifo_req <= '1'; + ELSIF fifo_active = '1' AND clear_fifo_cnt = '0' AND stop = '0' AND ddr_config = '0' AND video_control_register(vrcr_vcke) = '1' AND video_control_register(vrcr_vcs) = '1' THEN + fifo_req <= '1'; + ELSE + fifo_req <= '1'; + END IF; + + IF clear_fifo_cnt = '1' THEN + video_adr_cnt <= UNSIGNED(video_base_adr); + ELSIF sr_fifo_wre_i = '1' THEN + video_adr_cnt <= video_adr_cnt + 1; + END IF; + + IF mcs = "10" AND video_control_register(vrcr_vcke) = '1' AND video_control_register(vrcr_vcs) = '1' THEN + cpu_ddr_sync <= '1'; + ELSE + cpu_ddr_sync <= '0'; + END IF; + + IF ddr_refresh_sig /= x"0" AND video_control_register(vrcr_refresh_on) = '1' AND ddr_config = '0' AND refresh_time = '1' THEN + ddr_refresh_req <= '1'; + ELSE + ddr_refresh_req <= '0'; + END IF; + + IF ddr_refresh_cnt = 0 AND clk_main = '0' THEN + refresh_time <= '1'; + ELSE + refresh_time <= '0'; + END IF; + + IF refresh_time = '1' AND video_control_register(vrcr_refresh_on) = '1' AND ddr_config = '0' THEN + ddr_refresh_sig <= x"9"; + ELSIF ddr_state = DS_R6 AND video_control_register(vrcr_refresh_on) = '1' AND ddr_config = '0' THEN + ddr_refresh_sig <= ddr_refresh_sig - 1; + ELSE + ddr_refresh_sig <= x"0"; + END IF; + + IF bus_cyc_end = '1' THEN + bus_cyc <= '0'; + ELSIF ddr_state = DS_T1 AND cpu_ddr_sync = '1' AND cpu_req = '1' THEN + bus_cyc <= '1'; + ELSIF ddr_state = DS_T2A AND ddr_sel = '1' AND FB_WRn = '0' THEN + bus_cyc <= '1'; + ELSIF ddr_state = DS_T2A AND ddr_sel = '1' AND access_width /= LONG THEN + bus_cyc <= '1'; + ELSIF ddr_state = DS_T2B THEN + bus_cyc <= '1'; + ELSIF ddr_state = DS_T10F AND FB_WRn = '0' AND data_in(13 DOWNTO 12) = fifo_ba THEN + bus_cyc <= '1'; + ELSIF ddr_state = DS_T10F AND access_width /= LONG AND data_in(13 DOWNTO 12) = fifo_ba THEN + bus_cyc <= '1'; + ELSIF ddr_state = DS_C3 THEN + bus_cyc <= cpu_req; + END IF; + + IF ddr_state = DS_T1 AND cpu_ddr_sync = '1' AND cpu_req = '1' THEN + va_s <= cpu_row_adr; + ba_s <= cpu_ba; + ddr_access <= CPU; + ELSIF ddr_state = DS_T1 AND cpu_ddr_sync = '1' AND fifo_req = '1' THEN + va_p <= fifo_row_adr; + ba_p <= fifo_ba; + ddr_access <= FIFO; + ELSIF ddr_state = DS_T1 AND cpu_ddr_sync = '1' AND blitter_req = '0' THEN + va_p <= blitter_row_adr; + ba_p <= blitter_ba; + ddr_access <= BLITTER; + ELSIF ddr_state = DS_T2A AND ddr_sel = '1' AND FB_WRn = '0' THEN + va_s(10) <= '1'; + ddr_access <= CPU; + ELSIF ddr_state = DS_T2A AND ddr_sel = '1' AND access_width /= LONG THEN + va_s(10) <= '1'; + ddr_access <= CPU; + ELSIF ddr_state = DS_T2A THEN + -- ?? mfro + va_s(10) <= NOT (fifo_active AND fifo_req); + ddr_access <= FIFO; + fifo_bank_ok <= fifo_active AND fifo_req; + IF ddr_access = BLITTER AND blitter_req = '1' THEN + ddr_access <= BLITTER; + END IF; + -- ?? mfro BLITTER_AC <= BLITTER_ACTIVE AND blitter_req; + ELSIF ddr_state = DS_T2B THEN + fifo_bank_ok <= '0'; + ELSIF ddr_state = DS_T3 THEN + va_s(10) <= va_s(10); + IF (FB_WRn = '0' AND ddr_access = CPU) OR (BLITTER_WR = '1' AND ddr_access = BLITTER) THEN + va_s(9 DOWNTO 0) <= cpu_col_adr; + ba_s <= cpu_ba; + ELSIF fifo_active = '1' THEN + va_s(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr); + ba_s <= fifo_ba; + ELSIF ddr_access = BLITTER THEN + va_s(9 DOWNTO 0) <= blitter_col_adr; + ba_s <= blitter_ba; + END IF; + ELSIF ddr_state = DS_T4R THEN + -- mfro change next two statements + IF ddr_access = CPU THEN + SR_DDR_FB <= '1'; + ELSIF ddr_access = BLITTER THEN + SR_BLITTER_DACK <= '1'; + END IF; + ELSIF ddr_state = DS_T5R AND fifo_req = '1' AND fifo_bank_ok = '1' THEN + va_s(10) <= '0'; + va_s(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr); + ba_s <= fifo_ba; + ELSIF ddr_state = DS_T5R THEN + va_s(10) <= '1'; + ELSIF ddr_state = DS_T4W THEN + va_s(10) <= va_s(10); + -- mfro changed next IF + IF ddr_access = BLITTER THEN + SR_BLITTER_DACK <= '1'; + END IF; + ELSIF ddr_state = DS_T5W THEN + va_s(10) <= va_s(10); + IF ddr_access = CPU THEN + va_s(9 DOWNTO 0) <= cpu_col_adr; + ba_s <= cpu_ba; + ELSIF ddr_access = BLITTER THEN + va_s(9 DOWNTO 0) <= blitter_col_adr; + ba_s <= blitter_ba; + END IF; + IF ddr_access = BLITTER AND access_width = LONG THEN + SR_VDMP <= byte_sel & x"F"; + ELSIF ddr_access = BLITTER THEN + SR_VDMP <= byte_sel & x"0"; + ELSE + SR_VDMP <= byte_sel & x"0"; + END IF; + ELSIF ddr_state = DS_T6W THEN + SR_DDR_WR <= '1'; + SR_DDRWR_D_SEL <= '1'; + IF ddr_access = BLITTER OR access_width = LONG THEN + SR_VDMP <= x"FF"; + ELSE + SR_VDMP <= x"00"; + END IF; + ELSIF ddr_state = DS_T7W THEN + SR_DDR_WR <= '1'; + SR_DDRWR_D_SEL <= '1'; + ELSIF ddr_state = DS_T9W AND fifo_req = '1' AND fifo_bank_ok = '1' THEN + va_s(10) <= '0'; + va_s(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr); + ba_s <= fifo_ba; + ELSIF ddr_state = DS_T9W THEN + va_s(10) <= '0'; + ELSIF ddr_state = DS_T4F THEN + sr_fifo_wre_i <= '1'; + ELSIF ddr_state = DS_T5F AND fifo_req = '1' AND video_adr_cnt(7 DOWNTO 0) = x"FF" THEN + va_s(10) <= '1'; + ELSIF ddr_state = DS_T5F AND fifo_req = '1' THEN + va_s(10) <= '0'; + va_s(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr + "100"); + ba_s <= fifo_ba; + ELSIF ddr_state = DS_T5F THEN + va_s(10) <= '0'; + ELSIF ddr_state = DS_T6F THEN + sr_fifo_wre_i <= '1'; + ELSIF ddr_state = DS_T7F AND cpu_req = '1' AND FIFO_MW > STD_LOGIC_VECTOR (to_UNSIGNED(FIFO_LWM, FIFO_MW'length)) THEN + va_s(10) <= '1'; + ELSIF ddr_state = DS_T7F AND fifo_req = '1' AND video_adr_cnt(7 DOWNTO 0) = x"FF" THEN + va_s(10) <= '1'; + ELSIF ddr_state = DS_T7F AND fifo_req = '1' THEN + va_s(10) <= '0'; + va_s(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr + "100"); + ba_s <= fifo_ba; + ELSIF ddr_state = DS_T7F THEN + va_s(10) <= '1'; + ELSIF ddr_state = DS_T9F AND fifo_req = '1' AND video_adr_cnt(7 DOWNTO 0) = x"FF" THEN + va_s(10) <= '1'; + ELSIF ddr_state = DS_T9F AND fifo_req = '1' THEN + va_p(10) <= '0'; + va_p(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr + "100"); + ba_p <= fifo_ba; + ELSIF ddr_state = DS_T9F THEN + va_s(10) <= '1'; + ELSIF ddr_state = DS_T10F AND FB_WRn = '0' AND data_in(13 DOWNTO 12) = fifo_ba THEN + va_s(10) <= '1'; + ddr_access <= CPU; + ELSIF ddr_state = DS_T10F AND access_width /= LONG AND data_in(13 DOWNTO 12) = fifo_ba THEN + va_s(10) <= '1'; + ddr_access <= CPU; + ELSIF ddr_state = DS_T10F THEN + sr_fifo_wre_i <= '1'; + ELSIF ddr_state = DS_C6 THEN + va_s <= data_in(12 DOWNTO 0); + ba_s <= data_in(14 DOWNTO 13); + ELSIF ddr_state = DS_CB6 THEN + fifo_bank_ok <= '0'; + ELSIF ddr_state = DS_CB8 THEN + fifo_bank_ok <= '0'; + ELSIF ddr_state = DS_R2 THEN + fifo_bank_ok <= '0'; + ELSE + END IF; + END PROCESS P_CLK0; + + ddr_sel <= '1' WHEN FB_ALE = '1' AND data_in(31 DOWNTO 30) = "01" ELSE '0'; + + P_ddr_cs: PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(clk_main); + IF FB_ALE = '1' THEN + ddr_cs <= ddr_sel; + END IF; + END PROCESS P_ddr_cs; + + p_cpu_req: PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(DDR_SYNC_66M); + + IF ddr_sel = '1' AND FB_WRn = '1' AND ddr_config = '0' THEN + cpu_req <= '1'; + ELSIF ddr_sel = '1' AND access_width /= LONG AND ddr_config = '0' THEN -- Start WHEN NOT config AND NOT long word access. + cpu_req <= '1'; + ELSIF ddr_sel = '1' AND ddr_config = '1' THEN -- Config, start immediately. + cpu_req <= '1'; + ELSIF fb_regddr = FR_S1 AND FB_WRn = '0' THEN -- Long word write later. + cpu_req <= '1'; + ELSIF fb_regddr /= FR_S1 AND fb_regddr /= FR_S3 AND bus_cyc_end = '0' AND bus_cyc = '0' THEN -- Halt, bus cycle IN progress OR ready. + cpu_req <= '0'; + END IF; + END PROCESS p_cpu_req; + + p_refresh : PROCESS + -- Refresh: Always 8 at a time every 7.8us. + -- 7.8us x 8 = 62.4us = 2059 -> 2048 @ 33MHz. + BEGIN + WAIT UNTIL RISING_EDGE(CLK_33M); + ddr_refresh_cnt <= ddr_refresh_cnt + 1; -- Count 0 to 2047. + END PROCESS P_REFRESH; + + sr_fifo_wre <= sr_fifo_wre_i; + + VA <= data_in(26 DOWNTO 14) WHEN ddr_state = DS_T2A AND ddr_sel = '1' AND FB_WRn = '0' ELSE + data_in(26 DOWNTO 14) WHEN ddr_state = DS_T2A AND ddr_sel = '1' AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') ELSE + va_p WHEN ddr_state = DS_T2A ELSE + data_in(26 DOWNTO 14) WHEN ddr_state = DS_T10F AND FB_WRn = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE + data_in(26 DOWNTO 14) WHEN ddr_state = DS_T10F AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE + va_p WHEN ddr_state = DS_T10F ELSE + "0010000000000" WHEN ddr_state = DS_R2 AND ddr_refresh_sig = x"9" ELSE va_s; + + BA <= data_in(13 DOWNTO 12) WHEN ddr_state = DS_T2A AND ddr_sel = '1' AND FB_WRn = '0' ELSE + data_in(13 DOWNTO 12) WHEN ddr_state = DS_T2A AND ddr_sel = '1' AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') ELSE + ba_p WHEN ddr_state = DS_T2A ELSE + data_in(13 DOWNTO 12) WHEN ddr_state = DS_T10F AND FB_WRn = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE + data_in(13 DOWNTO 12) WHEN ddr_state = DS_T10F AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE + ba_p WHEN ddr_state = DS_T10F ELSE ba_s; + + vras <= '1' WHEN ddr_state = DS_T2A AND ddr_sel = '1' AND FB_WRn = '0' ELSE + '1' WHEN ddr_state = DS_T2A AND ddr_sel = '1' AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') ELSE + '1' WHEN ddr_state = DS_T2A AND ddr_access = FIFO AND fifo_req = '1' ELSE + '1' WHEN ddr_state = DS_T2A AND ddr_access = BLITTER AND blitter_req = '1' ELSE + '1' WHEN ddr_state = DS_T2B ELSE + '1' WHEN ddr_state = DS_T10F AND FB_WRn = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE + '1' WHEN ddr_state = DS_T10F AND (FB_SIZE0 = '0' OR FB_SIZE1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE + data_in(18) AND NOT FB_WRn AND NOT FB_SIZE0 AND NOT FB_SIZE1 WHEN ddr_state = DS_C7 ELSE + '1' WHEN ddr_state = DS_CB6 ELSE + '1' WHEN ddr_state = DS_CB8 ELSE + '1' WHEN ddr_state = DS_R2 ELSE '0'; + + vcas <= '1' WHEN ddr_state = DS_T4R ELSE + '1' WHEN ddr_state = DS_T6W ELSE + '1' WHEN ddr_state = DS_T4F ELSE + '1' WHEN ddr_state = DS_T6F ELSE + '1' WHEN ddr_state = DS_T8F ELSE + '1' WHEN ddr_state = DS_T10F AND vras = '0' ELSE + data_in(17) AND NOT FB_WRn AND NOT FB_SIZE0 AND NOT FB_SIZE1 WHEN ddr_state = DS_C7 ELSE + '1' WHEN ddr_state = DS_R2 AND ddr_refresh_sig /= x"9" ELSE '0'; + + vwe <= '1' WHEN ddr_state = DS_T6W ELSE + data_in(16) AND NOT FB_WRn AND NOT FB_SIZE0 AND NOT FB_SIZE1 WHEN ddr_state = DS_C7 ELSE + '1' WHEN ddr_state = DS_CB6 ELSE + '1' WHEN ddr_state = DS_CB8 ELSE + '1' WHEN ddr_state = DS_R2 AND ddr_refresh_sig = x"9" ELSE '0'; + + -- DDR controller: + -- VIDEO RAM CONTROL REGISTER (IS IN VIDEO_MUX_CTR) + -- $F0000400: BIT 0: VCKE; 1: NOT nVCS ;2:REFRESH ON , (0=FIFO AND CNT CLEAR); + -- 3: CONFIG; 8: fifo_active; + VCSn <= NOT(video_control_register(vrcr_refresh_on)); + ddr_config <= video_control_register(3); + fifo_active <= video_control_register(8); + + cpu_row_adr <= FB_ADR(26 DOWNTO 14); + cpu_ba <= FB_ADR(13 DOWNTO 12); + cpu_col_adr <= FB_ADR(11 DOWNTO 2); + vrasn <= NOT vras; + vcasn <= NOT vcas; + vwen <= NOT vwe; + + ddrwr_d_sel1 <= '1' WHEN ddr_access = BLITTER ELSE '0'; + + blitter_row_adr <= BLITTER_ADR(26 DOWNTO 14); + blitter_ba <= BLITTER_ADR(13 DOWNTO 12); + blitter_col_adr <= BLITTER_ADR(11 DOWNTO 2); + + fifo_row_adr <= STD_LOGIC_VECTOR (video_adr_cnt(22 DOWNTO 10)); + fifo_ba <= STD_LOGIC_VECTOR (video_adr_cnt(9 DOWNTO 8)); + fifo_col_adr <= video_adr_cnt(7 DOWNTO 0) & "00"; + + video_base_adr(22 DOWNTO 20) <= video_base_x_d; + video_base_adr(19 DOWNTO 12) <= video_base_h_d; + video_base_adr(11 DOWNTO 4) <= video_base_m_d; + video_base_adr(3 DOWNTO 0) <= video_base_l_d(7 DOWNTO 4); + + VDM_SEL <= vdm_sel_i; + vdm_sel_i <= video_base_l_d(3 DOWNTO 0); + + -- Current video address: + video_act_adr(26 DOWNTO 4) <= STD_LOGIC_VECTOR (video_adr_cnt - UNSIGNED(FIFO_MW)); + video_act_adr(3 DOWNTO 0) <= vdm_sel_i; + + P_VIDEO_REGS: PROCESS + -- Video registers. + BEGIN + WAIT UNTIL RISING_EDGE(clk_main); + IF video_base_l = '1' AND FB_WRn = '0' AND byte_sel(1) = '1' THEN + video_base_l_d <= data_in(23 DOWNTO 16); -- 16 byte boarders. + END IF; - if VIDEO_BASE_M = '1' and FB_WRn = '0' and BYTE_SEL(3) = '1' then - VIDEO_BASE_M_D <= DATA_IN(23 downto 16); - end if; + IF video_base_m = '1' AND FB_WRn = '0' AND byte_sel(3) = '1' THEN + video_base_m_d <= data_in(23 DOWNTO 16); + END IF; - if VIDEO_BASE_H = '1' and FB_WRn = '0' and BYTE_SEL(1) = '1' then - VIDEO_BASE_H_D <= DATA_IN(23 downto 16); - end if; + IF video_base_h = '1' AND FB_WRn = '0' AND byte_sel(1) = '1' THEN + video_base_h_d <= data_in(23 DOWNTO 16); + END IF; - if VIDEO_BASE_H = '1' and FB_WRn = '0' and BYTE_SEL(0) = '1' then - VIDEO_BASE_X_D <= DATA_IN(26 downto 24); - end if; - end process P_VIDEO_REGS; + IF video_base_h = '1' AND FB_WRn = '0' AND byte_sel(0) = '1' THEN + video_base_x_d <= data_in(26 DOWNTO 24); + END IF; + END PROCESS P_VIDEO_REGS; - FB_ADR_I <= FB_ADR & '0'; + fb_adr_i <= FB_ADR & '0'; - VIDEO_BASE_L <= '1' when FB_CS1n = '0' and FB_ADR_I(15 downto 0) = x"820D" else '0'; -- x"FF820D". - VIDEO_BASE_M <= '1' when FB_CS1n = '0' and FB_ADR_I(15 downto 0) = x"8204" else '0'; -- x"FF8203". - VIDEO_BASE_H <= '1' when FB_CS1n = '0' and FB_ADR_I(15 downto 0) = x"8202" else '0'; -- x"FF8201". + video_base_l <= '1' WHEN FB_CS1n = '0' AND fb_adr_i(15 DOWNTO 0) = x"820D" ELSE '0'; -- x"FF820D". + video_base_m <= '1' WHEN FB_CS1n = '0' AND fb_adr_i(15 DOWNTO 0) = x"8204" ELSE '0'; -- x"FF8203". + video_base_h <= '1' WHEN FB_CS1n = '0' AND fb_adr_i(15 DOWNTO 0) = x"8202" ELSE '0'; -- x"FF8201". - VIDEO_CNT_L <= '1' when FB_CS1n = '0' and FB_ADR_I(15 downto 0) = x"8208" else '0'; -- x"FF8209". - VIDEO_CNT_M <= '1' when FB_CS1n = '0' and FB_ADR_I(15 downto 0) = x"8206" else '0'; -- x"FF8207". - VIDEO_CNT_H <= '1' when FB_CS1n = '0' and FB_ADR_I(15 downto 0) = x"8204" else '0'; -- x"FF8205". + video_cnt_l <= '1' WHEN FB_CS1n = '0' AND fb_adr_i(15 DOWNTO 0) = x"8208" ELSE '0'; -- x"FF8209". + video_cnt_m <= '1' WHEN FB_CS1n = '0' AND fb_adr_i(15 DOWNTO 0) = x"8206" ELSE '0'; -- x"FF8207". + video_cnt_h <= '1' WHEN FB_CS1n = '0' AND fb_adr_i(15 DOWNTO 0) = x"8204" ELSE '0'; -- x"FF8205". - DATA_OUT(31 downto 24) <= "00000" & VIDEO_BASE_X_D when VIDEO_BASE_H = '1' else - "00000" & VIDEO_ACT_ADR(26 downto 24) when VIDEO_CNT_H = '1' else (others => '0'); + DATA_OUT(31 DOWNTO 24) <= "00000" & video_base_x_d WHEN video_base_h = '1' ELSE + "00000" & video_act_adr(26 DOWNTO 24) WHEN video_cnt_h = '1' ELSE (OTHERS => '0'); - DATA_EN_H <= (VIDEO_BASE_H or VIDEO_CNT_H) and not FB_OEn; + DATA_EN_H <= (video_base_h OR video_cnt_h) AND NOT FB_OEn; - DATA_OUT(23 downto 16) <= VIDEO_BASE_L_D when VIDEO_BASE_L = '1' else - VIDEO_BASE_M_D when VIDEO_BASE_M = '1' else - VIDEO_BASE_H_D when VIDEO_BASE_H = '1' else - VIDEO_ACT_ADR(7 downto 0) when VIDEO_CNT_L = '1' else - VIDEO_ACT_ADR(15 downto 8) when VIDEO_CNT_M = '1' else - VIDEO_ACT_ADR(23 downto 16) when VIDEO_CNT_H = '1' else (others => '0'); + DATA_OUT(23 DOWNTO 16) <= video_base_l_d WHEN video_base_l = '1' ELSE + video_base_m_d WHEN video_base_m = '1' ELSE + video_base_h_d WHEN video_base_h = '1' ELSE + video_act_adr(7 DOWNTO 0) WHEN video_cnt_l = '1' ELSE + video_act_adr(15 DOWNTO 8) WHEN video_cnt_m = '1' ELSE + video_act_adr(23 DOWNTO 16) WHEN video_cnt_h = '1' ELSE (OTHERS => '0'); - DATA_EN_L <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L or VIDEO_CNT_M or VIDEO_CNT_H) and not FB_OEn; -end architecture BEHAVIOUR; + DATA_EN_L <= (video_base_l OR video_base_m OR video_base_h OR video_cnt_l OR video_cnt_m OR video_cnt_h) AND NOT FB_OEn; +END ARCHITECTURE BEHAVIOUR; -- VA : Video DDR address multiplexed --- VA_P : latched VA, wenn FIFO_AC, BLITTER_AC --- VA_S : latch for default VA +-- va_p : latched VA, wenn FIFO_AC, BLITTER_AC +-- va_s : latch for default VA -- BA : Video DDR bank address multiplexed --- BA_P : latched BA, wenn FIFO_AC, BLITTER_AC --- BA_S : latch for default BA +-- ba_p : latched BA, wenn FIFO_AC, BLITTER_AC +-- ba_s : latch for default BA -- --FB_SIZE ersetzen. diff --git a/vhdl/rtl/vhdl/DMA/fbee_dma.vhd b/vhdl/rtl/vhdl/DMA/fbee_dma.vhd index 4e4c6d7..aa8228a 100644 --- a/vhdl/rtl/vhdl/DMA/fbee_dma.vhd +++ b/vhdl/rtl/vhdl/DMA/fbee_dma.vhd @@ -1,414 +1,414 @@ ---------------------------------------------------------------------- ---- ---- ----- This file is part of the 'Firebee' project. ---- ----- http://acp.atari.org ---- +---- ThIS file IS part of the 'Firebee' project. ---- +---- http://acp.atari.ORg ---- ---- ---- ---- Description: ---- ----- This design unit provides the DMA controller of the 'Firebee'---- ----- computer. It is optimized for the use of an Altera Cyclone ---- ----- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- ----- tion of the Firebee configware originally provided by Fredi ---- ----- Ashwanden and Wolfgang Förster. This release is in compa- ---- ----- rision to the first edition completely written in VHDL. ---- +---- ThIS design unit provides the DMA controller of the 'Firebee'---- +---- computer. It IS optimized fOR the use of an Altera Cyclone ---- +---- FPGA (EP3C40F484). ThIS IP-CORe IS based on the first edi- ---- +---- tion of the Firebee configware ORigINally provided by Fredi ---- +---- AshwANDen AND Wolfgang Förster. ThIS release IS IN compa- ---- +---- rISion to the first edition completely written IN VHDL. ---- ---- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- AuthOR(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@INventronik.de ---- ---- ---- ---------------------------------------------------------------------- ---- ---- ----- Copyright (C) 2012 Fredi Aschwanden, Wolfgang Förster ---- +---- Copyright (C) 2012 Fredi AschwANDen, Wolfgang Förster ---- ---- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General Public ---- ----- License as published by the Free Software Foundation; either ---- ----- version 2 of the License, or (at your option) any later ---- +---- ThIS source file IS free software; you can redIStribute it ---- +---- AND/OR modIFy it under the terms of the GNU General Public ---- +---- License as publIShed by the Free Software Foundation; either ---- +---- version 2 of the License, OR (at your option) any later ---- ---- version. ---- ---- ---- ----- This program is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more ---- +---- ThIS program IS dIStributed IN the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; withOUT even the implied ---- +---- warranty of MERCHANTABILITY OR FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License fOR mORe ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU General Public ---- ----- License along with this program; if not, write to the Free ---- ----- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- +---- License along with thIS program; IF NOT, write to the Free ---- +---- Software Foundation, Inc., 51 FranklIN Street, FIFth FloOR, ---- ---- Boston, MA 02110-1301, USA. ---- ---- ---- ---------------------------------------------------------------------- -- --- Revision History +-- RevISion HIStORy -- --- Revision 2K12B 20120801 WF +-- RevISion 2K12B 20120801 WF -- Initial Release of the second edition. -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; +LIBRARY IEEE; + USE IEEE.std_logic_1164.ALL; + USE IEEE.numeric_std.ALL; -entity FBEE_DMA is - port( - RESET : in std_logic; - CLK_MAIN : in std_logic; - CLK_FDC : in std_logic; +ENTITY FBEE_DMA IS + PORT( + RESET : IN STD_LOGIC; + CLK_MAIN : IN STD_LOGIC; + CLK_FDC : IN STD_LOGIC; - FB_ADR : in std_logic_vector(26 downto 0); - FB_ALE : in std_logic; - FB_SIZE : in std_logic_vector(1 downto 0); - FB_CSn : in std_logic_vector(2 downto 1); - FB_OEn : in std_logic; - FB_WRn : in std_logic; - FB_AD_IN : in std_logic_vector(31 downto 0); - FB_AD_OUT : out std_logic_vector(31 downto 0); - FB_AD_EN_31_24 : out std_logic; - FB_AD_EN_23_16 : out std_logic; - FB_AD_EN_15_8 : out std_logic; - FB_AD_EN_7_0 : out std_logic; + FB_ADR : IN STD_LOGIC_VECTOR(26 DOWNTO 0); + FB_ALE : IN STD_LOGIC; + FB_SIZE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + FB_CSn : IN STD_LOGIC_VECTOR(2 DOWNTO 1); + FB_OEn : IN STD_LOGIC; + FB_WRn : IN STD_LOGIC; + FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + FB_AD_EN_31_24 : OUT STD_LOGIC; + FB_AD_EN_23_16 : OUT STD_LOGIC; + FB_AD_EN_15_8 : OUT STD_LOGIC; + FB_AD_EN_7_0 : OUT STD_LOGIC; - ACSI_DIR : out std_logic; - ACSI_D_IN : in std_logic_vector(7 downto 0); - ACSI_D_OUT : out std_logic_vector(7 downto 0); - ACSI_D_EN : out std_logic; - ACSI_CSn : out std_logic; - ACSI_A1 : out std_logic; - ACSI_RESETn : out std_logic; - ACSI_DRQn : in std_logic; - ACSI_ACKn : out std_logic; + ACSI_DIR : OUT STD_LOGIC; + ACSI_D_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + ACSI_D_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ACSI_D_EN : OUT STD_LOGIC; + ACSI_CSn : OUT STD_LOGIC; + ACSI_A1 : OUT STD_LOGIC; + ACSI_RESETn : OUT STD_LOGIC; + ACSI_DRQn : IN STD_LOGIC; + ACSI_ACKn : OUT STD_LOGIC; - DATA_IN_FDC : in std_logic_vector(7 downto 0); - DATA_IN_SCSI : in std_logic_vector(7 downto 0); - DATA_OUT_FDC_SCSI : out std_logic_vector(7 downto 0); + DATA_IN_FDC : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DATA_IN_SCSI : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DATA_OUT_FDC_SCSI : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - DMA_DRQ_IN : in std_logic; -- From 1772. - DMA_DRQ_OUT : out std_logic; -- To Interrupt handler. - DMA_DRQ11 : out std_logic; -- To MFP. + DMA_DRQ_IN : IN STD_LOGIC; -- From 1772. + DMA_DRQ_OUT : OUT STD_LOGIC; -- To Interrupt hANDler. + DMA_DRQ11 : OUT STD_LOGIC; -- To MFP. - SCSI_DRQ : in std_logic; - SCSI_DACKn : out std_logic; - SCSI_INT : in std_logic; - SCSI_CSn : out std_logic; - SCSI_CS : out std_logic; + SCSI_DRQ : IN STD_LOGIC; + SCSI_DACKn : OUT STD_LOGIC; + SCSI_INT : IN STD_LOGIC; + SCSI_CSn : OUT STD_LOGIC; + SCSI_CS : OUT STD_LOGIC; - CA : out std_logic_vector(2 downto 0); - FLOPPY_HD_DD : in std_logic; - WDC_BSL0 : out std_logic; - FDC_CSn : out std_logic; - FDC_WRn : out std_logic; - FD_INT : in std_logic; - IDE_INT : in std_logic; - DMA_CS : out std_logic + CA : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + FLOPPY_HD_DD : IN STD_LOGIC; + WDC_BSL0 : OUT STD_LOGIC; + FDC_CSn : OUT STD_LOGIC; + FDC_WRn : OUT STD_LOGIC; + FD_INT : IN STD_LOGIC; + IDE_INT : IN STD_LOGIC; + DMA_CS : OUT STD_LOGIC ); -end entity FBEE_DMA; +END ENTITY FBEE_DMA; -architecture BEHAVIOUR of FBEE_DMA is - component dcfifo0 is - port( - aclr : in std_logic := '0'; - data : in std_logic_vector (7 downto 0); - rdclk : in std_logic ; - rdreq : in std_logic ; - wrclk : in std_logic ; - wrreq : in std_logic ; - q : out std_logic_vector (31 downto 0); - wrusedw : out std_logic_vector (9 downto 0) +ARCHITECTURE BEHAVIOUR of FBEE_DMA IS + COMPONENT dcfIFo0 IS + PORT( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); - end component; + END COMPONENT; - component dcfifo1 is - port( - aclr : in std_logic := '0'; - data : in std_logic_vector (31 downto 0); - rdclk : in std_logic ; - rdreq : in std_logic ; - wrclk : in std_logic ; - wrreq : in std_logic ; - q : out std_logic_vector (7 downto 0); - rdusedw : out std_logic_vector (9 downto 0) + COMPONENT dcfIFo1 IS + PORT( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); - end component; + END COMPONENT; - type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); - signal FCF_STATE : FCF_STATES; - signal NEXT_FCF_STATE : FCF_STATES; - signal FCF_CS : std_logic; - signal FCF_APH : std_logic; + TYPE fcf_states_t IS (FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); + SIGNAL fcf_state : fcf_states_t; + SIGNAL next_fcf_state : fcf_states_t; + SIGNAL fcf_cs : STD_LOGIC; + SIGNAL fcf_aph : STD_LOGIC; - signal DMA_MODE_CS : std_logic; - signal DMA_DATA_CS : std_logic; - signal DMA_MODE : std_logic_vector(15 downto 0); - signal DMA_DRQQ : std_logic; - signal DMA_DRQ11_I : std_logic; - signal DMA_REQ : std_logic; - signal DMA_ACTIVE : std_logic; - signal DMA_ACTIVE_NEW : std_logic; - signal DMA_DRQ_REG : std_logic_vector(1 downto 0); - signal DMA_STATUS : std_logic_vector(2 downto 0); - signal DMA_AZ_CS : std_logic; + SIGNAL dma_mode_cs : STD_LOGIC; + SIGNAL dma_data_cs : STD_LOGIC; + SIGNAL dma_mode : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL dma_drqq : STD_LOGIC; + SIGNAL dma_drq11_i : STD_LOGIC; + SIGNAL dma_req : STD_LOGIC; + SIGNAL dma_active : STD_LOGIC; + SIGNAL dma_active_new : STD_LOGIC; + SIGNAL dma_drq_reg : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dma_status : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL dma_az_cs : STD_LOGIC; - signal DMA_BYTECNT_CS : std_logic; - signal DMA_DIRECT_CS : std_logic; - signal DMA_TOP_CS : std_logic; - signal DMA_HIGH_CS : std_logic; - signal DMA_MID_CS : std_logic; - signal DMA_LOW_CS : std_logic; - signal DMA_ADR_CS : std_logic; - signal DMA_BYTECNT : std_logic_vector(31 downto 0); - signal DMA_TOP : std_logic_vector(7 downto 0); - signal DMA_HIGH : std_logic_vector(7 downto 0); - signal DMA_MID : std_logic_vector(7 downto 0); - signal DMA_LOW : std_logic_vector(7 downto 0); + SIGNAL dma_bytecnt_cs : STD_LOGIC; + SIGNAL dma_direct_cs : STD_LOGIC; + SIGNAL dma_top_cs : STD_LOGIC; + SIGNAL dma_high_cs : STD_LOGIC; + SIGNAL dma_mid_cs : STD_LOGIC; + SIGNAL dma_low_cs : STD_LOGIC; + SIGNAL dma_adr_cs : STD_LOGIC; + SIGNAL dma_bytecnt : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_top : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dma_high : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dma_mid : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dma_low : STD_LOGIC_VECTOR(7 DOWNTO 0); - signal DMA_SND_CS : std_logic; - signal SNDMACTL : std_logic_vector(7 downto 0); - signal SNDBASHI : std_logic_vector(7 downto 0); - signal SNDBASMI : std_logic_vector(7 downto 0); - signal SNDBASLO : std_logic_vector(7 downto 0); - signal SNDADRHI : std_logic_vector(7 downto 0); - signal SNDADRMI : std_logic_vector(7 downto 0); - signal SNDADRLO : std_logic_vector(7 downto 0); - signal SNDENDHI : std_logic_vector(7 downto 0); - signal SNDENDMI : std_logic_vector(7 downto 0); - signal SNDENDLO : std_logic_vector(7 downto 0); - signal SNDMODE : std_logic_vector(7 downto 0); + SIGNAL DMA_SND_CS : STD_LOGIC; + SIGNAL SNDMACTL : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SNDBASHI : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SNDBASMI : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SNDBASLO : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SNDADRHI : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SNDADRMI : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SNDADRLO : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SNDENDHI : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SNDENDMI : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SNDENDLO : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SNDMODE : STD_LOGIC_VECTOR(7 DOWNTO 0); - signal WDC_BSL : std_logic_vector(1 downto 0); - signal FDC_CS_In : std_logic; - signal CLR_FIFO : std_logic; - signal FDC_OUT : std_logic_vector(7 downto 0); - signal RDF_DIN : std_logic_vector(7 downto 0); - signal RDF_DOUT : std_logic_vector(31 downto 0); - signal RDF_AZ : std_logic_vector(9 downto 0); - signal RDF_RDE : std_logic; - signal RDF_WRE : std_logic; - signal WRF_DATA_OUT : std_logic_vector(7 downto 0); - signal WRF_AZ : std_logic_vector(9 downto 0); - signal WRF_RDE : std_logic; - signal WRF_WRE : std_logic; - signal WDC_BSL_CS : std_logic; - signal CA_I : std_logic_vector(2 downto 0); - signal FDC_CS : std_logic; - signal SCSI_CS_I : std_logic; - signal LONG : std_logic; - signal BYTE : std_logic; - signal FB_B1 : std_logic; - signal FB_B0 : std_logic; - signal WRF_DOUT : std_logic_vector(7 downto 0); - signal FB_AD_I : std_logic_vector(7 downto 0); - signal d : std_logic_vector(31 downto 0); -begin - LONG <= '1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '0' else '0'; - BYTE <= '1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '1' else '0'; - FB_B0 <= '1' when FB_ADR(0) = '0' or BYTE = '0' else '0'; - FB_B1 <= '1' when FB_ADR(0) = '1' or BYTE = '0' else '0'; + SIGNAL WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL FDC_CS_In : STD_LOGIC; + SIGNAL CLR_FIFO : STD_LOGIC; + SIGNAL FDC_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL RDF_DIN : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL RDF_DOUT : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL RDF_AZ : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL RDF_RDE : STD_LOGIC; + SIGNAL RDF_WRE : STD_LOGIC; + SIGNAL WRF_DATA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL WRF_AZ : STD_LOGIC_VECTOR(9 DOWNTO 0); + SIGNAL WRF_RDE : STD_LOGIC; + SIGNAL WRF_WRE : STD_LOGIC; + SIGNAL WDC_BSL_CS : STD_LOGIC; + SIGNAL CA_I : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL FDC_CS : STD_LOGIC; + SIGNAL SCSI_CS_I : STD_LOGIC; + SIGNAL LONG : STD_LOGIC; + SIGNAL BYTE : STD_LOGIC; + SIGNAL FB_B1 : STD_LOGIC; + SIGNAL FB_B0 : STD_LOGIC; + SIGNAL WRF_DOUT : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL FB_AD_I : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL d : STD_LOGIC_VECTOR(31 DOWNTO 0); +BEGIN + LONG <= '1' WHEN FB_SIZE(1) = '0' AND FB_SIZE(0) = '0' ELSE '0'; + BYTE <= '1' WHEN FB_SIZE(1) = '0' AND FB_SIZE(0) = '1' ELSE '0'; + FB_B0 <= '1' WHEN FB_ADR(0) = '0' OR BYTE = '0' ELSE '0'; + FB_B1 <= '1' WHEN FB_ADR(0) = '1' OR BYTE = '0' ELSE '0'; - FB_AD_OUT(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and FB_OEn = '0' else - x"00" when DMA_DATA_CS = '1' and FB_OEn = '0' else - DMA_TOP when DMA_ADR_CS = '1' and FB_OEn = '0' else - DMA_BYTECNT(31 downto 24) when DMA_BYTECNT_CS = '1' and FB_OEn = '0' else - DMA_MODE(15 downto 8) when DMA_DIRECT_CS = '1' and FB_OEn = '0' else - x"00" when DMA_MODE_CS = '1' and FB_OEn = '0' else - DMA_DRQ11_I & DMA_DRQ_REG & IDE_INT & FD_INT & SCSI_INT & RDF_AZ(9 downto 8) when DMA_AZ_CS = '1' and FB_OEn = '0' else - RDF_DOUT(7 downto 0) when FCF_CS = '1' and FB_OEn = '0' else x"00"; + FB_AD_OUT(31 DOWNTO 24) <= dma_top WHEN dma_top_cs = '1' AND FB_OEn = '0' ELSE + x"00" WHEN dma_data_cs = '1' AND FB_OEn = '0' ELSE + dma_top WHEN dma_adr_cs = '1' AND FB_OEn = '0' ELSE + dma_bytecnt(31 DOWNTO 24) WHEN dma_bytecnt_cs = '1' AND FB_OEn = '0' ELSE + dma_mode(15 DOWNTO 8) WHEN dma_direct_cs = '1' AND FB_OEn = '0' ELSE + x"00" WHEN dma_mode_cs = '1' AND FB_OEn = '0' ELSE + dma_drq11_i & dma_drq_reg & IDE_INT & FD_INT & SCSI_INT & RDF_AZ(9 DOWNTO 8) WHEN dma_az_cs = '1' AND FB_OEn = '0' ELSE + RDF_DOUT(7 DOWNTO 0) WHEN fcf_cs = '1' AND FB_OEn = '0' ELSE x"00"; - FB_AD_OUT(23 downto 16) <= "00000" & DMA_STATUS when DMA_MODE_CS = '1' and FB_OEn = '0' else - FDC_OUT when DMA_DATA_CS = '1' and DMA_MODE(4 downto 3) = "00" and FB_OEn = '0' else - DATA_IN_SCSI when DMA_DATA_CS = '1' and DMA_MODE(4 downto 3) = "01" and FB_OEn = '0' else - DMA_BYTECNT(16 downto 9) when DMA_DATA_CS = '1' and DMA_MODE(4) = '1' and FB_OEn = '0' else - "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & FLOPPY_HD_DD when WDC_BSL_CS = '1' and FB_OEn = '0' else - RDF_AZ(7 downto 0) when DMA_AZ_CS = '1' and FB_OEn = '0' else - SNDMACTL when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_OEn = '0' else - SNDBASHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_OEn = '0' else - SNDBASMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"2" and FB_OEn = '0' else - SNDBASLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"3" and FB_OEn = '0' else - SNDADRHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"4" and FB_OEn = '0' else - SNDADRMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"5" and FB_OEn = '0' else - SNDADRLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"6" and FB_OEn = '0' else - SNDENDHI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"7" and FB_OEn = '0' else - SNDENDMI when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_OEn = '0' else - SNDENDLO when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_OEn = '0' else - SNDMODE when DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_OEn = '0' else - DMA_HIGH when DMA_HIGH_CS = '1' and FB_OEn = '0' else - DMA_MID when DMA_MID_CS = '1' and FB_OEn = '0' else - DMA_LOW when DMA_LOW_CS = '1' and FB_OEn = '0' else - DMA_MODE(7 downto 0) when DMA_DIRECT_CS = '1' and FB_OEn = '0' else - DMA_HIGH when DMA_ADR_CS = '1' and FB_OEn = '0' else - DMA_BYTECNT(23 downto 16) when DMA_BYTECNT_CS = '1' and FB_OEn = '0' else - RDF_DOUT(15 downto 8) when FCF_CS = '1' and FB_OEn = '0' else x"00"; + FB_AD_OUT(23 DOWNTO 16) <= "00000" & dma_status WHEN dma_mode_cs = '1' AND FB_OEn = '0' ELSE + FDC_OUT WHEN dma_data_cs = '1' AND dma_mode(4 DOWNTO 3) = "00" AND FB_OEn = '0' ELSE + DATA_IN_SCSI WHEN dma_data_cs = '1' AND dma_mode(4 DOWNTO 3) = "01" AND FB_OEn = '0' ELSE + dma_bytecnt(16 DOWNTO 9) WHEN dma_data_cs = '1' AND dma_mode(4) = '1' AND FB_OEn = '0' ELSE + "0000" & (NOT dma_status(1)) & "0" & WDC_BSL(1) & FLOPPY_HD_DD WHEN WDC_BSL_CS = '1' AND FB_OEn = '0' ELSE + RDF_AZ(7 DOWNTO 0) WHEN dma_az_cs = '1' AND FB_OEn = '0' ELSE + SNDMACTL WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"0" AND FB_OEn = '0' ELSE + SNDBASHI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"1" AND FB_OEn = '0' ELSE + SNDBASMI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"2" AND FB_OEn = '0' ELSE + SNDBASLO WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"3" AND FB_OEn = '0' ELSE + SNDADRHI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"4" AND FB_OEn = '0' ELSE + SNDADRMI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"5" AND FB_OEn = '0' ELSE + SNDADRLO WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"6" AND FB_OEn = '0' ELSE + SNDENDHI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"7" AND FB_OEn = '0' ELSE + SNDENDMI WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"8" AND FB_OEn = '0' ELSE + SNDENDLO WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"9" AND FB_OEn = '0' ELSE + SNDMODE WHEN DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"10" AND FB_OEn = '0' ELSE + dma_high WHEN dma_high_cs = '1' AND FB_OEn = '0' ELSE + dma_mid WHEN dma_mid_cs = '1' AND FB_OEn = '0' ELSE + dma_low WHEN dma_low_cs = '1' AND FB_OEn = '0' ELSE + dma_mode(7 DOWNTO 0) WHEN dma_direct_cs = '1' AND FB_OEn = '0' ELSE + dma_high WHEN dma_adr_cs = '1' AND FB_OEn = '0' ELSE + dma_bytecnt(23 DOWNTO 16) WHEN dma_bytecnt_cs = '1' AND FB_OEn = '0' ELSE + RDF_DOUT(15 DOWNTO 8) WHEN fcf_cs = '1' AND FB_OEn = '0' ELSE x"00"; - FB_AD_OUT(15 downto 8) <= "0" & DMA_STATUS & "00" & WRF_AZ(9 downto 8) when DMA_AZ_CS = '1' and FB_OEn = '0' else - DMA_MID when DMA_ADR_CS = '1' and FB_OEn = '0' else - DMA_BYTECNT(15 downto 8) when DMA_BYTECNT_CS = '1' and FB_OEn = '0' else - RDF_DOUT(23 downto 16) when FCF_CS = '1' and FB_OEn = '0' else x"00"; + FB_AD_OUT(15 DOWNTO 8) <= "0" & dma_status & "00" & WRF_AZ(9 DOWNTO 8) WHEN dma_az_cs = '1' AND FB_OEn = '0' ELSE + dma_mid WHEN dma_adr_cs = '1' AND FB_OEn = '0' ELSE + dma_bytecnt(15 DOWNTO 8) WHEN dma_bytecnt_cs = '1' AND FB_OEn = '0' ELSE + RDF_DOUT(23 DOWNTO 16) WHEN fcf_cs = '1' AND FB_OEn = '0' ELSE x"00"; - FB_AD_OUT(7 downto 0) <= WRF_AZ(7 downto 0) when DMA_AZ_CS = '1' and FB_OEn = '0' else - DMA_LOW when DMA_ADR_CS = '1' and FB_OEn = '0' else - DMA_BYTECNT(7 downto 0) when DMA_BYTECNT_CS = '1' and FB_OEn = '0' else - RDF_DOUT(31 downto 24) when FCF_CS = '1' and FB_OEn = '0' else x"00"; + FB_AD_OUT(7 DOWNTO 0) <= WRF_AZ(7 DOWNTO 0) WHEN dma_az_cs = '1' AND FB_OEn = '0' ELSE + dma_low WHEN dma_adr_cs = '1' AND FB_OEn = '0' ELSE + dma_bytecnt(7 DOWNTO 0) WHEN dma_bytecnt_cs = '1' AND FB_OEn = '0' ELSE + RDF_DOUT(31 DOWNTO 24) WHEN fcf_cs = '1' AND FB_OEn = '0' ELSE x"00"; - FB_AD_EN_31_24 <= (DMA_TOP_CS or DMA_DATA_CS or DMA_ADR_CS or DMA_BYTECNT_CS or DMA_DIRECT_CS or - DMA_MODE_CS or DMA_AZ_CS or FCF_CS) and not FB_OEn; + FB_AD_EN_31_24 <= (dma_top_cs OR dma_data_cs OR dma_adr_cs OR dma_bytecnt_cs OR dma_direct_cs OR + dma_mode_cs OR dma_az_cs OR fcf_cs) AND NOT FB_OEn; - FB_AD_EN_23_16 <= (DMA_MODE_CS or DMA_DATA_CS or WDC_BSL_CS or DMA_AZ_CS or DMA_SND_CS or DMA_HIGH_CS or - DMA_MID_CS or DMA_LOW_CS or DMA_DIRECT_CS or DMA_ADR_CS or DMA_BYTECNT_CS or FCF_CS) and not FB_OEn; + FB_AD_EN_23_16 <= (dma_mode_cs OR dma_data_cs OR WDC_BSL_CS OR dma_az_cs OR DMA_SND_CS OR dma_high_cs OR + dma_mid_cs OR dma_low_cs OR dma_direct_cs OR dma_adr_cs OR dma_bytecnt_cs OR fcf_cs) AND NOT FB_OEn; - FB_AD_EN_15_8 <= (DMA_AZ_CS or DMA_ADR_CS or DMA_BYTECNT_CS or FCF_CS) and not FB_OEn; + FB_AD_EN_15_8 <= (dma_az_cs OR dma_adr_cs OR dma_bytecnt_cs OR fcf_cs) AND NOT FB_OEn; - FB_AD_EN_7_0 <= (DMA_AZ_CS or DMA_ADR_CS or DMA_BYTECNT_CS or FCF_CS) and not FB_OEn; + FB_AD_EN_7_0 <= (dma_az_cs OR dma_adr_cs OR dma_bytecnt_cs OR fcf_cs) AND NOT FB_OEn; - INBUFFER: process(CLK_MAIN) - begin - if rising_edge(CLK_MAIN) then - if FB_WRn = '0' THEN - FB_AD_I <= FB_AD_IN(23 downto 16); - end if; - end if; - end process INBUFFER; + INBUFFER: PROCESS(CLK_MAIN) + BEGIN + IF RISING_EDGE(CLK_MAIN) THEN + IF FB_WRn = '0' THEN + FB_AD_I <= FB_AD_IN(23 DOWNTO 16); + END IF; + END IF; + END PROCESS INBUFFER; - -- ACSI is currently disabled. + -- ACSI IS currently dISabled. ACSI_DIR <= '0'; ACSI_D_OUT <= x"00"; ACSI_D_EN <= '0'; ACSI_CSn <= '1'; ACSI_A1 <= CA_I(1); - ACSI_RESETn <= not RESET; + ACSI_RESETn <= NOT RESET; ACSI_ACKn <= '1'; SCSI_CS <= SCSI_CS_I; - DMA_MODE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C303" else '0'; -- F8606/2 - DMA_DATA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C302" else '0'; -- F8604/2 - FDC_CS <= '1' when DMA_DATA_CS = '1' and DMA_MODE(4 downto 3) = "00" and FB_B1 = '1' else '0'; - SCSI_CS_I <= '1' when DMA_DATA_CS = '1' and DMA_MODE(4 downto 3) = "01" and FB_B1 = '1' else '0'; - DMA_AZ_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"002010C" else '0'; -- F002'010C LONG - DMA_TOP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 - DMA_HIGH_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 - DMA_MID_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 - DMA_LOW_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 - DMA_DIRECT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"20100" else '0'; -- F002'0100 WORD - DMA_ADR_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"20104" else '0'; -- F002'0104 LONG - DMA_BYTECNT_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"20108" else '0'; -- F002'0108 LONG - DMA_SND_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(20 downto 6) = 15x"3E24" else '0'; -- F8900-F893F - FCF_CS <= '1' when FB_CSn(2) = '0' and FB_ADR(26 downto 0) = 27x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY - DMA_CS <= FCF_CS or DMA_MODE_CS or DMA_SND_CS or DMA_ADR_CS or DMA_DIRECT_CS or DMA_BYTECNT_CS; - WDC_BSL_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(19 downto 1) = 19x"7C307" else '0'; -- F860E/2 + dma_mode_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C303" ELSE '0'; -- F8606/2 + dma_data_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C302" ELSE '0'; -- F8604/2 + FDC_CS <= '1' WHEN dma_data_cs = '1' AND dma_mode(4 DOWNTO 3) = "00" AND FB_B1 = '1' ELSE '0'; + SCSI_CS_I <= '1' WHEN dma_data_cs = '1' AND dma_mode(4 DOWNTO 3) = "01" AND FB_B1 = '1' ELSE '0'; + dma_az_cs <= '1' WHEN FB_CSn(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"002010C" ELSE '0'; -- F002'010C LONG + dma_top_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C304" AND FB_B0 = '1' ELSE '0'; -- F8608/2 + dma_high_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C304" AND FB_B1 = '1' ELSE '0'; -- F8609/2 + dma_mid_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2 + dma_low_cs <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2 + dma_direct_cs <= '1' WHEN FB_CSn(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"20100" ELSE '0'; -- F002'0100 WORD + dma_adr_cs <= '1' WHEN FB_CSn(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"20104" ELSE '0'; -- F002'0104 LONG + dma_bytecnt_cs <= '1' WHEN FB_CSn(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"20108" ELSE '0'; -- F002'0108 LONG + DMA_SND_CS <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(20 DOWNTO 6) = 15x"3E24" ELSE '0'; -- F8900-F893F + fcf_cs <= '1' WHEN FB_CSn(2) = '0' AND FB_ADR(26 DOWNTO 0) = 27x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY + DMA_CS <= fcf_cs OR dma_mode_cs OR DMA_SND_CS OR dma_adr_cs OR dma_direct_cs OR dma_bytecnt_cs; + WDC_BSL_CS <= '1' WHEN FB_CSn(1) = '0' AND FB_ADR(19 DOWNTO 1) = 19x"7C307" ELSE '0'; -- F860E/2 - FCF_APH <= '1' when FB_ALE = '1' and FB_AD_IN(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY + fcf_aph <= '1' WHEN FB_ALE = '1' AND FB_AD_IN(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY - RDF_DIN <= DATA_IN_FDC when DMA_MODE(7) = '1' else DATA_IN_SCSI; - RDF_RDE <= '1' when FCF_APH = '1' and FB_WRn = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE + RDF_DIN <= DATA_IN_FDC WHEN dma_mode(7) = '1' ELSE DATA_IN_SCSI; + RDF_RDE <= '1' WHEN fcf_aph = '1' AND FB_WRn = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE - DATA_OUT_FDC_SCSI <= WRF_DOUT when DMA_ACTIVE = '1' and DMA_MODE(8) = '1' else FB_AD_I; -- BEI DMA WRITE <-FIFO SONST <-FB + DATA_OUT_FDC_SCSI <= WRF_DOUT WHEN dma_active = '1' AND dma_mode(8) = '1' ELSE FB_AD_I; -- BEI DMA WRITE <-FIFO SONST <-FB - CA_I(0) <= '1' when DMA_ACTIVE = '1' else DMA_MODE(0); - CA_I(1) <= '1' when DMA_ACTIVE = '1' else DMA_MODE(1); - CA_I(2) <= '1' when DMA_ACTIVE = '1' else DMA_MODE(2); + CA_I(0) <= '1' WHEN dma_active = '1' ELSE dma_mode(0); + CA_I(1) <= '1' WHEN dma_active = '1' ELSE dma_mode(1); + CA_I(2) <= '1' WHEN dma_active = '1' ELSE dma_mode(2); CA <= CA_I; - FDC_WRn <= (not DMA_MODE(8)) when DMA_ACTIVE = '1' else FB_WRn; + FDC_WRn <= (NOT dma_mode(8)) WHEN dma_active = '1' ELSE FB_WRn; - DMA_MODE_REGISTER: process(RESET, CLK_MAIN) - begin - if RESET = '1' then - DMA_MODE <= x"0000"; - elsif rising_edge(CLK_MAIN) then - if DMA_MODE_CS = '1' and FB_WRn = '0' and FB_B0 = '1' then - DMA_MODE(15 downto 8) <= FB_AD_IN(31 downto 24); - elsif DMA_MODE_CS = '1' and FB_WRn = '0' and FB_B1 = '1' then - DMA_MODE(7 downto 0) <= FB_AD_IN(23 downto 16); - end if; - end if; - end process DMA_MODE_REGISTER; + dma_mode_REGISTER: PROCESS(RESET, CLK_MAIN) + BEGIN + IF RESET = '1' THEN + dma_mode <= x"0000"; + ELSIF RISING_EDGE(CLK_MAIN) THEN + IF dma_mode_cs = '1' AND FB_WRn = '0' AND FB_B0 = '1' THEN + dma_mode(15 DOWNTO 8) <= FB_AD_IN(31 DOWNTO 24); + ELSIF dma_mode_cs = '1' AND FB_WRn = '0' AND FB_B1 = '1' THEN + dma_mode(7 DOWNTO 0) <= FB_AD_IN(23 DOWNTO 16); + END IF; + END IF; + END PROCESS dma_mode_REGISTER; - BYTECOUNTER: process(RESET, CLR_FIFO, CLK_MAIN) - begin - if RESET = '1' or CLR_FIFO = '1' THEN - DMA_BYTECNT <= x"00000000"; - elsif rising_edge(CLK_MAIN) then - if DMA_DATA_CS = '1' and FB_WRn = '0' and DMA_MODE(4) = '1' and FB_B1 = '1' then - DMA_BYTECNT(31 downto 17) <= "000000000000000"; - DMA_BYTECNT(16 downto 9) <= FB_AD_IN(23 downto 16); - DMA_BYTECNT(8 downto 0) <= "000000000"; - elsif DMA_BYTECNT_CS = '1' and FB_WRn = '0' then - DMA_BYTECNT <= FB_AD_IN; - end if; - end if; - end process BYTECOUNTER; + BYTECOUNTER: PROCESS(RESET, CLR_FIFO, CLK_MAIN) + BEGIN + IF RESET = '1' OR CLR_FIFO = '1' THEN + dma_bytecnt <= x"00000000"; + ELSIF RISING_EDGE(CLK_MAIN) THEN + IF dma_data_cs = '1' AND FB_WRn = '0' AND dma_mode(4) = '1' AND FB_B1 = '1' THEN + dma_bytecnt(31 DOWNTO 17) <= "000000000000000"; + dma_bytecnt(16 DOWNTO 9) <= FB_AD_IN(23 DOWNTO 16); + dma_bytecnt(8 DOWNTO 0) <= "000000000"; + ELSIF dma_bytecnt_cs = '1' AND FB_WRn = '0' THEN + dma_bytecnt <= FB_AD_IN; + END IF; + END IF; + END PROCESS BYTECOUNTER; - WDC_BSL_REG: process(RESET, CLK_MAIN) - begin - if RESET = '1' THEN + WDC_BSL_REG: PROCESS(RESET, CLK_MAIN) + BEGIN + IF RESET = '1' THEN WDC_BSL <= "00"; - elsif rising_edge(CLK_MAIN) then - if WDC_BSL_CS = '1' and FB_WRn = '0' and FB_B0 = '1' then - WDC_BSL <= FB_AD_IN(25 downto 24); - end if; + ELSIF RISING_EDGE(CLK_MAIN) THEN + IF WDC_BSL_CS = '1' AND FB_WRn = '0' AND FB_B0 = '1' THEN + WDC_BSL <= FB_AD_IN(25 DOWNTO 24); + END IF; WDC_BSL0 <= WDC_BSL(0); - end if; - end process WDC_BSL_REG; + END IF; + END PROCESS WDC_BSL_REG; -- Rausoptimieren? - FDC_REG: process(RESET, CLK_FDC, FDC_CS_In) - begin - if RESET = '1' then + FDC_REG: PROCESS(RESET, CLK_FDC, FDC_CS_In) + BEGIN + IF RESET = '1' THEN FDC_OUT <= x"00"; - elsif rising_edge(CLK_FDC) then - if FDC_CS_In = '0' then + ELSIF RISING_EDGE(CLK_FDC) THEN + IF FDC_CS_In = '0' THEN FDC_OUT <= DATA_IN_FDC; - end if; - end if; + END IF; + END IF; FDC_CSn <= FDC_CS_In; - end process FDC_REG; + END PROCESS FDC_REG; - DMA_ADRESSREGISTERS: process(RESET, CLK_MAIN) - begin - if RESET = '1' THEN - DMA_TOP <= x"00"; - DMA_HIGH <= x"00"; - DMA_MID <= x"00"; - DMA_LOW <= x"00"; - elsif rising_edge(CLK_MAIN) then - if FB_WRn = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then - DMA_TOP <= FB_AD_IN(31 downto 24); - end if; - if FB_WRn = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then - DMA_HIGH <= FB_AD_IN(23 downto 16); - end if; - if FB_WRn = '0' and DMA_MID_CS = '1' then - DMA_MID <= FB_AD_IN(23 downto 16); - elsif FB_WRn = '0' and DMA_ADR_CS = '1' then - DMA_MID <= FB_AD_IN(15 downto 8); - end if; - if FB_WRn = '0' and DMA_LOW_CS = '1' then - DMA_LOW <= FB_AD_IN(23 downto 16); - elsif FB_WRn = '0' and DMA_ADR_CS = '1' then - DMA_LOW <= FB_AD_IN(7 downto 0); - end if; - end if; - end process DMA_ADRESSREGISTERS; + DMA_ADRESSREGISTERS: PROCESS(RESET, CLK_MAIN) + BEGIN + IF RESET = '1' THEN + dma_top <= x"00"; + dma_high <= x"00"; + dma_mid <= x"00"; + dma_low <= x"00"; + ELSIF RISING_EDGE(CLK_MAIN) THEN + IF FB_WRn = '0' AND (dma_top_cs = '1' OR dma_adr_cs = '1') THEN + dma_top <= FB_AD_IN(31 DOWNTO 24); + END IF; + IF FB_WRn = '0' AND (dma_high_cs = '1' OR dma_adr_cs = '1') THEN + dma_high <= FB_AD_IN(23 DOWNTO 16); + END IF; + IF FB_WRn = '0' AND dma_mid_cs = '1' THEN + dma_mid <= FB_AD_IN(23 DOWNTO 16); + ELSIF FB_WRn = '0' AND dma_adr_cs = '1' THEN + dma_mid <= FB_AD_IN(15 DOWNTO 8); + END IF; + IF FB_WRn = '0' AND dma_low_cs = '1' THEN + dma_low <= FB_AD_IN(23 DOWNTO 16); + ELSIF FB_WRn = '0' AND dma_adr_cs = '1' THEN + dma_low <= FB_AD_IN(7 DOWNTO 0); + END IF; + END IF; + END PROCESS DMA_ADRESSREGISTERS; - DMA_STATUS(0) <= '1'; -- DMA OK - DMA_STATUS(1) <= '1' when DMA_BYTECNT /= x"00000000" and DMA_BYTECNT(31) = '0' else '0'; -- When byts and not negative. - DMA_STATUS(2) <= '0' when DMA_DRQ_IN = '1' or SCSI_DRQ = '1' else '0'; + dma_status(0) <= '1'; -- DMA OK + dma_status(1) <= '1' WHEN dma_bytecnt /= x"00000000" AND dma_bytecnt(31) = '0' ELSE '0'; -- When byts AND NOT negative. + dma_status(2) <= '0' WHEN DMA_DRQ_IN = '1' OR SCSI_DRQ = '1' ELSE '0'; - DMA_REQ <= '1' when ((DMA_DRQ_IN = '1' and DMA_MODE(7) = '1') or (SCSI_DRQ = '1' and DMA_MODE(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODE(6) = '0' and CLR_FIFO = '0' else '0'; - DMA_DRQ_OUT <= '1' when DMA_DRQ_REG = "11" and DMA_MODE(6) = '0' else '0'; - DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODE(8) = '0' and unsigned(RDF_AZ) > 15 and DMA_MODE(6) = '0' else - '1' when DMA_STATUS(1) = '1' and DMA_MODE(8) = '1' and unsigned(WRF_AZ) < 512 and DMA_MODE(6) = '0' else '0'; - DMA_DRQ11_I <= '1' when DMA_DRQ_REG = "11" and DMA_MODE(6) = '0' else '0'; - DMA_DRQ11 <= DMA_DRQ11_I; + dma_req <= '1' WHEN ((DMA_DRQ_IN = '1' AND dma_mode(7) = '1') OR (SCSI_DRQ = '1' AND dma_mode(7) = '0')) AND dma_status(1) = '1' AND dma_mode(6) = '0' AND CLR_FIFO = '0' ELSE '0'; + DMA_DRQ_OUT <= '1' WHEN dma_drq_reg = "11" AND dma_mode(6) = '0' ELSE '0'; + dma_drqq <= '1' WHEN dma_status(1) = '1' AND dma_mode(8) = '0' AND unsigned(RDF_AZ) > 15 AND dma_mode(6) = '0' ELSE + '1' WHEN dma_status(1) = '1' AND dma_mode(8) = '1' AND unsigned(WRF_AZ) < 512 AND dma_mode(6) = '0' ELSE '0'; + dma_drq11_i <= '1' WHEN dma_drq_reg = "11" AND dma_mode(6) = '0' ELSE '0'; + DMA_DRQ11 <= dma_drq11_i; - SPIKEFILTER: process(RESET, CLK_FDC) - begin - if RESET = '1' THEN - DMA_DRQ_REG <= "00"; - elsif rising_edge(CLK_FDC) then - DMA_DRQ_REG(0) <= DMA_DRQQ; - DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; - end if; - end process SPIKEFILTER; + SPIKEFILTER: PROCESS(RESET, CLK_FDC) + BEGIN + IF RESET = '1' THEN + dma_drq_reg <= "00"; + ELSIF RISING_EDGE(CLK_FDC) THEN + dma_drq_reg(0) <= dma_drqq; + dma_drq_reg(1) <= dma_drq_reg(0) AND dma_drqq; + END IF; + END PROCESS SPIKEFILTER; - READ_FIFO: dcfifo0 - port map( + READ_FIFO: dcfIFo0 + PORT MAP( aclr => CLR_FIFO, data => RDF_DIN, rdclk => CLK_MAIN, @@ -419,24 +419,24 @@ begin wrusedw => RDF_AZ ); - FIFO_WRITE_CTRL: process(RESET, CLK_MAIN) - begin - if RESET = '1' THEN + FIFO_WRITE_CTRL: PROCESS(RESET, CLK_MAIN) + BEGIN + IF RESET = '1' THEN WRF_WRE <= '0'; - elsif rising_edge(CLK_MAIN) then - if FCF_APH = '1' and FB_WRn = '0' then + ELSIF RISING_EDGE(CLK_MAIN) THEN + IF fcf_aph = '1' AND FB_WRn = '0' THEN WRF_WRE <= '1'; - else + ELSE WRF_WRE <= '0'; - end if; - end if; - end process FIFO_WRITE_CTRL; + END IF; + END IF; + END PROCESS FIFO_WRITE_CTRL; - d <= FB_AD_IN(7 downto 0) & FB_AD_IN(15 downto 8) & FB_AD_IN(23 downto 16) & FB_AD_IN(31 downto 24); + d <= FB_AD_IN(7 DOWNTO 0) & FB_AD_IN(15 DOWNTO 8) & FB_AD_IN(23 DOWNTO 16) & FB_AD_IN(31 DOWNTO 24); - WRITE_FIFO: dcfifo1 - port map( + WRITE_FIFO: dcfIFo1 + PORT MAP( aclr => CLR_FIFO, data => d, rdclk => CLK_FDC, @@ -447,9 +447,9 @@ begin rdusedw => WRF_AZ ); - SOUNDREGS: process(RESET, CLK_MAIN) - begin - if RESET = '1' then + SOUNDREGS: PROCESS(RESET, CLK_MAIN) + BEGIN + IF RESET = '1' THEN SNDMACTL <= x"00"; SNDBASHI <= x"00"; SNDBASMI <= x"00"; @@ -461,129 +461,129 @@ begin SNDENDMI <= x"00"; SNDENDLO <= x"00"; SNDMODE <= x"00"; - elsif CLK_MAIN = '1' and CLK_MAIN' event then - if DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_WRn = '0' and FB_B1 ='1' then - SNDMACTL <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_WRn = '0' and FB_B1 ='1' then - SNDBASHI <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"2" and FB_WRn = '0' and FB_B1 ='1' then - SNDBASMI <= FB_AD_IN(23downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"3" and FB_WRn = '0' and FB_B1 ='1' then - SNDBASLO <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"4" and FB_WRn = '0' and FB_B1 ='1' then - SNDADRHI <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"5" and FB_WRn = '0' and FB_B1 ='1' then - SNDADRMI <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"6" and FB_WRn = '0' and FB_B1 ='1' then - SNDADRLO <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"7" and FB_WRn = '0' and FB_B1 ='1' then - SNDENDHI <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_WRn = '0' and FB_B1 ='1' then - SNDENDMI <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_WRn = '0' and FB_B1 ='1' then - SNDENDLO <= FB_AD_IN(23 downto 16); - elsif DMA_SND_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_WRn = '0' and FB_B1 ='1' then - SNDMODE <= FB_AD_IN(23 downto 16); - end if; - end if; - end process SOUNDREGS; + ELSIF CLK_MAIN = '1' AND CLK_MAIN' event THEN + IF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"0" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDMACTL <= FB_AD_IN(23 DOWNTO 16); + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"1" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDBASHI <= FB_AD_IN(23 DOWNTO 16); + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"2" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDBASMI <= FB_AD_IN(23DOWNTO 16); + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"3" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDBASLO <= FB_AD_IN(23 DOWNTO 16); + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"4" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDADRHI <= FB_AD_IN(23 DOWNTO 16); + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"5" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDADRMI <= FB_AD_IN(23 DOWNTO 16); + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"6" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDADRLO <= FB_AD_IN(23 DOWNTO 16); + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"7" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDENDHI <= FB_AD_IN(23 DOWNTO 16); + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"8" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDENDMI <= FB_AD_IN(23 DOWNTO 16); + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"9" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDENDLO <= FB_AD_IN(23 DOWNTO 16); + ELSIF DMA_SND_CS = '1' AND FB_ADR(5 DOWNTO 1) = 5x"10" AND FB_WRn = '0' AND FB_B1 ='1' THEN + SNDMODE <= FB_AD_IN(23 DOWNTO 16); + END IF; + END IF; + END PROCESS SOUNDREGS; - CLEAR_BY_TOGGLE: process(RESET, CLK_MAIN, DMA_MODE) - variable DMA_DIR_OLD : std_logic; - begin - if RESET = '1' THEN + CLEAR_BY_TOGGLE: PROCESS(RESET, CLK_MAIN, dma_mode) + VARIABLE DMA_DIR_OLD : STD_LOGIC; + BEGIN + IF RESET = '1' THEN DMA_DIR_OLD := '0'; - elsif CLK_MAIN = '1' and CLK_MAIN' event then - if DMA_MODE_CS = '0' then - DMA_DIR_OLD := DMA_MODE(8); - end if; - end if; - CLR_FIFO <= DMA_MODE(8) xor DMA_DIR_OLD; - end process CLEAR_BY_TOGGLE; + ELSIF CLK_MAIN = '1' AND CLK_MAIN' event THEN + IF dma_mode_cs = '0' THEN + DMA_DIR_OLD := dma_mode(8); + END IF; + END IF; + CLR_FIFO <= dma_mode(8) xOR DMA_DIR_OLD; + END PROCESS CLEAR_BY_TOGGLE; - FCF_REG: process(RESET, CLK_FDC) - begin - if RESET = '1' then - FCF_STATE <= FCF_IDLE; - DMA_ACTIVE <= '0'; - elsif rising_edge(CLK_FDC) then - FCF_STATE <= NEXT_FCF_STATE; - DMA_ACTIVE <= DMA_ACTIVE_NEW; - end if; - end process FCF_REG; + FCF_REG: PROCESS(RESET, CLK_FDC) + BEGIN + IF RESET = '1' THEN + fcf_state <= FCF_IDLE; + dma_active <= '0'; + ELSIF RISING_EDGE(CLK_FDC) THEN + fcf_state <= next_fcf_state; + dma_active <= dma_active_new; + END IF; + END PROCESS FCF_REG; - FCF_DECODER: process(FCF_STATE, DMA_REQ, FDC_CS, SCSI_CS_I, DMA_ACTIVE, DMA_MODE) - begin - case FCF_STATE is - when FCF_IDLE => + FCF_DECODER: PROCESS(fcf_state, dma_req, FDC_CS, SCSI_CS_I, dma_active, dma_mode) + BEGIN + CASE fcf_state IS + WHEN FCF_IDLE => SCSI_CSn <= '1'; FDC_CS_In <= '1'; RDF_WRE <= '0'; WRF_RDE <= '0'; SCSI_DACKn <= '1'; - if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS_I = '1' then - DMA_ACTIVE_NEW <= DMA_REQ; - NEXT_FCF_STATE <= FCF_T0; - else - DMA_ACTIVE_NEW <= '0'; - NEXT_FCF_STATE <= FCF_IDLE; - end if; - when FCF_T0 => + IF dma_req = '1' OR FDC_CS = '1' OR SCSI_CS_I = '1' THEN + dma_active_new <= dma_req; + next_fcf_state <= FCF_T0; + ELSE + dma_active_new <= '0'; + next_fcf_state <= FCF_IDLE; + END IF; + WHEN FCF_T0 => SCSI_CSn <= '1'; FDC_CS_In <= '1'; RDF_WRE <= '0'; SCSI_DACKn <= '1'; - DMA_ACTIVE_NEW <= DMA_REQ; - WRF_RDE <= DMA_MODE(8) and DMA_REQ; -- Write -> Read from FIFO - if DMA_REQ = '0' and DMA_ACTIVE = '1' then -- Spike? - NEXT_FCF_STATE <= FCF_IDLE; -- Yes -> Start - else - NEXT_FCF_STATE <= FCF_T1; - end if; - when FCF_T1 => + dma_active_new <= dma_req; + WRF_RDE <= dma_mode(8) AND dma_req; -- Write -> Read from FIFO + IF dma_req = '0' AND dma_active = '1' THEN -- Spike? + next_fcf_state <= FCF_IDLE; -- Yes -> Start + ELSE + next_fcf_state <= FCF_T1; + END IF; + WHEN FCF_T1 => RDF_WRE <= '0'; WRF_RDE <= '0'; - DMA_ACTIVE_NEW <= DMA_ACTIVE; - SCSI_CSn <= not SCSI_CS_I; - FDC_CS_In <= DMA_MODE(4) or DMA_MODE(3); - SCSI_DACKn <= DMA_MODE(7) and DMA_ACTIVE; - NEXT_FCF_STATE <= FCF_T2; - when FCF_T2 => + dma_active_new <= dma_active; + SCSI_CSn <= NOT SCSI_CS_I; + FDC_CS_In <= dma_mode(4) OR dma_mode(3); + SCSI_DACKn <= dma_mode(7) AND dma_active; + next_fcf_state <= FCF_T2; + WHEN FCF_T2 => RDF_WRE <= '0'; WRF_RDE <= '0'; - DMA_ACTIVE_NEW <= DMA_ACTIVE; - SCSI_CSn <= not SCSI_CS_I; - FDC_CS_In <= DMA_MODE(4) or DMA_MODE(3); - SCSI_DACKn <= DMA_MODE(7) and DMA_ACTIVE; - NEXT_FCF_STATE <= FCF_T3; - when FCF_T3 => + dma_active_new <= dma_active; + SCSI_CSn <= NOT SCSI_CS_I; + FDC_CS_In <= dma_mode(4) OR dma_mode(3); + SCSI_DACKn <= dma_mode(7) AND dma_active; + next_fcf_state <= FCF_T3; + WHEN FCF_T3 => RDF_WRE <= '0'; WRF_RDE <= '0'; - DMA_ACTIVE_NEW <= DMA_ACTIVE; - SCSI_CSn <= not SCSI_CS_I; - FDC_CS_In <= DMA_MODE(4) or DMA_MODE(3); - SCSI_DACKn <= DMA_MODE(7) and DMA_ACTIVE; - NEXT_FCF_STATE <= FCF_T6; - when FCF_T6 => + dma_active_new <= dma_active; + SCSI_CSn <= NOT SCSI_CS_I; + FDC_CS_In <= dma_mode(4) OR dma_mode(3); + SCSI_DACKn <= dma_mode(7) AND dma_active; + next_fcf_state <= FCF_T6; + WHEN FCF_T6 => WRF_RDE <= '0'; - DMA_ACTIVE_NEW <= DMA_ACTIVE; - SCSI_CSn <= not SCSI_CS_I; - FDC_CS_In <= DMA_MODE(4) or DMA_MODE(3); - SCSI_DACKn <= DMA_MODE(7) and DMA_ACTIVE; - RDF_WRE <= not DMA_MODE(8) and DMA_ACTIVE; -- Read -> Write to FIFO - NEXT_FCF_STATE <= FCF_T7; - when FCF_T7 => + dma_active_new <= dma_active; + SCSI_CSn <= NOT SCSI_CS_I; + FDC_CS_In <= dma_mode(4) OR dma_mode(3); + SCSI_DACKn <= dma_mode(7) AND dma_active; + RDF_WRE <= NOT dma_mode(8) AND dma_active; -- Read -> Write to FIFO + next_fcf_state <= FCF_T7; + WHEN FCF_T7 => SCSI_CSn <= '1'; FDC_CS_In <= '1'; RDF_WRE <= '0'; WRF_RDE <= '0'; SCSI_DACKn <= '1'; - DMA_ACTIVE_NEW <= '0'; - if FDC_CS = '1' and DMA_REQ = '0' then - NEXT_FCF_STATE <= FCF_T7; - else - NEXT_FCF_STATE <= FCF_IDLE; - end if; - end case; - end process FCF_DECODER; -end architecture BEHAVIOUR; + dma_active_new <= '0'; + IF FDC_CS = '1' AND dma_req = '0' THEN + next_fcf_state <= FCF_T7; + ELSE + next_fcf_state <= FCF_IDLE; + END IF; + END CASE; + END PROCESS FCF_DECODER; +END ARCHITECTURE BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd index 3d29d8a..9686523 100644 --- a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd +++ b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd @@ -1,1321 +1,1311 @@ ----------------------------------------------------------------------- ----- ---- ----- This file is part of the 'Firebee' project. ---- ----- http://acp.atari.org ---- ----- ---- ----- Description: ---- ----- This design unit provides the toplevel of the 'Firebee' ---- ----- computer. It is optimized for the use of an Altera Cyclone ---- ----- FPGA (EP3C40F484). This IP-Core is based on the first edi- ---- ----- tion of the Firebee configware originally provided by Fredi ---- ----- Ashwanden and Wolfgang Förster. This release is in compa- ---- ----- rision to the first edition completely written in VHDL. ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2012 Wolfgang Förster ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General Public ---- ----- License as published by the Free Software Foundation; either ---- ----- version 2 of the License, or (at your option) any later ---- ----- version. ---- ----- ---- ----- This program is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU General Public ---- ----- License along with this program; if not, write to the Free ---- ----- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ----- Boston, MA 02110-1301, USA. ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K12B 20120801 WF --- Initial Release of the second edition, the most important changes are listed below. --- Structural work: --- Replaced the graphical top level by a VHDL model. --- The new toplevel is now FIREBEE_V1. --- Replaced the graphical Video Top Level by a VHDL model --- The DDR_CTR is now DDR_CTRL. --- Rewritten the DDR_CTR in VHDL. --- Moved the DDR_CTRL to the FIREBEE_V1 top level. --- Moved the BLITTER to the FIREBEE_V1 top level. --- Removed the VIDEO_MOD_MUX_CLUTCTR. --- Extracted from the AHDL code of MOD_MUX_CLUTCTR the new VIDEO_CTRL. --- VIDEO_CTRL is now written in VHDL. --- Removed the FalconIO_SDCard_IDE_CF. --- Moved the keyboard ACIA from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. --- Moved the MIDI ACIA from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. --- Moved the soundchip module from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. --- Moved the multi function port (MFP) from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. --- Moved the floppy disk controller (FDC) from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. --- Moved the SCSI controller from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. --- Extracted a DMA logic from FalconIO_SDCard_IDE_CF which is now located in the FIREBEE_V1 top level. --- Extracted a IDE_CF_SD_ROM logic from FalconIO_SDCard_IDE_CF which is now located in the FIREBEE_V1 top level. --- Moved the PADDLE logic from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. --- Rewritten the interrupt handler in VHDL. --- Extracted the real time clock (RTC) logic from the interrupt handler (VHDL). --- The RTC is now located in the FIREBEE_V1 top level. --- Several code cleanups: --- Resolved the tri state logic in all modules. The only tri states are now in the --- top level FIREBEE_V1. --- Replaced several Altera lpm modules to achieve a manufacturer independant code. --- However we have still some modules like memory or FIFOs which are required up to now. --- Removed the VDR latch. --- Removed the AMKBD filter. --- Updated all Suska-Codes (ACIA, MFP, 5380, 1772, 2149) to the latest code base. --- The sound module works now on the positive clock edge. --- The multi function port works now on the positive clock edge. --- Naming conventions: --- Replaced the 'n' prefixes with 'n' postfixes to achieve consistent signal names. --- Replaced the old ACP_xx signal names by FBEE_xx (ACP is the old working title). --- Improvements (hopefully) --- Fixed the VIDEO_RECONFIG strobe logic in the video control section. --- Others: --- Provided file headers to all Firebee relevant design units. --- Provided a timequest constraint file. --- Switched all code elements to English language. --- Provided a complete new file structure for the project. --- - -library work; -use work.firebee_pkg.all; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity firebee is - port( - RSTO_MCFn : in std_logic; -- reset signal from Coldfire - CLK_33M : in std_logic; -- 33 MHz clock - CLK_MAIN : in std_logic; -- 33 MHz clock - - CLK_24M576 : out std_logic; -- - CLK_25M : out std_logic; - CLK_DDR_OUT : out std_logic; - CLK_DDR_OUTn : out std_logic; - CLK_USB : out std_logic; - - FB_AD : inout std_logic_vector(31 downto 0); - FB_ALE : in std_logic; - FB_BURSTn : in std_logic; - FB_CSn : in std_logic_vector(3 downto 1); - FB_SIZE : in std_logic_vector(1 downto 0); - FB_OEn : in std_logic; - FB_WRn : in std_logic; - FB_TAn : out std_logic; - - DACK1n : in std_logic; - DREQ1n : out std_logic; - - MASTERn : in std_logic; -- determines if the Firebee is PCI master (='0') or slave. Not used so far. - TOUT0n : in std_logic; -- Not used so far. - - LED_FPGA_OK : out std_logic; - RESERVED_1 : out std_logic; - - VA : out std_logic_vector(12 downto 0); - BA : out std_logic_vector(1 downto 0); - VWEn : out std_logic; - VCASn : out std_logic; - VRASn : out std_logic; - VCSn : out std_logic; - - CLK_PIXEL : out std_logic; - SYNCn : out std_logic; - VSYNC : out std_logic; - HSYNC : out std_logic; - BLANKn : out std_logic; - - VR : out std_logic_vector(7 downto 0); - VG : out std_logic_vector(7 downto 0); - VB : out std_logic_vector(7 downto 0); - - VDM : out std_logic_vector(3 downto 0); - - VD : inout std_logic_vector(31 downto 0); - VD_QS : out std_logic_vector(3 downto 0); - - PD_VGAn : out std_logic; - VCKE : out std_logic; - PIC_INT : in std_logic; - E0_INT : in std_logic; - DVI_INT : in std_logic; - PCI_INTAn : in std_logic; - PCI_INTBn : in std_logic; - PCI_INTCn : in std_logic; - PCI_INTDn : in std_logic; - - IRQn : out std_logic_vector(7 downto 2); - TIN0 : out std_logic; - - YM_QA : out std_logic; - YM_QB : out std_logic; - YM_QC : out std_logic; - - LP_D : inout std_logic_vector(7 downto 0); - LP_DIR : out std_logic; - - DSA_D : out std_logic; - LP_STR : out std_logic; - DTR : out std_logic; - RTS : out std_logic; - CTS : in std_logic; - RI : in std_logic; - DCD : in std_logic; - LP_BUSY : in std_logic; - RxD : in std_logic; - TxD : out std_logic; - MIDI_IN : in std_logic; - MIDI_OLR : out std_logic; - MIDI_TLR : out std_logic; - PIC_AMKB_RX : in std_logic; - AMKB_RX : in std_logic; - AMKB_TX : out std_logic; - DACK0n : in std_logic; -- Not used. - - SCSI_DRQn : in std_logic; - SCSI_MSGn : in std_logic; - SCSI_CDn : in std_logic; - SCSI_IOn : in std_logic; - SCSI_ACKn : out std_logic; - SCSI_ATNn : out std_logic; - SCSI_SELn : inout std_logic; - SCSI_BUSYn : inout std_logic; - SCSI_RSTn : inout std_logic; - SCSI_DIR : out std_logic; - SCSI_D : inout std_logic_vector(7 downto 0); - SCSI_PAR : inout std_logic; - - ACSI_DIR : out std_logic; - ACSI_D : inout std_logic_vector(7 downto 0); - ACSI_CSn : out std_logic; - ACSI_A1 : out std_logic; - ACSI_RESETn : out std_logic; - ACSI_ACKn : out std_logic; - ACSI_DRQn : in std_logic; - ACSI_INTn : in std_logic; - - FDD_DCHGn : in std_logic; - FDD_SDSELn : out std_logic; - FDD_HD_DD : in std_logic; - FDD_RDn : in std_logic; - FDD_TRACK00 : in std_logic; - FDD_INDEXn : in std_logic; - FDD_WPn : in std_logic; - FDD_MOT_ON : out std_logic; - FDD_WR_GATE : out std_logic; - FDD_WDn : out std_logic; - FDD_STEP : out std_logic; - FDD_STEP_DIR : out std_logic; - - ROM4n : out std_logic; - ROM3n : out std_logic; - - RP_UDSn : out std_logic; - RP_LDSn : out std_logic; - SD_CLK : out std_logic; - SD_D3 : inout std_logic; - SD_CMD_D1 : inout std_logic; - SD_D0 : in std_logic; - SD_D1 : in std_logic; - SD_D2 : in std_logic; - SD_CARD_DETECT : in std_logic; - SD_WP : in std_logic; - - CF_WP : in std_logic; - CF_CSn : out std_logic_vector(1 downto 0); - - DSP_IO : inout std_logic_vector(17 downto 0); - DSP_SRD : inout std_logic_vector(15 downto 0); - DSP_SRCSn : out std_logic; - DSP_SRBLEn : out std_logic; - DSP_SRBHEn : out std_logic; - DSP_SRWEn : out std_logic; - DSP_SROEn : out std_logic; - - IDE_INT : in std_logic; - IDE_RDY : in std_logic; - IDE_RES : out std_logic; - IDE_WRn : out std_logic; - IDE_RDn : out std_logic; - IDE_CSn : out std_logic_vector(1 downto 0) - ); -end entity firebee; - -architecture Structure of firebee is - component altpll1 - port( - inclk0 : in std_logic := '0'; - c0 : out std_logic ; - c1 : out std_logic ; - c2 : out std_logic ; - locked : out std_logic - ); - end component; - - component altpll2 - port( - inclk0 : in std_logic := '0'; - c0 : out std_logic ; - c1 : out std_logic ; - c2 : out std_logic ; - c3 : out std_logic ; - c4 : out std_logic - ); - end component; - - component altpll3 - port( - inclk0 : in std_logic := '0'; - c0 : out std_logic ; - c1 : out std_logic ; - c2 : out std_logic ; - c3 : out std_logic - ); - end component; - - component altpll4 - port( - areset : in std_logic := '0'; - configupdate : in std_logic := '0'; - inclk0 : in std_logic := '0'; - scanclk : in std_logic := '1'; - scanclkena : in std_logic := '0'; - scandata : in std_logic := '0'; - c0 : out std_logic ; - locked : out std_logic ; - scandataout : out std_logic ; - scandone : out std_logic - ); - end component; - - component altpll_reconfig1 - port( - busy : out std_logic; - clock : in std_logic; - counter_param : in std_logic_VECTOR (2 downto 0) := (others => '0'); - counter_type : in std_logic_VECTOR (3 downto 0) := (others => '0'); - data_in : in std_logic_VECTOR (8 downto 0) := (others => '0'); - data_out : out std_logic_VECTOR (8 downto 0); - pll_areset : out std_logic; - pll_areset_in : in std_logic := '0'; - pll_configupdate : out std_logic; - pll_scanclk : out std_logic; - pll_scanclkena : out std_logic; - pll_scandata : out std_logic; - pll_scandataout : in std_logic := '0'; - pll_scandone : in std_logic := '0'; - read_param : in std_logic := '0'; - reconfig : in std_logic := '0'; - reset : in std_logic; - write_param : in std_logic := '0' - ); - end component; - - signal ACIA_CS : std_logic; - signal ACIA_IRQn : std_logic; - signal ACSI_D_OUT : std_logic_vector(7 downto 0); - signal ACSI_D_EN : std_logic; - signal BLANK_In : std_logic; - signal BLITTER_ADR : std_logic_vector(31 downto 0); - signal BLITTER_DACK_SR : std_logic; - signal BLITTER_DOUT : std_logic_vector(127 downto 0); - signal BLITTER_ON : std_logic; - signal BLITTER_RUN : std_logic; - signal BLITTER_SIG : std_logic; - signal BLITTER_TA : std_logic; - signal BLITTER_WR : std_logic; - signal BYTE : std_logic; -- When Byte -> 1 - signal CA : std_logic_vector(2 downto 0); - signal CLK_2M0 : std_logic; - signal CLK_2M4576 : std_logic; - signal CLK_25M_I : std_logic; - signal CLK_48M : std_logic; - signal CLK_500K : std_logic; - signal CLK_DDR : std_logic_vector(3 downto 0); - signal CLK_FDC : std_logic; - signal CLK_PIXEL_I : std_logic; - signal CLK_VIDEO : std_logic; - signal DA_OUT_X : std_logic_vector(7 downto 0); - signal DATA_EN_BLITTER : std_logic; - signal DATA_EN_H_DDR_CTRL : std_logic; - signal DATA_EN_L_DDR_CTRL : std_logic; - signal DATA_IN_FDC_SCSI : std_logic_vector(7 downto 0); - signal DATA_OUT_ACIA_I : std_logic_vector(7 downto 0); - signal DATA_OUT_ACIA_II : std_logic_vector(7 downto 0); - signal DATA_OUT_BLITTER : std_logic_vector(31 downto 0); - signal DATA_OUT_DDR_CTRL : std_logic_vector(31 downto 16); - signal DATA_OUT_FDC : std_logic_vector(7 downto 0); - signal DATA_OUT_MFP : std_logic_vector(7 downto 0); - signal DATA_OUT_SCSI : std_logic_vector(7 downto 0); - signal DINTn : std_logic; - signal DDR_D_IN_N : std_logic_vector(31 downto 0); - signal DDR_FB : std_logic_vector(4 downto 0); - signal DDR_SYNC_66M : std_logic; - signal DDR_WR : std_logic; - signal DDRWR_D_SEL : std_logic_vector(1 downto 0); - signal DMA_CS : std_logic; - signal DRQ11_DMA : std_logic; - signal DRQ_FDC : std_logic; - signal DRQ_DMA : std_logic; - signal DSP_INT : std_logic; - signal DSP_IO_EN : std_logic; - signal DSP_IO_OUT : std_logic_vector(17 downto 0); - signal DSP_SRD_EN : std_logic; - signal DSP_SRD_OUT : std_logic_vector(15 downto 0); - signal DSP_TA : std_logic; - signal DTACK_OUT_MFPn : std_logic; - signal FALCON_IO_TA : std_logic; - signal FB_AD_EN_15_0_VIDEO : std_logic; - signal FB_AD_EN_31_16_VIDEO : std_logic; - signal FB_AD_EN_7_0_DMA : std_logic; - signal FB_AD_EN_7_0_IH : std_logic; - signal FB_AD_EN_15_8_DMA : std_logic; - signal FB_AD_EN_15_8_IH : std_logic; - signal FB_AD_EN_23_16_DMA : std_logic; - signal FB_AD_EN_23_16_IH : std_logic; - signal FB_AD_EN_31_24_DMA : std_logic; - signal FB_AD_EN_31_24_IH : std_logic; - signal FB_AD_EN_DSP : std_logic; - signal FB_AD_EN_RTC : std_logic; - signal FB_AD_OUT_DMA : std_logic_vector(31 downto 0); - signal FB_AD_OUT_DSP : std_logic_vector(31 downto 0); - signal FB_AD_OUT_IH : std_logic_vector(31 downto 0); - signal FB_AD_OUT_RTC : std_logic_vector(7 downto 0); - signal FB_AD_OUT_VIDEO : std_logic_vector(31 downto 0); - signal FB_ADR : std_logic_vector(31 downto 0); - signal FB_B0 : std_logic; -- UPPER Byte BEI 16 std_logic BUS - signal FB_B1 : std_logic; -- LOWER Byte BEI 16 std_logic BUS - signal FB_DDR : std_logic_vector(127 downto 0); - signal FB_LE : std_logic_vector(3 downto 0); - signal FB_VDOE : std_logic_vector(3 downto 0); - signal FBEE_CONF : std_logic_vector(31 downto 0); - signal FD_INT : std_logic; - signal FDC_CSn : std_logic; - signal FDC_WRn : std_logic; - signal FIFO_CLR : std_logic; - signal FIFO_MW : std_logic_vector(8 downto 0); - signal HD_DD_OUT : std_logic; - signal HSYNC_I : std_logic; - signal IDE_CF_TA : std_logic; - signal IDE_RES_I : std_logic; - signal INT_HANDLER_TA : std_logic; - signal IRQ_KEYBDn : std_logic; - signal IRQ_MIDIn : std_logic; - signal KEYB_RxD : std_logic; - signal LDS : std_logic; - signal LOCKED : std_logic; - signal LP_D_X : std_logic_vector(7 downto 0); - signal LP_DIR_X : std_logic; - signal MFP_CS : std_logic; - signal MFP_INTACK : std_logic; - signal MFP_INTn : std_logic; - signal MIDI_OUT : std_logic; - signal PADDLE_CS : std_logic; - signal PLL_ARESET : std_logic; - signal PLL_SCANCLK : std_logic; - signal PLL_SCANDATA : std_logic; - signal PLL_SCANCLKENA : std_logic; - signal PLL_CONFIGUPDATE : std_logic; - signal PLL_SCANDONE : std_logic; - signal PLL_SCANDATAOUT : std_logic; - signal RESETn : std_logic; - signal SCSI_BSY_EN : std_logic; - signal SCSI_BSY_OUTn : std_logic; - signal SCSI_CS : std_logic; - signal SCSI_CSn : std_logic; - signal SCSI_D_EN : std_logic; - signal SCSI_DACKn : std_logic; - signal SCSI_DBP_EN : std_logic; - signal SCSI_DBP_OUTn : std_logic; - signal SCSI_DRQ : std_logic; - signal SCSI_INT : std_logic; - signal SCSI_D_OUTn : std_logic_vector(7 downto 0); - signal SCSI_RST_EN : std_logic; - signal SCSI_RST_OUTn : std_logic; - signal SCSI_SEL_EN : std_logic; - signal SCSI_SEL_OUTn : std_logic; - signal SD_CD_D3_EN : std_logic; - signal SD_CD_D3_OUT : std_logic; - signal SD_CMD_D1_EN : std_logic; - signal SD_CMD_D1_OUT : std_logic; - signal SNDCS : std_logic; - signal SNDCS_I : std_logic; - signal SNDIR_I : std_logic; - signal SR_DDR_FB : std_logic; - signal SR_DDR_WR : std_logic; - signal SR_DDRWR_D_SEL : std_logic; - signal SR_FIFO_WRE : std_logic; - signal SR_VDMP : std_logic_vector(7 downto 0); - signal TDO : std_logic; - signal TIMEBASE : unsigned (17 downto 0); - signal VD_EN : std_logic; - signal VD_EN_I : std_logic; - signal VD_OUT : std_logic_vector(31 downto 0); - signal VD_QS_EN : std_logic; - signal VD_QS_OUT : std_logic_vector(3 downto 0); - signal VD_VZ : std_logic_vector(127 downto 0); - signal VDM_SEL : std_logic_vector(3 downto 0); - signal VDP_IN : std_logic_vector(63 downto 0); - signal VDP_OUT : std_logic_vector(63 downto 0); - signal VDP_Q1 : std_logic_vector(31 downto 0); - signal VDP_Q2 : std_logic_vector(31 downto 0); - signal VDP_Q3 : std_logic_vector(31 downto 0); - signal VDR : std_logic_vector(31 downto 0); - signal VIDEO_DDR_TA : std_logic; - signal VIDEO_MOD_TA : std_logic; - signal VIDEO_RAM_CTR : std_logic_vector(15 downto 0); - signal VIDEO_RECONFIG : std_logic; - signal VR_BUSY : std_logic; - signal VR_D : std_logic_vector(8 downto 0); - signal VR_RD : std_logic; - signal VR_WR : std_logic; - signal VSYNC_I : std_logic; - signal WDC_BSL0 : std_logic; - -begin - I_PLL1: altpll1 - port map( - inclk0 => CLK_MAIN, - c0 => CLK_2M4576, -- 2.4576 MHz - c1 => CLK_24M576, -- 24.576 MHz - c2 => CLK_48M, -- 48 MHz - locked => LOCKED - ); - - I_PLL2: altpll2 - port map( - inclk0 => CLK_MAIN, - c0 => CLK_DDR(0), -- 132 MHz / 240° - c1 => CLK_DDR(1), -- 132 MHz / 0° - c2 => CLK_DDR(2), -- 132 MHz / 180° - c3 => CLK_DDR(3), -- 132 MHz / 105° - c4 => DDR_SYNC_66M -- 66 MHz / 270° - ); - - I_PLL3: altpll3 - port map( - inclk0 => CLK_MAIN, - c0 => CLK_2M0, -- 2 MHz - c1 => CLK_FDC, -- 16 MHz - c2 => CLK_25M_I, -- 25 MHz - c3 => CLK_500K -- 500 KHz - ); - - I_PLL4: altpll4 - port map( - inclk0 => CLK_MAIN, - areset => PLL_ARESET, - scanclk => PLL_SCANCLK, - scandata => PLL_SCANDATA, - scanclkena => PLL_SCANCLKENA, - configupdate => PLL_CONFIGUPDATE, - c0 => CLK_VIDEO, -- configurable video clk, set to 96 MHz initially - scandataout => PLL_SCANDATAOUT, - scandone => PLL_SCANDONE - --locked => -- Not used. - ); - - I_RECONFIG: altpll_reconfig1 -- to enable reconfiguration of altpll4 (video clock) - port map( - reconfig => VIDEO_RECONFIG, - read_param => VR_RD, - write_param => VR_WR, - data_in => FB_AD(24 downto 16), -- FIXED: this looks like a typo. Must be FB_AD(24 downto 16) instead of FB_ADR(24 downto 16) - counter_type => FB_ADR(5 downto 2), - counter_param => FB_ADR(8 downto 6), - pll_scandataout => PLL_SCANDATAOUT, - pll_scandone => PLL_SCANDONE, - clock => CLK_MAIN, - reset => not RESETn, - pll_areset_in => '0', -- Not used. - busy => VR_BUSY, - data_out => VR_D, - pll_scandata => PLL_SCANDATA, - pll_scanclk => PLL_SCANCLK, - pll_scanclkena => PLL_SCANCLKENA, - pll_configupdate => PLL_CONFIGUPDATE, - pll_areset => PLL_ARESET - ); - - CLK_25M <= CLK_25M_I; - CLK_USB <= CLK_48M; - CLK_DDR_OUT <= CLK_DDR(0); - CLK_DDR_OUTn <= not CLK_DDR(0); - CLK_PIXEL <= CLK_PIXEL_I; - - P_TIMEBASE: process - begin - wait until rising_edge(CLK_500K); - TIMEBASE <= TIMEBASE + 1; - end process P_TIMEBASE; - - RESETn <= RSTO_MCFn and LOCKED; - IDE_RES <= not IDE_RES_I and RESETn; - DREQ1n <= DACK1n; - LED_FPGA_OK <= TIMEBASE(17); - - FALCON_IO_TA <= ACIA_CS or SNDCS or not DTACK_OUT_MFPn or PADDLE_CS or IDE_CF_TA or DMA_CS; - FB_TAn <= '0' when (BLITTER_TA or VIDEO_DDR_TA or VIDEO_MOD_TA or FALCON_IO_TA or DSP_TA or INT_HANDLER_TA)= '1' else 'Z'; - - ACIA_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 3) & "000" = x"FFFC00" else '0'; -- FFFC00 - FFFC07 - MFP_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 6) & "000000" = x"FFFA00" else '0'; -- FFFA00/40 - PADDLE_CS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 6) & "000000"= x"FF9200" else '0'; -- FF9200-FF923F - SNDCS <= '1' when FB_CSn(1) = '0' and FB_ADR(23 downto 2) & "00" = x"FF8800" else '0'; -- FF8800-FF8803 - SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1) = '0' else '0'; - SNDIR_I <= '1' when SNDCS = '1' and FB_WRn = '0' else '0'; - - LP_D <= LP_D_X when LP_DIR_X = '0' else (others => 'Z'); - LP_DIR <= LP_DIR_X; - - ACSI_D <= ACSI_D_OUT when ACSI_D_EN = '1' else (others => 'Z'); - - SCSI_D <= SCSI_D_OUTn when SCSI_D_EN = '1' else (others => 'Z'); - SCSI_DIR <= '0' when SCSI_D_EN = '1' else '1'; - SCSI_PAR <= SCSI_DBP_OUTn when SCSI_DBP_EN = '1' else 'Z'; - SCSI_RSTn <= SCSI_RST_OUTn when SCSI_RST_EN = '1' else 'Z'; - SCSI_BUSYn <= SCSI_BSY_OUTn when SCSI_BSY_EN = '1' else 'Z'; - SCSI_SELn <= SCSI_SEL_OUTn when SCSI_SEL_EN = '1' else 'Z'; - - KEYB_RxD <= '0' when AMKB_RX = '0' or PIC_AMKB_RX = '0' else '1'; -- get keyboard data either from PIC (PS/2) or from Atari keyboard - - SD_D3 <= SD_CD_D3_OUT when SD_CD_D3_EN = '1' else 'Z'; - SD_CMD_D1 <= SD_CMD_D1_OUT when SD_CMD_D1_EN = '1' else 'Z'; - - DSP_IO <= DSP_IO_OUT when DSP_IO_EN = '1' else (others => 'Z'); - DSP_SRD <= DSP_SRD_OUT when DSP_SRD_EN = '1' else (others => 'Z'); - - HD_DD_OUT <= FDD_HD_DD when FBEE_CONF(29) = '0' else WDC_BSL0; - LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; - ACIA_IRQn <= IRQ_KEYBDn and IRQ_MIDIn; - MFP_INTACK <= '1' when FB_CSn(2) = '0' and FB_ADR(19 downto 0) = x"20000" else '0'; --F002'0000 - DINTn <= '0' when IDE_INT = '1' and FBEE_CONF(28) = '1' else - '0' when FD_INT = '1' else - '0' when SCSI_INT = '1' and FBEE_CONF(28) = '1' else '1'; - - MIDI_TLR <= MIDI_OUT; - MIDI_OLR <= MIDI_OUT; - - BYTE <= '1' when FB_SIZE(1) = '0' and FB_SIZE(0) = '1' else '0'; - FB_B0 <= '1' when FB_ADR(0) = '0' or BYTE = '0' else '0'; - FB_B1 <= '1' when FB_ADR(0) = '1' or BYTE = '0' else '0'; - - FB_AD(31 downto 24) <= DATA_OUT_BLITTER(31 downto 24) when DATA_EN_BLITTER = '1' else - VDP_Q1(31 downto 24) when FB_VDOE = x"2" else - VDP_Q2(31 downto 24) when FB_VDOE = x"4" else - VDP_Q3(31 downto 24) when FB_VDOE = x"8" else - FB_AD_OUT_VIDEO(31 downto 24) when FB_AD_EN_31_16_VIDEO = '1' else - FB_AD_OUT_DSP(31 downto 24) when FB_AD_EN_DSP = '1' else - FB_AD_OUT_IH(31 downto 24) when FB_AD_EN_31_24_IH = '1' else - FB_AD_OUT_DMA(31 downto 24) when FB_AD_EN_31_24_DMA = '1' else - VDR(31 downto 24) when FB_VDOE = x"1" else - DATA_OUT_DDR_CTRL(31 downto 24) when DATA_EN_H_DDR_CTRL = '1' else - DA_OUT_X when SNDCS_I = '1' and FB_OEn = '0' else - x"00" when MFP_INTACK = '1' and FB_OEn = '0' else - DATA_OUT_ACIA_I when ACIA_CS = '1' and FB_ADR(2) = '0' and FB_OEn = '0' else - DATA_OUT_ACIA_II when ACIA_CS = '1' and FB_ADR(2) = '1' and FB_OEn = '0' else - x"BF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"A" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"B" and FB_OEn = '0' else - x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_OEn = '0' else - x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"11" and FB_OEn = '0' else (others => 'Z'); - - FB_AD(23 downto 16) <= DATA_OUT_BLITTER(23 downto 16) when DATA_EN_BLITTER = '1' else - VDP_Q1(23 downto 16) when FB_VDOE = x"2" else - VDP_Q2(23 downto 16) when FB_VDOE = x"4" else - VDP_Q3(23 downto 16) when FB_VDOE = x"8" else - FB_AD_OUT_VIDEO(23 downto 16) when FB_AD_EN_31_16_VIDEO = '1' else - FB_AD_OUT_DSP(23 downto 16) when FB_AD_EN_DSP = '1' else - FB_AD_OUT_IH(23 downto 16) when FB_AD_EN_23_16_IH = '1' else - FB_AD_OUT_DMA(23 downto 16) when FB_AD_EN_23_16_DMA = '1' else - VDR(23 downto 16) when FB_VDOE = x"1" else - DATA_OUT_DDR_CTRL(23 downto 16) when DATA_EN_L_DDR_CTRL = '1' else - DATA_OUT_MFP when MFP_CS = '1' and FB_OEn = '0' else - x"00" when MFP_INTACK = '1' and FB_OEn = '0' else - FB_AD_OUT_RTC when FB_AD_EN_RTC = '1' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"0" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"1" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"8" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"9" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"A" and FB_OEn = '0' else - x"FF" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"B" and FB_OEn = '0' else - x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"10" and FB_OEn = '0' else - x"00" when PADDLE_CS = '1' and FB_ADR(5 downto 1) = 5x"11" and FB_OEn = '0' else (others => 'Z'); - - FB_AD(15 downto 8) <= DATA_OUT_BLITTER(15 downto 8) when DATA_EN_BLITTER = '1' else - VDP_Q1(15 downto 8) when FB_VDOE = x"2" else - VDP_Q2(15 downto 8) when FB_VDOE = x"4" else - VDP_Q3(15 downto 8) when FB_VDOE = x"8" else - FB_AD_OUT_VIDEO(15 downto 8) when FB_AD_EN_15_0_VIDEO = '1' else - FB_AD_OUT_DSP(15 downto 8) when FB_AD_EN_DSP = '1' else - FB_AD_OUT_IH(15 downto 8) when FB_AD_EN_15_8_IH = '1' else - FB_AD_OUT_DMA(15 downto 8) when FB_AD_EN_15_8_DMA = '1' else - VDR(15 downto 8) when FB_VDOE = x"1" else - "000000" & DATA_OUT_MFP(7 downto 6) when MFP_INTACK = '1' and FB_OEn = '0' else (others => 'Z'); - - FB_AD(7 downto 0) <= DATA_OUT_BLITTER(7 downto 0) when DATA_EN_BLITTER = '1' else - VDP_Q1(7 downto 0) when FB_VDOE = x"2" else - VDP_Q2(7 downto 0) when FB_VDOE = x"4" else - VDP_Q3(7 downto 0) when FB_VDOE = x"8" else - FB_AD_OUT_VIDEO(7 downto 0) when FB_AD_EN_15_0_VIDEO = '1' else - FB_AD_OUT_DSP(7 downto 0) when FB_AD_EN_DSP = '1' else - FB_AD_OUT_IH(7 downto 0) when FB_AD_EN_7_0_IH = '1' else - FB_AD_OUT_DMA(7 downto 0) when FB_AD_EN_7_0_DMA = '1' else - VDR(7 downto 0) when FB_VDOE = x"1" else - DATA_OUT_MFP(5 downto 0) & "00" when MFP_INTACK = '1' and FB_OEn = '0' else (others => 'Z'); - - SYNCHRONIZATION: process - begin - wait until rising_edge(DDR_SYNC_66M); - if FB_ALE = '1' then - FB_ADR <= FB_AD; -- latch Flexbus address - end if; - -- - if VD_EN_I = '0' then - VDR <= VD; - else - VDR <= VD_OUT; - end if; - -- - if FB_LE(0) = '1' then - FB_DDR(127 downto 96) <= FB_AD; - end if; - -- - if FB_LE(1) = '1' then - FB_DDR(95 downto 64) <= FB_AD; - end if; - -- - if FB_LE(2) = '1' then - FB_DDR(63 downto 32) <= FB_AD; - end if; - -- - if FB_LE(3) = '1' then - FB_DDR(31 downto 0) <= FB_AD; - end if; - end process SYNCHRONIZATION; - - VIDEO_OUT: process - begin - wait until rising_edge(CLK_PIXEL_I); - VSYNC <= VSYNC_I; - HSYNC <= HSYNC_I; - BLANKn <= BLANK_In; - end process VIDEO_OUT; - - P_DDR_WR: process - begin - wait until rising_edge(CLK_DDR(3)); - DDR_WR <= SR_DDR_WR; - DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL; - end process P_DDR_WR; - - VD_QS_EN <= DDR_WR; - VD <= VD_OUT when VD_EN = '1' else (others => 'Z'); - - VD_QS_OUT(0) <= CLK_DDR(0); - VD_QS_OUT(1) <= CLK_DDR(0); - VD_QS_OUT(2) <= CLK_DDR(0); - VD_QS_OUT(3) <= CLK_DDR(0); - VD_QS <= VD_QS_OUT when VD_QS_EN = '1' else (others => 'Z'); - - DDR_DATA_IN_N: process - begin - wait until rising_edge(CLK_DDR(1)); - DDR_D_IN_N <= VD; - end process DDR_DATA_IN_N; - -- - DDR_DATA_IN_P: process - begin - wait until rising_edge(CLK_DDR(1)); - VDP_IN(31 downto 0) <= VD; - VDP_IN(63 downto 32) <= DDR_D_IN_N; - end process DDR_DATA_IN_P; - - DDR_DATA_OUT_P: process(CLK_DDR(3)) - variable DDR_D_OUT_H : std_logic_vector(31 downto 0); - variable DDR_D_OUT_L : std_logic_vector(31 downto 0); - begin - if CLK_DDR(3) = '1' and CLK_DDR(3)' event then - DDR_D_OUT_H := VDP_OUT(63 downto 32); - DDR_D_OUT_L := VDP_OUT(31 downto 0); - VD_EN <= SR_DDR_WR or DDR_WR; - end if; - -- - case CLK_DDR(3) is - when '1' => VD_OUT <= DDR_D_OUT_H; - when others => VD_OUT <= DDR_D_OUT_L; - end case; - end process DDR_DATA_OUT_P; - - with DDRWR_D_SEL select - VDP_OUT <= BLITTER_DOUT(63 downto 0) when "11", - BLITTER_DOUT(127 downto 64) when "10", - FB_DDR(63 downto 0) when "01", - FB_DDR(127 downto 64) when "00", - (others => 'Z') when others; - - VD_EN_I <= SR_DDR_WR or DDR_WR; - - VDP_Q_BUFFER: process - begin - wait until rising_edge(CLK_DDR(0)); - DDR_FB <= SR_DDR_FB & DDR_FB(4 downto 1); - -- - if DDR_FB(1) = '1' then - VDP_Q1 <= VDP_IN(31 downto 0); - end if; - -- - if DDR_FB(0) = '1' then - VDP_Q2 <= VDP_IN(63 downto 32); - VDP_Q3 <= VDP_IN(31 downto 0); - end if; - end process VDP_Q_BUFFER; - - I_DDR_CTRL: DDR_CTRL_V1 - port map( - CLK_MAIN => CLK_MAIN, - DDR_SYNC_66M => DDR_SYNC_66M, - FB_ADR => FB_ADR, - FB_CS1n => FB_CSn(1), - FB_OEn => FB_OEn, - FB_SIZE0 => FB_SIZE(0), - FB_SIZE1 => FB_SIZE(1), - FB_ALE => FB_ALE, - FB_WRn => FB_WRn, - BLITTER_ADR => BLITTER_ADR, - BLITTER_SIG => BLITTER_SIG, - BLITTER_WR => BLITTER_WR, - SR_BLITTER_DACK => BLITTER_DACK_SR, - BA => BA, - VA => VA, - FB_LE => FB_LE, - CLK_33M => CLK_33M, - VRASn => VRASn, - VCASn => VCASn, - VWEn => VWEn, - VCSn => VCSn, - FIFO_CLR => FIFO_CLR, - DDRCLK0 => CLK_DDR(0), - VIDEO_RAM_CTR => VIDEO_RAM_CTR, - VCKE => VCKE, - DATA_IN => FB_AD, - DATA_OUT => DATA_OUT_DDR_CTRL, - DATA_EN_H => DATA_EN_H_DDR_CTRL, - DATA_EN_L => DATA_EN_L_DDR_CTRL, - VDM_SEL => VDM_SEL, - FIFO_MW => FIFO_MW, - FB_VDOE => FB_VDOE, - SR_FIFO_WRE => SR_FIFO_WRE, - SR_DDR_FB => SR_DDR_FB, - SR_DDR_WR => SR_DDR_WR, - SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, - SR_VDMP => SR_VDMP, - VIDEO_DDR_TA => VIDEO_DDR_TA, - DDRWR_D_SEL1 => DDRWR_D_SEL(1) - ); - - I_BLITTER: FBEE_BLITTER - port map( - RESETn => RESETn, - CLK_MAIN => CLK_MAIN, - CLK_DDR0 => CLK_DDR(0), - FB_ADR => FB_ADR, - FB_ALE => FB_ALE, - FB_SIZE1 => FB_SIZE(1), - FB_SIZE0 => FB_SIZE(0), - FB_CSn => FB_CSn, - FB_OEn => FB_OEn, - FB_WRn => FB_WRn, - DATA_IN => FB_AD, - DATA_OUT => DATA_OUT_BLITTER, - DATA_EN => DATA_EN_BLITTER, - BLITTER_ADR => BLITTER_ADR, - BLITTER_SIG => BLITTER_SIG, - BLITTER_WR => BLITTER_WR, - BLITTER_ON => BLITTER_ON, - BLITTER_RUN => BLITTER_RUN, - BLITTER_DIN => VD_VZ, - BLITTER_DOUT => BLITTER_DOUT, - BLITTER_TA => BLITTER_TA, - BLITTER_DACK_SR => BLITTER_DACK_SR - ); - - I_VIDEOSYSTEM: VIDEO_SYSTEM - port map( - CLK_MAIN => CLK_MAIN, - CLK_33M => CLK_33M, - CLK_25M => CLK_25M_I, - CLK_VIDEO => CLK_VIDEO, - CLK_DDR3 => CLK_DDR(3), - CLK_DDR2 => CLK_DDR(2), - CLK_DDR0 => CLK_DDR(0), - CLK_PIXEL => CLK_PIXEL_I, - - VR_D => VR_D, - VR_BUSY => VR_BUSY, - - FB_ADR => FB_ADR, - FB_AD_IN => FB_AD, - FB_AD_OUT => FB_AD_OUT_VIDEO, - FB_AD_EN_31_16 => FB_AD_EN_31_16_VIDEO, - FB_AD_EN_15_0 => FB_AD_EN_15_0_VIDEO, - FB_ALE => FB_ALE, - FB_CSn => FB_CSn, - FB_OEn => FB_OEn, - FB_WRn => FB_WRn, - FB_SIZE1 => FB_SIZE(1), - FB_SIZE0 => FB_SIZE(0), - - VDP_IN => VDP_IN, - - VR_RD => VR_RD, - VR_WR => VR_WR, - VIDEO_RECONFIG => VIDEO_RECONFIG, - - RED => VR, - GREEN => VG, - BLUE => VB, - VSYNC => VSYNC_I, - HSYNC => HSYNC_I, - SYNCn => SYNCn, - BLANKn => BLANK_In, - - PD_VGAn => PD_VGAn, - VIDEO_MOD_TA => VIDEO_MOD_TA, - - VD_VZ => VD_VZ, - SR_FIFO_WRE => SR_FIFO_WRE, - SR_VDMP => SR_VDMP, - FIFO_MW => FIFO_MW, - VDM_SEL => VDM_SEL, - VIDEO_RAM_CTR => VIDEO_RAM_CTR, - FIFO_CLR => FIFO_CLR, - VDM => VDM, - BLITTER_ON => BLITTER_ON, - BLITTER_RUN => BLITTER_RUN - ); - - I_INTHANDLER: INTHANDLER - port map( - CLK_MAIN => CLK_MAIN, - RESETn => RESETn, - FB_ADR => FB_ADR, - FB_CSn => FB_CSn(2 downto 1), - FB_OEn => FB_OEn, - FB_SIZE0 => FB_SIZE(0), - FB_SIZE1 => FB_SIZE(1), - FB_WRn => FB_WRn, - FB_AD_IN => FB_AD, - FB_AD_OUT => FB_AD_OUT_IH, - FB_AD_EN_31_24 => FB_AD_EN_31_24_IH, - FB_AD_EN_23_16 => FB_AD_EN_23_16_IH, - FB_AD_EN_15_8 => FB_AD_EN_15_8_IH, - FB_AD_EN_7_0 => FB_AD_EN_7_0_IH, - PIC_INT => PIC_INT, - E0_INT => E0_INT, - DVI_INT => DVI_INT, - PCI_INTAn => PCI_INTAn, - PCI_INTBn => PCI_INTBn, - PCI_INTCn => PCI_INTCn, - PCI_INTDn => PCI_INTDn, - MFP_INTn => MFP_INTn, - DSP_INT => DSP_INT, - VSYNC => VSYNC_I, - HSYNC => HSYNC_I, - DRQ_DMA => DRQ_DMA, - IRQn => IRQn, - INT_HANDLER_TA => INT_HANDLER_TA, - FBEE_CONF => FBEE_CONF, - TIN0 => TIN0 - ); - - I_DMA: FBEE_DMA - port map( - RESET => not RESETn, - CLK_MAIN => CLK_MAIN, - CLK_FDC => CLK_FDC, - - FB_ADR => FB_ADR(26 downto 0), - FB_ALE => FB_ALE, - FB_SIZE => FB_SIZE, - FB_CSn => FB_CSn(2 downto 1), - FB_OEn => FB_OEn, - FB_WRn => FB_WRn, - FB_AD_IN => FB_AD, - FB_AD_OUT => FB_AD_OUT_DMA, - FB_AD_EN_31_24 => FB_AD_EN_31_24_DMA, - FB_AD_EN_23_16 => FB_AD_EN_23_16_DMA, - FB_AD_EN_15_8 => FB_AD_EN_15_8_DMA, - FB_AD_EN_7_0 => FB_AD_EN_7_0_DMA, - - ACSI_DIR => ACSI_DIR, - ACSI_D_IN => ACSI_D, - ACSI_D_OUT => ACSI_D_OUT, - ACSI_D_EN => ACSI_D_EN, - ACSI_CSn => ACSI_CSn, - ACSI_A1 => ACSI_A1, - ACSI_RESETn => ACSI_RESETn, - ACSI_DRQn => ACSI_DRQn, - ACSI_ACKn => ACSI_ACKn, - - DATA_IN_FDC => DATA_OUT_FDC, - DATA_IN_SCSI => DATA_OUT_SCSI, - DATA_OUT_FDC_SCSI => DATA_IN_FDC_SCSI, - - DMA_DRQ_IN => DRQ_FDC, - DMA_DRQ_OUT => DRQ_DMA, - DMA_DRQ11 => DRQ11_DMA, - - SCSI_DRQ => SCSI_DRQ, - SCSI_DACKn => SCSI_DACKn, - SCSI_INT => SCSI_INT, - SCSI_CSn => SCSI_CSn, - SCSI_CS => SCSI_CS, - - CA => CA, - FLOPPY_HD_DD => FDD_HD_DD, - WDC_BSL0 => WDC_BSL0, - FDC_CSn => FDC_CSn, - FDC_WRn => FDC_WRn, - FD_INT => FD_INT, - IDE_INT => IDE_INT, - DMA_CS => DMA_CS - ); - - I_IDE_CF_SD_ROM: IDE_CF_SD_ROM - port map( - RESET => not RESETn, - CLK_MAIN => CLK_MAIN, - - FB_ADR => FB_ADR(19 downto 5), - FB_CS1n => FB_CSn(1), - FB_WRn => FB_WRn, - FB_B0 => FB_B0, - FB_B1 => FB_B1, - - FBEE_CONF => FBEE_CONF(31 downto 30), - - RP_UDSn => RP_UDSn, - RP_LDSn => RP_LDSn, - - SD_CLK => SD_CLK, - SD_D0 => SD_D0, - SD_D1 => SD_D1, - SD_D2 => SD_D2, - SD_CD_D3_IN => SD_D3, - SD_CD_D3_OUT => SD_CD_D3_OUT, - SD_CD_D3_EN => SD_CD_D3_EN, - SD_CMD_D1_IN => SD_CMD_D1, - SD_CMD_D1_OUT => SD_CMD_D1_OUT, - SD_CMD_D1_EN => SD_CMD_D1_EN, - SD_CARD_DETECT => SD_CARD_DETECT, - SD_WP => SD_WP, - - IDE_RDY => IDE_RDY, - IDE_WRn => IDE_WRn, - IDE_RDn => IDE_RDn, - IDE_CSn => IDE_CSn, - -- IDE_DRQn =>, -- Not used. - IDE_CF_TA => IDE_CF_TA, - - ROM4n => ROM4n, - ROM3n => ROM3n, - - CF_WP => CF_WP, - CF_CSn => CF_CSn - ); - - I_DSP: DSP - port map( - CLK_33M => CLK_33M, - CLK_MAIN => CLK_MAIN, - FB_OEn => FB_OEn, - FB_WRn => FB_WRn, - FB_CS1n => FB_CSn(1), - FB_CS2n => FB_CSn(2), - FB_SIZE0 => FB_SIZE(0), - FB_SIZE1 => FB_SIZE(1), - FB_BURSTn => FB_BURSTn, - FB_ADR => FB_ADR, - RESETn => RESETn, - FB_CS3n => FB_CSn(3), - SRCSn => DSP_SRCSn, - SRBLEn => DSP_SRBLEn, - SRBHEn => DSP_SRBHEn, - SRWEn => DSP_SRWEn, - SROEn => DSP_SROEn, - DSP_INT => DSP_INT, - DSP_TA => DSP_TA, - FB_AD_IN => FB_AD, - FB_AD_OUT => FB_AD_OUT_DSP, - FB_AD_EN => FB_AD_EN_DSP, - IO_IN => DSP_IO, - IO_OUT => DSP_IO_OUT, - IO_EN => DSP_IO_EN, - SRD_IN => DSP_SRD, - SRD_OUT => DSP_SRD_OUT, - SRD_EN => DSP_SRD_EN - ); - - I_SOUND: WF2149IP_TOP_SOC - port map( - SYS_CLK => CLK_MAIN, - RESETn => RESETn, - - WAV_CLK => CLK_2M0, - SELn => '1', - - BDIR => SNDIR_I, - BC2 => '1', - BC1 => SNDCS_I, - - A9n => '0', - A8 => '1', - DA_IN => FB_AD(31 downto 24), - DA_OUT => DA_OUT_X, - - IO_A_IN => x"00", -- All port pins are dedicated outputs. - IO_A_OUT(7) => IDE_RES_I, - IO_A_OUT(6) => LP_DIR_X, - IO_A_OUT(5) => LP_STR, - IO_A_OUT(4) => DTR, - IO_A_OUT(3) => RTS, - IO_A_OUT(2) => RESERVED_1, - IO_A_OUT(1) => DSA_D, - IO_A_OUT(0) => FDD_SDSELn, - -- IO_A_EN => TOUT0n, -- Not required. - IO_B_IN => LP_D, - IO_B_OUT => LP_D_X, - -- IO_B_EN => -- Not used. - - OUT_A => YM_QA, - OUT_B => YM_QB, - OUT_C => YM_QC - ); - - I_MFP: WF68901IP_TOP_SOC - port map( - -- System control: - CLK => CLK_MAIN, - RESETn => RESETn, - -- Asynchronous bus control: - DSn => not LDS, - CSn => not MFP_CS, - RWn => FB_WRn, - DTACKn => DTACK_OUT_MFPn, - -- Data and Adresses: - RS => FB_ADR(5 downto 1), - DATA_IN => FB_AD(23 downto 16), - DATA_OUT => DATA_OUT_MFP, - -- DATA_EN => DATA_EN_MFP, -- Not used. - GPIP_IN(7) => not DRQ11_DMA, - GPIP_IN(6) => not RI, - GPIP_IN(5) => DINTn, - GPIP_IN(4) => ACIA_IRQn, - GPIP_IN(3) => DSP_INT, - GPIP_IN(2) => not CTS, - GPIP_IN(1) => not DCD, - GPIP_IN(0) => LP_BUSY, - -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. - -- GPIP_EN =>, -- Not used; all GPIPs are direction input. - -- Interrupt control: - IACKn => not MFP_INTACK, - IEIn => '0', - -- IEOn =>, -- Not used. - IRQn => MFP_INTn, - -- Timers and timer control: - XTAL1 => CLK_2M4576, - TAI => '0', - TBI => BLANK_In, - -- TAO =>, - -- TBO =>, - -- TCO =>, - TDO => TDO, - -- Serial I/O control: - RC => TDO, - TC => TDO, - SI => RxD, - SO => TxD - -- SO_EN => -- Not used. - -- DMA control: - -- RRn => -- Not used. - -- TRn => -- Not used. - ); - - I_ACIA_MIDI: WF6850IP_TOP_SOC - port map( - CLK => CLK_MAIN, - RESETn => RESETn, - - CS2n => '0', - CS1 => FB_ADR(2), - CS0 => ACIA_CS, - E => ACIA_CS, - RWn => FB_WRN, - RS => FB_ADR(1), - - DATA_IN => FB_AD(31 downto 24), - DATA_OUT => DATA_OUT_ACIA_II, - -- DATA_EN => -- Not used. - - TXCLK => CLK_500K, - RXCLK => CLK_500K, - RXDATA => MIDI_IN, - CTSn => '0', - DCDn => '0', - - IRQn => IRQ_MIDIn, - TXDATA => MIDI_OUT - --RTSn => -- Not used. - ); - - I_ACIA_KEYBOARD: WF6850IP_TOP_SOC - port map( - CLK => CLK_MAIN, - RESETn => RESETn, - - CS2n => FB_ADR(2), - CS1 => '1', - CS0 => ACIA_CS, - E => ACIA_CS, - RWn => FB_WRn, - RS => FB_ADR(1), - - DATA_IN => FB_AD(31 downto 24), - DATA_OUT => DATA_OUT_ACIA_I, - -- DATA_EN => Not used. - - TXCLK => CLK_500K, - RXCLK => CLK_500K, - RXDATA => KEYB_RxD, - - CTSn => '0', - DCDn => '0', - - IRQn => IRQ_KEYBDn, - TXDATA => AMKB_TX - --RTSn => -- Not used. - ); - - I_SCSI: WF5380_TOP_SOC - port map( - CLK => CLK_FDC, - RESETn => RESETn, - ADR => CA, - DATA_IN => DATA_IN_FDC_SCSI, - DATA_OUT => DATA_OUT_SCSI, - --DATA_EN =>, - -- Bus and DMA controls: - CSn => SCSI_CSn, - RDn => not FDC_WRn or not SCSI_CS, - WRn => FDC_WRn or not SCSI_CS, - EOPn => '1', - DACKn => SCSI_DACKn, - DRQ => SCSI_DRQ, - INT => SCSI_INT, - -- READY =>, - -- SCSI bus: - DB_INn => SCSI_D, - DB_OUTn => SCSI_D_OUTn, - DB_EN => SCSI_D_EN, - DBP_INn => SCSI_PAR, - DBP_OUTn => SCSI_DBP_OUTn, - DBP_EN => SCSI_DBP_EN, -- wenn 1 dann output - RST_INn => SCSI_RSTn, - RST_OUTn => SCSI_RST_OUTn, - RST_EN => SCSI_RST_EN, - BSY_INn => SCSI_BUSYn, - BSY_OUTn => SCSI_BSY_OUTn, - BSY_EN => SCSI_BSY_EN, - SEL_INn => SCSI_SELn, - SEL_OUTn => SCSI_SEL_OUTn, - SEL_EN => SCSI_SEL_EN, - ACK_INn => '1', - ACK_OUTn => SCSI_ACKn, - -- ACK_EN => ACK_EN, - ATN_INn => '1', - ATN_OUTn => SCSI_ATNn, - -- ATN_EN => ATN_EN, - REQ_INn => SCSI_DRQn, - -- REQ_OUTn => REQ_OUTn, - -- REQ_EN => REQ_EN, - IOn_IN => SCSI_IOn, - -- IOn_OUT => IOn_OUT, - -- IO_EN => IO_EN, - CDn_IN => SCSI_CDn, - -- CDn_OUT => CDn_OUT, - -- CD_EN => CD_EN, - MSG_INn => SCSI_MSGn - -- MSG_OUTn => MSG_OUTn, - -- MSG_EN => MSG_EN - ); - - I_FDC: WF1772IP_TOP_SOC - port map( - CLK => CLK_FDC, - RESETn => RESETn, - CSn => FDC_CSn, - RWn => FDC_WRn, - A1 => CA(2), - A0 => CA(1), - DATA_IN => DATA_IN_FDC_SCSI, - DATA_OUT => DATA_OUT_FDC, - -- DATA_EN => CD_EN_FDC, - RDn => FDD_RDn, - TR00n => FDD_TRACK00, - IPn => FDD_INDEXn, - WPRTn => FDD_WPn, - DDEn => '0', -- Fixed to MFM. - HDTYPE => HD_DD_OUT, - MO => FDD_MOT_ON, - WG => FDD_WR_GATE, - WD => FDD_WDn, - STEP => FDD_STEP, - DIRC => FDD_STEP_DIR, - DRQ => DRQ_FDC, - INTRQ => FD_INT - ); - - I_RTC: RTC - port map( - CLK_MAIN => CLK_MAIN, - FB_ADR => FB_ADR(19 downto 0), - FB_CS1n => FB_CSn(1), - FB_SIZE0 => FB_SIZE(0), - FB_SIZE1 => FB_SIZE(1), - FB_WRn => FB_WRn, - FB_OEn => FB_OEn, - FB_AD_IN => FB_AD(23 downto 16), - FB_AD_OUT => FB_AD_OUT_RTC, - FB_AD_EN_23_16 => FB_AD_EN_RTC, - PIC_INT => PIC_INT - ); -end architecture; - -configuration NO_SCSI of firebee is - for Structure - for all: - WF5380_TOP_SOC use entity work.WF5380_TOP_SOC(LIGHT); - end for; - end for; -end configuration no_scsi; - -configuration FULL of firebee is - for Structure - -- default configuration - end for; -end configuration FULL; +---------------------------------------------------------------------- +---- ---- +---- This file is part of the 'Firebee' project. ---- +---- http://acp.atari.ORg ---- +---- ---- +---- Description: ---- +---- This design unit provides the toplevel of the 'Firebee' ---- +---- computer. It is optimized fOR the use of an Altera Cyclone ---- +---- FPGA (EP3C40F484). This IP-CORe is based on the first edi- ---- +---- tion of the Firebee configware ORigINally provided by Fredi ---- +---- Ashwanden and Wolfgang Förster. This release is IN compa- ---- +---- rision to the first edition completely written IN VHDL. ---- +---- ---- +---- AuthOR(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@INventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2012 Wolfgang Förster ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/OR modIFy it under the terms of the GNU General Public ---- +---- License as published by the Free Software Foundation; either ---- +---- version 2 of the License, OR (at your option) any later ---- +---- version. ---- +---- ---- +---- This program is distributed IN the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; WITHOUT even the implied ---- +---- warranty of MERCHANTABILITY OR FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License fOR mORe ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along WITH this program; IF NOT, write to the Free ---- +---- Software Foundation, Inc., 51 FranklIN Street, FIFth FloOR, ---- +---- Boston, MA 02110-1301, USA. ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision HistORy +-- +-- Revision 2K12B 20120801 WF +-- Initial Release of the second edition, the most imPORTant changes are listed below. +-- Structural wORk: +-- Replaced the graphical top level by a VHDL model. +-- The new toplevel is now FIREBEE_V1. +-- Replaced the graphical Video Top Level by a VHDL model +-- The DDR_CTR is now DDR_CTRL. +-- Rewritten the DDR_CTR IN VHDL. +-- Moved the DDR_CTRL to the FIREBEE_V1 top level. +-- Moved the BLITTER to the FIREBEE_V1 top level. +-- Removed the VIDEO_MOD_MUX_CLUTCTR. +-- Extracted from the AHDL code of MOD_MUX_CLUTCTR the new VIDEO_CTRL. +-- VIDEO_CTRL is now written IN VHDL. +-- Removed the FalconIO_SDCard_IDE_CF. +-- Moved the keyboard ACIA from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. +-- Moved the MIDI ACIA from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. +-- Moved the soundchip module from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. +-- Moved the multi function PORT (MFP) from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. +-- Moved the floppy disk controller (FDC) from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. +-- Moved the SCSI controller from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. +-- Extracted a DMA logic from FalconIO_SDCard_IDE_CF which is now located IN the FIREBEE_V1 top level. +-- Extracted a IDE_CF_SD_ROM logic from FalconIO_SDCard_IDE_CF which is now located IN the FIREBEE_V1 top level. +-- Moved the PADDLE logic from FalconIO_SDCard_IDE_CF to the FIREBEE_V1 top level. +-- Rewritten the INterrupt handler IN VHDL. +-- Extracted the real time clock (RTC) logic from the INterrupt handler (VHDL). +-- The RTC is now located IN the FIREBEE_V1 top level. +-- Several code cleanups: +-- Resolved the tri state logic IN all modules. The only tri states are now IN the +-- top level FIREBEE_V1. +-- Replaced several Altera lpm modules to achieve a manufacturer INdepENDant code. +-- However we have still some modules like memORy OR FIFOs which are required up to now. +-- Removed the vdr latch. +-- Removed the AMKBD filter. +-- Updated all Suska-Codes (ACIA, MFP, 5380, 1772, 2149) to the latest code base. +-- The sound module wORks now on the positive clock edge. +-- The multi function PORT wORks now on the positive clock edge. +-- NamINg conventions: +-- Replaced the 'n' prefixes WITH 'n' postfixes to achieve consistent SIGNAL names. +-- Replaced the old ACP_xx SIGNAL names by FBEE_xx (ACP is the old wORkINg title). +-- Improvements (hopefully) +-- Fixed the video_reconfig strobe logic IN the video control section. +-- Others: +-- Provided file headers to all Firebee relevant design units. +-- Provided a timequest constraINt file. +-- Switched all code elements to English language. +-- Provided a complete new file structure fOR the project. +-- + +LIBRARY wORk; + USE wORk.firebee_pkg.ALL; + +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + USE IEEE.numeric_std.ALL; + +ENTITY firebee IS + PORT( + RSTO_MCFn : IN STD_LOGIC; -- reset SIGNAL from Coldfire + CLK_33M : IN STD_LOGIC; -- 33 MHz clock + CLK_MAIN : IN STD_LOGIC; -- 33 MHz clock + + CLK_24M576 : OUT STD_LOGIC; -- + CLK_25M : OUT STD_LOGIC; + clk_ddr_OUT : OUT STD_LOGIC; + clk_ddr_OUTn : OUT STD_LOGIC; + CLK_USB : OUT STD_LOGIC; + + FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + FB_ALE : IN STD_LOGIC; + FB_BURSTn : IN STD_LOGIC; + FB_CSn : IN STD_LOGIC_VECTOR(3 DOWNTO 1); + FB_SIZE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + FB_OEn : IN STD_LOGIC; + FB_WRn : IN STD_LOGIC; + FB_TAn : OUT STD_LOGIC; + + DACK1n : IN STD_LOGIC; + DREQ1n : OUT STD_LOGIC; + + MASTERn : IN STD_LOGIC; -- determINes IF the Firebee is PCI master (='0') OR slave. Not used so far. + TOUT0n : IN STD_LOGIC; -- Not used so far. + + LED_FPGA_OK : OUT STD_LOGIC; + RESERVED_1 : OUT STD_LOGIC; + + VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + VWEn : OUT STD_LOGIC; + VcaSn : OUT STD_LOGIC; + VRASn : OUT STD_LOGIC; + VCSn : OUT STD_LOGIC; + + CLK_PIXEL : OUT STD_LOGIC; + SYNCn : OUT STD_LOGIC; + VSYNC : OUT STD_LOGIC; + HSYNC : OUT STD_LOGIC; + BLANKn : OUT STD_LOGIC; + + VR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + VG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + VB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + + VDM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + VD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + VD_QS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + PD_VGAn : OUT STD_LOGIC; + VCKE : OUT STD_LOGIC; + PIC_INT : IN STD_LOGIC; + E0_INT : IN STD_LOGIC; + DVI_INT : IN STD_LOGIC; + PCI_INTAn : IN STD_LOGIC; + PCI_INTBn : IN STD_LOGIC; + PCI_INTCn : IN STD_LOGIC; + PCI_INTDn : IN STD_LOGIC; + + IRQn : OUT STD_LOGIC_VECTOR(7 DOWNTO 2); + TIN0 : OUT STD_LOGIC; + + YM_QA : OUT STD_LOGIC; + YM_QB : OUT STD_LOGIC; + YM_QC : OUT STD_LOGIC; + + LP_D : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); + LP_DIR : OUT STD_LOGIC; + + DSA_D : OUT STD_LOGIC; + LP_STR : OUT STD_LOGIC; + DTR : OUT STD_LOGIC; + RTS : OUT STD_LOGIC; + CTS : IN STD_LOGIC; + RI : IN STD_LOGIC; + DCD : IN STD_LOGIC; + LP_BUSY : IN STD_LOGIC; + RxD : IN STD_LOGIC; + TxD : OUT STD_LOGIC; + MIDI_IN : IN STD_LOGIC; + MIDI_OLR : OUT STD_LOGIC; + MIDI_TLR : OUT STD_LOGIC; + PIC_AMKB_RX : IN STD_LOGIC; + AMKB_RX : IN STD_LOGIC; + AMKB_TX : OUT STD_LOGIC; + DACK0n : IN STD_LOGIC; -- Not used. + + scsi_drqn : IN STD_LOGIC; + SCSI_MSGn : IN STD_LOGIC; + SCSI_CDn : IN STD_LOGIC; + SCSI_IOn : IN STD_LOGIC; + SCSI_ACKn : OUT STD_LOGIC; + SCSI_ATNn : OUT STD_LOGIC; + SCSI_SELn : INOUT STD_LOGIC; + SCSI_BUSYn : INOUT STD_LOGIC; + SCSI_RSTn : INOUT STD_LOGIC; + SCSI_DIR : OUT STD_LOGIC; + SCSI_D : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); + SCSI_PAR : INOUT STD_LOGIC; + + ACSI_DIR : OUT STD_LOGIC; + ACSI_D : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ACSI_CSn : OUT STD_LOGIC; + ACSI_A1 : OUT STD_LOGIC; + ACSI_reset_n : OUT STD_LOGIC; + ACSI_ACKn : OUT STD_LOGIC; + ACSI_DRQn : IN STD_LOGIC; + ACSI_INTn : IN STD_LOGIC; + + FDD_DCHGn : IN STD_LOGIC; + FDD_SDSELn : OUT STD_LOGIC; + FDD_HD_DD : IN STD_LOGIC; + FDD_RDn : IN STD_LOGIC; + FDD_TRACK00 : IN STD_LOGIC; + FDD_INDEXn : IN STD_LOGIC; + FDD_WPn : IN STD_LOGIC; + FDD_MOT_ON : OUT STD_LOGIC; + FDD_WR_GATE : OUT STD_LOGIC; + FDD_WDn : OUT STD_LOGIC; + FDD_STEP : OUT STD_LOGIC; + FDD_STEP_DIR : OUT STD_LOGIC; + + ROM4n : OUT STD_LOGIC; + ROM3n : OUT STD_LOGIC; + + RP_UDSn : OUT STD_LOGIC; + RP_ldsn : OUT STD_LOGIC; + SD_CLK : OUT STD_LOGIC; + SD_D3 : INOUT STD_LOGIC; + SD_CMD_D1 : INOUT STD_LOGIC; + SD_D0 : IN STD_LOGIC; + SD_D1 : IN STD_LOGIC; + SD_D2 : IN STD_LOGIC; + SD_caRD_DETECT : IN STD_LOGIC; + SD_WP : IN STD_LOGIC; + + CF_WP : IN STD_LOGIC; + CF_CSn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + DSP_IO : INOUT STD_LOGIC_VECTOR(17 DOWNTO 0); + DSP_SRD : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); + DSP_SRCSn : OUT STD_LOGIC; + DSP_SRBLEn : OUT STD_LOGIC; + DSP_SRBHEn : OUT STD_LOGIC; + DSP_SRWEn : OUT STD_LOGIC; + DSP_SROEn : OUT STD_LOGIC; + + IDE_INT : IN STD_LOGIC; + IDE_RDY : IN STD_LOGIC; + IDE_RES : OUT STD_LOGIC; + IDE_WRn : OUT STD_LOGIC; + IDE_RDn : OUT STD_LOGIC; + IDE_CSn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); +END ENTITY firebee; + +ARCHITECTURE Structure of firebee is + COMPONENT altpll1 + PORT( + INclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT altpll2 + PORT( + INclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT altpll3 + PORT( + INclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT altpll4 + PORT( + areset : IN STD_LOGIC := '0'; + configupdate : IN STD_LOGIC := '0'; + INclk0 : IN STD_LOGIC := '0'; + scanclk : IN STD_LOGIC := '1'; + scanclkena : IN STD_LOGIC := '0'; + scandata : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC ; + scandataOUT : OUT STD_LOGIC ; + scandone : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT altpll_reconfig1 + PORT( + busy : OUT STD_LOGIC; + clock : IN STD_LOGIC; + counter_param : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0'); + counter_type : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); + data_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0) := (OTHERS => '0'); + data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + pll_areset : OUT STD_LOGIC; + pll_areset_in : IN STD_LOGIC := '0'; + pll_configupdate : OUT STD_LOGIC; + pll_scanclk : OUT STD_LOGIC; + pll_scanclkena : OUT STD_LOGIC; + pll_scandata : OUT STD_LOGIC; + pll_scandataout : IN STD_LOGIC := '0'; + pll_scandone : IN STD_LOGIC := '0'; + read_param : IN STD_LOGIC := '0'; + reconfig : IN STD_LOGIC := '0'; + reset : IN STD_LOGIC; + write_param : IN STD_LOGIC := '0' + ); + END COMPONENT; + + SIGNAL acia_cs : STD_LOGIC; + SIGNAL acia_irq_n : STD_LOGIC; + SIGNAL acsi_d_out : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL acsi_d_en : STD_LOGIC; + SIGNAL blank_i_n : STD_LOGIC; + SIGNAL blitter_adr : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL blitter_dack_sr : STD_LOGIC; + SIGNAL blitter_dout : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL blitter_on : STD_LOGIC; + SIGNAL blitter_run : STD_LOGIC; + SIGNAL blitter_sig : STD_LOGIC; + SIGNAL blitter_ta : STD_LOGIC; + SIGNAL blitter_wr : STD_LOGIC; + SIGNAL byte : STD_LOGIC; -- When Byte -> 1 + SIGNAL ca : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL clk_2m0 : STD_LOGIC; + SIGNAL clk_2m4576 : STD_LOGIC; + SIGNAL clk_25m_i : STD_LOGIC; + SIGNAL clk_48m : STD_LOGIC; + SIGNAL clk_500k : STD_LOGIC; + SIGNAL clk_ddr : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL clk_fdc : STD_LOGIC; + SIGNAL clk_pixel_i : STD_LOGIC; + SIGNAL clk_video : STD_LOGIC; + SIGNAL da_out_x : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL data_en_blitter : STD_LOGIC; + SIGNAL data_en_h_ddr_ctrl : STD_LOGIC; + SIGNAL data_en_l_ddr_ctrl : STD_LOGIC; + SIGNAL data_in_fdc_scsi : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL data_out_acia_i : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL data_out_acia_iI : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL data_out_blitter : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_ddr_ctrl : STD_LOGIC_VECTOR(31 DOWNTO 16); + SIGNAL data_out_fdc : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL data_out_mfp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL data_out_scsi : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL dint_n : STD_LOGIC; + SIGNAL ddr_d_in_n : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL ddr_fb : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL ddr_sync_66m : STD_LOGIC; + SIGNAL ddr_wr : STD_LOGIC; + SIGNAL ddrwr_d_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL dma_cs : STD_LOGIC; + SIGNAL drq11_dma : STD_LOGIC; + SIGNAL drq_fdc : STD_LOGIC; + SIGNAL drq_dma : STD_LOGIC; + SIGNAL dsp_int : STD_LOGIC; + SIGNAL dsp_io_en : STD_LOGIC; + SIGNAL dsp_io_out : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL dsp_srd_en : STD_LOGIC; + SIGNAL dsp_srd_out : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL dsp_ta : STD_LOGIC; + SIGNAL dtack_out_mfp_n : STD_LOGIC; + SIGNAL falcon_io_ta : STD_LOGIC; + + SIGNAL fb_ad_en_15_0_video : STD_LOGIC; + SIGNAL fb_ad_en_31_16_video : STD_LOGIC; + SIGNAL fb_ad_en_7_0_dma : STD_LOGIC; + SIGNAL fb_ad_en_7_0_ih : STD_LOGIC; + SIGNAL fb_ad_en_15_8_dma : STD_LOGIC; + SIGNAL fb_ad_en_15_8_ih : STD_LOGIC; + SIGNAL fb_ad_en_23_16_dma : STD_LOGIC; + SIGNAL fb_ad_en_23_16_ih : STD_LOGIC; + SIGNAL fb_ad_en_31_24_dma : STD_LOGIC; + SIGNAL fb_ad_en_31_24_ih : STD_LOGIC; + + SIGNAL fb_ad_en_dsp : STD_LOGIC; + SIGNAL fb_ad_en_rtc : STD_LOGIC; + SIGNAL fb_ad_out_dma : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fb_ad_out_dsp : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fb_ad_out_ih : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fb_ad_out_rtc : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL fb_ad_out_video : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fb_adr : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fb_b0 : STD_LOGIC; -- UPPER Byte BEI 16 STD_LOGIC BUS + SIGNAL fb_b1 : STD_LOGIC; -- LOWER Byte BEI 16 STD_LOGIC BUS + SIGNAL fb_ddr : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL fb_le : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL fb_vdoe : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL fbee_conf : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fd_int : STD_LOGIC; + SIGNAL fdc_cs_n : STD_LOGIC; + SIGNAL fdc_wr_n : STD_LOGIC; + SIGNAL fifo_clr : STD_LOGIC; + SIGNAL fifo_mw : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL hd_dd_out : STD_LOGIC; + SIGNAL hsync_i : STD_LOGIC; + SIGNAL ide_cf_ta : STD_LOGIC; + SIGNAL ide_res_i : STD_LOGIC; + SIGNAL int_handler_ta : STD_LOGIC; + SIGNAL irq_keybd_n : STD_LOGIC; + SIGNAL irq_midi_n : STD_LOGIC; + SIGNAL keyb_rxd : STD_LOGIC; + SIGNAL lds : STD_LOGIC; + SIGNAL locked : STD_LOGIC; + SIGNAL lp_d_x : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL lp_dir_x : STD_LOGIC; + SIGNAL mfp_cs : STD_LOGIC; + SIGNAL mfp_intack : STD_LOGIC; + SIGNAL mfp_int_n : STD_LOGIC; + SIGNAL midi_out : STD_LOGIC; + SIGNAL paddle_cs : STD_LOGIC; + SIGNAL pll_areset : STD_LOGIC; + SIGNAL pll_scanclk : STD_LOGIC; + SIGNAL pll_scandata : STD_LOGIC; + SIGNAL pll_scanclkena : STD_LOGIC; + SIGNAL pll_configupdate : STD_LOGIC; + SIGNAL pll_scandone : STD_LOGIC; + SIGNAL pll_scandataout : STD_LOGIC; + SIGNAL reset_n : STD_LOGIC; + SIGNAL scsi_bsy_en : STD_LOGIC; + SIGNAL scsi_bsy_out_n : STD_LOGIC; + SIGNAL scsi_cs : STD_LOGIC; + SIGNAL scsi_csn : STD_LOGIC; + SIGNAL scsi_d_en : STD_LOGIC; + SIGNAL scsi_dack_n : STD_LOGIC; + SIGNAL scsi_dbp_en : STD_LOGIC; + SIGNAL scsi_dbp_out_n : STD_LOGIC; + SIGNAL scsi_drq : STD_LOGIC; + SIGNAL scsi_int : STD_LOGIC; + SIGNAL scsi_d_out_n : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL scsi_rst_en : STD_LOGIC; + SIGNAL scsi_rst_out_n : STD_LOGIC; + SIGNAL scsi_sel_en : STD_LOGIC; + SIGNAL SCSI_SEL_OUTn : STD_LOGIC; + SIGNAL sd_cd_d3_en : STD_LOGIC; + SIGNAL sd_cd_d3_out : STD_LOGIC; + SIGNAL sd_cmd_d1_en : STD_LOGIC; + SIGNAL sd_cmd_d1_out : STD_LOGIC; + + SIGNAL sndcs : STD_LOGIC; + SIGNAL sndcs_i : STD_LOGIC; + SIGNAL sndir_i : STD_LOGIC; + SIGNAL sr_ddr_fb : STD_LOGIC; + SIGNAL sr_ddr_wr : STD_LOGIC; + SIGNAL sr_ddrwr_d_sel : STD_LOGIC; + SIGNAL sr_fifo_wre : STD_LOGIC; + SIGNAL sr_vdmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL tdo : STD_LOGIC; + SIGNAL timebase : unsigned (17 DOWNTO 0); + SIGNAL vd_en : STD_LOGIC; + SIGNAL vd_en_i : STD_LOGIC; + SIGNAL vd_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL vd_qs_en : STD_LOGIC; + SIGNAL vd_qs_out : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL vd_vz : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL vdm_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL vdp_in : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL vdp_out : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL vdp_q1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL vdp_q2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL vdp_q3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL vdr : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL video_ddr_ta : STD_LOGIC; + SIGNAL video_mod_ta : STD_LOGIC; + SIGNAL video_ram_ctr : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL video_reconfig : STD_LOGIC; + SIGNAL vr_busy : STD_LOGIC; + SIGNAL vr_d : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL vr_rd : STD_LOGIC; + SIGNAL vr_wr : STD_LOGIC; + SIGNAL vsync_i : STD_LOGIC; + SIGNAL wdc_bsl0 : STD_LOGIC; + +BEGIN + I_PLL1: altpll1 + PORT MAP( + inclk0 => CLK_MAIN, + c0 => clk_2m4576, -- 2.4576 MHz + c1 => CLK_24M576, -- 24.576 MHz + c2 => clk_48m, -- 48 MHz + locked => locked + ); + + I_PLL2: altpll2 + PORT MAP( + inclk0 => CLK_MAIN, + c0 => clk_ddr(0), -- 132 MHz / 240° + c1 => clk_ddr(1), -- 132 MHz / 0° + c2 => clk_ddr(2), -- 132 MHz / 180° + c3 => clk_ddr(3), -- 132 MHz / 105° + c4 => ddr_sync_66m -- 66 MHz / 270° + ); + + I_PLL3: altpll3 + PORT MAP( + inclk0 => CLK_MAIN, + c0 => clk_2m0, -- 2 MHz + c1 => clk_fdc, -- 16 MHz + c2 => clk_25m_i, -- 25 MHz + c3 => clk_500k -- 500 KHz + ); + + I_PLL4: altpll4 + PORT MAP( + inclk0 => CLK_MAIN, + areset => pll_areset, + scanclk => pll_scanclk, + scandata => pll_scandata, + scanclkena => pll_scanclkena, + configupdate => pll_configupdate, + c0 => clk_video, -- configurable video clk, set to 96 MHz INitially + scandataOUT => pll_scandataout, + scandone => pll_scandone + --locked => -- Not used. + ); + + I_RECONFIG: altpll_reconfig1 -- to enable reconfiguration of altpll4 (video clock) + PORT MAP( + reconfig => video_reconfig, + read_param => vr_rd, + write_param => vr_wr, + data_in => FB_AD(24 DOWNTO 16), -- FIXED: this looks like a typo. Must be FB_AD(24 DOWNTO 16) INstead of fb_adr(24 DOWNTO 16) + counter_type => fb_adr(5 DOWNTO 2), + counter_param => fb_adr(8 DOWNTO 6), + pll_scandataout => pll_scandataout, + pll_scandone => pll_scandone, + clock => CLK_MAIN, + reset => NOT reset_n, + pll_areset_in => '0', -- Not used. + busy => vr_busy, + data_out => vr_d, + pll_scandata => pll_scandata, + pll_scanclk => pll_scanclk, + pll_scanclkena => pll_scanclkena, + pll_configupdate => pll_configupdate, + pll_areset => pll_areset + ); + + CLK_25M <= clk_25m_i; + CLK_USB <= clk_48m; + clk_ddr_OUT <= clk_ddr(0); + clk_ddr_OUTn <= NOT clk_ddr(0); + CLK_PIXEL <= clk_pixel_i; + + P_timebase: PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(clk_500k); + timebase <= timebase + 1; + END PROCESS P_timebase; + + reset_n <= RSTO_MCFn and locked; + IDE_RES <= NOT ide_res_i and reset_n; + DREQ1n <= DACK1n; + LED_FPGA_OK <= timebase(17); + + falcon_io_ta <= acia_cs OR sndcs OR NOT dtack_out_mfp_n OR paddle_cs OR ide_cf_ta OR dma_cs; + FB_TAn <= '0' WHEN (blitter_ta OR video_ddr_ta OR video_mod_ta OR falcon_io_ta OR dsp_ta OR int_handler_ta)= '1' ELSE 'Z'; + + acia_cs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 3) & "000" = x"FFFC00" ELSE '0'; -- FFFC00 - FFFC07 + mfp_cs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 6) & "000000" = x"FFFA00" ELSE '0'; -- FFFA00/40 + paddle_cs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 6) & "000000"= x"FF9200" ELSE '0'; -- FF9200-FF923F + sndcs <= '1' WHEN FB_CSn(1) = '0' and fb_adr(23 DOWNTO 2) & "00" = x"FF8800" ELSE '0'; -- FF8800-FF8803 + sndcs_i <= '1' WHEN sndcs = '1' and fb_adr (1) = '0' ELSE '0'; + sndir_i <= '1' WHEN sndcs = '1' and FB_WRn = '0' ELSE '0'; + + LP_D <= lp_d_x WHEN lp_dir_x = '0' ELSE (OTHERS => 'Z'); + LP_DIR <= lp_dir_x; + + ACSI_D <= acsi_d_out WHEN acsi_d_en = '1' ELSE (OTHERS => 'Z'); + + SCSI_D <= scsi_d_out_n WHEN scsi_d_en = '1' ELSE (OTHERS => 'Z'); + SCSI_DIR <= '0' WHEN scsi_d_en = '1' ELSE '1'; + SCSI_PAR <= scsi_dbp_out_n WHEN scsi_dbp_en = '1' ELSE 'Z'; + SCSI_RSTn <= scsi_rst_out_n WHEN scsi_rst_en = '1' ELSE 'Z'; + SCSI_BUSYn <= scsi_bsy_out_n WHEN scsi_bsy_en = '1' ELSE 'Z'; + SCSI_SELn <= SCSI_SEL_OUTn WHEN scsi_sel_en = '1' ELSE 'Z'; + + keyb_rxd <= '0' WHEN AMKB_RX = '0' OR PIC_AMKB_RX = '0' ELSE '1'; -- get keyboard data either from PIC (PS/2) OR from Atari keyboard + + SD_D3 <= sd_cd_d3_out WHEN sd_cd_d3_en = '1' ELSE 'Z'; + SD_CMD_D1 <= sd_cmd_d1_out WHEN sd_cmd_d1_en = '1' ELSE 'Z'; + + DSP_IO <= dsp_io_out WHEN dsp_io_en = '1' ELSE (OTHERS => 'Z'); + DSP_SRD <= dsp_srd_out WHEN dsp_srd_en = '1' ELSE (OTHERS => 'Z'); + + hd_dd_out <= FDD_HD_DD WHEN fbee_conf(29) = '0' ELSE wdc_bsl0; + lds <= '1' WHEN mfp_cs = '1' OR mfp_intack = '1' ELSE '0'; + acia_irq_n <= irq_keybd_n and irq_midi_n; + mfp_intack <= '1' WHEN FB_CSn(2) = '0' and fb_adr(19 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000 + dint_n <= '0' WHEN IDE_INT = '1' and fbee_conf(28) = '1' ELSE + '0' WHEN fd_int = '1' ELSE + '0' WHEN scsi_int = '1' and fbee_conf(28) = '1' ELSE '1'; + + MIDI_TLR <= midi_out; + MIDI_OLR <= midi_out; + + byte <= '1' WHEN FB_SIZE(1) = '0' and FB_SIZE(0) = '1' ELSE '0'; + fb_b0 <= '1' WHEN fb_adr(0) = '0' OR byte = '0' ELSE '0'; + fb_b1 <= '1' WHEN fb_adr(0) = '1' OR byte = '0' ELSE '0'; + + FB_AD(31 DOWNTO 24) <= data_out_blitter(31 DOWNTO 24) WHEN data_en_blitter = '1' ELSE + vdp_q1(31 DOWNTO 24) WHEN fb_vdoe = x"2" ELSE + vdp_q2(31 DOWNTO 24) WHEN fb_vdoe = x"4" ELSE + vdp_q3(31 DOWNTO 24) WHEN fb_vdoe = x"8" ELSE + fb_ad_out_video(31 DOWNTO 24) WHEN fb_ad_en_31_16_video = '1' ELSE + fb_ad_out_dsp(31 DOWNTO 24) WHEN fb_ad_en_dsp = '1' ELSE + fb_ad_out_ih(31 DOWNTO 24) WHEN fb_ad_en_31_24_ih = '1' ELSE + fb_ad_out_dma(31 DOWNTO 24) WHEN fb_ad_en_31_24_dma = '1' ELSE + vdr(31 DOWNTO 24) WHEN fb_vdoe = x"1" ELSE + data_out_ddr_ctrl(31 DOWNTO 24) WHEN data_en_h_ddr_ctrl = '1' ELSE + da_out_x WHEN sndcs_i = '1' and FB_OEn = '0' ELSE + x"00" WHEN mfp_intack = '1' and FB_OEn = '0' ELSE + data_out_acia_i WHEN acia_cs = '1' and fb_adr(2) = '0' and FB_OEn = '0' ELSE + data_out_acia_iI WHEN acia_cs = '1' and fb_adr(2) = '1' and FB_OEn = '0' ELSE + x"BF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"0" and FB_OEn = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"1" and FB_OEn = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"8" and FB_OEn = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"9" and FB_OEn = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"A" and FB_OEn = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"B" and FB_OEn = '0' ELSE + x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"10" and FB_OEn = '0' ELSE + x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"11" and FB_OEn = '0' ELSE (OTHERS => 'Z'); + + FB_AD(23 DOWNTO 16) <= data_out_blitter(23 DOWNTO 16) WHEN data_en_blitter = '1' ELSE + vdp_q1(23 DOWNTO 16) WHEN fb_vdoe = x"2" ELSE + vdp_q2(23 DOWNTO 16) WHEN fb_vdoe = x"4" ELSE + vdp_q3(23 DOWNTO 16) WHEN fb_vdoe = x"8" ELSE + fb_ad_out_video(23 DOWNTO 16) WHEN fb_ad_en_31_16_video = '1' ELSE + fb_ad_out_dsp(23 DOWNTO 16) WHEN fb_ad_en_dsp = '1' ELSE + fb_ad_out_ih(23 DOWNTO 16) WHEN fb_ad_en_23_16_ih = '1' ELSE + fb_ad_out_dma(23 DOWNTO 16) WHEN fb_ad_en_23_16_dma = '1' ELSE + vdr(23 DOWNTO 16) WHEN fb_vdoe = x"1" ELSE + data_out_ddr_ctrl(23 DOWNTO 16) WHEN data_en_l_ddr_ctrl = '1' ELSE + data_out_mfp WHEN mfp_cs = '1' and FB_OEn = '0' ELSE + x"00" WHEN mfp_intack = '1' and FB_OEn = '0' ELSE + fb_ad_out_rtc WHEN fb_ad_en_rtc = '1' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"0" and FB_OEn = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"1" and FB_OEn = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"8" and FB_OEn = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"9" and FB_OEn = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"A" and FB_OEn = '0' ELSE + x"FF" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"B" and FB_OEn = '0' ELSE + x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"10" and FB_OEn = '0' ELSE + x"00" WHEN paddle_cs = '1' and fb_adr(5 DOWNTO 1) = 5x"11" and FB_OEn = '0' ELSE (OTHERS => 'Z'); + + FB_AD(15 DOWNTO 8) <= data_out_blitter(15 DOWNTO 8) WHEN data_en_blitter = '1' ELSE + vdp_q1(15 DOWNTO 8) WHEN fb_vdoe = x"2" ELSE + vdp_q2(15 DOWNTO 8) WHEN fb_vdoe = x"4" ELSE + vdp_q3(15 DOWNTO 8) WHEN fb_vdoe = x"8" ELSE + fb_ad_out_video(15 DOWNTO 8) WHEN fb_ad_en_15_0_video = '1' ELSE + fb_ad_out_dsp(15 DOWNTO 8) WHEN fb_ad_en_dsp = '1' ELSE + fb_ad_out_ih(15 DOWNTO 8) WHEN fb_ad_en_15_8_ih = '1' ELSE + fb_ad_out_dma(15 DOWNTO 8) WHEN fb_ad_en_15_8_dma = '1' ELSE + vdr(15 DOWNTO 8) WHEN fb_vdoe = x"1" ELSE + "000000" & data_out_mfp(7 DOWNTO 6) WHEN mfp_intack = '1' and FB_OEn = '0' ELSE (OTHERS => 'Z'); + + FB_AD(7 DOWNTO 0) <= data_out_blitter(7 DOWNTO 0) WHEN data_en_blitter = '1' ELSE + vdp_q1(7 DOWNTO 0) WHEN fb_vdoe = x"2" ELSE + vdp_q2(7 DOWNTO 0) WHEN fb_vdoe = x"4" ELSE + vdp_q3(7 DOWNTO 0) WHEN fb_vdoe = x"8" ELSE + fb_ad_out_video(7 DOWNTO 0) WHEN fb_ad_en_15_0_video = '1' ELSE + fb_ad_out_dsp(7 DOWNTO 0) WHEN fb_ad_en_dsp = '1' ELSE + fb_ad_out_ih(7 DOWNTO 0) WHEN fb_ad_en_7_0_ih = '1' ELSE + fb_ad_out_dma(7 DOWNTO 0) WHEN fb_ad_en_7_0_dma = '1' ELSE + vdr(7 DOWNTO 0) WHEN fb_vdoe = x"1" ELSE + data_out_mfp(5 DOWNTO 0) & "00" WHEN mfp_intack = '1' and FB_OEn = '0' ELSE (OTHERS => 'Z'); + + synchronization : PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(ddr_sync_66m); + IF FB_ALE = '1' THEN + fb_adr <= FB_AD; -- latch Flexbus address + END IF; + -- + IF vd_en_i = '0' THEN + vdr <= VD; + ELSE + vdr <= vd_out; + END IF; + -- + IF fb_le(0) = '1' THEN + fb_ddr(127 DOWNTO 96) <= FB_AD; + END IF; + -- + IF fb_le(1) = '1' THEN + fb_ddr(95 DOWNTO 64) <= FB_AD; + END IF; + -- + IF fb_le(2) = '1' THEN + fb_ddr(63 DOWNTO 32) <= FB_AD; + END IF; + -- + IF fb_le(3) = '1' THEN + fb_ddr(31 DOWNTO 0) <= FB_AD; + END IF; + END PROCESS SYNCHRONIZATION; + + VIDEO_OUT: PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(clk_pixel_i); + VSYNC <= vsync_i; + HSYNC <= hsync_i; + BLANKn <= blank_i_n; + END PROCESS VIDEO_OUT; + + P_ddr_wr: PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(clk_ddr(3)); + ddr_wr <= sr_ddr_wr; + ddrwr_d_sel(0) <= sr_ddrwr_d_sel; + END PROCESS P_ddr_wr; + + vd_qs_en <= ddr_wr; + VD <= vd_out WHEN vd_en = '1' ELSE (OTHERS => 'Z'); + + vd_qs_out(0) <= clk_ddr(0); + vd_qs_out(1) <= clk_ddr(0); + vd_qs_out(2) <= clk_ddr(0); + vd_qs_out(3) <= clk_ddr(0); + VD_QS <= vd_qs_out WHEN vd_qs_en = '1' ELSE (OTHERS => 'Z'); + + DDR_DATA_IN_N: PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(clk_ddr(1)); + ddr_d_in_n <= VD; + END PROCESS DDR_DATA_IN_N; + -- + DDR_DATA_IN_P: PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(clk_ddr(1)); + vdp_in(31 DOWNTO 0) <= VD; + vdp_in(63 DOWNTO 32) <= ddr_d_in_n; + END PROCESS DDR_DATA_IN_P; + + DDR_DATA_OUT_P: PROCESS(clk_ddr(3)) + variable DDR_D_OUT_H : STD_LOGIC_VECTOR(31 DOWNTO 0); + variable DDR_D_OUT_L : STD_LOGIC_VECTOR(31 DOWNTO 0); + BEGIN + IF clk_ddr(3) = '1' and clk_ddr(3)' event THEN + DDR_D_OUT_H := vdp_out(63 DOWNTO 32); + DDR_D_OUT_L := vdp_out(31 DOWNTO 0); + vd_en <= sr_ddr_wr OR ddr_wr; + END IF; + -- + case clk_ddr(3) is + WHEN '1' => vd_out <= DDR_D_OUT_H; + WHEN OTHERS => vd_out <= DDR_D_OUT_L; + END case; + END PROCESS DDR_DATA_OUT_P; + + WITH ddrwr_d_sel select + vdp_out <= blitter_dout(63 DOWNTO 0) WHEN "11", + blitter_dout(127 DOWNTO 64) WHEN "10", + fb_ddr(63 DOWNTO 0) WHEN "01", + fb_ddr(127 DOWNTO 64) WHEN "00", + (OTHERS => 'Z') WHEN OTHERS; + + vd_en_i <= sr_ddr_wr OR ddr_wr; + + VDP_Q_BUFFER: PROCESS + BEGIN + WAIT UNTIL RISING_EDGE(clk_ddr(0)); + ddr_fb <= sr_ddr_fb & ddr_fb(4 DOWNTO 1); + -- + IF ddr_fb(1) = '1' THEN + vdp_q1 <= vdp_in(31 DOWNTO 0); + END IF; + -- + IF ddr_fb(0) = '1' THEN + vdp_q2 <= vdp_in(63 DOWNTO 32); + vdp_q3 <= vdp_in(31 DOWNTO 0); + END IF; + END PROCESS VDP_Q_BUFFER; + + I_DDR_CTRL: DDR_CTRL_V1 + PORT MAP( + CLK_MAIN => CLK_MAIN, + ddr_sync_66m => ddr_sync_66m, + fb_adr => fb_adr, + FB_CS1n => FB_CSn(1), + FB_OEn => FB_OEn, + FB_SIZE0 => FB_SIZE(0), + FB_SIZE1 => FB_SIZE(1), + FB_ALE => FB_ALE, + FB_WRn => FB_WRn, + blitter_adr => blitter_adr, + blitter_sig => blitter_sig, + blitter_wr => blitter_wr, + SR_BLITTER_DACK => blitter_dack_sr, + BA => BA, + VA => VA, + fb_le => fb_le, + CLK_33M => CLK_33M, + VRASn => VRASn, + VcaSn => VcaSn, + VWEn => VWEn, + VCSn => VCSn, + fifo_clr => fifo_clr, + DDRCLK0 => clk_ddr(0), + video_control_register => video_ram_ctr, + VCKE => VCKE, + DATA_IN => FB_AD, + DATA_OUT => data_out_ddr_ctrl, + DATA_EN_H => data_en_h_ddr_ctrl, + DATA_EN_L => data_en_l_ddr_ctrl, + vdm_sel => vdm_sel, + fifo_mw => fifo_mw, + fb_vdoe => fb_vdoe, + sr_fifo_wre => sr_fifo_wre, + sr_ddr_fb => sr_ddr_fb, + sr_ddr_wr => sr_ddr_wr, + sr_ddrwr_d_sel => sr_ddrwr_d_sel, + sr_vdmp => sr_vdmp, + video_ddr_ta => video_ddr_ta, + ddrwr_d_sel1 => ddrwr_d_sel(1) + ); + + I_BLITTER: FBEE_BLITTER + PORT MAP( + resetn => reset_n, + CLK_MAIN => CLK_MAIN, + clk_ddr0 => clk_ddr(0), + fb_adr => fb_adr, + FB_ALE => FB_ALE, + FB_SIZE1 => FB_SIZE(1), + FB_SIZE0 => FB_SIZE(0), + FB_CSn => FB_CSn, + FB_OEn => FB_OEn, + FB_WRn => FB_WRn, + DATA_IN => FB_AD, + DATA_OUT => data_out_blitter, + DATA_EN => data_en_blitter, + blitter_adr => blitter_adr, + blitter_sig => blitter_sig, + blitter_wr => blitter_wr, + blitter_on => blitter_on, + blitter_run => blitter_run, + BLITTER_DIN => vd_vz, + blitter_dout => blitter_dout, + blitter_ta => blitter_ta, + blitter_dack_sr => blitter_dack_sr + ); + + I_VIDEOSYSTEM: VIDEO_SYSTEM + PORT MAP( + CLK_MAIN => CLK_MAIN, + CLK_33M => CLK_33M, + CLK_25M => clk_25m_i, + clk_video => clk_video, + clk_ddr3 => clk_ddr(3), + clk_ddr2 => clk_ddr(2), + clk_ddr0 => clk_ddr(0), + CLK_PIXEL => clk_pixel_i, + + vr_d => vr_d, + vr_busy => vr_busy, + + fb_adr => fb_adr, + FB_AD_IN => FB_AD, + FB_AD_OUT => fb_ad_out_video, + FB_AD_EN_31_16 => fb_ad_en_31_16_video, + FB_AD_EN_15_0 => fb_ad_en_15_0_video, + FB_ALE => FB_ALE, + FB_CSn => FB_CSn, + FB_OEn => FB_OEn, + FB_WRn => FB_WRn, + FB_SIZE1 => FB_SIZE(1), + FB_SIZE0 => FB_SIZE(0), + + vdp_in => vdp_in, + + vr_rd => vr_rd, + vr_wr => vr_wr, + video_reconfig => video_reconfig, + + RED => VR, + GREEN => VG, + BLUE => VB, + VSYNC => vsync_i, + HSYNC => hsync_i, + SYNCn => SYNCn, + BLANKn => blank_i_n, + + PD_VGAn => PD_VGAn, + video_mod_ta => video_mod_ta, + + vd_vz => vd_vz, + sr_fifo_wre => sr_fifo_wre, + sr_vdmp => sr_vdmp, + fifo_mw => fifo_mw, + vdm_sel => vdm_sel, + video_ram_ctr => video_ram_ctr, + fifo_clr => fifo_clr, + VDM => VDM, + blitter_on => blitter_on, + blitter_run => blitter_run + ); + + I_INTHANDLER: INTHANDLER + PORT MAP( + CLK_MAIN => CLK_MAIN, + resetn => reset_n, + fb_adr => fb_adr, + FB_CSn => FB_CSn(2 DOWNTO 1), + FB_OEn => FB_OEn, + FB_SIZE0 => FB_SIZE(0), + FB_SIZE1 => FB_SIZE(1), + FB_WRn => FB_WRn, + FB_AD_IN => FB_AD, + FB_AD_OUT => fb_ad_out_ih, + FB_AD_EN_31_24 => fb_ad_en_31_24_ih, + FB_AD_EN_23_16 => fb_ad_en_23_16_ih, + FB_AD_EN_15_8 => fb_ad_en_15_8_ih, + FB_AD_EN_7_0 => fb_ad_en_7_0_ih, + PIC_INT => PIC_INT, + E0_INT => E0_INT, + DVI_INT => DVI_INT, + PCI_INTAn => PCI_INTAn, + PCI_INTBn => PCI_INTBn, + PCI_INTCn => PCI_INTCn, + PCI_INTDn => PCI_INTDn, + mfp_intn => mfp_int_n, + dsp_int => dsp_int, + VSYNC => vsync_i, + HSYNC => hsync_i, + drq_dma => drq_dma, + IRQn => IRQn, + int_handler_ta => int_handler_ta, + fbee_conf => fbee_conf, + TIN0 => TIN0 + ); + + I_DMA: FBEE_DMA + PORT MAP( + RESET => NOT reset_n, + CLK_MAIN => CLK_MAIN, + clk_fdc => clk_fdc, + + fb_adr => fb_adr(26 DOWNTO 0), + FB_ALE => FB_ALE, + FB_SIZE => FB_SIZE, + FB_CSn => FB_CSn(2 DOWNTO 1), + FB_OEn => FB_OEn, + FB_WRn => FB_WRn, + FB_AD_IN => FB_AD, + FB_AD_OUT => fb_ad_out_dma, + FB_AD_EN_31_24 => fb_ad_en_31_24_dma, + FB_AD_EN_23_16 => fb_ad_en_23_16_dma, + FB_AD_EN_15_8 => fb_ad_en_15_8_dma, + FB_AD_EN_7_0 => fb_ad_en_7_0_dma, + + ACSI_DIR => ACSI_DIR, + ACSI_D_IN => ACSI_D, + acsi_d_out => acsi_d_out, + acsi_d_en => acsi_d_en, + ACSI_CSn => ACSI_CSn, + ACSI_A1 => ACSI_A1, + ACSI_resetn => ACSI_reset_n, + ACSI_DRQn => ACSI_DRQn, + ACSI_ACKn => ACSI_ACKn, + + DATA_IN_FDC => data_out_fdc, + DATA_IN_SCSI => data_out_scsi, + data_out_fdc_SCSI => data_in_fdc_scsi, + + DMA_DRQ_IN => drq_fdc, + DMA_DRQ_OUT => drq_dma, + DMA_DRQ11 => drq11_dma, + + scsi_drq => scsi_drq, + scsi_dackn => scsi_dack_n, + scsi_int => scsi_int, + scsi_csn => scsi_csn, + scsi_cs => scsi_cs, + + ca => ca, + FLOPPY_HD_DD => FDD_HD_DD, + wdc_bsl0 => wdc_bsl0, + fdc_csn => fdc_cs_n, + fdc_wrn => fdc_wr_n, + fd_int => fd_int, + IDE_INT => IDE_INT, + dma_cs => dma_cs + ); + + I_IDE_CF_SD_ROM: IDE_CF_SD_ROM + PORT MAP( + RESET => NOT reset_n, + CLK_MAIN => CLK_MAIN, + + fb_adr => fb_adr(19 DOWNTO 5), + FB_CS1n => FB_CSn(1), + FB_WRn => FB_WRn, + fb_b0 => fb_b0, + fb_b1 => fb_b1, + + fbee_conf => fbee_conf(31 DOWNTO 30), + + RP_UDSn => RP_UDSn, + RP_ldsn => RP_ldsn, + + SD_CLK => SD_CLK, + SD_D0 => SD_D0, + SD_D1 => SD_D1, + SD_D2 => SD_D2, + SD_CD_D3_IN => SD_D3, + sd_cd_d3_out => sd_cd_d3_out, + sd_cd_d3_en => sd_cd_d3_en, + SD_CMD_D1_IN => SD_CMD_D1, + sd_cmd_d1_out => sd_cmd_d1_out, + sd_cmd_d1_en => sd_cmd_d1_en, + SD_caRD_DETECT => SD_caRD_DETECT, + SD_WP => SD_WP, + + IDE_RDY => IDE_RDY, + IDE_WRn => IDE_WRn, + IDE_RDn => IDE_RDn, + IDE_CSn => IDE_CSn, + -- IDE_DRQn =>, -- Not used. + ide_cf_ta => ide_cf_ta, + + ROM4n => ROM4n, + ROM3n => ROM3n, + + CF_WP => CF_WP, + CF_CSn => CF_CSn + ); + + I_DSP: DSP + PORT MAP( + CLK_33M => CLK_33M, + CLK_MAIN => CLK_MAIN, + FB_OEn => FB_OEn, + FB_WRn => FB_WRn, + FB_CS1n => FB_CSn(1), + FB_CS2n => FB_CSn(2), + FB_SIZE0 => FB_SIZE(0), + FB_SIZE1 => FB_SIZE(1), + FB_BURSTn => FB_BURSTn, + fb_adr => fb_adr, + resetn => reset_n, + FB_CS3n => FB_CSn(3), + SRCSn => DSP_SRCSn, + SRBLEn => DSP_SRBLEn, + SRBHEn => DSP_SRBHEn, + SRWEn => DSP_SRWEn, + SROEn => DSP_SROEn, + dsp_int => dsp_int, + dsp_ta => dsp_ta, + FB_AD_IN => FB_AD, + FB_AD_OUT => fb_ad_out_dsp, + FB_AD_EN => fb_ad_en_dsp, + IO_IN => DSP_IO, + IO_OUT => dsp_io_out, + IO_EN => dsp_io_en, + SRD_IN => DSP_SRD, + SRD_OUT => dsp_srd_out, + SRD_EN => dsp_srd_en + ); + + I_SOUND: WF2149IP_TOP_SOC + PORT MAP( + SYS_CLK => CLK_MAIN, + resetn => reset_n, + + WAV_CLK => clk_2m0, + SELn => '1', + + BDIR => sndir_i, + BC2 => '1', + BC1 => sndcs_i, + + A9n => '0', + A8 => '1', + DA_IN => FB_AD(31 DOWNTO 24), + DA_OUT => da_out_x, + + IO_A_IN => x"00", -- All port pINs are dedicated OUTputs. + IO_A_OUT(7) => ide_res_i, + IO_A_OUT(6) => lp_dir_x, + IO_A_OUT(5) => LP_STR, + IO_A_OUT(4) => DTR, + IO_A_OUT(3) => RTS, + IO_A_OUT(2) => RESERVED_1, + IO_A_OUT(1) => DSA_D, + IO_A_OUT(0) => FDD_SDSELn, + -- IO_A_EN => TOUT0n, -- Not required. + IO_B_IN => LP_D, + IO_B_OUT => lp_d_x, + -- IO_B_EN => -- Not used. + + OUT_A => YM_QA, + OUT_B => YM_QB, + OUT_C => YM_QC + ); + + I_MFP: WF68901IP_TOP_SOC + PORT MAP( + -- System control: + CLK => CLK_MAIN, + resetn => reset_n, + -- Asynchronous bus control: + DSn => NOT lds, + CSn => NOT mfp_cs, + RWn => FB_WRn, + DTACKn => dtack_out_mfp_n, + -- Data and Adresses: + RS => fb_adr(5 DOWNTO 1), + DATA_IN => FB_AD(23 DOWNTO 16), + DATA_OUT => data_out_mfp, + -- DATA_EN => DATA_EN_MFP, -- Not used. + GPIP_IN(7) => NOT drq11_dma, + GPIP_IN(6) => NOT RI, + GPIP_IN(5) => dint_n, + GPIP_IN(4) => acia_irq_n, + GPIP_IN(3) => dsp_int, + GPIP_IN(2) => NOT CTS, + GPIP_IN(1) => NOT DCD, + GPIP_IN(0) => LP_BUSY, + -- GPIP_OUT =>, -- Not used; all GPIPs are direction INput. + -- GPIP_EN =>, -- Not used; all GPIPs are direction INput. + -- Interrupt control: + IACKn => NOT mfp_intack, + IEIn => '0', + -- IEOn =>, -- Not used. + IRQn => mfp_int_n, + -- Timers and timer control: + XTAL1 => clk_2m4576, + TAI => '0', + TBI => blank_i_n, + -- TAO =>, + -- TBO =>, + -- TCO =>, + tdo => tdo, + -- Serial I/O control: + RC => tdo, + TC => tdo, + SI => RxD, + SO => TxD + -- SO_EN => -- Not used. + -- DMA control: + -- RRn => -- Not used. + -- TRn => -- Not used. + ); + + I_ACIA_MIDI: WF6850IP_TOP_SOC + PORT MAP( + CLK => CLK_MAIN, + resetn => reset_n, + + CS2n => '0', + CS1 => fb_adr(2), + CS0 => acia_cs, + E => acia_cs, + RWn => FB_WRN, + RS => fb_adr(1), + + DATA_IN => FB_AD(31 DOWNTO 24), + DATA_OUT => data_out_acia_iI, + -- DATA_EN => -- Not used. + + TXCLK => clk_500k, + RXCLK => clk_500k, + RXDATA => MIDI_IN, + CTSn => '0', + DCDn => '0', + + IRQn => irq_midi_n, + TXDATA => midi_out + --RTSn => -- Not used. + ); + + I_ACIA_KEYBOARD: WF6850IP_TOP_SOC + PORT MAP( + CLK => CLK_MAIN, + resetn => reset_n, + + CS2n => fb_adr(2), + CS1 => '1', + CS0 => acia_cs, + E => acia_cs, + RWn => FB_WRn, + RS => fb_adr(1), + + DATA_IN => FB_AD(31 DOWNTO 24), + DATA_OUT => data_out_acia_i, + -- DATA_EN => Not used. + + TXCLK => clk_500k, + RXCLK => clk_500k, + RXDATA => keyb_rxd, + + CTSn => '0', + DCDn => '0', + + IRQn => irq_keybd_n, + TXDATA => AMKB_TX + --RTSn => -- Not used. + ); + + I_SCSI: WF5380_TOP_SOC + PORT MAP( + CLK => clk_fdc, + resetn => reset_n, + ADR => ca, + DATA_IN => data_in_fdc_scsi, + DATA_OUT => data_out_scsi, + --DATA_EN =>, + -- Bus and DMA controls: + CSn => scsi_csn, + RDn => NOT fdc_wr_n OR NOT scsi_cs, + WRn => fdc_wr_n OR NOT scsi_cs, + EOPn => '1', + DACKn => scsi_dack_n, + DRQ => scsi_drq, + INT => scsi_int, + -- READY =>, + -- SCSI bus: + DB_INn => SCSI_D, + DB_OUTn => scsi_d_out_n, + DB_EN => scsi_d_en, + DBP_INn => SCSI_PAR, + DBP_OUTn => scsi_dbp_out_n, + DBP_EN => scsi_dbp_en, -- wenn 1 dann OUTput + RST_INn => SCSI_RSTn, + RST_OUTn => scsi_rst_out_n, + RST_EN => scsi_rst_en, + BSY_INn => SCSI_BUSYn, + BSY_OUTn => scsi_bsy_out_n, + BSY_EN => scsi_bsy_en, + SEL_INn => SCSI_SELn, + SEL_OUTn => SCSI_SEL_OUTn, + SEL_EN => scsi_sel_en, + ACK_INn => '1', + ACK_OUTn => SCSI_ACKn, + -- ACK_EN => ACK_EN, + ATN_INn => '1', + ATN_OUTn => SCSI_ATNn, + -- ATN_EN => ATN_EN, + REQ_INn => scsi_drqn, + -- REQ_OUTn => REQ_OUTn, + -- REQ_EN => REQ_EN, + IOn_IN => SCSI_IOn, + -- IOn_OUT => IOn_OUT, + -- IO_EN => IO_EN, + CDn_IN => SCSI_CDn, + -- CDn_OUT => CDn_OUT, + -- CD_EN => CD_EN, + MSG_INn => SCSI_MSGn + -- MSG_OUTn => MSG_OUTn, + -- MSG_EN => MSG_EN + ); + + I_FDC: WF1772IP_TOP_SOC + PORT MAP( + CLK => clk_fdc, + resetn => reset_n, + CSn => fdc_cs_n, + RWn => fdc_wr_n, + A1 => ca(2), + A0 => ca(1), + DATA_IN => data_in_fdc_scsi, + DATA_OUT => data_out_fdc, + -- DATA_EN => CD_EN_FDC, + RDn => FDD_RDn, + TR00n => FDD_TRACK00, + IPn => FDD_INDEXn, + WPRTn => FDD_WPn, + DDEn => '0', -- Fixed to MFM. + HDTYPE => hd_dd_out, + MO => FDD_MOT_ON, + WG => FDD_WR_GATE, + WD => FDD_WDn, + STEP => FDD_STEP, + DIRC => FDD_STEP_DIR, + DRQ => drq_fdc, + INTRQ => fd_int + ); + + I_RTC: RTC + PORT MAP( + CLK_MAIN => CLK_MAIN, + fb_adr => fb_adr(19 DOWNTO 0), + FB_CS1n => FB_CSn(1), + FB_SIZE0 => FB_SIZE(0), + FB_SIZE1 => FB_SIZE(1), + FB_WRn => FB_WRn, + FB_OEn => FB_OEn, + FB_AD_IN => FB_AD(23 DOWNTO 16), + FB_AD_OUT => fb_ad_out_rtc, + FB_AD_EN_23_16 => fb_ad_en_rtc, + PIC_INT => PIC_INT + ); +END ARCHITECTURE; + diff --git a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd index d6e24bd..9cbd579 100644 --- a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd +++ b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd @@ -166,7 +166,7 @@ package firebee_pkg is FB_ALE : in std_logic; FB_WRn : in std_logic; FIFO_CLR : in std_logic; - VIDEO_RAM_CTR : in std_logic_vector(15 downto 0); + video_control_register : in std_logic_vector(15 downto 0); BLITTER_ADR : in std_logic_vector(31 downto 0); BLITTER_SIG : in std_logic; BLITTER_WR : in std_logic; @@ -356,7 +356,7 @@ package firebee_pkg is BLITTER_WR : out std_logic; BLITTER_TA : out std_logic ); - end component; + end component; component DSP is port( @@ -575,4 +575,4 @@ package firebee_pkg is PIC_INT : in std_logic ); end component RTC; -end firebee_pkg; +end firebee_pkg;